WO2018068847A1

WO2018068847A1 - Highly linear digital-to-time converter for low noise all-digital phase locked loop

Info

Publication number: WO2018068847A1
Application number: PCT/EP2016/074481
Authority: WO
Inventors: Pasquale Lamanna; Danilo CARDISCIANI
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2016-10-12
Filing date: 2016-10-12
Publication date: 2018-04-19
Anticipated expiration: 2019-04-12
Also published as: CN109863697A; CN109863697B

Abstract

The present invention relates to an apparatus and method for generating an analog output voltage perfectly linear according to the digital input code associated with a capacitor array DAC. An array of n capacitors is split into a first and second array of respective x and n-x capacitors. In a first phase, the x and n-x capacitors are respectively connected in parallel with a first and second capacitor to form a respective first and second group of capacitors. In a second phase, the first and second groups are separately charged. In a third phase, the charged capacitors are connected to each other to obtain the analog output voltage across the second capacitor, which varies linearly according to a digital input code x corresponding to an x-bit digital input. In a fourth phase, the second capacitor is disconnected from the other capacitors and charged or discharged by a constant current source.

Description

HIGHLY LINEAR DIGITAL-TO-TIME CONVERTER FOR LOW NOISE ALL-DIGITAL PHASE LOCKED LOOP

TECHNICAL FIELD

The invention relates to the field of a digital phase locked loop, and more particularly to a linear digital-to-time converter intended for a low noise all-digital phase locked loop.

BACKGROUND

High resolution, high linearity, low noise and low power digital-to-time converters (DTCs) are required to implement high performance fractional-N all digital phase locked loops (ADPLLs) based on a binary phase detector (BPD). The linearity specification in terms of integral-non-linearity (INL) is rather hard to meet in an ADPLL for radio applications because the output spur level of the ADPLL depends on the INL. Moreover, the noise specification is very tight as the DTC noise is added to the reference noise and contributes to the output phase noise of the ADPLL. A DTC, also commonly referred as a delay line, is an electronic circuit that receives at its input a clock signal and a digital control word and generates at its output a delayed copy of its input clock signal. The basic element of a DTC is a variable delay element. If a delay tuning is linear, a high-linearity DTC can be realized and only two points are sufficient for calibration. Most existing DTCs, as found in "A 2.9-to-4.0 GHz fractional-N digital PLL with bang-bang phase detector and 560 fsrms integrated jitter at 4.5 mW power", IEEE J. Solid-State Circuits, vol. 46, no. 12, pp. 2745-2758 (December 2011), by D. Tasca, M. Zanuso, G. Marzin, S. Levantino, C. Samori and A. L. Lacaita, are implemented using a coarse/fine architecture. Although that simplifies the construction, the coarse/fine architectures are inherently prone to linearity issues and a non-monotonic behavior, particularly at the transition between the fine and coarse control, and complex calibrations are often required to align the fine and coarse components.

Other delay lines, as found for example in "A wideband 3.6 GHz digital ΔΣ fractional-N PLL with phase interpolation divider and digital spur cancellation", IEEE J. Solid-State Circuits, vol. 46, no. 3, pp. 627- 638 (March 2011), by M. Zanuso, S. Levantino, C. Samori and A. L. Lacaita, are implemented using delay stages comprising digital inverters, wherein the desired delay is selected by a multiplexer at the output. However, the standard issues met with those delay lines are the bad matching between the inverters, the high current consumption and the added noise. Another kind of delay line exploits a voltage ramp generated by a current source charging a capacitor, wherein a comparator flags when the voltage on the capacitor reaches the threshold voltage level. The varia ble delay can be generated by: - switched capacitors, as depicted in Fig. 1 and found in "A 5.3GHz digital-to-time-converter-based fractional-N a ll-digital PLL", IEEE International Solid-State Circuits Conference (ISSCC), pp.54-56, 20-24 February 2011, by N. Pavlovic and J. Bergervoet;

- switched current sources, as depicted in Fig. 2 and found in "Spur-free all-digital PLL in 65nm for mobile phones", I EEE International Solid-State Circuits Conference (ISSCC), pp.52-54, 20-24 February 2011, by R. B. Staszewski, K. Waheed, S. Vemulapalli, F. Dulger, J. Wallberg, Chih-Ming Hung and O. Eliezer; and

- a com bination of switched capacitors and switched current sources, as depicted in Fig. 3.

All those three possibilities generate a voltage ramp with a varia ble slope. However, when a varia ble slope ramp is at the input of a threshold comparator, the linearity is strongly degraded by the intrinsic non-linear behavior of the comparator, as depicted in Fig. 4 and found in "A comprehensive delay macro modeling for su b-micrometer CMOS logics", I EEE Journal of Solid-State Circuits, January 1999, by M. Daga and D. Auvergne. Solutions based on a ramp voltage with constant slope reduce the integral non linearity, IN L, error associated with such a varia ble slope. As depicted in Fig. 5, a Capacitor Array Digital to Analog Converter (CDAC), having 2^m-l capacitors for an input code with a resolution of m bits, is connected in parallel with a capacitor CI (Fig. 5a) or in parallel with a capacitor C2 (Fig. 5b). However, the voltage value is not linear versus the digital input code in none of those two configurations.

In Fig. 5a, in a first phase, the CDAC adds a capacitance value CX=X*CLSB to a capacitor CI by means of a switch T3. In a second phase denoted as a charging phase, the CI and Cx capacitors are then connected to the power supply VDD by means of a switch Tl, such that the charge Q satisfies the relation: Q(X)=VDD*(C1+X*CLSB). During a third phase denoted as a sharing phase, the switch Tl is turned off and the CI and Cx capacitors are connected to a capacitor C2, which has a zero initial charge, by means of a switch T2. Thereby, the following equation is obtained :

CI + *C_LSB

Vc(x) = VDD * (4)

CI + C2 + *C_LSB wherein the voltage value Vc(x) is however non-linear with the digital input code x. In Fig. 5b, in a first phase, the CDAC adds a capacitance value CX=X*CLSB to a capacitor C2 by means of a switch T5. In a second phase denoted as a charging phase, a capacitor CI is then connected to the power supply VDD by means of a switch Tl such that the charge Q satisfies the relation: Q=VDD*(C1). During a third phase denoted as a sharing phase, the switch Tl is turned off and the capacitor CI is connected to the C2 and Cx capacitors, which have a zero initial charge, by mea ns of a switch T2. Thereby, the following equation is obtained : ci

Vc x = VDD * (5)

C1 + C2 + X*C_LSB wherein the voltage value Vc(x) is still non-linear with the digital input code x.

Assumed that the CDAC of Fig. 5 has a resolution of m-bit, it is then built of n=2^m-l equal capacitors. At code x, x capacitors with a total value of X*C_LSB are connected, while the remaining n-x capacitors with a total value of (n-x)*C_Ls_B are always left unconnected to the other ca pacitors (CI, C2) by remaining connected to a floating node.

Instead of using CDAC architecture to set the voltage Vc(x), solutions using complex current steering digital-to-analog converters (DACs) exist, but require a large area and a high power consu mption. In addition, such DACs have an output noise that is usually too high for an ADPLL application.

SUM MARY

It is therefore an object of the present invention to provide an apparatus and method for generating an analog output voltage that varies linearly according to an x-bit digital input, and an apparatus and method for adjusta bly generating a time delay that starts from the generated analog output voltage, the apparatuses having a simple and compact design and a low-noise and energy-efficient configuration.

The object is achieved by the features of the independent claims. Further embodiments of the invention are apparent from the dependent claims, the description and the figures.

According to a first aspect, the invention relates to an apparatus for generating an analog output voltage from a digital input signal x. The apparatus comprises a first capacitor connected to a first node; a second capacitor (C2) connected to a second node (N2); a nd a capacitor array of n elementary capacitors from a capacitor array digital-to-analog converter. The n elementary capacitors can be connected in parallel to the first capacitor (CI) and the second capacitor (C2). In a charging phase a first array of x elementary capacitors of the capacitor array are connected in parallel to the first capacitor (CI) and a second array of n-x elementary capacitors of the capacitor array are connected in parallel to the second capacitor (C2), wherein x is the digital input signal. In a charge sharing phase the n elementary capacitors of the capacitor array are connected in parallel to the first capacitor (CI) and the second capacitor (C2).

According to a first implementation of the apparatus according to the first aspect, the first array of x elementary capacitors is connected to a first terminal and the second array of n-x capacitors is connected to a second terminal. The apparatus further comprises a plurality of switching elements adapted to operate according to a switching sequence, wherein the switching sequence comprises:

- during a first phase, connecting the first array of x capacitors in parallel with the first capacitor through a connection of the first terminal to the first node, and connecting the second array of n-x capacitors in parallel with the second capacitor through a connection of the second terminal to the second node;

- during a second phase following the first phase, separately charging the first array of x capacitors connected in parallel with the first capacitor and the second array of n-x capacitors connected in parallel with the second capacitor; and

- during a third phase following the second phase, interrupting the step of charging and connecting in parallel the first array of x capacitors connected in parallel with the first capacitor and the second array of n-x capacitors connected in parallel with the second capacitor as to obtain the analog output voltage across the second capacitor. Thereby, the apparatus can generate an analog output voltage that varies linearly according to a digital input code x corresponding to an x-bit digital input.

According to a second implementation of the apparatus according to the first or second aspect, the first array of x capacitors connected in parallel with the first capacitor is charged to a first reference voltage level during the second phase, and the second array of n-x capacitors connected in parallel with the second capacitor is charged to a second reference voltage level. The second reference voltage may be, for instance, ground.

Thereby, the reference voltage levels can have any values such that the apparatus can be used in both the analog domain and the digital domain. As an example in the digital domain, the first reference voltage can be a supply voltage, for example VDD, and the second reference voltage can be a ground voltage. As another example in the digital domain, the first reference voltage can be a ground voltage and the second reference voltage can be a supply voltage, for example VDD. According to a third implementation of the apparatus according to the second implementation of the first aspect, the plurality of switching elements comprises a first switching element connected between the first reference voltage and the first node, a second switching element connected between the first node and the second node, a third switching element connected between the first node and the first terminal, a fourth switching element connected between the second reference voltage and the second node and a fifth switching element connected between the second node and the second terminal.

Thereby, the first, second and third phases can be controllable through the first to fifth switching elements.

According to a fourth implementation of the apparatus according to the third implementation of the first aspect, the third and fifth switching elements are in a conductive state and the second and fourth switching elements are in a non-conductive state during the first phase, whereas the first, third, fourth and fifth switching elements are in a conductive state and the second switching element is in a non-conductive state during the second phase and the second, third and fifth switching elements are in a conductive state and the first and fourth switching elements are in a non- conductive state during the third phase.

Thereby, the state of the switching elements during the switching sequence can be clearly identified. It should be noted that the first switching element during the first phase can be either in a non- conductive state or in a conductive state. However, the conductive state of the first switching element during the first phase advantageously allows the first array of x capacitors and the first capacitor to be more quickly charged during the second phase. According to a fifth implementation of the apparatus according to the first implementation of the first aspect, the plurality of switching elements can comprise respective transistors operating in the switching mode.

Thereby, the apparatus can be made of only capacitors and transistors. Thus, the apparatus has a simple and compact design and a low-noise and energy-efficient configuration. The above object is also solved in accordance with a second aspect.

According to the second aspect, the invention relates to an apparatus for adjustably generating a time delay during a charging phase, the apparatus comprising the apparatus according to the first aspect or any of the implementation thereof, a constant current source adapted to charge, during a fourth phase following the third phase, the second capacitor starting from an initial voltage value corresponding to the analog output voltage in order to generate a voltage ramp having a constant slope, and a comparator adapted to input the voltage across the second capacitor and generate the time delay corresponding to the charging time taken by the voltage across the second capacitor to reach a threshold voltage of the comparator starting from the initial voltage value.

Thereby, the charge is linear and a voltage ramp with a constant slope and starting from an initial voltage value varying linearly according to a digital input code x can be generated, which allows the time delay to be adjustable according to the digital input code x. In addition, the apparatus exhibits a simple and compact design while having a low-noise and energy-efficient configuration.

According to a first implementation of the apparatus according to the second aspect, the initial voltage value is set according to x corresponding to the x-bit digital input in order to be lower than the threshold voltage of the comparator.

Thereby, an output edge can be generated at the output of the comparator as soon as the voltage ramp crosses upwards the threshold value of the comparator.

According to a second implementation of the apparatus according to the second aspect or the first implementation of the second aspect, the step of charging the second capacitor comprises disconnecting the second capacitor from the first capacitor, the first array of x capacitors and the second array of n-x capacitors, and connecting the second capacitor to the constant current source through a sixth switching element. Thereby, the current charging phase can be controllable through the sixth switching element and the current of the constant current source can entirely flow through the second capacitor.

The above object is also solved in accordance with a third aspect. According to the third aspect, the invention relates to an apparatus for adjustably generating a time delay during a current discharging phase, the apparatus comprising the apparatus according to the first aspect or any of the implementations thereof, a constant current source adapted to discharge, during a fourth phase following the third phase, the second capacitor starting from an initial voltage value corresponding to the analog output voltage in order to generate a voltage ramp having a constant slope, and a comparator adapted to input the voltage across the second capacitor and generate the time delay corresponding to the discharging time taken by the voltage across the second capacitor to reach a threshold voltage of the comparator starting from the initial voltage value.

Thereby, the current discharge can be linear and a voltage ramp with a constant slope and starting from an initial voltage value varying linearly according to a digital input code x can be generated, which allows the time delay to be adjustable according to the digital input code x. In addition, the apparatus exhibits a simple and compact design while having a low-noise and energy-efficient configuration.

According to a first implementation of the apparatus according to the third aspect, the initial voltage value is set according to x corresponding to the x-bit digital input in order to be higher than the threshold voltage of the comparator.

Thereby, an output edge can be generated at the output of the comparator as soon as the voltage ramp crosses downwards the threshold value of the comparator.

According to a second implementation of the apparatus according to the third aspect or the first implementation of the third aspect, the step of current discharging the second capacitor comprises disconnecting the second capacitor from the first capacitor, the first array of x capacitors and the second array of n-x capacitors, and connecting the second capacitor to the constant current source through a sixth switching element. Thereby, the current discharging phase can be controllable through the sixth switching element and the current of the constant current source can entirely flow through the second capacitor.

According to a third implementation of the apparatus according to the second implementation of the second aspect or the second implementation of the third aspect, the sixth switching element is in a non-conductive state during the first, second and third phases and in a conductive state during the fourth phase, and the second, fourth and fifth switching elements are in a non-conductive state during the fourth phase.

Thereby, the state of the sixth switching element during the switching sequence can be clearly identified.

According to a fourth implementation of the apparatus according to the third implementation of the third aspect, the sixth switching element comprises a transistor operating in the switching mode. Thereby, the apparatus can have a simple and compact design and a low-noise and energy-efficient configuration.

According to a fifth implementation of the apparatus according to the second aspect or the third aspect, the comparator is a CMOS inverter or an analog comparator.

Thereby, the comparator can have a simple and compact design.

The above object is also solved in accordance with a fourth aspect. According to the fourth aspect, the invention relates to a linear digital-to-time converter comprising the apparatus according to the second or third aspect.

The above object is also solved in accordance with a fifth aspect. According to the fifth aspect, the invention relates to a digital phase locked loop comprising the apparatus according to the second, third or fourth aspect.

The above object is also solved in accordance with a sixth aspect. According to the sixth aspect, the invention relates to a method for generating an analog output voltage from a digital input signal x, by controlling an apparatus including a first capacitor connected to a first node, a second capacitor connected to a second node and a capacitor array of n elementary capacitors from a capacitor array digital-to-analog converter, CDAC, the n elementary capacitors being connectable in parallel to the first capacitor and the second capacitor. The method comprises: in a charging phase connecting a first array of x elementary capacitors of the capacitor array in parallel to the first capacitor and connecting a second array of n-x elementary capacitors of the capacitor array in parallel to the second capacitor, x is the digital input signal. In a charge sharing phase connecting the n elementary capacitors of the capacitor array in parallel to the first capacitor and the second capacitor.

According to a first implementation of the method according to the sixth aspect, the first array of x elementary capacitors is connected to a first terminal and the second array of n-x elementary capacitors is connected to a second terminal, and wherein the apparatus further includes a plurality of switching elements adapted to operate according to a switching sequence. The method further comprises:

- during a first phase of the switching sequence, connecting the first array of x capacitors in parallel with the first capacitor through a connection of the first terminal to the first node, and connecting the second array of n-x capacitors in parallel with the second capacitor through a connection of the second terminal to the second node;

- during a second phase of the switching sequence following the first phase, separately charging the first array of x capacitors connected in parallel with the first capacitor and the second array of n-x capacitors connected in parallel with the second capacitor; and

- during a third phase of the switching sequence following the second phase, interrupting the step of charging and connecting in parallel the first array of x capacitors connected in parallel with the first capacitor and the second array of n-x capacitors connected in parallel with the second capacitor as to obtain a voltage across the second capacitor, the voltage across the second capacitor being the analog output voltage. The above object is also solved in accordance with a seventh aspect.

According to the seventh aspect, the invention relates to a method for adjustably generating a time delay during a charging phase, the method comprising applying the steps of the method according to the sixth aspect, charging, during a fourth phase following the third phase, the second capacitor starting from an initial voltage value corresponding to the analog output voltage in order to generate a voltage ramp having a constant slope, and inputting the voltage across the second capacitor and generating the time delay corresponding to the current charging time taken by the second capacitor to reach a threshold voltage of the comparator starting from the initial voltage value, the initial voltage value being set according to x corresponding to the x-bit digital input in order to be lower than the threshold voltage of the comparator. According to a first implementation of the method according to the seventh aspect, the step of current charging comprises disconnecting the second capacitor from the first capacitor, the first array of x capacitors and the second array of n-x capacitors, and connecting, after the step of

disconnecting, the second capacitor to a constant current source through a sixth switching element.

The above object is also solved in accordance with an eighth aspect.

According to the eighth aspect, the invention relates to a method for adjustably generating a time delay during a current discharging phase, the method comprising applying the steps of the method according to the sixth aspect, current discharging, during a fourth phase following the third phase, the second capacitor starting from an initial voltage value corresponding to the analog output voltage in order to generate a voltage ramp having a constant slope, and inputting the voltage across the second capacitor and generating the time delay corresponding to the current discharging time taken by the second capacitor to reach a threshold voltage of the comparator starting from the initial voltage value, the initial voltage value being set according to x corresponding to the x-bit digital input in order to be higher than the threshold voltage of the comparator.

According to a first implementation of the method according to the eighth aspect, the step of current discharging comprises disconnecting the second capacitor from the first capacitor, the first array of x capacitors and the second array of n-x capacitors, and connecting, after the step of disconnecting, the second capacitor to a constant current source through a sixth switching element.

The above object is also solved in accordance with a ninth aspect. According to the ninth aspect, the invention relates to a computer program comprising a program code for performing the method according to any one of the sixth, seventh and eighth aspects and/or any one of their respective implementation forms when executed on a computer.

Thereby, the method can be performed in an automatic and repeatable manner.

The computer program can be performed by any one of the above apparatuses. The apparatuses can be programmably arranged to perform the computer program. Embodiments of the invention can be implemented in hardware, software or in any combination thereof.

It shall further be understood that a preferred embodiment of the invention can also be any combination of the dependent claims or above embodiments with the respective independent claims.

These and other aspects of the invention will be apparent and elucidated with reference to the embodiments described hereinafter.

BRIEF DESCRIPTION OF THE DRAWINGS

In the following detailed portion of the present disclosure, the invention will be explained in more detail with reference to the exemplary embodiments shown in the drawings, in which:

Fig. 1 shows a conventional delay line circuit, the variable delay of which is generated by switched capacitors, and the corresponding variable slope voltage ramp starting from an initial voltage value equal to zero; Fig. 2 shows a conventional delay line circuit, the variable delay of which is generated by switched current sources, and the corresponding variable slope voltage ramp starting from an initial voltage value equal to zero;

Fig. 3 shows a conventional delay line circuit, the variable delay of which is generated by a combination of switched capacitors, and switched current sources and the corresponding variable slope voltage ramp starting from an initial voltage value equal to zero;

Fig. 4 shows the non-linear behavior of a threshold comparator receiving a variable slope ramp;

Fig. 5 shows a conventional voltage generator circuit comprising a capacitor array digital-to- analog converter (CDAC) connected at an input of the voltage generator circuit as shown in Fig. 5a and at an output of the voltage generator circuit as shown in Fig. 5b; Fig. 6 shows the generation of a constant slope voltage ramp by the charge of a capacitor through a constant current source and a threshold comparison through a comparator;

Fig. 7a shows a voltage generator circuit according to a first embodiment of the invention;

Fig. 7b shows a detail of a voltage generator circuit according to an embodiment of the

invention;

Fig. 8 shows a voltage generator circuit according to a second embodiment of the invention;

Fig. 9 shows a digital-to-time converter circuit according to a third embodiment of the

invention;

Fig. 10 shows a digital-to-time converter circuit according to a fourth embodiment of the

invention.

Identical reference signs are used for identical or at least functionally equivalent features. DETAILED DESCRIPTION OF EMBODIMENTS OF THE INVENTION

The present invention is based on the observation that, conventional solutions based on CDAC capacitor array still do not allow to generate a voltage, which is linear in the digital input code. The present invention as described below provides an apparatus that is able to generate an initial voltage value on a capacitor that is linear with an input digital code. Using a conventional CDAC this would not be possible as the input-output relation is not linear as shown in equation 4 and 5 in the background section. The new CDAC described below, implemented together with a constant slope technique allows to generate a very linear delay.

To avoid the INL error associated with such a variable slope, the constant-slope method, in which the ramp keeps a constant slope, is used. In that method, an apparatus for generating an analog output voltage, or voltage generator circuit, generates a voltage ramp, by using a constant current source charging a capacitor starting from an initial value (Vc) that is set according to a digital code x. The voltage generator circuit generates a voltage, which is constant in time and varies linearly with input code x. The input code x is a digital control word representing a number. The constant current source generates a constant slope voltage ramp on a capacitor from the initial value Vc set by the voltage generator as will be described in detail below. The initial value Vc is linear versus the digital code x.

The voltage generator circuit may be used, for instance, in a DTC which exploits the generated voltage to set the initial voltage value (linearly dependent from an input digital code) in a capacitor, constant current source and a comparator with a threshold voltage (Vth).

To generate a voltage ramp with a controlled slope (S=AV/At), a current (I) is used to charge a capacitor as shown in Fig. 6, where the slope (S) satisfies the following equation:

S = l/C (1)

The delay time (td) of that voltage ramp from the zero voltage to the threshold voltage (Vth) satisfi the following equation: td = Vth/S (2)

Thus, the delay function contains two distinct actions, namely a ramp generation and a threshold comparison. The ramp generation produces a ramp with a controlled slope, while the threshold comparison defines a decision threshold (Vth) and produces an output edge as soon as said threshold has been reached. The biggest technica l challenge of the constant ramp technique is to generate the initial value (Vc) according to a digital input code x, namely Vc(x), in a very linear way.

For generalization purposes, the voltage ramp can start from an initial value Vc(x) different from zero. In that case, the corresponding delay time td(x) satisfies the following equation:

(-Vc(x) + Vth)/S (3)

To generate the initial voltage Vc as a fu nction of the digital input code x, wherein x spans from 0 to n=2^m-l for a m-bit resolution, a capacitor array, such as for instance a digital-to-analog converter (CDAC), is used. Accordingly, a capacitor C is charged with a charge Q (m bits) that is linear with the digital input code x. The capacitor array includes 2^m-l elementary equal capacitors CLse and can be controlled so that the output capacitance value of the capacitor array is a linear function of the digital control code: CCDAC(X)=X*CLSB. From the well-known capacitor relation Q=CV, the voltage V is a linear function of its charge Q. The voltage generator circuit according to one em bodiment of the invention is configured to generate an analog output voltage (Vc) from a digital input signal x. The digital input signal may be a digital control word input to a DTC device comprising the voltage generator circuit. The voltage generator circuit comprises a first capacitor CI connected to a first node N l. The first node N l may be in turn connecta ble through a switch to a reference voltage source V_ref,i- The voltage generator circuit further comprises a second capacitor C2 connected to a second node N2, and the capacitor array of n=2^m-l elementary capacitors CLSB- The n elementary capacitors are connecta ble in parallel to the first capacitor CI or the second capacitor C2. According to the invention, in a charging phase a first array of x elementary capacitors of the capacitor array are connected in parallel to the first capacitor CI and the complementary n-x elementary capacitors (forming a second array) are connected in parallel to the second capacitor C2. As explained a bove, for a resolution of m bit x is a value between 0 and 2^m-l corresponding to the input digital control word x. Accordingly, after the charging phase the charge accumulated in the capacitor CI and in x elementary capacitors CLSB in the capacitor array is Q_ch = V_{re tl} ^■ (C + xC_LSB). In this phase the remaining n-x elementary capacitors in the capacitor array are connected to a second reference voltage, for instance to ground.

In a charge sharing phase the n elementary capacitors of the capacitor array are connected in parallel to the first capacitor (CI) and the second capacitor (C2). Such a configuration allows to generate a constant voltage, which has a linear dependence from the digital input signal. In other words, the generated constant voltage and the digital input signal are linearly dependent.

The above described voltage generator circuit in com bination with a constant current source a nd a threshold comparator implements a DTC based on the constant slope ramp technique. Such architecture based only on capacitors and switches will be very low power and very low noise because no active devices are used and complex architectures, like current steering DACs (high power, high noise and high area occupation) are avoided. The linearity performance is very good as the constant slope ramp technique is used. Furthermore, the current process technology allows a very good matching for the elements of the Capacitive DAC array. Therefore, manufacturing of the above described architecture is easy and cost effective.

Fig. 7a shows a voltage generator circuit 100 according to an embodiment of the invention. The voltage generator circuit comprises a ca pacitor array of n capacitors (each one having a capacitance value equal to CLSB) from a capacitor a rray, such as a digital-to-analog converter (CDAC), a first capacitor (CI), a second capacitor (C2) and a plurality of switching elements (T1-T5). The capacitor array and the first and second capacitors are connected to a main circuit line including a first and a second node N l and N2 and among themselves by the switching elements. The capacitor array of n capacitors (Cn, where is split into a first array of x elementary capacitors (Cx, where CX=X*CLSB) and a second array of n-x elementary capacitors (Cn-x, where Cn- the first array of x capacitors (Cx) being connected to a first terminal (El) a nd the second array of n-x capacitors (Cn-x) being connected to a second terminal (E2). The first capacitor (CI) is connected to a first node (Nl), while the second capacitor (C2) is connected to a second node (N2). Furthermore, the plurality of switching elements (T1-T5) comprises a first, second, third, fourth and fifth switching element (Tl, T2, T3, T4, T5) and is adapted to operate according to a switching sequence comprising a first, second, third and fou rth phase. The splitting of the elementary capacitors in the capacitor array may vary and is set based on the input digital signal. This splitting is schematically represented in figure 7a by the switch T2. A detailed illustration of a possible internal structure of the capacitor array is shown in figure 7b. It should be clear that each elementary capacitor Ci (where Ci is a generic elementary capacitor with the index i in the range [1; 2^m-l]) can be connected to the node Nl by the switch T3i or to the node N2 by the switch T5i. Only one a mong T3i and T5i can be on at the same time. Figure 7b shows the case where x capacitors are connected to node Nl and n-x are connected to node N2.The notation f indicates that the corresponding switch is off. Although the scheme illustrated in figure 7b refers to the

embodiment of figure 7a, it should be clear that the capacitor array and in particular the first and second arrays of elementary capacitors in any of the embodiments of the present invention may be implemented in the same way.

Referring to figure 7a, during the first phase, the first array of x capacitors (Cx) is connected in parallel with the first capacitor (CI) by turning on the third switching element (T3) connected between the first node (N l) and the first terminal (El), and the second array of n-x capacitors (Cn-x) is connected in parallel with the second capacitor (C2) by turning on the fifth switching element (T5) connected between the second node (N2) and the second terminal (E2). Du ring that first phase, the second switching element (T2) connected between the first node (Nl) and the second node (N2) and the fourth switching element (T4) connected between a second reference voltage (Vref2) and the second node (N2) remain turned off, i.e., in a non-conductive state. On the other hand, the first switching element (Tl) can remain either turned off (i.e., in a non-conductive state) or turned on (i.e., in a conductive state). The first switching element (Tl) being connected between a first reference voltage (Vrefl) and the first node (El), the conductive state of the first switching element (Tl) during the first phase allows the first array of x capacitors (Cx) and the first ca pacitor (CI) to be more quickly charged during the second phase. During that second phase following the first phase, a first group of capacitors formed of the first array of x capacitors (Cx) connected in parallel with the first capacitor (CI) and a second group of capacitors formed of the second array of n-x capacitors (Cn-x) connected in parallel with the second capacitor (C2) are separately charged by turning off the second switching element (T2) and turning on the first, third, fourth and fifth switching elements (Tl, T3, T4, T5). The elementary capacitors

Cx+i,..., Cn-i and C2 are charged to a predefined known value, which could be 0 if the reference voltage Vref2 is ground. In general Vref2 could be any value between 0 and VDD but different from Vrefl.

During the third phase following the second phase, the step of charging is interrupted and the first and second groups of capacitors are connected in parallel with each other as to obtain the analog output voltage (Vc) across the second capacitor (C2).

To determine the analog output voltage (Vc) from an exemplary embodiment, we refer to Fig. 8 showing a voltage generator circuit 200 according to a second embodiment of the invention corresponding to another embodiment of the voltage generator circuit 100, wherein the first reference voltage (Vrefl) is connected to a power supply (VDD), the second reference voltage (Vref2) is connected to a ground terminal (GND) and all the capacitors (CI, C2, Cx, Cn-x) are connected to the ground terminal (GND). It should however be understood that the first and second reference voltages (Vrefl, Vref2) can have other analog voltage levels such that the voltage generator circuit 100 can operate in either an analog domain or a digital domain, and some or all of the capacitors (CI, C2, Cx, Cn-x) can be connected to a voltage terminal other than the ground terminal (GND). Moreover, in another exemplary embodiment of the voltage generator circuit 100, the first reference voltage (Vrefl) can be connected to the ground terminal (GND), the second reference voltage (Vref2) can be connected to the power supply (VDD) and the whole capacitors (CI, C2, Cx, Cn-x) can stay connected to the ground terminal (GND). In Fig. 8, during the first phase, x capacitors (Cx) from the CDAC are connected in parallel with the first capacitor (CI) by means of the third switching element (T3) as to form the first group of capacitors and n-x capacitors (Cn-x) from the CDAC are connected in parallel with the second capacitor (C2) by means of the fifth switching element (T5) as to form the second group of capacitors. During the second phase referring to a charging phase, the first group of capacitors is connected to the power supply (VDD) by means of the first switching element (Tl) and the second group of capacitors is connected to the ground terminal (GND) by means of the fourth switching element (T4), such that the charge Q accumulated during that phase satisfies the relation: Q=VDD*(Cl+x*C).

During the third phase referring to a sharing phase, the first and fourth switching elements (Tl, T4) are turned off and the first and second groups of capacitors are connected to each other by means of the second switching element (T2). Thereby, the charge Q is shared on all the capacitors (CI, C2, Cx, Cn-x) such that the following equation is obtained:

[CI + C2 + (n - x) * C_LSB + x * C_LSB] * Vc = VDD * (CI + x * C_LSB) (6) Therefrom the analog output voltage (Vc) can be derived as follows:

_{VD D} ^ C1 *C_{LSB =} VDD * CI ₊ VDD *C_{LSB =}

C1 + C2 + n*C_LSB C1 + C2 + n*C_LSB C1 + C2 + n*C_LSB

Thus, a linear relation between the analog output voltage (Vc) and x corresponding to the digital input code x can be obtained, such that Vc can be denoted as Vc(x).

Fig. 9 shows a digital-to-time converter (DTC) circuit 300 according to a third embodiment of the invention. The DTC circuit 300 comprises the voltage generator circuit 100 according to the first embodiment of the invention, a constant current source (CCS), a comparator and a sixth switching element (T6).

During a fourth phase following the third phase, the second capacitor (C2) is disconnected from the first group of capacitors (CI, Cx) and the n-x capacitors (Cn-x) by turning off the second and fifth switching elements (T2, T5). The constant current source (CCS) linearly charges with a constant current (I), by means of the sixth switching element (T6), the second capacitor (C2) starting from an initial voltage value corresponding to the analog output voltage (Vc) across the second capacitor (C2) obtained during the third phase. The initial voltage value Vc(x) is set according to the digital input code x in order to be lower than the threshold voltage of the comparator. Thereby, a voltage ramp having a positive constant slope and starting from the initial voltage value is generated.

The voltage across the second capacitor (C2) is provided to an input of the comparator, e.g., a CMOS inverter or an analog comparator, such that a time delay (td) is generated as follows:

C2 *(Vth - Vc(x))

td = (8) where td corresponds to the charging time taken by the voltage across the second capacitor to reach a threshold voltage (Vth) of the comparator starting from the initial voltage value (Vc). Thus, the time delay (td) is dependent on the initial voltage value (Vc) and therefore on x corresponding to the digital input code x.

An output edge can then be generated at an output of the comparator as soon as the voltage ramp crosses upwards the threshold value of the comparator.

Fig. 10 shows a digital-to-time converter (DTC) circuit 400 according to a fourth embodiment of the invention. The fourth embodiment differs from the third embodiment in that the constant current source (CCS) is configured to linearly discharge, by means of the sixth switching element (T6), the second capacitor (C2) starting from an initial voltage value corresponding to the analog output voltage (Vc) across the second capacitor (C2) obtained during the third phase. The initial voltage value Vc(x) is set according to the digital input code x in order to be higher than the threshold voltage of the comparator. Thereby, a voltage ramp having a negative constant slope and starting from the initial voltage value is generated.

C2*(Vc(x) - Vth)

td = (9) where td corresponds to the charging time taken by the voltage across the second capacitor to reach a threshold voltage (Vth) of the comparator starting from the initial voltage value (Vc). Thus, the time delay (td) is dependent on the initial voltage value (Vc) and therefore on x corresponding to the digital input code x.

An output edge can then be generated at an output of the comparator as soon as the voltage ramp crosses downwards the threshold value of the comparator.

It should be noted that the first, second, third, fourth, fifth and sixth switching elements (T1-T6) may be respective transistors operating in the switching mode.

It should be further noted that any one of the preceding embodiments of the present invention can be combined in cascade in order to increase a resolution and/or an output delay range. One of the main application fields of the DTC can be related to the fractional frequency generation in digital phase locked loops (DPLLs) and all digital phase locked loops (ADPLLs). The DTC can then be used to generate a delayed copy of a reference clock and controlled with a saw tooth ramp of digital codes in order to generate a delay linearly increasing or decreasing with the time. The phase shift generated by the DTC creates a fractional frequency at the input of a phase detector of the ADPLL. The DTC can also be put on the feed back path to create a linear phase shift on a feed back input of the phase detector.

In summary, the present invention relates to an apparatus and method for generating an analog output voltage (Vc) perfectly linear according to the d igital input code associated with a capacitor array digital-to-analog converter (CDAC). Using such a CDAC, an array of n capacitors, each of which has a capacitance value equal to CLSB, is split into a first array of x capacitors (Cx) and a second array of n-x capacitors (Cn-x). In a first phase, the x a nd n-x capacitors (Cx, Cn-x) are respectively connected in parallel with a first and second capacitor (CI, C2) as to form a respective first and second group of capacitors (Cl+Cx, C2+Cn-x). In a second phase, the first and second groups of capacitors (Cl+Cx, C2+Cn-x) are separately charged . In a third phase, the charged capacitors (CI, C2, Cx, Cn-x) are connected to each other as to obtain the analog output voltage (Vc) across the second capacitor (C2), which varies linearly according to a d igital input code x corresponding to an x-bit digital input. In a fourth phase, the second capacitor (C2) is disconnected apart from the other capacitors (CI, Cx, Cn-x) and charged or discharged by a constant current source (CCS).

While the invention has been illustrated and described in detail in the d rawings and the foregoing description, such illustration and description are to be considered illustrative or exemplary and not restrictive. The invention is not limited to the d isclosed em bodiments. From reading the present disclosure, other mod ifications will be apparent to a person skilled in the art. Such modifications may involve other features which are already known in the art and which may be used instead of or in addition to features already described herein.

The invention has been described in conjunction with various embodiments herein. However, other variations to the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed invention, from a study of the d rawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other elements or steps, and the indefinite article "a" or "an" does not exclude a plurality. A single processor or other unit may fulfill the functions of several items recited in the claims. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage. A computer program may be stored/distributed on a suitable medium, such as an optical storage medium or a solid-state medium supplied together with or as part of other hardware, but may also be distributed in other forms, such as via the Internet or other wired or wireless telecommunication systems.

Although the present invention has been described with reference to specific features and embodiments thereof, it is evident that various modifications and combinations can be made thereto without departing from the spirit and scope of the invention. The specification and drawings are, accordingly, to be regarded simply as an illustration of the invention as defined by the appended claims, and are contemplated to cover any and all modifications, variations, combinations or equivalents that fall within the scope of the present invention.

Claims

1. An apparatus for generating an analog output voltage (Vc) from a digital input signal x, the apparatus comprising:

a first capacitor (CI) connected to a first node (Nl);

a second capacitor (C2) connected to a second node (N2);

a capacitor array of n elementary capacitors from a capacitor array digital-to-analog converter, CDAC, the n elementary capacitors being connectable in parallel to the first capacitor (CI) or to the second capacitor (C2);

wherein

in a charging phase a first array of x elementary capacitors of the capacitor array are connected in parallel to the first capacitor (CI) and a second array of n-x elementary capacitors of the capacitor array is connected in parallel to the second capacitor (C2), x being the digital input signal; and

in a charge sharing phase the n elementary capacitors of the capacitor array are connected in parallel to the first capacitor (CI) and the second capacitor (C2).

2. The apparatus according to claim 1, wherein the first array of x elementary capacitors is

connected to a first terminal (El) and the second array of n-x capacitors is connected to a second terminal (E2);

the apparatus further comprising:

a plurality of switching elements (T1-T5) adapted to operate according to a switching sequence;

wherein the switching sequence comprises:

- during a first phase, connecting the first array of x capacitors in parallel with the first capacitor (CI) through a connection of the first terminal to the first node, and connecting the second array of n-x capacitors in parallel with the second capacitor (C2) through a connection of the second terminal to the second node;

during a second phase following the first phase, separately charging the first array of x capacitors connected in parallel with the first capacitor (CI) and the second array of n-x capacitors connected in parallel with the second capacitor (C2); and

during a third phase following the second phase, interrupting the step of charging and connecting in parallel the first array of x capacitors connected in parallel with the first capacitor (CI) and the second array of n-x capacitors connected in parallel with the second capacitor (C2) as to obtain the analog output voltage (Vc) across the second capacitor (C2).

3. The apparatus of claim 1 or 2, wherein the first array of x ca pacitors connected in parallel with the first capacitor (CI) is charged to a first reference voltage (Vref 1) level during the second phase, and the second array of n-x capacitors connected in parallel with the second capacitor (C2) is charged to a second reference voltage (Vref2) level.

4. The apparatus of claim 2, wherein the plurality of switching elements (T1-T5) comprises: a first switching element (Tl) connected between the first reference voltage (Vrefl) and the first node (N l);

a second switching element (T2) connected between the first node (N l) and the second node (N2);

a third switching element (T3) connected between the first node (N l) and the first terminal (El);

a fourth switching element (T4) connected between the second reference voltage (Vref2) and the second node (N2); and

- a fifth switching element (T5) connected between the second node (N2) and the second

terminal (E2).

5. The apparatus of claim 4, wherein:

during the first phase, the third and fifth switching elements (T3, T5) are in a conductive state and the second and fou rth switching elements (Tl, T2, T4) are in a non-conductive state; during the second phase, the first, third, fourth a nd fifth switching elements (Tl, T3, T4, T5) are in a conductive state and the second switching element (T2) is in a non-cond uctive state; and during the third phase, the second, third and fifth switching elements (T2, T3, T5) are in a conductive state and the first and fou rth switching elements (Tl, T4) are in a non-cond uctive state.

6. The apparatus of claim 2, wherein the plurality of switching elements (T1-T5) comprise respective transistors operating in the switching mode.

7. An apparatus for adjusta bly generating a time delay (td) during a charging phase, the apparatus comprising:

the a pparatus as claimed in any of claims 1 to 6;

a constant current source (CCS) adapted to charge, during a fou rth phase following the third phase, the second capacitor (C2) starting from an initial voltage value corresponding to the analog output voltage (Vc) in order to generate a voltage ramp having a constant slope; and a comparator adapted to input the voltage across the second capacitor (C2) and generate the time delay (td) corresponding to the charging time taken by the voltage across the second capacitor (C2) to reach a threshold voltage (Vth) of the comparator starting from the initial voltage value (Vc).

8. The apparatus of claim 7, wherein the initial voltage value (Vc) is set according to x corresponding to the x-bit digital input in order to be lower than the threshold voltage (Vth) of the comparator.

9. The apparatus of claim 7 or 8, wherein the step of charging the second capacitor (C2) comprises:

disconnecting the second capacitor (C2) from the first capacitor (CI), the first array of x capacitors and the second array of n-x capacitors; and

connecting the second capacitor (C2) to the constant current source (CCS) through a sixth switching element (T6).

10. An apparatus for adjustably generating a time delay (td) during a current discharging phase, the apparatus comprising:

the apparatus as claimed in any one of claims 1 to 6;

- a constant current source (CCS) adapted to discharge, during a fourth phase following the third phase, the second capacitor (C2) starting from an initial voltage value corresponding to the analog output voltage (Vc) in order to generate a voltage ramp having a constant slope; and a comparator adapted to input the voltage across the second capacitor (C2) and generate the time delay (td) corresponding to the discharging time taken by the voltage across the second capacitor (C2) to reach a threshold voltage (Vth) of the comparator starting from the initial voltage value (Vc).

11. The apparatus of claim 10, wherein the initial voltage value (Vc) is set according to x corresponding to the x-bit digital input in order to be higher than the threshold voltage (Vth) of the comparator.

12. The apparatus of claim 10 or 11, wherein the step of current discharging the second capacitor (C2) comprises: disconnecting the second capacitor (C2) from the first capacitor (CI), the first array of x capacitors and the second array of n-x capacitors; and connecting the second capacitor (C2) to the constant current source (CCS) through a sixth switching element (T6).

13. The apparatus of claim 9 or 12, wherein:

during the first, second and third phases, the sixth switching element (T6) is in a non- conductive state; and

during the fourth phase, the sixth switching element (T6) is in a conductive state and the second, fourth and fifth switching elements (T2, T4, T5) are in a non-conductive state.

14. The apparatus of claim 13, wherein the sixth switching element (T6) comprises a transistor operating in the switching mode.

15. The apparatus of claim 7 or 10, wherein the comparator is a CMOS inverter or an analog comparator.

16. A linear digital-to-time converter (DTC) comprising the apparatus as claimed in claim 6 or 9.

17. A method for generating an analog output voltage (Vc) from a digital input signal x, by controlling an apparatus including a first capacitor (CI) connected to a first node (Nl), a second capacitor (C2) connected to a second node (N2) and a capacitor array of n elementary capacitors from a capacitor array digital-to-analog converter, CDAC, the n elementary capacitors being connectable in parallel to the first capacitor (CI) or to the second capacitor (C2);

the method comprising:

in a charging phase connecting a first array of x elementary capacitors of the capacitor array in parallel to the first capacitor (CI) and connecting a second array of n-x elementary capacitors of the capacitor array in parallel to the second capacitor (C2), x being the digital input signal; and

- in a charge sharing phase connecting the n elementary capacitors of the capacitor array in parallel to the first capacitor (CI) and the second capacitor (C2).

18. The method according to claim 17, wherein: the first array of x elementary capacitors is connected to a first terminal (El) and the second array of n-x elementary capacitors of the capacitor array is connected to a second terminal (E2); and

the apparatus further includes a plurality of switching elements (T1-T5) adapted to operate according to a switching sequence,

the method further comprising:

during a first phase of the switching sequence, connecting the first array of x capacitors in parallel with the first capacitor (CI) through a connection of the first terminal to the first node, and connecting the second array of n-x capacitors in parallel with the second capacitor (C2) through a connection of the second terminal to the second node;

during a second phase of the switching sequence following the first phase, separately charging the first array of x capacitors connected in parallel with the first capacitor (CI) and the second array of n-x capacitors connected in parallel with the second capacitor (C2); and

during a third phase of the switching sequence following the second phase, interrupting the step of charging and connecting in parallel the first array of x capacitors connected in parallel with the first capacitor (CI) and the second array of n-x capacitors connected in parallel with the second capacitor (C2) as to obtain a voltage across the second capacitor (C2), the voltage across the second capacitor (C2) being the analog output voltage (Vc).

19. A method for adjustably generating a time delay (td) during a charging phase, the method comprising: applying the steps of the method as claimed in claim 17 or 18; charging, during a fourth phase following the third phase, the second capacitor (C2) starting from an initial voltage value corresponding to the analog output voltage (Vc) in order to generate a voltage ramp having a constant slope; and inputting the voltage across the second capacitor (C2) and generating the time delay (td) corresponding to the current charging time taken by the second capacitor (C2) to reach a threshold voltage (Vth) of the comparator starting from the initial voltage value (Vc), the initial voltage value being set according to x corresponding to the x-bit digital input in order to be lower than the threshold voltage (Vth) of the comparator.

20. The method of claim 19, wherein the step of current charging comprises: disconnecting the second capacitor (C2) from the first capacitor (CI), the first array of x capacitors and the second array of n-x capacitors; and connecting, after the step of disconnecting, the second capacitor (C2) to a constant current source (CCS) through a sixth switching element (T6).

21. A method for adjustably generating a time delay (td) during a current discharging phase, the method comprising: applying the steps of the method as claimed in claim 17 or 18; - current discharging, during a fourth phase following the third phase, the second capacitor (C2) starting from an initial voltage value corresponding to the analog output voltage (Vc) in order to generate a voltage ramp having a constant slope; and inputting the voltage across the second capacitor (C2) and generating the time delay (td) corresponding to the current discharging time taken by the second capacitor (C2) to reach a threshold voltage (Vth) of the comparator starting from the initial voltage value (Vc), the initial voltage value being set according to x corresponding to the x-bit digital input in order to be higher than the threshold voltage (Vth) of the comparator.

22. The method of claim 21, wherein the step of current discharging comprises: - disconnecting the second capacitor (C2) from the first capacitor (CI), the first array of x

capacitors and the second array of n-x capacitors; and connecting, after the step of disconnecting, the second capacitor (C2) to a constant current source (CCS) through a sixth switching element (T6).

23. A computer program comprising a program code for performing the method according to any one of claims 17 to 22 when executed on a computer.