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WO2018142840A1 - Procédé de traitement de substrat, support d'enregistrement informatique et système de traitement de substrat - Google Patents

Procédé de traitement de substrat, support d'enregistrement informatique et système de traitement de substrat Download PDF

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Publication number
WO2018142840A1
WO2018142840A1 PCT/JP2018/000025 JP2018000025W WO2018142840A1 WO 2018142840 A1 WO2018142840 A1 WO 2018142840A1 JP 2018000025 W JP2018000025 W JP 2018000025W WO 2018142840 A1 WO2018142840 A1 WO 2018142840A1
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WO
WIPO (PCT)
Prior art keywords
heat treatment
resist pattern
substrate
substrate temperature
processing
Prior art date
Application number
PCT/JP2018/000025
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English (en)
Japanese (ja)
Inventor
剛 野上
Original Assignee
東京エレクトロン株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 東京エレクトロン株式会社 filed Critical 東京エレクトロン株式会社
Priority to JP2018566001A priority Critical patent/JP6706696B2/ja
Publication of WO2018142840A1 publication Critical patent/WO2018142840A1/fr

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    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/20—Exposure; Apparatus therefor
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/26—Processing photosensitive materials; Apparatus therefor
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/26—Processing photosensitive materials; Apparatus therefor
    • G03F7/38—Treatment before imagewise removal, e.g. prebaking
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34

Definitions

  • the present invention relates to a substrate processing method, a computer storage medium, and a substrate processing system for performing a photolithography process on a substrate and forming a resist pattern on the substrate.
  • a resist coating process is performed on a semiconductor wafer (hereinafter referred to as “wafer”) to form a resist film, and a predetermined pattern is exposed on the resist film.
  • Wafer exposure process post-exposure baking process (hereinafter referred to as “PEB process”) that is heated to promote the chemical reaction of the resist film after exposure, and development process that develops the exposed resist film.
  • PEB process post-exposure baking process
  • the resist pattern determines the pattern shape of the underlying film to be processed, and it is necessary to form the resist pattern uniformly on the wafer surface with strict dimensions.
  • Patent Document 1 a photolithography process using a chemically amplified resist is performed to form a resist pattern on a wafer, and a dimension such as a line width of the resist pattern is measured.
  • the resist pattern dimensions by correcting the heating temperature of the PEB process.
  • the correction of the heating temperature is performed, for example, by correcting the temperature of the hot plate that places and heats the wafer. That is, the hot plate temperature in the stable state of the PEB process is adjusted using a correlation equation between the hot plate temperature and the pattern profile (Zernike coefficient which is a characteristic component).
  • a system for correcting the heating temperature of the PEB process as described above that is, a system for correcting the processing conditions of the processing apparatus, conventionally, for example, the APC ( There is an Advanced Process Control (advanced process control) system.
  • Patent Document 2 proposes process management using an SPC (Statistical Process Control) method for selecting a management target and defining and setting an abnormality determination. Specifically, for example, when an abnormality occurs in the quality characteristic (resist pattern dimension), the processing parameter (PEB processing heating temperature) of the processing apparatus is corrected using a predetermined definition formula.
  • SPC Statistical Process Control
  • Patent Document 3 proposes a method for optimizing a recipe indicating a wafer processing condition (a heating temperature of PEB processing) by performing wafer processing and inspection and repeating trial and check. Specifically, a plurality of candidate recipes are stored in the database unit, and each candidate recipe is sequentially used to process and inspect the wafer. Based on the inspection result, the best recipe is selected from the plurality of candidate recipes. Select. In such a case, the work load on the operator is reduced by automatically repeating the trial and check.
  • a wafer processing condition a heating temperature of PEB processing
  • the present invention has been made in view of such a point, and an object thereof is to uniformly form a resist pattern on a substrate within the substrate surface.
  • one embodiment of the present invention is a substrate processing method for performing a photolithography process on a substrate and forming a resist pattern on the substrate, and a plurality of heat treatment apparatuses for performing a heat treatment in the photolithography process
  • the substrate temperature is measured over time, and a temperature difference calculating step for calculating a difference in substrate temperature between the heat treatment apparatuses and a photolithography process including heat treatment using the plurality of heat treatment apparatuses are performed on the substrate.
  • measure the resist pattern dimension calculate the difference in resist pattern dimension between heat treatment apparatuses, and use the difference in the substrate temperature and the difference in the resist pattern dimension to determine the substrate temperature.
  • model derivation step of deriving the reaction model has a condition setting step of setting the processing conditions of the substrate processing using the reaction model.
  • the reaction rate at the start and end of the heat treatment is zero, the reaction rate is continuous in the time direction, and the product sum of the substrate temperature and the reaction model is the resist pattern dimension.
  • An evaluation function is determined so as to be close to the difference between the above, the optimization problem is solved for the reaction model, and the reaction model is determined.
  • the measurement of the substrate temperature in the temperature difference calculating step and the measurement of the resist pattern dimension in the dimensional difference calculating step are, for example, setup and maintenance of a processing apparatus that performs photolithography processing, or input of a chemical solution such as a resist solution It can be collected when adjusting later processing conditions. That is, normal inspection data can be used for the substrate temperature and resist pattern dimensions.
  • the model deriving step it is possible to automatically model a function of time with respect to the reaction rate, that is, a pattern latent image forming process every moment in the heat treatment step, using the temperature difference and the dimensional difference.
  • irregular operations different from normal operations such as special data collection and correlation formulation are almost unnecessary.
  • the substrate processing conditions can be set using the reaction model in the condition setting step.
  • a heat treatment recipe hot plate temperature
  • a substrate processing path is selected so that a good resist pattern dimension can be obtained. It can be carried out.
  • the resist pattern can be uniformly formed on the substrate surface on the substrate while reducing machine differences between the processing apparatuses.
  • the throughput of the substrate processing can be improved and the productivity can be improved.
  • a readable computer storage medium storing a program that operates on a computer of a control unit that controls the substrate processing system so that the substrate processing method is executed by the substrate processing system. It is.
  • a substrate processing system that performs a photolithography process on a substrate and forms a resist pattern on the substrate, and includes a plurality of heat treatment apparatuses that perform heat treatment on the substrate, A dimension measuring device for measuring a resist pattern dimension, and a control unit for setting processing conditions for substrate processing, wherein the control unit measures the substrate temperature over time in the plurality of heat treatment apparatuses, A temperature difference calculating step for calculating a difference in substrate temperature in the substrate, and performing a photolithography process on the substrate using the plurality of heat treatment apparatuses, forming a resist pattern on the substrate, and then measuring a resist pattern dimension in the dimension measuring apparatus Dimensional difference calculating step for calculating a difference in resist pattern dimension between heat treatment apparatuses, difference in substrate temperature, and resist A model derivation step for calculating a reaction rate for converting the substrate temperature into a resist pattern size using the difference in turn size, and deriving a reaction model that is a function of time for the reaction rate, and using the
  • the reaction rate at the start and end of the heat treatment is zero, the reaction rate is continuous in the time direction, and the product sum of the substrate temperature and the reaction model is the resist pattern dimension.
  • An evaluation function is determined so as to be close to the difference between the above, the optimization problem is solved for the reaction model, and the reaction model is determined.
  • the present invention it is possible to uniformly form a resist pattern on a substrate on a substrate while reducing machine differences between processing apparatuses.
  • the throughput of substrate processing can be improved and productivity can be improved.
  • FIG. 1 is a plan view schematically showing the outline of the configuration of the substrate processing system 1.
  • 2 and 3 are a front view and a rear view, respectively, schematically showing the outline of the internal configuration of the substrate processing system 1.
  • the substrate processing system 1 is a coating and developing processing system that performs photolithography processing on a wafer W as a substrate will be described as an example.
  • the substrate processing system 1 includes a cassette station 10 in which a cassette C containing a plurality of wafers W is loaded and unloaded, and a processing station 11 having a plurality of various processing apparatuses for performing predetermined processing on the wafers W. And an interface station 13 that transfers the wafer W to and from the exposure apparatus 12 adjacent to the processing station 11 is integrally connected.
  • the cassette station 10 is provided with a cassette mounting table 20.
  • the cassette mounting table 20 is provided with a plurality of cassette mounting plates 21 on which the cassette C is mounted when the cassette C is carried into and out of the substrate processing system 1.
  • the cassette station 10 is provided with a wafer transfer device 23 that is movable on a transfer path 22 extending in the X direction as shown in FIG.
  • the wafer transfer device 23 is also movable in the vertical direction and the vertical axis direction ( ⁇ direction), and includes a cassette C on each cassette mounting plate 21 and a delivery device for a third block G3 of the processing station 11 described later.
  • the wafer W can be transferred between the two.
  • the processing station 11 is provided with a plurality of, for example, four blocks including various devices, that is, a first block G1 to a fourth block G4.
  • the first block G1 is provided on the front side of the processing station 11 (X direction negative direction side in FIG. 1), and on the back side of the processing station 11 (X direction positive direction side in FIG. 1, upper side in the drawing). Is provided with a second block G2.
  • the third block G3 described above is provided on the cassette station 10 side (the Y direction negative direction side in FIG. 1) of the processing station 11, and the interface station 13 side (the Y direction positive side in FIG. 1) of the processing station 11 is provided.
  • a fourth block G4 is provided on the direction side.
  • a plurality of liquid processing apparatuses for example, a development processing apparatus 30 for developing the wafer W, an antireflection film (hereinafter referred to as “lower reflection” below the resist film of the wafer W).
  • a lower anti-reflection film forming apparatus 31 for forming an anti-reflection film a resist coating apparatus 32 for applying a resist solution to the wafer W to form a resist film, and an anti-reflection film (hereinafter referred to as an anti-reflection film) on the resist film of the wafer W.
  • An upper antireflection film forming apparatus 33 for forming “an upper antireflection film”) is arranged in this order from the bottom.
  • the development processing device 30, the lower antireflection film forming device 31, the resist coating device 32, and the upper antireflection film forming device 33 are arranged side by side in the horizontal direction.
  • the number and arrangement of the development processing device 30, the lower antireflection film forming device 31, the resist coating device 32, and the upper antireflection film forming device 33 can be arbitrarily selected.
  • the lower antireflection film forming device 31 for example, spin coating for applying a predetermined processing solution onto the wafer W is performed.
  • spin coating for example, the processing liquid is discharged onto the wafer W from an application nozzle, and the wafer W is rotated to diffuse the processing liquid to the surface of the wafer W.
  • heat treatment apparatuses 40 to 43 for performing heat treatment such as heating and cooling of the wafer W, and hydrophobic treatment for improving the fixability between the resist solution and the wafer W are performed.
  • a hydrophobic processing device 44 and a peripheral exposure device 45 for exposing the outer peripheral portion of the wafer W are provided side by side in the vertical direction and the horizontal direction.
  • the number and arrangement of the heat treatment apparatuses 40 to 43, the hydrophobic treatment apparatus 44, and the peripheral exposure apparatus 45 can be arbitrarily selected.
  • the heat treatment apparatus 40 performs a pre-baking process (hereinafter referred to as “PAB process”) in which the wafer W after the resist coating process is heated, and may be referred to as a PAB apparatus 40 hereinafter.
  • the heat treatment apparatus 41 performs a post-exposure baking process (hereinafter referred to as “PEB process”) that heat-treats the wafer W after the exposure process, and may be referred to as a PEB apparatus 41 hereinafter.
  • the heat treatment apparatus 42 performs a post-baking process (hereinafter referred to as “POST process”) in which the wafer W after the development process is heated, and may be referred to as a POST apparatus 42 hereinafter.
  • the heat treatment apparatus 43 is an apparatus that performs other heat treatment. The configuration of these heat treatment apparatuses 40 to 43 will be described later.
  • a plurality of delivery devices 50, 51, 52, 53, 54, 55, 56 are provided in order from the bottom.
  • the fourth block G4 is provided with a plurality of delivery devices 60, 61, 62 in order from the bottom.
  • a wafer transfer area D is formed in an area surrounded by the first block G1 to the fourth block G4.
  • a plurality of wafer transfer devices 70 having transfer arms 70a that are movable in the Y direction, the X direction, the ⁇ direction, and the vertical direction are arranged.
  • the wafer transfer device 70 moves in the wafer transfer area D and transfers the wafer W to a predetermined device in the surrounding first block G1, second block G2, third block G3, and fourth block G4. it can.
  • the wafer transfer area D is provided with a shuttle transfer device 80 that transfers the wafer W linearly between the third block G3 and the fourth block G4.
  • the shuttle transport device 80 is linearly movable, for example, in the Y direction in FIG.
  • the shuttle transfer device 80 moves in the Y direction while supporting the wafer W, and can transfer the wafer W between the transfer device 52 of the third block G3 and the transfer device 62 of the fourth block G4.
  • a wafer transfer device 90 is provided next to the third block G3 on the positive side in the X direction.
  • the wafer transfer device 90 includes a transfer arm 90a that can move in the X direction, the ⁇ direction, and the vertical direction, for example.
  • the wafer transfer device 90 moves up and down while supporting the wafer W, and can transfer the wafer W to each delivery device in the third block G3.
  • the interface station 13 is provided with a wafer transfer device 100 and a delivery device 101.
  • the wafer transfer apparatus 100 includes a transfer arm 100a that is movable in the Y direction, the ⁇ direction, and the vertical direction, for example.
  • the wafer transfer apparatus 100 can support the wafer W on the transfer arm 100a and transfer the wafer W between the transfer apparatuses, the transfer apparatus 101, and the exposure apparatus 12 in the fourth block G4.
  • the control unit 200 is a computer, for example, and has a program storage unit (not shown).
  • the program storage unit stores a program for controlling the processing of the wafer W in the substrate processing system 1.
  • the program is recorded on a computer-readable storage medium such as a computer-readable hard disk (HD), flexible disk (FD), compact disk (CD), magnetic optical desk (MO), or memory card. Or installed in the control unit 200 from the storage medium.
  • a computer-readable storage medium such as a computer-readable hard disk (HD), flexible disk (FD), compact disk (CD), magnetic optical desk (MO), or memory card.
  • a dimension measuring device 210 that measures the dimension of a resist pattern formed on the wafer W in the substrate processing system 1 is provided outside the substrate processing system 1.
  • the dimension measuring apparatus 210 measures a resist pattern dimension using, for example, a scatterometry method. Specifically, for example, the wafer W is irradiated with light from an oblique direction, and the light reflected by the wafer W is detected. The light intensity distribution in the wafer surface obtained from the detected light is collated with a virtual light intensity distribution stored in advance, and a resist pattern dimension corresponding to the collated virtual light intensity distribution is obtained. In the present embodiment, for example, the line width of the resist pattern is measured as the resist pattern dimension.
  • the dimension measuring device 210 may be provided inside the substrate processing system 1. In such a case, the dimension measuring apparatus 210 is disposed at an arbitrary position inside the substrate processing system 1. For example, an inspection station (not shown) may be provided between the cassette station 10 and the processing station 11, and the dimension measuring device 210 may be disposed in this inspection station.
  • a cassette C containing a plurality of wafers W is loaded into the cassette station 10 of the substrate processing system 1 and placed on the cassette placing plate 21. Thereafter, the wafers W in the cassette C are sequentially taken out by the wafer transfer device 23 and transferred to the transfer device 53 of the third block G3 of the processing station 11.
  • the wafer W is transferred to the heat treatment apparatus 40 of the second block G2 by the wafer transfer apparatus 70 and subjected to temperature adjustment processing. Thereafter, the wafer W is transferred to, for example, the lower antireflection film forming device 31 of the first block G1 by the wafer transfer device 70, and a lower antireflection film is formed on the wafer W. Thereafter, the wafer W is transferred to the heat treatment apparatus 40 of the second block G2, and heat treatment is performed. Thereafter, the wafer W is returned to the delivery device 53 of the third block G3.
  • the wafer W is transferred by the wafer transfer device 90 to the delivery device 54 of the same third block G3. Thereafter, the wafer W is transferred by the wafer transfer apparatus 70 to the hydrophobizing apparatus 44 of the second block G2, and subjected to the hydrophobizing process.
  • the wafer W is transferred to the resist coating device 32 by the wafer transfer device 70, and a resist solution is applied onto the wafer W to form a resist film. Thereafter, the wafer W is transferred to the PAB apparatus 40 by the wafer transfer apparatus 70 and subjected to PAB processing. Thereafter, the wafer W is transferred by the wafer transfer device 70 to the transfer device 55 of the third block G3.
  • the wafer W is transferred to the upper antireflection film forming apparatus 33 by the wafer transfer apparatus 70, and an upper antireflection film is formed on the wafer W. Thereafter, the wafer W is transferred to the heat treatment apparatus 43 by the wafer transfer apparatus 70, heated, and the temperature is adjusted. Thereafter, the wafer W is transferred to the peripheral exposure device 45 and subjected to peripheral exposure processing.
  • the wafer W is transferred by the wafer transfer device 70 to the delivery device 56 of the third block G3.
  • the wafer W is transferred to the transfer device 52 by the wafer transfer device 90 and transferred to the transfer device 62 of the fourth block G4 by the shuttle transfer device 80. Thereafter, the wafer W is transferred to the exposure apparatus 12 by the wafer transfer apparatus 100 of the interface station 13 and subjected to exposure processing in a predetermined pattern.
  • the wafer W is transferred by the wafer transfer apparatus 100 to the delivery apparatus 60 of the fourth block G4. Thereafter, the wafer W is transferred to the PEB apparatus 41 by the wafer transfer apparatus 70 and subjected to PEB processing.
  • the wafer W is transferred to the development processing apparatus 30 by the wafer transfer apparatus 70 and developed.
  • the wafer W is transferred to the POST apparatus 42 by the wafer transfer apparatus 90 and subjected to the POST process.
  • the wafer W is transferred to the delivery device 50 of the third block G3 by the wafer transfer device 70, and then transferred to the cassette C of the predetermined cassette mounting plate 21 by the wafer transfer device 23 of the cassette station 10.
  • a series of photolithography steps is completed.
  • FIG. 4 is a longitudinal sectional view schematically showing an outline of the configuration of the PEB device 41.
  • FIG. 5 is a plan view schematically showing the outline of the configuration of the PEB apparatus 41.
  • the PEB apparatus 41 has a processing container 300 that can be closed inside.
  • a loading / unloading port (not shown) for the wafer W is formed on the side surface of the processing container 300 on the wafer transfer region D side, and an opening / closing shutter (not shown) is provided at the loading / unloading port.
  • a heating unit 310 that heat-processes the wafer W and a cooling unit 311 that cools the wafer W and adjusts the temperature are provided.
  • the heating unit 310 and the cooling unit 311 are arranged side by side in the Y direction.
  • the heating unit 310 includes a lid 320 that is located on the upper side and can be moved up and down, and a hot plate housing portion 321 that is located on the lower side and forms the processing chamber R integrally with the lid 320.
  • the lid 320 has a substantially cylindrical shape with an open bottom surface.
  • An exhaust part 320 a is provided at the center of the upper surface of the lid 320.
  • the atmosphere in the processing chamber R is uniformly exhausted from the exhaust unit 320a.
  • the hot plate accommodating portion 321 includes an annular holding member 331 that accommodates the hot plate 330 and holds the outer peripheral portion of the hot plate 330, and a substantially cylindrical support ring 332 that surrounds the outer periphery of the holding member 331.
  • the hot plate 330 has a thick and substantially disk shape, and can place and heat the wafer W thereon.
  • the heating plate 330 incorporates a heater 333 that generates heat by power supply, for example.
  • the heating temperature of the hot plate 330 is controlled by the control unit 200, for example, and the wafer W placed on the hot plate 330 is heated to a predetermined temperature.
  • the hot plate 330 is provided with temperature sensors 334 to 338 for measuring the temperature of the wafer W placed on the hot plate 330.
  • the temperature sensor 334 is arranged at the center of the hot plate 330, and the temperature sensors 335 to 338 are arranged on the concentric circles of the hot plate 330 at equal intervals (90 degree intervals).
  • the temperature sensor 334 measures the temperature at the measurement point k1 in the center portion of the wafer W, and the temperature sensors 335 to 338 measure the temperatures at the measurement points k2 to k5 in the outer peripheral portion of the wafer W, respectively.
  • positioning and the number of the temperature sensors (measurement point of the wafer W) of the hot plate 330 are not limited to this embodiment, and can be set arbitrarily.
  • three elevating pins 340 for supporting the wafer W from below and elevating it are provided below the hot plate 330.
  • the elevating pin 340 can be moved up and down by the elevating drive unit 341. Near the central portion of the hot plate 330, through holes 342 that penetrate the hot plate 330 in the thickness direction are formed, for example, at three locations.
  • the elevating pins 340 are inserted through the through holes 342 and can protrude from the upper surface of the heat plate 330.
  • the cooling unit 311 has a cooling plate 350.
  • the cooling plate 350 has a substantially square flat plate shape, and the end surface on the heat plate 330 side is curved in an arc shape.
  • two slits 351 are formed along the Y direction.
  • the slit 351 is formed from the end surface of the cooling plate 350 on the hot plate 330 side to the vicinity of the central portion of the cooling plate 350.
  • the slit 351 can prevent the cooling plate 350 from interfering with the lifting pins 340 of the heating unit 310 and the lifting pins 360 of the cooling unit 311 described later.
  • the cooling plate 350 includes a cooling member (not shown) such as cooling water or a Peltier element.
  • the cooling temperature of the cooling plate 350 is controlled by the control unit 200, for example, and the wafer W placed on the cooling plate 350 is cooled to a predetermined temperature.
  • the cooling plate 350 is supported by the support arm 352.
  • a drive unit 353 is attached to the support arm 352.
  • the drive unit 353 is attached to a rail 354 extending in the Y direction.
  • the rail 354 extends from the cooling unit 311 to the heating unit 310. With this driving unit 353, the cooling plate 350 can move between the heating unit 310 and the cooling unit 311 along the rail 354.
  • elevating pins 360 for supporting the wafer W from below and elevating it are provided below the cooling plate 350.
  • the elevating pin 360 can be moved up and down by an elevating drive unit 361.
  • the elevating pins 360 are inserted through the slits 351 and can protrude from the upper surface of the cooling plate 350.
  • the wafer W is transferred from the wafer transfer device 70 to the lift pins 360 that have been lifted and waited in advance. Subsequently, the lift pins 360 are lowered, and the wafer W is placed on the cooling plate 350.
  • the driving unit 353 moves the cooling plate 350 along the rail 354 to the upper side of the hot plate 330, and the wafer W is transferred to the lift pins 340 that have been lifted and waited in advance. Thereafter, after the lid 320 is closed, the elevating pins 340 are lowered and the wafer W is placed on the hot plate 330. Then, the wafer W on the hot plate 330 is heated to a predetermined temperature.
  • the elevating pins 340 are raised, and the cooling plate 350 is moved above the hot plate 330. Subsequently, the wafer W is transferred from the lift pins 340 to the cooling plate 350, and the cooling plate 350 moves to the loading / unloading side. During the movement of the cooling plate 350, the wafer W is cooled to a predetermined temperature.
  • the present inventor has high operational sensitivity with respect to the chemically amplified resist in order to form a resist pattern uniformly on the wafer W on the wafer W while reducing machine differences between the processing apparatuses in the substrate processing system 1. Focusing on the PEB treatment, modeling was performed to clarify the reaction mechanism of the PEB treatment. Specifically, in PEB processing, the correlation between the wafer temperature and the resist pattern dimension that changes over time was modeled.
  • reaction model the progress of the reaction during the PEB process can be estimated, and information obtained from the reaction model can be fed back to the wafer process. Further, by using this reaction model, it is possible to separate the influence of PEB processing and other processes (resist coating processing, PAB processing, exposure processing, development processing, etc.) on the resist pattern dimensions. Then, it becomes possible to optimize wafer processing.
  • reaction model uses a wafer temperature in PEB processing and a resist pattern dimension obtained by performing photolithography processing.
  • the PEB apparatus 41 is provided with temperature sensors 334 to 338 for measuring the temperature of the wafer W placed on the hot platen 330.
  • the temperature profile of the hot plate 330 is adjusted by measuring the temperatures of the measurement points k1 to k5 of the wafer W using these temperature sensors 334 to 338.
  • the substrate processing system 1 is provided with a plurality of PEB apparatuses 41, and the wafer temperature is acquired for each PEB apparatus 41.
  • FIG. 7 is a graph showing the change over time of the wafer temperature in the PEB process acquired as described above for each of the measurement points k1 to k5.
  • the horizontal axis in FIG. 7 indicates time t, and the horizontal axis indicates the wafer temperature ⁇ [k, t].
  • k is the number of the measurement point of the wafer W.
  • the hot plate temperature profile is adjusted so that the wafer temperature ⁇ [k, t] shown in FIG. 7 falls within a preset allowable range.
  • the wafer temperature ⁇ [k, t] acquired at this time is recorded in association with each PEB apparatus 41 in which the hot plate temperature profile is adjusted.
  • the wafer temperature ⁇ [k, t] for each PEB apparatus 41 is used for deriving the reaction model.
  • the processing of each processing apparatus in the substrate processing system 1 is subsequently performed. Conditions (processing recipes and parameters) are adjusted. Then, after a series of photolithography processes are performed in the substrate processing system 1 to form a resist pattern on the wafer W, the dimension of the resist pattern is measured by the dimension measuring device 210 to confirm the finish of the resist pattern.
  • the substrate processing system 1 is provided with a plurality of types of processing apparatuses, for example, a plurality of PAB apparatuses 40 and a plurality of PEB apparatuses 41 are provided.
  • a processing step in the photolithography process is performed by selecting one processing apparatus from a plurality of processing apparatuses.
  • the path of the processing apparatus through which the wafer W passes when performing each processing step is referred to as a “processing path”. Then, a resist pattern dimension is acquired for each processing path.
  • the resist pattern dimensions are acquired for each shot in the exposure process. If there is a shot that coincides with the measurement points k1 to k5 of the wafer W, the resist pattern dimension l [k] in that shot is extracted. If there is no shot that coincides with the measurement points k1 to k5 on the wafer W, for example, the resist pattern dimension in the shot nearest to the measurement points k1 to k5 is substituted, or the shots around the measurement points k1 to k5 are used. The resist pattern dimension is calculated by appropriate two-dimensional interpolation. Then, the resist pattern dimension l [k] corresponding to the measurement points k1 to k5 of the wafer W is acquired.
  • the resist pattern dimension l [k] acquired in this way is recorded in association with each processing path. These resist pattern dimensions l [k] are used to derive a reaction model.
  • the wafer temperature ⁇ [k, t] and the resist pattern dimension l [k] are acquired when setting up or maintaining the PEB apparatus 41 or when processing conditions after adding a chemical solution such as a resist solution are acquired. be able to. That is, inspection data acquired at normal time is used for the wafer temperature ⁇ [k, t] and the resist pattern dimension l [k]. For this reason, in order to derive a reaction model, there is almost no need for irregular operations that are different from normal operations such as special data collection and correlation formulation.
  • the substrate processing system 1 is provided with a plurality of various processing apparatuses for performing a photolithography process.
  • two first PAB apparatuses 40 (A1) and a second PAB apparatus 40 (A2) are used as processing paths.
  • Combination of two first PEB devices 41 (E1) and second PEB devices 41 (E2), two first development processing devices 30 (D1) and second development processing devices 30 (D2), and others The processing path which made these processing apparatuses common is illustrated.
  • the wafer temperature ⁇ [k, t] of the second PEB device 41 (E2) is subtracted from the wafer temperature ⁇ [k, t] of the first PEB device 41 (E1) to obtain a PEB device.
  • a wafer temperature difference ⁇ [k, t] between 41 is calculated.
  • the resist pattern dimension l [k] shown in FIG. 9 is averaged for each group of the first PEB device 41 (E1) and the second PEB device 41 (E2). Thereafter, as shown in FIG. 10, the average resist pattern dimension l [k] of the second PEB apparatus 41 (E2) is subtracted from the average resist pattern dimension l [k] of the first PEB apparatus 41 (E1) to obtain a PEB apparatus. A resist pattern dimension difference ⁇ l [k] between 41 is calculated.
  • the wafer temperature difference ⁇ [k, t] and the resist pattern dimension difference ⁇ l [k] may be collectively referred to as “difference data”.
  • the processing paths shown in FIGS. 9 and 10 are examples, and the selection of the processing path can be arbitrarily performed.
  • there are two PEB devices 41 and there is one difference data between the PEB devices 41.
  • there are three PEB devices 41 there are three difference data.
  • the difference data is six.
  • the number of difference data is the number of combinations of PEB devices 41.
  • the number of the difference data is i.
  • the reaction model c [t] is derived from the wafer temperature difference ⁇ [k, t] and the resist pattern dimension difference ⁇ l [k].
  • This reaction model c [t] is a weighting factor in the time direction for the wafer temperature difference ⁇ [k, t]. Specifically, the product sum of the reaction model c [t] and the wafer temperature difference ⁇ [k, t], that is, the product of the reaction model c [t] and the wafer temperature difference ⁇ [k, t] is integrated at the time t. If c [t] is determined so that the value is close to the resist pattern dimension difference ⁇ l [k], the c [t] becomes a reaction model.
  • reaction model c [t] is the information itself of the latent image formation speed (hereinafter referred to as “reaction speed”) of the resist pattern that changes with time during the PEB process.
  • reaction speed the latent image formation speed
  • c [t] may be referred to as a reaction model and may be referred to as a reaction rate, but both have the same meaning.
  • T is the PEB processing time including heating and cooling.
  • the reaction rate c [t] is continuous in the time direction, and as described above, the product sum of the reaction model c [t] and the wafer temperature difference ⁇ [k, t] becomes the resist pattern dimension difference ⁇ l [k].
  • the reaction model c [t] is determined so as to be close.
  • the optimization problem is solved so that the evaluation function represented by the following formula (1) approaches zero, and the reaction model c [t] is determined. That is, when several patterns of reaction models c [t] are prepared, the constraint condition is satisfied, and optimization calculation is performed where the evaluation function of the following formula (1) approaches zero, one reaction model c [t] is obtained. To be determined.
  • F evaluation function
  • C [t] reaction model
  • ⁇ [t, k] wafer temperature difference
  • ⁇ l [k] resist pattern dimension difference
  • t PEB processing elapsed time with zero PEB processing start.
  • T time at the end of PEB processing
  • k number of measurement points of wafer temperature (number of measurement points of resist pattern dimension)
  • K total number of measurement points of wafer temperature (total number of measurement points of resist pattern dimension)
  • i Total number of difference data acquired from a plurality of PEB apparatuses (total number of differences in wafer temperature, total number of differences in resist pattern dimensions)
  • the first term on the right side of the above formula (1) indicates a condition that the reaction rate c [t] is continuous in the time direction. This is the sum of squares of the change amount of c [t] in one data acquisition interval (sampling time interval), and a small value indicates that the time change of c [t] is smooth.
  • the second term on the right side of the above equation (1) indicates a condition that the product sum of the reaction model c [t] and the wafer temperature difference ⁇ [k, t] is close to the resist pattern dimension difference ⁇ l [k]. If the sum of products ⁇ c [t] ⁇ ⁇ [k, t] and ⁇ l [k] is small and the value is small, the resist pattern dimension component (hereinafter referred to as “ This indicates that the accuracy of predicting “PEB component” is high.
  • the sensitivity information ⁇ is calculated. It may be added to the evaluation function.
  • the sensitivity information ⁇ is information indicating how much the resist pattern dimension changes when the wafer temperature changes by 1 ° C.
  • the third term on the right side of the above equation (2) is the sum of squares of the deviation between the actual sensitivity information ⁇ and the sensitivity estimated from the reaction model c [t], that is, the time integral value of the reaction model c [t].
  • the condition that the time integral value of the reaction model c [t] is close to the sensitivity information ⁇ is shown.
  • the reaction model c [t] shown in FIG. 11 can be automatically derived using the evaluation function of the above formula (1) or formula (2).
  • the horizontal axis indicates time t
  • the vertical axis indicates the reaction model c [t]. Since the reaction mechanism of PEB processing is automatically modeled in this way, it is not necessary to take time and labor as in the prior art, and the throughput of wafer processing can be improved and productivity can be improved.
  • reaction model c [t] is uniquely determined for the type of resist. Therefore, the reaction model c [t] is a model common to the plurality of PEB apparatuses 41.
  • reaction model c [t] for PEB processing.
  • the reaction model c [t] is close to zero, it means that the reaction rate is close to zero.
  • a time zone in which the latent image formation speed of the resist pattern is slow in PEB processing indicates that the chemical reaction is not progressing, and is not so meaningful from the viewpoint of the PEB processing.
  • the time when the reaction rate is zero in the cooling process after heating is a wasteful process time, and there is no problem even if it is positively excluded from the PEB treatment.
  • a time zone tc in which the reaction model c [t] is almost zero is cut.
  • the cooling time of the wafer W is specified in the heat treatment conditions (recipe setting, etc.) of the PEB process
  • the time zone tc is cut from the cooling time. If it does so, the processing time of the whole PEB process can be shortened, the throughput of a wafer process can be improved, and productivity can be improved.
  • an in-plane average is calculated for the wafer temperature ⁇ [k, t] recorded for each PEB apparatus 41.
  • the in-plane average wafer temperature in the p PEB apparatus 41 is represented by ⁇ p mean [t]. That is, the in-plane average wafer temperature in the first PEB apparatus 41 (E1) is ⁇ 1 mean [t], and the in-plane average wafer temperature in the second PEB apparatus 41 (E2) is ⁇ 2 mean [t].
  • the product sum of the reaction model c [t] and the wafer temperature ⁇ [k, t] recorded for each PEB apparatus 41 that is, the reaction model c [t] and the wafer temperature difference ⁇ [k, t ] Is integrated over time t.
  • This sum of products is estimated as a dimensional component (hereinafter referred to as “PEB component”) l ′ [k] of the resist pattern formed due to the PEB process out of the resist pattern size l [k].
  • PEB component in the p PEB apparatus 41 is assumed to be l'p [k]. That is, the PEB component in the first PEB device 41 (E1) is l'1 [k], and the PEB component in the second PEB device 41 (E2) is l'2 [k].
  • the in-plane average PEB component in the p PEB apparatus 41 is defined as l′ p mean . That is, the in-plane average PEB component in the first PEB device 41 (E1) is l′ 1 mean , and the in-plane average PEB component in the second PEB device 41 (E2) is l′ 2 mean .
  • the machine difference can be canceled by using the in-plane average wafer temperature ⁇ p mean [t], the in-plane average PEB component l′ p mean and the reaction model c [t]. It is possible to derive the operation amount of the wafer temperature necessary for the above.
  • the wafer temperature operation magnification obtained by the following equation (3) is used.
  • G wafer temperature operation magnification
  • l′ 1 mean : in-plane average PEB component in the first PEB apparatus 41 (E1)
  • l′ 2 mean : in-plane average PEB component in the second PEB apparatus 41
  • C [ t] Reaction model
  • ⁇ 1 mean [t]: In-plane average wafer temperature in the first PEB apparatus 41 (E1)
  • t PEB processing elapsed time with zero PEB processing start
  • T PEB processing end time time
  • the operation amount ⁇ 1 mean of the wafer temperature in the first PEB apparatus 41 (E1) is calculated by the following equation (6).
  • the machine difference between the PEB apparatuses 41 can be canceled, and the in-plane average wafer temperature ⁇ 1 mean [t] in the first PEB apparatus (E1) is changed to the in-plane average in the second PEB apparatus 41 (E2). It can approach the average wafer temperature ⁇ 2 mean [t].
  • ⁇ 1 mean Manipulation amount of wafer temperature in the first PEB apparatus 41 (E1)
  • ⁇ 1 mean [t] In-plane average wafer temperature in the first PEB apparatus 41 (E1)
  • ⁇ b Heating temperature of PEB
  • G Wafer temperature operation magnification
  • the correlation between the operation amount of the hot plate temperature in the PEB apparatus 41 and the change amount of the wafer temperature is obtained in advance.
  • the wafer temperature operation amount ⁇ 1 mean in the first PEB apparatus 41 (E1) obtained using the wafer temperature operation magnification of the above equation (3) is The temperature of the hot plate 330 is set in terms of the hot plate temperature manipulated variable.
  • the temperature of the hot plate 330 in the first PEB device 41 (E1) can be set without using an operator. Then, using the difference between the in-plane average PEB components l′ 1 mean and l′ 2 mean , the machine difference between the PEB apparatuses 41 can be canceled, and the resist pattern can be formed uniformly in the wafer plane. .
  • the first PEB device 41 (E1) with respect to the second PEB device 41 (E2) is obtained by using the difference between the in-plane average PEB components l′ 1 mean and l′ 2 mean in the equation (3).
  • the average value of the in-plane average PEB components l′ 1 mean and l′ 2 mean may be used.
  • the wafer temperature operation magnification G is calculated using the following equation (4), and the wafer temperature operation amount ⁇ 1 mean in the first PEB apparatus 41 (E1) is calculated using the above equation (6). . Further, the wafer temperature operation magnification G is calculated using the following equation (5), and the operation amount ⁇ 2 mean of the wafer temperature in the second PEB apparatus 41 (E2) is calculated using the equation corresponding to the above equation (6). To do.
  • the machine difference between the PEB apparatuses 41 can be canceled without an operator, and the resist pattern can be formed uniformly on the wafer surface.
  • the resist pattern dimension l [k] for all the processing paths can be measured. Is not limited. For example, as shown in FIG. 15, when the resist pattern dimension l [k] of the processing path passing through the second PAB apparatus (A2) is not acquired in the first PEB apparatus 41 (E1), In some cases, the resist pattern dimension l [k] of the processing path passing through the first PAB apparatus (A1) is not acquired in the PEB apparatus 41 (E2). In this embodiment, the resist pattern dimension l [k] of such a processing path is estimated, and an optimal processing path is selected.
  • the PEB component l′ 1 [k] in the first PEB device 41 (E1) and the PEB component l′ 2 [k] in the second PEB device 41 (E2) are calculated. . Since the calculation method of these PEB components l′ 1 [k] and l′ 2 [k] is the same as the calculation method for the second usage method, detailed description thereof is omitted.
  • the PEB component l′ 1 [k] is subtracted from the resist pattern dimension l [k] in the first PEB apparatus 41 (E1). Then, processing other than the first PEB device 41 (E1), that is, a resist pattern dimension component (hereinafter referred to as other processing component) l ′′ 1 [k] caused by the first PAB device 40 (A1). Is estimated.
  • other processing component a resist pattern dimension component (hereinafter referred to as other processing component) l ′′ 1 [k] caused by the first PAB device 40 (A1).
  • the first PEB device 41 (E1) and the second PAB device 40 (E2) are added.
  • the resist pattern dimensions of all the processing paths are obtained for the first PEB apparatus 41 (E1) as shown in FIG.
  • the second PAB device 40 is compared to the first PEB device 41 (E1).
  • A2) and the first development processing apparatus 30 (D1) are selected.
  • the second PEB device 41 (E2) and the first PAB device 40 (E1 are added as shown in FIG. 17, the second PEB device 41 (E2) and the first PAB device 40 (E1 Then, the resist pattern dimensions of all the processing paths are obtained for the second PEB apparatus 42 (E2) as shown in FIG.
  • the first PAB apparatus can be selected with respect to the second PEB apparatus 41 (E2). 40 (A1) and the second development processing apparatus 30 (D2) are selected.
  • the resist pattern dimension l [k] of all the processing paths can be estimated. Accordingly, since the optimum processing path can be selected from as many processing paths as possible, the in-plane uniformity of the resist pattern can be improved.
  • the average temperature of the hot plate 330 in the PEB apparatus 41 is adjusted to make the resist pattern uniform in the surface.
  • the hot plate 330 may be partitioned into a plurality of regions, the above embodiment may be performed for each region, and the temperature may be adjusted for each region.
  • the second usage method of the reaction model c [t] described above will be described using specific data.
  • the data shown in the present embodiment is virtual data.
  • reaction model c [t] is derived in advance.
  • the wafer temperature ⁇ 1 [k, t] in the first PEB apparatus is acquired.
  • ⁇ 1 mean [t] is calculated as the in-plane average wafer temperature from the wafer temperature ⁇ 1 [k, t]
  • ⁇ 1 mean [t] ⁇ 1 mean [0] is calculated.
  • the PEB component l′ 1 [k] is calculated using the reaction model c [t] shown in FIG. 19, and the in-plane average PEB component l′ 1 mean is further calculated.
  • the in-plane average PEB component l′ 1 mean is calculated to be 113.6 nm.
  • the wafer temperature ⁇ 2 [k, t] in the second PEB apparatus is acquired.
  • ⁇ 2 mean [t] is calculated as the in-plane average wafer temperature from the wafer temperature ⁇ 2 [k, t]
  • ⁇ 2 mean [t] ⁇ 2 mean [0] is calculated.
  • the PEB component l′ 2 [k] is calculated using the reaction model c [t] shown in FIG. 19, and the in-plane average PEB component l′ 2 mean is calculated.
  • the in-plane average PEB component l′ 2 mean is calculated to be 113.364 nm.
  • the wafer temperature operation magnification G in the first PEB apparatus is calculated as 0.997378. That is, when the wafer temperature ⁇ 1 [k, t] is multiplied by 0.997378 in the first PEB apparatus, a value close to the wafer temperature ⁇ 2 [k, t] in the second PEB apparatus is obtained.
  • the operation amount ⁇ 1 mean of the wafer temperature in the first PEB apparatus is calculated as ⁇ 0.20978 ° C. That is, when ⁇ 0.20978 ° C. is added to the wafer temperature ⁇ 1 [k, t] in the first PEB apparatus, a value close to the wafer temperature ⁇ 2 [k, t] in the second PEB apparatus is obtained.
  • the heating temperature ⁇ b of the PEB process in the first PEB apparatus is 100 ° C.
  • the wafer temperature manipulated variable ⁇ 1 mean of ⁇ 0.20978 ° C. is divided by a coefficient a of 0.4317 to obtain a hot plate temperature manipulated variable ⁇ b.
  • ⁇ b is calculated to be ⁇ 0.48593 ° C.
  • ⁇ b + ⁇ b is calculated, and the temperature of the hot plate in the first PEB apparatus is updated. As described above, in this embodiment, the temperature of the hot plate in the first PEB apparatus is updated from 100 ° C. to 99.5407 ° C.

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  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
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  • Photosensitive Polymer And Photoresist Processing (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)

Abstract

Selon la présente invention, dans ce procédé de traitement de substrat : des températures de substrat sont mesurées dans le temps sur une pluralité de dispositifs de traitement thermique utilisés pour un traitement thermique de façon à calculer des différences de température de substrat entre les dispositifs de traitement thermique respectifs ; après la formation d'un motif de réserve sur le substrat, une mesure est prise des dimensions du motif de réserve ; des calculs sont effectués pour déterminer des différences de dimensions de motif de réserve entre les dispositifs de traitement thermique respectifs ; une vitesse de réaction servant à convertir une température de substrat en dimensions de motif de réserve est calculée à l'aide des différences de température de substrat et des différences de dimensions de motif de réserve ; et un modèle de réaction est dérivé qui est une fonction du temps par rapport à ladite vitesse de réaction. Afin de dériver le modèle de réaction, la vitesse de réaction au début et à la fin du traitement thermique est réglée à zéro, et un problème d'optimisation lié au mode de réaction est résolu par détermination d'une fonction d'évaluation de telle sorte que la vitesse de réaction devienne continue dans la direction du temps et qu'une somme de produits entre les différences de température de substrat et le modèle de réaction avoisine les différences de dimensions de motif de réserve. En utilisant ledit modèle de réaction, une condition de traitement destinée au traitement de substrat est réglée.
PCT/JP2018/000025 2017-02-01 2018-01-04 Procédé de traitement de substrat, support d'enregistrement informatique et système de traitement de substrat WO2018142840A1 (fr)

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JP2024083583A (ja) * 2020-09-16 2024-06-21 株式会社Ｓｃｒｅｅｎホールディングス 基板処理装置、及び、基板処理方法
JP7712417B2 (ja) 2020-09-16 2025-07-23 株式会社Ｓｃｒｅｅｎホールディングス 基板処理装置、及び、基板処理方法

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