[go: up one dir, main page]

WO2018143751A1 - Dispositif à semiconducteur et dispositif d'affichage le comprenant - Google Patents

Dispositif à semiconducteur et dispositif d'affichage le comprenant Download PDF

Info

Publication number
WO2018143751A1
WO2018143751A1 PCT/KR2018/001518 KR2018001518W WO2018143751A1 WO 2018143751 A1 WO2018143751 A1 WO 2018143751A1 KR 2018001518 W KR2018001518 W KR 2018001518W WO 2018143751 A1 WO2018143751 A1 WO 2018143751A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
disposed
semiconductor
electrode
substrate
Prior art date
Application number
PCT/KR2018/001518
Other languages
English (en)
Korean (ko)
Inventor
이상열
김청송
문지형
박선우
조현민
문용태
Original Assignee
엘지이노텍 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from KR1020170016228A external-priority patent/KR102633028B1/ko
Priority claimed from KR1020170106702A external-priority patent/KR102332450B1/ko
Priority claimed from KR1020170145897A external-priority patent/KR102385209B1/ko
Application filed by 엘지이노텍 주식회사 filed Critical 엘지이노텍 주식회사
Publication of WO2018143751A1 publication Critical patent/WO2018143751A1/fr

Links

Images

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
    • H05B33/00—Electroluminescent light sources
    • H05B33/12—Light sources with substantially two-dimensional radiating surfaces
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80—Constructional details
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80—Constructional details
    • H10H20/81—Bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80—Constructional details
    • H10H20/81—Bodies
    • H10H20/811—Bodies having quantum effect structures or superlattices, e.g. tunnel junctions
    • H10H20/812—Bodies having quantum effect structures or superlattices, e.g. tunnel junctions within the light-emitting regions, e.g. having quantum confinement structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80—Constructional details
    • H10H20/81—Bodies
    • H10H20/814—Bodies having reflecting means, e.g. semiconductor Bragg reflectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80—Constructional details
    • H10H20/81—Bodies
    • H10H20/819—Bodies characterised by their shape, e.g. curved or truncated substrates
    • H10H20/82—Roughened surfaces, e.g. at the interface between epitaxial layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80—Constructional details
    • H10H20/83—Electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80—Constructional details
    • H10H20/85—Packages
    • H10H20/857—Interconnections, e.g. lead-frames, bond wires or solder balls

Definitions

  • the embodiment relates to a semiconductor device and a display device including the same.
  • a light emitting diode is one of light emitting devices that emit light when a current is applied.
  • Light emitting diodes can emit high-efficiency light at low voltage, resulting in excellent energy savings.
  • the luminance problem of the light emitting diode has been greatly improved, and has been applied to various devices such as a backlight unit, a display board, a display, and a home appliance of a liquid crystal display.
  • a light emitting diode having AlGaInP uses a GaAs substrate as a growth substrate, but in order to fabricate a semiconductor chip type, it is necessary to remove the GaAs substrate to prevent light absorption.
  • GaAs substrate is difficult to remove by the conventional laser lift-off (LLO) process, there is a problem that harmful gas is emitted during the process.
  • LLO laser lift-off
  • a light emitting diode having AlGaInP uses a GaAs substrate as a growth substrate, there is a limit to removing a GaAs substrate to prevent light absorption in order to manufacture a semiconductor device type.
  • the embodiment provides a vertical or horizontal chip type red semiconductor device, a semiconductor chip, and a display device including the same and a manufacturing method thereof.
  • the semiconductor device of the embodiment provides light in the red wavelength band.
  • a semiconductor device including GaAs is provided by using laser lift-off.
  • a bonding layer disposed on the substrate; At least one semiconductor structure including a first conductivity type semiconductor layer, a second conductivity type semiconductor layer, and an active layer disposed between the first conductivity type semiconductor layer and the second conductivity type semiconductor layer; A first electrode connected to the first conductive semiconductor layer; A second electrode connected to the second conductive semiconductor layer; And an insulating layer covering the bonding layer and the semiconductor structure.
  • the insulating layer may cover a portion of the first electrode and a portion of the second electrode.
  • the insulating layer may cover the side surface of the bonding layer.
  • the second conductivity type semiconductor layer is a first conductivity type semiconductor layer.
  • a first cladding layer may be further included between the active layer and the first conductive semiconductor layer.
  • a sacrificial layer disposed on at least one of an upper portion of the bonding layer and a lower portion of the bonding layer.
  • the semiconductor structure may be plural in number.
  • a display device includes a coupling layer, a first conductive semiconductor layer, a second conductive semiconductor layer, and an active layer disposed between the first conductive semiconductor layer and the second conductive semiconductor layer. And a semiconductor structure disposed on the coupling layer, a first electrode connected to the first conductive semiconductor layer, a second electrode connected to the second conductive semiconductor layer, and an insulating layer covering the coupling layer and the semiconductor structure.
  • a semiconductor chip comprising a; A panel substrate disposed under the semiconductor chip; And a driving device electrically connected to the semiconductor chip.
  • a bonding layer is disposed on a substrate, and a first conductive semiconductor layer, a second conductive semiconductor layer, the first conductive semiconductor layer, and the second conductive semiconductor are disposed.
  • Disposing a semiconductor structure comprising an active layer disposed between the layers and disposed on the bonding layer; Disposing a second substrate on the semiconductor structure; Separating the first substrate; Disposing a bonding layer on the semiconductor structure, and disposing a third substrate on the bonding layer; Separating the second substrate; Primary etching to a portion of the first conductive semiconductor layer of the semiconductor structure; Disposing a first electrode on the first conductive semiconductor layer and disposing a second electrode on the second conductive semiconductor layer; Secondary etching to an upper portion of the third substrate; And disposing an insulating layer covering the bonding layer and the semiconductor structure.
  • the method may further include disposing a bonding layer on the semiconductor structure and disposing a sacrificial layer between the bonding layer and the third substrate.
  • a first conductive semiconductor layer may be disposed on the coupling layer, an active layer may be disposed on the first conductive semiconductor layer, and a second conductive semiconductor layer may be disposed on the active layer.
  • a display device manufacturing method comprises the steps of irradiating a laser to a semiconductor device comprising a plurality of semiconductor chips disposed on a substrate; Separating at least one of the plurality of semiconductor chips from a substrate and joining with a first bonding layer disposed under the transfer mechanism; Disposing at least one of the plurality of semiconductor chips on a panel substrate, and bonding the second bonding layer on the panel substrate; And irradiating light to separate at least one of the first bonding layer and the plurality of semiconductor chips and to cure the second bonding layer.
  • the semiconductor device comprises a substrate; A bonding layer disposed on the substrate; A semiconductor structure including a first conductivity type semiconductor layer, a second conductivity type semiconductor layer, and an active layer disposed between the first conductivity type semiconductor layer and the second conductivity type semiconductor layer; A first electrode connected to the first conductive semiconductor layer; A second electrode connected to the second conductive semiconductor layer; And an insulating layer covering the bonding layer and the semiconductor structure.
  • a portion of the first electrode, the second electrode, and the insulating layer may be bonded to the first bonding layer.
  • the transport mechanism may be separated from at least one of the plurality of semiconductor chips.
  • Laser lift off device includes a laser unit for irradiating a laser light; An optical unit for guiding the laser light to an irradiation position; A stage holding a semiconductor element at the irradiation position; And an accommodating part surrounding the stage, wherein the accommodating part may include a first exhaust part for discharging gas discharged from the semiconductor device.
  • the first exhaust part may be disposed on a side of the accommodation part.
  • the apparatus may further include a housing surrounding the laser unit, the optical unit, the stage, and the receiving unit.
  • the housing The housing,
  • It may include a second exhaust disposed in the upper portion.
  • the first exhaust part comprises a plurality of exhaust holes.
  • the stage includes a plurality of regions
  • the accommodation part may include a plurality of flow paths formed between the plurality of areas and the plurality of exhaust holes.
  • a semiconductor device includes a sacrificial layer; A bonding layer disposed on the sacrificial layer; At least one semiconductor structure including a first conductivity type semiconductor layer, a second conductivity type semiconductor layer, and an active layer disposed between the first conductivity type semiconductor layer and the second conductivity type semiconductor layer; A first electrode connected to the first conductive semiconductor layer; And a second electrode connected to the second conductive semiconductor layer, wherein the sacrificial layer has a thickness ratio of 1: 1.5 to 1:50.
  • the sacrificial layer may further include an insulating layer disposed on the coupling layer and the semiconductor structure.
  • the insulating layer may cover a portion of the first electrode and a portion of the second electrode.
  • the second conductivity type semiconductor layer may include a 2-1 conductivity type semiconductor layer disposed on the active layer; And a 2-2 conductive semiconductor layer disposed on the 2-1 conductive semiconductor layer.
  • a first cladding layer may be further included between the active layer and the first conductive semiconductor layer.
  • the bonding layer may have a surface roughness of 1 nm or less.
  • An electronic device is a semiconductor device; And a case accommodating the semiconductor element, wherein the semiconductor element comprises: a sacrificial layer; A bonding layer disposed on the sacrificial layer; At least one semiconductor structure including a first conductivity type semiconductor layer, a second conductivity type semiconductor layer, and an active layer disposed between the first conductivity type semiconductor layer and the second conductivity type semiconductor layer; A first electrode connected to the first conductive semiconductor layer; And a second electrode connected to the second conductive semiconductor layer, wherein the sacrificial layer has a thickness ratio of 1: 1.5 to 1:50.
  • a semiconductor device may include a bonding layer; An intermediate layer disposed on the bonding layer; A reflective layer disposed on the intermediate layer; A first conductivity type semiconductor layer disposed on the reflective layer; An active layer disposed on the first conductivity type semiconductor layer; A second conductivity type semiconductor layer disposed on the active layer; A reflective layer disposed under the first conductive semiconductor layer; A first electrode electrically connected to the first conductive semiconductor layer; And a second electrode electrically connected to the second conductivity type semiconductor layer.
  • It may further include a sacrificial layer disposed below the bonding layer.
  • the first conductivity type semiconductor layer may include AlInP, and a doping concentration may be 10 19 or more.
  • the reflective layer may include AlGaAs.
  • the first electrode and the second electrode may each include a portion of the exposed area.
  • the second conductivity type semiconductor layer may include a 2-1 conductivity type semiconductor layer disposed on the active layer; And a 2-2 conductive semiconductor layer disposed on the 2-1 conductive semiconductor layer.
  • a first cladding layer may be further included between the active layer and the first conductive semiconductor layer.
  • An electronic device includes a semiconductor element; And a case accommodating the semiconductor element, wherein the semiconductor element comprises: a bonding layer; An intermediate layer disposed on the bonding layer; A reflective layer disposed on the intermediate layer; A first conductivity type semiconductor layer disposed on the reflective layer; An active layer disposed on the first conductivity type semiconductor layer; A second conductivity type semiconductor layer disposed on the active layer; A reflective layer disposed under the first conductive semiconductor layer; A first electrode electrically connected to the first conductive semiconductor layer; And a second electrode electrically connected to the second conductivity type semiconductor layer.
  • the red semiconductor device may be implemented in a form including a plurality of vertical or horizontal semiconductor chips.
  • the semiconductor element which is excellent in light extraction efficiency can be manufactured.
  • a semiconductor device including GaAs can be manufactured by using laser lift-off.
  • FIG. 1 is a plan view and a cross-sectional view of a semiconductor device according to a first embodiment
  • 2A to 2I illustrate a method of manufacturing a semiconductor device according to the first embodiment
  • FIG 3 is a plan view and a cross-sectional view of a semiconductor device according to a second exemplary embodiment of the present invention.
  • FIG. 4 is a sectional view showing a modification of the semiconductor element according to the first embodiment
  • FIG. 5 is a cross-sectional view of a semiconductor device according to a third embodiment
  • 6A to 6F illustrate a method of manufacturing a semiconductor device according to the third embodiment
  • FIG. 7A to 7D illustrate a method of manufacturing a display device using the semiconductor device according to the first embodiment.
  • FIG. 8 is a diagram illustrating a laser lift-off device according to an embodiment
  • FIG. 9 is a plan view of a laser lift-off device according to an embodiment
  • FIG. 11 is a sectional view showing a laser lift-off device according to the embodiment.
  • FIG. 12 is a view showing a modification of the cross-sectional view of the laser lift-off device according to the embodiment of FIG. 11,
  • FIG. 13 is a cross-sectional view and a plan view of a semiconductor device according to a fourth embodiment
  • FIGS. 14A to 14F are flowcharts illustrating a method of manufacturing a semiconductor device according to the fourth embodiment
  • 15A to 15E are flowcharts illustrating a process of transferring a semiconductor device to a display device according to a fourth embodiment
  • 16 is a graph illustrating transmittance for each wavelength according to a thickness of a sacrificial layer of a semiconductor device according to an embodiment
  • 17 is a graph illustrating transmittance for each wavelength of a bonding layer of a semiconductor device according to an embodiment
  • FIG. 18 is a photograph of a sacrificial layer and a bonding layer of a semiconductor device according to an embodiment
  • 20A is a cross-sectional view and a plan view of a semiconductor device according to a fifth embodiment
  • FIG. 20B is an enlarged view of a portion A in FIG. 20A.
  • 21A to 21F are flowcharts of a method of manufacturing a semiconductor device, according to the fifth embodiment.
  • 22A to 22B illustrate a process of transferring a semiconductor device of a wafer onto a donor substrate.
  • 23A to 23C are flowcharts illustrating a process of transferring a semiconductor device from a wafer to a donor substrate
  • 24 is a conceptual diagram in which a semiconductor element on a donor substrate is transferred to a panel substrate of a display device
  • 25A to 25B are flowcharts illustrating a process of transferring a semiconductor device to a panel substrate of a display device
  • FIG. 26 is a modification of FIG. 20A
  • FIG. 27 is a sectional view of a semiconductor device according to a sixth embodiment
  • 28A to 28H are flowcharts illustrating a method of manufacturing a semiconductor device according to the sixth embodiment.
  • FIG. 29 is a modification of FIG. 27.
  • FIG. 30 is a conceptual diagram of a display device to which a semiconductor device is transferred according to an exemplary embodiment.
  • the semiconductor device package according to the present embodiment may include a small semiconductor device.
  • the small semiconductor device may refer to the structural size of the semiconductor device.
  • the compact semiconductor device may have a structural size of 1 ⁇ m to 100 ⁇ m.
  • the semiconductor device according to the embodiment may have a structural size of 30 ⁇ m to 60 ⁇ m as described below, but is not necessarily limited thereto.
  • technical features or aspects of the embodiments may be applied to semiconductor devices on a smaller scale.
  • the semiconductor device according to the embodiment of the present invention may generate red light having a peak wavelength of 530 nm to 700 nm. However, it is not limited to this wavelength band.
  • each of the embodiments described below may be combined in two or more.
  • FIG. 1 is a plan view and a cross-sectional view of a semiconductor device according to a first embodiment.
  • the semiconductor device may include a substrate 110, a sacrificial layer 120 disposed on the substrate 110, a bonding layer 130 disposed on the sacrificial layer 120, An active layer 142 disposed between the first conductivity type semiconductor layer 141, the second conductivity type semiconductor layer 143b, and the first conductivity type semiconductor layer 141 and the second conductivity type semiconductor layer 143b. And a semiconductor structure 140 disposed on the bonding layer 130, a first electrode 151 connected to the first conductive semiconductor layer 141, and a second conductive semiconductor layer 143b. The second electrode 152, the coupling layer 130, and the insulating layer 160 covering the semiconductor structure 140 may be included.
  • the substrate 110 may be made of a conductive material.
  • the substrate 110 may include a metal or a semiconductor material.
  • the substrate 110 may be a metal having excellent electrical conductivity and / or thermal conductivity. In this case, heat generated during the operation of the semiconductor device may be quickly released to the outside.
  • the substrate 110 is the same as the third substrate described below with reference to FIGS. 2A to 2I.
  • the substrate 110 may include any one of GaAs, sapphire (Al 2 O 3), SiC, Si, GaN, ZnO, GaP, InP, Ge, and Ga203.
  • the sacrificial layer 120 may be disposed on the substrate 110.
  • the sacrificial layer 120 may be removed while transferring the semiconductor device to the display device.
  • the sacrificial layer 120 may be separated by a laser irradiated during the transfer.
  • the sacrificial layer 120 may be formed to be separated at the wavelength of the irradiated laser.
  • the wavelength of the laser may be 532 nm or 1064 nm.
  • the sacrificial layer 120 may include oxide or nitride. However, the present invention is not limited thereto.
  • the sacrificial layer 120 may be a silicate or silicic acid type in the case of an SOG thin film.
  • the sacrificial layer 120 may include silicate, siloxane, methyl silsequioxane (MSQ), hydrogen silsequioxane (HSQ), MQS + HSQ, perhydrosilazane (TCPS), or polysilazane when the SOD (Spin On Dielectrics) thin film.
  • MSQ methyl silsequioxane
  • HSQ hydrogen silsequioxane
  • MQS + HSQ perhydrosilazane
  • TCPS perhydrosilazane
  • polysilazane when the SOD (Spin On Dielectrics) thin film.
  • SOD Spin On Dielectrics
  • the sacrificial layer 120 may be formed by an E-beam evaporator, a thermal evaporator, a metal organic chemical vapor deposition (MOCVD), a sputtering and a pulsed laser deposition (PLD) method. It is not limited to this.
  • the bonding layer 130 may be disposed on the sacrificial layer 120. However, the present invention is not limited thereto and may be disposed under the sacrificial layer 120.
  • the bonding layer 130 may include any one of C, O, N, and H, and the bonding layer 130 may include a resin, but is not limited thereto.
  • the thickness d1 of the bonding layer 130 may be 1.8 ⁇ m to 2.2 ⁇ m. However, the present invention is not limited thereto. Here, the thickness may be a length in the X-axis direction.
  • the first direction (X-axis direction) includes a first-first direction (X1-axis direction) and a first-second direction (X2-axis direction) in the thickness direction of the semiconductor structure 140.
  • the first-first direction is a direction from the first conductive semiconductor layer 141 to the second conductive semiconductor layer 143 in the thickness direction of the semiconductor structure 140.
  • the 1-2 direction is a direction from the second conductive semiconductor layer 143 toward the first conductive semiconductor layer 141 in the thickness direction of the semiconductor structure 140.
  • the second direction (Y-axis direction) may be a direction perpendicular to the first direction (X-axis direction).
  • the second direction (Y-axis direction) includes a second-first direction (Y1-axis direction) and a second-second direction (Y2-axis direction).
  • the semiconductor structure 140 may be disposed on the bonding layer 130.
  • the semiconductor structure 140 may be formed between the first conductivity type semiconductor layer 141, the second conductivity type semiconductor layer 143b, and the first conductivity type semiconductor layer 141 and the second conductivity type semiconductor layer 143b. It may include an active layer 142 disposed in.
  • the first conductivity type semiconductor layer 141 may be disposed on the coupling layer 130.
  • the thickness d2 of the first conductive semiconductor layer 141 may be 1.8 ⁇ m to 2.2 ⁇ m.
  • the present invention is not limited thereto.
  • the first conductive semiconductor layer 141 may be formed of a compound semiconductor such as a group III-V group or a group II-VI, and may be doped with a first dopant.
  • the first conductive semiconductor layer 141 may have InxAlyGa1-x-yP (0 ⁇ x ⁇ 1, 0 ⁇ y ⁇ 1, 0 ⁇ x + y ⁇ 1) or InxAlyGa1-x-yN (0 ⁇ x ⁇ 1, 0 It may include a semiconductor material having a composition formula of ⁇ y ⁇ 1, 0 ⁇ x + y ⁇ 1).
  • the first dopant may be an n-type dopant such as Si, Ge, Sn, Se, or Te.
  • the first conductive semiconductor layer 141 doped with the first dopant may be an n-type semiconductor layer.
  • the first conductive semiconductor layer 141 may include at least one of AlGaP, InGaP, AlInGaP, InP, GaN, InN, AlN, InGaN, AlGaN, InAlGaN, AlInN, AlGaAs, InGaAs, AlInGaAs, and GaP.
  • the first conductive semiconductor layer 141 may be formed using a chemical vapor deposition method (CVD) or a molecular beam epitaxy (MBE) or a method such as sputtering or hydroxide vapor phase epitaxy (HVPE), but is not limited thereto. .
  • CVD chemical vapor deposition method
  • MBE molecular beam epitaxy
  • HVPE hydroxide vapor phase epitaxy
  • the first electrode 151 may be disposed on the first conductive semiconductor layer 141.
  • the first conductivity type semiconductor layer 141 may be electrically connected to the first electrode 151.
  • the first electrode 151 may be disposed on a portion of the upper surface of the first conductive semiconductor layer 141.
  • the first electrode 151 may be disposed below the second electrode 152.
  • the first electrode 151 may be indium tin oxide (ITO), indium zinc oxide (IZO), indium zinc tin oxide (IZTO), indium aluminum zinc oxide (IZAZO), indium gallium zinc oxide (IGZO), or indium gallium tin (IGTO).
  • ITO indium tin oxide
  • IZO indium zinc oxide
  • IZTO indium zinc tin oxide
  • IZAZO indium aluminum zinc oxide
  • IGZO indium gallium zinc oxide
  • IGTO indium gallium tin
  • At least one of Au, Hf, and the like may be formed, but is not limited thereto.
  • the first electrode 151 may be applied to all of the electrode forming methods commonly used, such as stuffing, coating, and deposition.
  • the first clad layer 144 may be disposed on the first conductive semiconductor layer 141.
  • the first clad layer 144 may be disposed between the first conductivity type semiconductor layer 141 and the active layer 142.
  • the first clad layer 144 may include a plurality of layers.
  • the first clad layer 144 may include an AlInP-based layer / AlInGaP-based layer.
  • the thickness d3 of the first cladding layer 144 may be 0.45 ⁇ m to 0.55 ⁇ m. However, the present invention is not limited thereto.
  • the active layer 142 may be disposed on the first clad layer 144.
  • the active layer 142 may be disposed between the first conductivity type semiconductor layer 141 and the second conductivity type semiconductor layer 143b.
  • the active layer 142 is a layer where electrons (or holes) injected through the first conductivity type semiconductor layer 141 and holes (or electrons) injected through the 2-1 conductivity type semiconductor layer 143a meet each other.
  • the active layer 142 transitions to a low energy level as electrons and holes recombine, and may generate light having an ultraviolet wavelength.
  • the active layer 142 may have any one of a single well structure, a multi well structure, a single quantum well structure, a multi quantum well (MQW) structure, a quantum dot structure, or a quantum line structure, and the active layer 142. ) Is not limited thereto.
  • the active layer 142 may be formed of a pair structure of any one or more of GaInP / AlGaInP, GaP / AlGaP, InGaP / AlGaP, InGaN / GaN, InGaN / InGaN, GaN / AlGaN, InAlGaN / GaN, GaAs / AlGaAs, InGaAs / AlGaAs.
  • the present invention is not limited thereto.
  • the thickness d4 of the active layer 142 may be 0.54 ⁇ m to 0.66. However, the present invention is not limited thereto.
  • Electrons are cooled in the first cladding layer 144 so that the active layer 142 may generate more radiation recombination.
  • the second conductivity type semiconductor layer 143 may be disposed on the active layer 142.
  • the second conductive semiconductor layer 143 may include a 2-1 conductive semiconductor layer 143a and a 2-2 conductive semiconductor layer 143b.
  • the 2-1 conductivity type semiconductor layer 143a may be disposed on the active layer 142.
  • the 2-2 conductivity type semiconductor layer 143b may be disposed on the 2-1 conductivity type semiconductor layer 143a.
  • the 2-1 conductive semiconductor layer 143a may include TSBR and P-AllnP.
  • the thickness d5 of the 2-1 conductive semiconductor layer 143a may be 0.57 ⁇ m to 0.70 ⁇ m.
  • the present invention is not limited thereto.
  • the 2-1 conductive semiconductor layer 143a may be formed of a compound semiconductor, such as a III-V group or a II-VI group.
  • the second dopant may be doped in the 2-1 conductive semiconductor layer 143a.
  • the 2-1 conductive semiconductor layer 143a may have InxAlyGa1-x-yP (0 ⁇ x ⁇ 1, 0 ⁇ y ⁇ 1, 0 ⁇ x + y ⁇ 1) or InxAlyGa1-x-yN (0 ⁇ x ⁇ 1 , 0 ⁇ y ⁇ 1, 0 ⁇ x + y ⁇ 1).
  • the p-type dopant may include Mg, Zn, Ca, Sr, Ba, or the like.
  • the 2-1 conductive semiconductor layer 143a may be a p-type semiconductor layer when the 2-1 conductive semiconductor layer 143a doped with the second dopant is doped.
  • the 2-2 conductivity type semiconductor layer 143b may be disposed on the 2-1 conductivity type semiconductor layer 143a.
  • the second-second conductive semiconductor layer 143b may include a p-type GaP-based layer.
  • the second-second conductivity type semiconductor layer 143b may include a superlattice structure of a GaP layer / InxGa1-xP layer (where 0 ⁇ x ⁇ 1).
  • Mg having a concentration of about 10 ⁇ 10 18 may be doped into the 2-2 conductivity type semiconductor layer 143b, but is not limited thereto.
  • the second conductive semiconductor layer 143b may be formed of a plurality of layers, and Mg may be doped only in some layers.
  • the thickness d6 of the second-2 conductivity type semiconductor layer 143b may be 0.9 ⁇ m to 1.1 ⁇ m. However, the present invention is not limited thereto.
  • the second electrode 152 may be disposed on the second-second conductive semiconductor layer 143b.
  • the second electrode 152 may be electrically connected to the second-second conductive semiconductor layer 143b.
  • the second electrode 152 includes indium tin oxide (ITO), indium zinc oxide (IZO), indium zinc tin oxide (IZTO), indium aluminum zinc oxide (IZAO), indium gallium zinc oxide (IGZO), and indium gallium tin (IGTO) oxide), aluminum zinc oxide (AZO), antimony tin oxide (ATO), gallium zinc oxide (GZO), IZO (IZO Nitride), AGZO (Al-Ga ZnO), IGZO (In-Ga ZnO), ZnO, IrOx, RuOx, NiO, RuOx / ITO, Ni / IrOx / Au, or Ni / IrOx / Au / ITO, Ag, Ni, Cr, Ti, Al, Rh, Pd, Ir, Sn, In, Ru, Mg, Zn, Pt At least one of Au, Hf, and the like may be formed, but is not limited thereto.
  • the second electrode 152 may be applied to all of the electrode forming methods commonly used, such as stuffing, coating, and deposition.
  • the insulating layer 160 may cover the coupling layer 130, the sacrificial layer 120, and the semiconductor structure 140.
  • the insulating layer 160 may cover the side of the sacrificial layer 120, the side of the coupling layer 130, and the side of the semiconductor structure 140.
  • the coupling layer 130, the sacrificial layer 120, and the semiconductor structure 140 may not be exposed.
  • the insulating layer 160 may cover a portion of the upper surface of the first electrode 151. In addition, the insulating layer 160 may cover a portion of the upper surface of the second electrode 152. A portion of the upper surface of the first electrode 151 may be exposed. A portion of the upper surface of the second electrode 152 may be exposed.
  • the insulating layer 160 may be made of an insulating material.
  • the insulating layer 160 may be formed by selecting at least one selected from the group consisting of SiO 2, SixOy, Si 3 N 4, SixNy, SiO x Ny, Al 2 O 3, TiO 2, AlN, and the like, but is not limited thereto.
  • 2A to 2I illustrate a method of manufacturing a semiconductor device according to the first embodiment.
  • the bonding layer 130 is disposed on a substrate, and the first conductive semiconductor layer 141, the second conductive semiconductor layer 143, and the first conductive semiconductor layer are disposed.
  • a semiconductor device may include a first substrate 1 and a semiconductor structure 140.
  • the semiconductor structure 140 may be disposed on the first substrate 1 and the first substrate 1.
  • the semiconductor structure 140 may include the first conductive semiconductor layer 141, the first cladding layer 144 disposed on the first conductive semiconductor layer 141, and the active layer disposed on the first cladding layer 144 ( 142, the 2-1 conductive semiconductor layer 143a disposed on the active layer 142, and the 2-2 conductive semiconductor layer 143b disposed on the 2-1 conductive semiconductor layer 143a. It may include.
  • the first substrate 1 may include a material having excellent thermal conductivity.
  • the first substrate 1 may be a conductive substrate or an insulating substrate.
  • the first substrate 1 may use at least one of GaAs, sapphire (Al 2 O 3), SiC, Si, GaN, ZnO, GaP, InP, Ge, and Ga203.
  • An uneven structure may be formed on the first substrate 1, but is not limited thereto. Impurities on the surface may be removed by wet cleaning the first substrate 1.
  • the first conductivity type semiconductor layer 141 may be disposed on the first substrate 1.
  • the first cladding layer 144 may be disposed on the first conductive semiconductor layer 141.
  • the first conductivity type first semiconductor layer may be formed by, for example, chemical vapor deposition (CVD), molecular beam epitaxy (MBE), sputtering, or hydroxide vapor phase epitaxy (HVPE), but is not limited thereto.
  • the active layer 142 may be disposed on the first clad layer 144.
  • the second conductivity-type semiconductor layer 143 may be disposed on the active layer 142.
  • the 2-1 conductive semiconductor layer 143a may be disposed on the active layer 142.
  • the 2-2 conductivity type semiconductor layer 143b may be disposed on the 2-1 conductivity type semiconductor layer 143a.
  • the second substrate 2 may be disposed on the semiconductor device.
  • the second substrate 2 may be disposed on the second-second conductive semiconductor layer 143b.
  • the second substrate 2 may be a conductive substrate and / or an insulating substrate.
  • the second substrate 2 may include a sapphire substrate, but is not limited thereto.
  • the first substrate 1 may be separated from the semiconductor device.
  • the first substrate 1 may be removed by a process such as laser lift-off.
  • the coupling layer 130 may be disposed on the first conductivity type semiconductor layer 141.
  • the sacrificial layer 120 may be disposed on the bonding layer 130.
  • the third substrate 110 may be disposed on the sacrificial layer 120.
  • the sacrificial layer 120 may include a material such as SiO 2, SiN x, TiO 2, polyimide, or the like.
  • the sacrificial layer 120 may be formed by a conventional epitaxial thin film forming method such as PECVD, MOCVD, or spin coating (for polyimide).
  • PECVD PECVD
  • MOCVD MOCVD
  • spin coating for polyimide
  • the bonding layer 130 may include a resin, but is not limited thereto.
  • the third substrate 110 may be disposed on the sacrificial layer 120.
  • the third substrate 110 may serve as a support for supporting the semiconductor structure 140, the coupling layer 130, and the sacrificial layer 120.
  • the third substrate 110 may be formed so that the laser beam is transmitted when transferred to the display device.
  • the irradiated laser wavelength is 532 nm or 1064 nm
  • the laser of 532 nm or 1064 nm wavelength is transmitted through the third substrate 110 and absorbed in the sacrificial layer 120, and the sacrificial layer 120 is irradiated.
  • the second substrate 2 may be removed by laser lift off (LLO).
  • LLO laser lift off
  • primary etching may be performed from a portion of the semiconductor structure 140 to a portion of the first conductivity type semiconductor layer 141.
  • the primary etching may be by wet etching or dry etching, but is not limited thereto.
  • a second electrode 152 may be disposed on the semiconductor structure 140.
  • the second electrode 152 may be electrically connected to the second-second conductive semiconductor layer 143b.
  • the first electrode 151 and the second electrode 152 may be applied to all of the electrode forming methods commonly used, such as stuffing, coating, and deposition. However, the present invention is not limited thereto.
  • the first electrode 151 and the second electrode 152 may be disposed at different positions from the third substrate 110.
  • the first electrode 151 may be disposed on the first conductivity type semiconductor layer 141.
  • the second electrode 152 may be disposed on the second-second conductive semiconductor layer 143b.
  • the second electrode 152 may be disposed above the first electrode 151.
  • the present invention is not limited thereto.
  • the first electrode 151 may be disposed above the second electrode 152.
  • the first electrode 151 may be disposed on the first conductive semiconductor layer 141.
  • the first electrode 151 may be electrically connected to the first conductivity type semiconductor layer 141.
  • Secondary etching may be performed to the top surface of the third substrate 110. Secondary etching may be by wet etching or dry etching, but is not limited thereto.
  • the secondary etching may etch a thickness larger than the primary etching, but is not limited thereto.
  • secondary etching may be performed up to the sacrificial layer 120 or the bonding layer 130.
  • the semiconductor device disposed on the third substrate 110 through secondary etching may be isolated in the form of a plurality of chips.
  • the insulating layer 160 may be covered to cover the sacrificial layer 120, the coupling layer 130, and the semiconductor structure 140.
  • the insulating layer 160 may cover side surfaces of the sacrificial layer 120, the coupling layer 130, and the semiconductor structure 140.
  • the insulating layer 160 may cover a portion of the upper surface of the first electrode 151. A portion of the upper surface of the first electrode 151 may be exposed.
  • the insulating layer 160 may cover a portion of the upper surface of the second electrode 152. A portion of the upper surface of the second electrode 152 may be exposed.
  • a portion of the insulating layer 160 may be disposed on the top surface of the third substrate 110. A portion of the insulating layer 160 may be disposed between adjacent semiconductor chips.
  • FIG 3 is a plan view and a cross-sectional view of a semiconductor device according to a second exemplary embodiment of the present invention.
  • a semiconductor device in the second embodiment of the present invention, includes a substrate, a sacrificial layer 120 disposed on the substrate, a coupling layer 130 disposed on the sacrificial layer 120, and a first conductivity type semiconductor.
  • the semiconductor structure 140 disposed on the layer 130, the first electrode 151 connected to the first conductive semiconductor layer 141, and the second electrode connected to the second-2 conductive semiconductor layer 143b. 152 and an insulating layer 160 covering the coupling layer 130 and the semiconductor structure 140.
  • the substrate, the sacrificial layer 120 and the bonding layer 130 may be applied in the same manner as described with reference to FIG. 1.
  • the semiconductor structure 140 may be disposed on the bonding layer 130.
  • the semiconductor structure 140 may be formed between the first conductivity type semiconductor layer 141, the second conductivity type semiconductor layer 143b, and the first conductivity type semiconductor layer 141 and the second conductivity type semiconductor layer 143b. It may include an active layer 142 disposed in.
  • the second-second conductive semiconductor layer 143b may be disposed on the bonding layer 130.
  • the thickness d7 of the second-2 conductivity type semiconductor layer 143b may be 3.15 ⁇ m to 3.85 ⁇ m.
  • the present invention is not limited thereto.
  • the 2-2 conductivity type semiconductor layer 143b may be disposed on the 2-1 conductivity type semiconductor layer 143a.
  • the second-second conductive semiconductor layer 143b may include a p-type GaP-based layer.
  • the second-second conductivity type semiconductor layer 143b may include a superlattice structure of a GaP layer / InxGa1-xP layer (where 0 ⁇ x ⁇ 1).
  • the second electrode 152 may be disposed on the second-second conductive semiconductor layer 143b.
  • the second-second conductive semiconductor layer 143b may be electrically connected to the second electrode 152.
  • the second electrode 152 may be disposed on one side of the top surface of the 2-2 conductivity type semiconductor layer 143b. The second electrode 152 may be located below the first electrode 151.
  • the 2-1 conductive semiconductor layer 143a may be disposed on the 2-2 conductive semiconductor layer 143b.
  • the 2-1 conductive semiconductor layer 143a may be disposed between the 2-2 conductive semiconductor layer 143b and the active layer 142.
  • the thickness d8 of the 2-1 conductive semiconductor layer 143a may be 0.57 ⁇ m to 0.69 ⁇ m. However, the present invention is not limited thereto.
  • the 2-1 conductive semiconductor layer 143a may have InxAlyGa1-x-yP (0 ⁇ x ⁇ 1, 0 ⁇ y ⁇ 1, 0 ⁇ x + y ⁇ 1) or InxAlyGa1-x-yN (0 ⁇ x ⁇ 1 , 0 ⁇ y ⁇ 1, 0 ⁇ x + y ⁇ 1).
  • the p-type dopant may include Mg, Zn, Ca, Sr, Ba, or the like.
  • the 2-1 conductive semiconductor layer 143a may be a p-type semiconductor layer when the 2-1 conductive semiconductor layer 143a doped with the second dopant is doped.
  • the 2-1 conductive semiconductor layer 143a may include TSBR and AlInP.
  • the active layer 142 may be disposed on the 2-1 conductive semiconductor layer 143a.
  • the active layer 142 is a layer where electrons (or holes) injected through the first conductivity type semiconductor layer 141 and holes (or electrons) injected through the 2-1 conductivity type semiconductor layer 143a meet each other.
  • the active layer 142 transitions to a low energy level as electrons and holes recombine, and may generate light having an ultraviolet wavelength.
  • the active layer 142 may have any one of a single well structure, a multi well structure, a single quantum well structure, a multi quantum well (MQW) structure, a quantum dot structure, or a quantum line structure, and the active layer 142. ) Is not limited thereto.
  • the active layer 142 may be formed of a pair structure of any one or more of GaInP / AlGaInP, GaP / AlGaP, InGaP / AlGaP, InGaN / GaN, InGaN / InGaN, GaN / AlGaN, InAlGaN / GaN, GaAs / AlGaAs, InGaAs / AlGaAs.
  • the present invention is not limited thereto.
  • the thickness d9 of the active layer 142 may be 0.54 ⁇ m to 0.66. However, the present invention is not limited thereto.
  • the first clad layer 144 may be disposed on the active layer 142.
  • the first clad may be disposed between the active layer 142 and the first conductive semiconductor layer 141.
  • the first clad layer 144 may include AlInP.
  • the thickness d10 of the first clad layer 144 may be 0.45 ⁇ m to 0.55 ⁇ m.
  • the present invention is not limited thereto.
  • the first conductivity type semiconductor layer 141 may be disposed on the first cladding layer 144.
  • the first conductive semiconductor layer 141 may be formed of a compound semiconductor such as a group III-V group or a group II-VI, and may be doped with a first dopant.
  • the first conductive semiconductor layer 141 may have InxAlyGa1-x-yP (0 ⁇ x ⁇ 1, 0 ⁇ y ⁇ 1, 0 ⁇ x + y ⁇ 1) or InxAlyGa1-x-yN (0 ⁇ x ⁇ 1, 0 It may include a semiconductor material having a composition formula of ⁇ y ⁇ 1, 0 ⁇ x + y ⁇ 1).
  • the first dopant may be an n-type dopant such as Si, Ge, Sn, Se, or Te.
  • the first conductive semiconductor layer 141 doped with the first dopant may be an n-type semiconductor layer.
  • the first conductive semiconductor layer 141 may include at least one of AlGaP, InGaP, AlInGaP, InP, GaN, InN, AlN, InGaN, AlGaN, InAlGaN, AlInN, AlGaAs, InGaAs, AlInGaAs, and GaP.
  • the first conductive semiconductor layer 141 may be formed using a chemical vapor deposition method (CVD), molecular beam epitaxy (MBE), sputtering or hydroxide vapor phase epitaxy (HVPE), but is not limited thereto.
  • CVD chemical vapor deposition method
  • MBE molecular beam epitaxy
  • HVPE hydroxide vapor phase epitaxy
  • the thickness d11 of the first conductive semiconductor layer 141 may be 0.45 ⁇ m to 5.5 ⁇ m. However, the present invention is not limited thereto.
  • the first electrode 151 may be disposed on the first conductivity type semiconductor layer 141.
  • the first electrode 151 may be electrically connected to the first conductivity type semiconductor layer 141.
  • the first electrode 151 may be located above the second electrode 152.
  • the insulating layer 160 may cover the sacrificial layer 120, the coupling layer 130, and the semiconductor structure 140.
  • the insulating layer 160 may cover side surfaces of the sacrificial layer 120, the coupling layer 130, and the semiconductor structure 140.
  • the insulating layer 160 may cover a portion of the upper surface of the first electrode 151. A portion of the upper surface of the first electrode 151 may be exposed.
  • the insulating layer 160 may cover a portion of the upper surface of the second electrode 152. A portion of the upper surface of the second electrode 152 may be exposed.
  • FIG 4 is a sectional view showing a modification of the semiconductor device according to the first embodiment.
  • positions of the coupling layer 130 and the sacrificial layer 120 may be interchanged.
  • the bonding layer 130 and the sacrificial layer 120 may be separated from the semiconductor device.
  • the semiconductor chip disposed as the panel of the display device may include only the semiconductor structure 140 or may include a semiconductor structure 140 and any one of a bonding layer and a sacrificial layer.
  • FIG. 5 is a cross-sectional view illustrating a semiconductor device in accordance with a third embodiment
  • FIGS. 6A to 6F illustrate a method of manufacturing a semiconductor device in accordance with a third embodiment.
  • the semiconductor device may include a substrate 110, a sacrificial layer 120 disposed on the substrate 110, a bonding layer 130 disposed on the sacrificial layer 120, and bonding
  • the fourth substrate 170 is described as an intermediate layer in FIG. 13 and below.
  • the substrate 110, the sacrificial layer 120, the bonding layer 130, the semiconductor structure 140, the first electrode 151, and the second electrode may be applied in the same manner as described with reference to FIG. 1.
  • the fourth substrate may be a GaAs substrate.
  • the fourth substrate 170 may include an ion layer I by implanting ions into the fourth substrate 170.
  • the ion may include, but is not limited to, hydrogen (H) ion.
  • the ion layer I may be disposed at a predetermined distance from one surface of the fourth substrate 170.
  • the fourth substrate 170 may include a 4-1st substrate 170a and a 4-2th substrate 170b.
  • the ion layer I may be formed spaced apart from 0.4 ⁇ m to 0.6 ⁇ m from one surface of the fourth substrate 170. That is, the thickness of the 4-1st substrate 170a may be 0.4 ⁇ m to 0.6 ⁇ m.
  • the sacrificial layer 120 may be disposed between the substrate 110 and the bonding layer 130 as described above with reference to FIG. 2D.
  • the 4-1st substrate 170a may be disposed on the bonding layer 130, and the bonding layer 130 and the 4-1st substrate 170a may be bonded to each other.
  • the bonding layer 130 may include SiO 2, and the bonding layer 130 may be bonded to the 4-1st substrate 170a through an O 2 plasma treatment.
  • the sacrificial layer 120 is disposed on the substrate 110
  • the bonding layer 130 is disposed on the sacrificial layer 120
  • the fourth-first substrate 170a is disposed on the bonding layer 130.
  • the ion layer I and the fourth-2 substrate 170b may be disposed on the fourth-1st substrate 170a.
  • a fourth substrate 170 may be disposed on the bonding layer 130.
  • the ion layer I of FIG. 6B may be removed by fluid jet cleaving, such that the 4-2th substrate 170b may be separated from the 4-1st substrate 170a.
  • the separated 4-2 substrate 170b may be reused as the substrate. This can provide the effect of manufacturing cost and cost reduction.
  • the fourth substrate 170 disposed on the bonding layer 130 refers to the 4-1st substrate 170a of FIG. 6B, but the fourth substrate 170 will be described below.
  • the semiconductor structure 140 may be disposed on the fourth substrate 170. Since the fourth substrate 170 is polished on the upper surface of the fourth substrate 170 in contact with the semiconductor structure 140, the upper surface of the fourth substrate 170 may be flat. For example, chemical mechanical planarization may be performed on the upper surface of the fourth substrate 170, and the semiconductor structure 140 may be disposed on the upper surface of the fourth substrate 170 after the planarization.
  • primary etching may be performed from a portion of the semiconductor structure 140 to a portion of the first conductive semiconductor layer 141. This may be applied in the same manner as in FIG. 2F.
  • the primary etching may be by wet etching or dry etching, but is not limited thereto.
  • a second electrode 152 may be disposed on the semiconductor structure 140.
  • the second electrode 152 may be electrically connected to the second-second conductive semiconductor layer 143b.
  • the first electrode 151 and the second electrode 152 may be applied to all of the electrode forming methods commonly used, such as stuffing, coating, and deposition. However, the present invention is not limited thereto.
  • the first electrode 151 and the second electrode 152 may be disposed at different positions from the third substrate 110.
  • the first electrode 151 may be disposed on the first conductivity type semiconductor layer 141.
  • the second electrode 152 may be disposed on the second-second conductive semiconductor layer 143b.
  • the second electrode 152 may be disposed above the first electrode 151.
  • the present invention is not limited thereto.
  • the first electrode 151 may be disposed above the second electrode 152.
  • the first electrode 151 may be disposed on the first conductive semiconductor layer 141.
  • the first electrode 151 may be electrically connected to the first conductivity type semiconductor layer 141. This may be equally applied to the contents described with reference to FIG. 2G.
  • Second etching may be performed to the upper surface of the third substrate 110.
  • Secondary etching may be by wet etching or dry etching, but is not limited thereto.
  • the secondary etching may etch a thickness larger than the primary etching, but is not limited thereto.
  • the semiconductor device disposed on the third substrate 110 through secondary etching may be isolated in the form of a plurality of chips. This may be equally applicable to the description of FIG. 2H.
  • the insulating layer 160 may be covered to cover the sacrificial layer 120, the coupling layer 130, the fourth substrate 170, and the semiconductor structure 140.
  • the insulating layer 160 may cover side surfaces of the sacrificial layer 120, the coupling layer 130, the fourth substrate 170, and the semiconductor structure 140.
  • the insulating layer 160 may cover a portion of the upper surface of the first electrode 151. A portion of the upper surface of the first electrode 151 may be exposed.
  • the insulating layer 160 may cover a portion of the upper surface of the second electrode 152. A portion of the upper surface of the second electrode 152 may be exposed. A portion of the insulating layer 160 may be disposed on the upper surface of the third substrate 110. A portion of the insulating layer 160 may be disposed between adjacent semiconductor chips.
  • FIGS. 7A to 7D illustrate a method of manufacturing a display device using the semiconductor device according to the first embodiment.
  • a method of manufacturing a display device includes separating a semiconductor chip 10 from a substrate by selectively irradiating a laser to a semiconductor device including a plurality of semiconductor chips 10 disposed on a substrate, and separating the semiconductor. Disposing the chip 10 on the panel substrate, it is possible to discharge the gas generated in the separating step.
  • the substrate may be a third substrate 110 of a semiconductor device different from the first embodiment.
  • at least one of the plurality of semiconductor chips 10 may be bonded to the first bonding layer 211 disposed under the transfer mechanism 210 and separated from the substrate.
  • the disposing on the panel substrate may include disposing at least one of the plurality of semiconductor chips 10 on the panel substrate, bonding the second bonding layer on the panel substrate, and irradiating light to the first bonding layer 211. And separating at least one of the plurality of semiconductor chips 10 and curing the second bonding layer.
  • the semiconductor element includes a substrate; A bonding layer 130 disposed on the substrate; A first conductive semiconductor layer 141, a second conductive semiconductor layer 143, and an active layer 142 disposed between the first conductive semiconductor layer 141 and the second conductive semiconductor layer 143.
  • a semiconductor structure 140 including and disposed on the bonding layer 130; A first electrode 151 connected to the first conductive semiconductor layer 141; A second electrode 152 connected to the second conductive semiconductor layer 143; And an insulating layer 160 covering the coupling layer 130 and the semiconductor structure 140.
  • first electrode 151, the second electrode 152, and the insulating layer 160 may be bonded to the first bonding layer 211 in a step of separating from the substrate.
  • the transfer mechanism 210 may be separated from at least one of the plurality of semiconductor chips 10 in the curing step with the second bonding layer 310.
  • a laser beam may be irradiated onto the third substrate 110 of the semiconductor device according to the first embodiment.
  • the laser light which is a strong energy source, may be irradiated through the transparent sapphire back-side.
  • the laser light may be radiated onto some semiconductor chips 10 of the semiconductor device.
  • the present invention is not limited thereto and may be irradiated to the entire semiconductor chip 10.
  • Laser absorption occurs between the third substrate 110 and the bonding layer 130, thereby thermo-chemical dissolution in the sacrificial layer 120 disposed between the third substrate 110 and the bonding layer 130. Reaction may occur. As a result, some of the semiconductor chips 10 may be lifted off from the third substrate 110. At this time, harmful gas may be generated by the reaction of the sacrificial layer 120.
  • the harmful gas may include arsenic (As) and phosphorus (P), but is not limited thereto.
  • the laser lift-off device 500 may include a laser unit 510 for irradiating laser light and a laser light to the irradiation position.
  • the optical unit 520 may include a stage 530 in which the semiconductor device is disposed at an irradiation position, a receiving unit 540 surrounding the stage 530, and a housing 550 surrounding the outside.
  • the laser unit 510 may emit laser light.
  • the laser unit 510 may be a KrF excimer laser, but is not limited thereto.
  • the laser source may be pulse oscillation, but is not limited thereto.
  • the optical unit 520 may include a mask 522 for irradiating the laser light in a desired pattern, and a lens group 521 for appropriately enlarging or shaping the beam of the laser light irradiated on the mask 522.
  • the mask 522 may include openings in the shape of the irradiation pattern.
  • the opening of the mask 522 may also be rectangular.
  • the stage 530 may be a member that maintains a semiconductor device position on an upper surface.
  • the semiconductor device may be the semiconductor device according to the first embodiment mentioned above.
  • the stage 530 may be provided with a mechanism for vacuum suction and holding of the semiconductor device, if necessary, but is not limited thereto.
  • stage 530 may have various shapes.
  • the semiconductor device may be circular, but is not limited thereto.
  • Laser light may be irradiated onto the semiconductor device disposed on the stage 530. Specifically, laser light absorption may occur between the third substrate 110 and the bonding layer 130. A thermo-chemical dissolution reaction may occur in the sacrificial layer 120 disposed between the third substrate 110 and the bonding layer 130. The plurality of semiconductor chips 10 included in the semiconductor device may be lifted off from the third substrate 110. At this time, harmful gas may be released by the reaction of the sacrificial layer 120.
  • FIG. 9 is a plan view of the laser lift off device 500 according to the embodiment, and FIG. 10 is a modification of the plan view of the laser lift off device 500 of FIG. 9.
  • the stage 530 may be divided into a plurality of regions. For example, it may be partitioned into four parts.
  • the receiving part 540 may be disposed on an outer surface of the stage 530 and surround the stage 530.
  • the accommodating part 540 may include a first exhaust part 541 for discharging the gas discharged from the sacrificial layer of the semiconductor device.
  • the first exhaust part 541 may be disposed on the side of the receiving part 540.
  • the first exhaust part 541 may include a plurality of exhaust holes 541a, 541b, 541c, and 541d.
  • the shape of the plurality of exhaust holes 541a, 541b, 541c, and 541d may vary.
  • the receiving part 540 includes a plurality of flow paths L1, L2, and L3 formed between the plurality of regions S1, S2, S3, and S4 of the stage 530 and the plurality of exhaust holes 541a, 541b, 541c, and 541d. , L4).
  • the gas discharged from the plurality of areas S1, S2, S3, and S4 of the stage 530 may be discharged through any one of the plurality of flow paths L1, L2, L3, and L4.
  • the accommodating part 540 includes a plurality of partitions P1, P2, P3, which are formed between the stage 530 and the exhaust holes 541a, 541b, 541c, and 541d to form a plurality of flow paths L1, L2, L3, and L4. P4).
  • the gas discharged from the first region S1 may be discharged only through the first exhaust hole 541a.
  • the present invention is not limited thereto and may be variously applied according to the position of the partitions P1, P2, P3, and P4 and the shape of the accommodation portion.
  • It may further include a moving mechanism (not shown) for moving the irradiation position of the laser light with respect to the stage 530.
  • the housing 550 may surround the laser unit 510, the optical unit 520, the stage 530, and the receiving unit 540.
  • the housing 550 may include a second exhaust part 551 disposed thereon.
  • the second exhaust unit 551 may discharge the remaining gas from the gas discharged through the first exhaust unit 541.
  • the second exhaust unit 551 may also include a plurality of exhaust holes, but is not limited thereto.
  • FIG 11 illustrates a cross-sectional view of a laser lift off device 500 according to an embodiment.
  • the semiconductor device may be moved to be disposed on the stage 530.
  • the semiconductor device may be loaded onto the stage 530 through the upper portion of the exhaust hole of the receiving portion 540 by a moving device (not shown).
  • the laser light may be irradiated onto the semiconductor device on the stage 530, and the sacrificial layer 120 may be removed by irradiation of the laser light. And while the sacrificial layer 120 is removed, harmful gas may be emitted. Noxious gas can be discharged into the exhaust hole.
  • FIG. 12 is a diagram showing a modification of the cross-sectional view of the laser lift-off device 500 according to the embodiment of FIG. 11.
  • the semiconductor device may be loaded onto the stage 530 through a lower portion of the exhaust hole by a moving device (not shown).
  • the moving slit 542 may be disposed below the exhaust hole.
  • the moving slit 542 may be opened or closed when loading the semiconductor device onto the stage 530.
  • the laser light may be irradiated onto the semiconductor device on the stage 530, and the sacrificial layer 120 may be removed by irradiation of the laser light.
  • the harmful gas emitted from the sacrificial layer 120 while the sacrificial layer 120 is removed may be discharged to the exhaust part 541 on the moving slit 542.
  • the semiconductor chip may be separated from the third substrate 110 by removing the sacrificial layer 120.
  • the semiconductor chip may be the semiconductor chip mentioned in FIG. 7A.
  • the first bonding layer 211 disposed under the transfer mechanism 210 may be joined to a portion of the insulating layer 160, the upper surface of the first electrode 151, and the upper surface of the second electrode 152.
  • the conveying mechanism 210 may include a conveying tool 212 disposed above the first bonding layer 211.
  • the transfer tool 212 may have an uneven structure to easily bond the semiconductor chip and the first bonding layer 211.
  • the present invention is not limited thereto.
  • the semiconductor chip 10 may be separated from the third substrate 110 in a state of being bonded to the first bonding layer 211 of the transfer mechanism 210. As a result, the insulating layer 160 between the adjacent semiconductor chips 10 may be separated.
  • some semiconductor chips 10 may be disposed on the third substrate 110. That is, the semiconductor chip 10 that is not bonded to the first bonding layer 211 of the transport mechanism 210 may be disposed on the third substrate 110.
  • the semiconductor chip 10 bonded to the transport mechanism 210 may be transported onto the panel.
  • the second bonding layer 310 may be disposed on the panel.
  • the semiconductor chip 10 bonded to the transport mechanism 210 can be bonded to the second bonding layer 310 on the panel.
  • the second bonding layer 310 may be bonded to a portion of the bonding layer 130 and the insulating layer 160 under the semiconductor chip 10. Light may be irradiated to the first bonding layer 211 and the second bonding layer 310 on the transport mechanism 210.
  • Light may be separated between the semiconductor chip 10 and the first bonding layer 211 bonded to each other. On the contrary, light may harden the second bonding layer 310. As a result, the bonding between the semiconductor chip 10 and the second bonding layer 310 can be strengthened.
  • the transport mechanism 210 may be separated from the semiconductor chip 10.
  • the semiconductor chip 10 may be disposed on the panel.
  • the same upper surface as another semiconductor chip disposed in the display device may be formed according to the thickness of the bonding layer 130.
  • the display apparatus may be manufactured by repeating the processes described with reference to FIGS. 7A to 7D.
  • the process of manufacturing the display device described with reference to 7a to 7d may be equally applied to the semiconductor device described with reference to FIGS. 3, 4 and 5 as well as the semiconductor device according to the first embodiment.
  • separation may occur between the bonding layer 130 and the substrate 110.
  • FIG 13 is a sectional view and a plan view of a semiconductor device according to the fourth embodiment.
  • the semiconductor device may include a sacrificial layer 120, a coupling layer 130 disposed on the sacrificial layer 120, an intermediate layer 170 disposed on the coupling layer 130, The first conductive semiconductor layer 141 disposed on the intermediate layer 170, the first cladding layer 144 disposed on the first conductive semiconductor layer, and the active layer disposed on the first cladding layer 144 ( 142, a second conductive semiconductor layer 143 disposed on the active layer, a first electrode 151 electrically connected to the first conductive semiconductor layer, and an electrical connection with the second conductive semiconductor layer.
  • the second electrode 152 and the sacrificial layer 120, the coupling layer 130, the first conductive semiconductor layer 141, the first cladding layer 144, the active layer 142, and the second conductive semiconductor layer 142 ) May include an insulating layer 160.
  • the sacrificial layer 120 may be a layer disposed on the bottom of the semiconductor device according to the embodiment. That is, the sacrificial layer 120 may be a layer disposed on the outermost side in the first-second direction (X2 axis direction). The sacrificial layer 120 may be disposed on a substrate (not shown).
  • the maximum width W1 in the second direction (Y-axis direction) of the sacrificial layer 120 may be 30 ⁇ m to 60 ⁇ m.
  • the first direction includes a first-first direction and a first-second direction in the thickness direction of the semiconductor structure 140.
  • the first-first direction is a direction from the first conductive semiconductor layer 141 to the second conductive semiconductor layer 143 in the thickness direction of the semiconductor structure 140.
  • the 1-2 direction is a direction from the second conductive semiconductor layer 143 toward the first conductive semiconductor layer 141 in the thickness direction of the semiconductor structure 140.
  • the second direction (Y-axis direction) may be a direction perpendicular to the first direction (X-axis direction).
  • the second direction (Y-axis direction) includes a second-first direction (Y1-axis direction) and a second-second direction (Y2-axis direction).
  • the sacrificial layer 120 may be a layer left while transferring the semiconductor device to the display device.
  • the sacrificial layer 120 may be partially separated by a laser irradiated during the transfer, and the other part may be left.
  • the sacrificial layer 120 may include a material that can be separated from the wavelength of the irradiated laser.
  • the wavelength of the laser may be any one of 266 nm, 532 nm, and 1064 nm, but is not limited thereto.
  • the sacrificial layer 120 may include oxide or nitride. However, the present invention is not limited thereto.
  • the sacrificial layer 120 may include an oxide-based material as a material having less deformation generated during epitaxial growth.
  • the sacrificial layer 120 may be formed of indium tin oxide (ITO), indium zinc oxide (IZO), indium zinc tin oxide (IZTO), indium aluminum zinc oxide (IZAZO), indium gallium zinc oxide (IGZO), and indium gallium tin oxide (IGTO).
  • ITO indium tin oxide
  • IZO indium zinc oxide
  • IZTO indium zinc tin oxide
  • IZAZO indium aluminum zinc oxide
  • IGZO indium gallium zinc oxide
  • IGTO indium gallium tin oxide
  • the sacrificial layer 120 may have a thickness d12 of 20 nm or more in the first direction (X-axis direction).
  • the sacrificial layer 120 may have a thickness d12 of 40 nm or more in the first direction (X-axis direction).
  • the sacrificial layer 120 may be formed by an E-beam evaporator, a thermal evaporator, a metal organic chemical vapor deposition (MOCVD), a sputtering and a pulsed laser deposition (PLD) method. It is not limited to this.
  • the bonding layer 130 may be disposed on the sacrificial layer 120.
  • the bonding layer 130 may include a material such as SiO 2, SiN x, TiO 2, polyimide, resin, or the like.
  • the thickness d13 of the bonding layer 130 may be 30 nm to 1 ⁇ m. However, the present invention is not limited thereto. Here, the thickness may be a length in the X-axis direction.
  • the bonding layer 130 may be annealed to bond the sacrificial layer 120 and the intermediate layer 170 to each other. At this time, the peeling may occur while the hydrogen ions in the bonding layer 130 are discharged. Thus, the bonding layer 130 may have a surface roughness of 1 nm or less. By such a configuration, the separation layer and the bonding layer can be easily bonded.
  • the bonding layer 130 and the sacrificial layer 120 may be interchanged with each other.
  • the intermediate layer 170 may be disposed on the bonding layer 130.
  • the intermediate layer 170 may include GaAs.
  • the intermediate layer 170 may be combined with the sacrificial layer 120 through the bonding layer 130.
  • the semiconductor structure 140 may be disposed on the intermediate layer 170.
  • the semiconductor structure 140 is on the first conductive semiconductor layer 141 disposed on the intermediate layer 170, the first cladding layer 144 and the first cladding layer 144 disposed on the first conductive semiconductor layer.
  • the active layer 142 may be disposed on the active layer 142, and the second conductive semiconductor layer 143 may be disposed on the active layer 142.
  • the first conductivity type semiconductor layer 141 may be disposed on the intermediate layer 170.
  • the thickness d15 of the first conductive semiconductor layer 141 may be 1.8 ⁇ m to 2.2 ⁇ m.
  • the present invention is not limited thereto.
  • the first conductive semiconductor layer 141 may be formed of a compound semiconductor such as a group III-V group or a group II-VI, and may be doped with a first dopant.
  • the first conductive semiconductor layer 141 may have InxAlyGa1-x-yP (0 ⁇ x ⁇ 1, 0 ⁇ y ⁇ 1, 0 ⁇ x + y ⁇ 1) or InxAlyGa1-x-yN (0 ⁇ x ⁇ 1, 0 It may include a semiconductor material having a composition formula of ⁇ y ⁇ 1, 0 ⁇ x + y ⁇ 1).
  • the first dopant may be an n-type dopant such as Si, Ge, Sn, Se, or Te.
  • the first conductive semiconductor layer 141 doped with the first dopant may be an n-type semiconductor layer.
  • the first conductive semiconductor layer 141 may include at least one of AlGaP, InGaP, AlInGaP, InP, GaN, InN, AlN, InGaN, AlGaN, InAlGaN, AlInN, AlGaAs, InGaAs, AlInGaAs, and GaP.
  • the first conductive semiconductor layer 141 may be formed using a chemical vapor deposition method (CVD) or a molecular beam epitaxy (MBE) or a method such as sputtering or hydroxide vapor phase epitaxy (HVPE), but is not limited thereto. .
  • CVD chemical vapor deposition method
  • MBE molecular beam epitaxy
  • HVPE hydroxide vapor phase epitaxy
  • the first clad layer 144 may be disposed on the first conductive semiconductor layer 141.
  • the first clad layer 144 may be disposed between the first conductivity type semiconductor layer 141 and the active layer 142.
  • the first clad layer 144 may include a plurality of layers.
  • the first clad layer 144 may include an AlInP-based layer / AlInGaP-based layer.
  • the thickness d16 of the first cladding layer 144 may be 0.45 ⁇ m to 0.55 ⁇ m. However, the present invention is not limited thereto.
  • the active layer 142 may be disposed on the first clad layer 144.
  • the active layer 142 may be disposed between the first conductive semiconductor layer 141 and the second conductive semiconductor layer 143.
  • the active layer 142 is a layer where electrons (or holes) injected through the first conductive semiconductor layer 141 meet holes (or electrons) injected through the second conductive semiconductor layer 143.
  • the active layer 142 transitions to a low energy level as electrons and holes recombine, and may generate light having an ultraviolet wavelength.
  • the active layer 142 may have any one of a single well structure, a multi well structure, a single quantum well structure, a multi quantum well (MQW) structure, a quantum dot structure, or a quantum line structure, and the active layer 142. ) Is not limited thereto.
  • the active layer 142 may be formed of a pair structure of any one or more of GaInP / AlGaInP, GaP / AlGaP, InGaP / AlGaP, InGaN / GaN, InGaN / InGaN, GaN / AlGaN, InAlGaN / GaN, GaAs / AlGaAs, InGaAs / AlGaAs.
  • the present invention is not limited thereto.
  • the thickness d17 of the active layer 142 may be 0.54 ⁇ m to 0.66 ⁇ m. However, the present invention is not limited thereto.
  • Electrons are cooled in the first cladding layer 144 so that the active layer 142 may generate more radiation recombination.
  • the second conductivity type semiconductor layer 143 may be disposed on the active layer 142.
  • the second conductive semiconductor layer 143 may include a 2-1 conductive semiconductor layer 143a and a 2-2 conductive semiconductor layer 143b.
  • the 2-1 conductivity type semiconductor layer 143a may be disposed on the active layer 142.
  • the 2-2 conductivity type semiconductor layer 143b may be disposed on the 2-1 conductivity type semiconductor layer 143a.
  • the 2-1 conductive semiconductor layer 143a may include TSBR and P-AllnP.
  • the thickness d18 of the 2-1 conductivity type semiconductor layer 143a may be 0.57 ⁇ m to 0.70 ⁇ m.
  • the present invention is not limited thereto.
  • the 2-1 conductive semiconductor layer 143a may be formed of a compound semiconductor, such as a III-V group or a II-VI group.
  • the second dopant may be doped in the 2-1 conductive semiconductor layer 143a.
  • the 2-1 conductive semiconductor layer 143a may have InxAlyGa1-x-yP (0 ⁇ x ⁇ 1, 0 ⁇ y ⁇ 1, 0 ⁇ x + y ⁇ 1) or InxAlyGa1-x-yN (0 ⁇ x ⁇ 1 , 0 ⁇ y ⁇ 1, 0 ⁇ x + y ⁇ 1).
  • the p-type dopant may include Mg, Zn, Ca, Sr, Ba, or the like.
  • the 2-1 conductive semiconductor layer 143a may be a p-type semiconductor layer when the 2-1 conductive semiconductor layer 143a doped with the second dopant is doped.
  • the 2-2 conductivity type semiconductor layer 143b may be disposed on the 2-1 conductivity type semiconductor layer 143a.
  • the second-second conductive semiconductor layer 143b may include a p-type GaP-based layer.
  • the second-second conductivity type semiconductor layer 143b may include a superlattice structure of a GaP layer / InxGa1-xP layer (where 0 ⁇ x ⁇ 1).
  • Mg having a concentration of about 10 ⁇ 10 18 may be doped into the 2-2 conductivity type semiconductor layer 143b, but is not limited thereto.
  • the second conductive semiconductor layer 143b may be formed of a plurality of layers, and Mg may be doped only in some layers.
  • the thickness d19 of the second-2 conductivity type semiconductor layer 143b may be 0.9 ⁇ m to 1.1 ⁇ m. However, the present invention is not limited thereto.
  • the first electrode 151 may be disposed on the first conductivity type semiconductor layer 141.
  • the first electrode 151 may be electrically connected to the first conductivity type semiconductor layer 141.
  • the first electrode 151 may be disposed on a portion of the upper surface on which mesa etching is performed in the first conductivity type semiconductor layer 141. Accordingly, the first electrode 151 may be disposed below the second electrode 152 disposed on the upper surface of the second conductive semiconductor layer 143.
  • the shortest width W2 in the second-second direction (Y2-axis direction) between the edge and the second electrode 152 in the second-second direction (Y2-axis direction) of the insulating layer 160 is 2.5 ⁇ m to 3.5 ⁇ m.
  • the shortest width W6 in the 2-1 direction (Y1 axis direction) between the edge and the first electrode 151 in the 2-1 direction (Y1 axis direction) of the insulating layer 160 is 2.5 ⁇ m to 3.5 ⁇ m.
  • the first electrode 151 may be indium tin oxide (ITO), indium zinc oxide (IZO), indium zinc tin oxide (IZTO), indium aluminum zinc oxide (IZAZO), indium gallium zinc oxide (IGZO), or indium gallium tin (IGTO).
  • ITO indium tin oxide
  • IZO indium zinc oxide
  • IZTO indium zinc tin oxide
  • IZAZO indium aluminum zinc oxide
  • IGZO indium gallium zinc oxide
  • IGTO indium gallium tin
  • At least one of Au, Hf, and the like may be formed, but is not limited thereto.
  • the first electrode 151 may be applied to all of the electrode forming methods commonly used, such as stuffing, coating, and deposition.
  • the second electrode 152 may be disposed on the second-second conductive semiconductor layer 143b.
  • the second electrode 152 may be electrically connected to the second-second conductive semiconductor layer 143b.
  • the second electrode 152 includes indium tin oxide (ITO), indium zinc oxide (IZO), indium zinc tin oxide (IZTO), indium aluminum zinc oxide (IZAO), indium gallium zinc oxide (IGZO), and indium gallium tin (IGTO) oxide), aluminum zinc oxide (AZO), antimony tin oxide (ATO), gallium zinc oxide (GZO), IZO (IZO Nitride), AGZO (Al-Ga ZnO), IGZO (In-Ga ZnO), ZnO, IrOx, RuOx, NiO, RuOx / ITO, Ni / IrOx / Au, or Ni / IrOx / Au / ITO, Ag, Ni, Cr, Ti, Al, Rh, Pd, Ir, Sn, In, Ru, Mg, Zn, Pt At least one of Au, Hf, and the like may be formed, but is not limited thereto.
  • the second electrode 152 may be applied to all of the electrode forming methods commonly used, such as stuffing, coating, and deposition.
  • the first electrode 151 may have a larger width in the second direction (Y-axis direction) than the second electrode 152. However, it is not limited to this length.
  • the insulating layer 160 may cover the sacrificial layer 120, the coupling layer 130, and the semiconductor structure 140.
  • the insulating layer 160 may cover the side of the sacrificial layer 120 and the side of the bonding layer 130.
  • the insulating layer 160 may cover a portion of the upper surface of the first electrode 151.
  • the first electrode 151 may be electrically connected to the electrode or the pad through the exposed upper surface to inject the current.
  • the second electrode 152 may include an exposed upper surface like the first electrode 151.
  • the insulating layer 160 may cover the coupling layer 130 and the sacrificial layer 120, and the sacrificial layer 120 and the coupling layer 130 may not be exposed to the outside.
  • the insulating layer 160 may cover a portion of the upper surface of the first electrode 151. In addition, the insulating layer 160 may cover a portion of the upper surface of the second electrode 152. A portion of the upper surface of the first electrode 151 may be exposed. A portion of the upper surface of the second electrode 152 may be exposed.
  • the top surface of the exposed first electrode 151 and the top surface of the exposed second electrode 152 may be circular, but are not limited thereto.
  • the distance W4 in the second direction (Y-axis direction) between the center point of the exposed upper surface of the first electrode 151 and the center point of the upper surface of the second electrode 152 may be 20 ⁇ m to 30 ⁇ m.
  • the center point refers to a point that bisects the width of each of the exposed first electrode and the exposed second electrode in the second direction (Y-axis direction).
  • the maximum width W5 is in the 2-1 axis direction (Y1 axis direction) between the center point of the exposed first electrode 151 and the edge of the first electrode 151 in the 2-1 axis direction (Y1 axis direction). 5.5 ⁇ m to 7.5 ⁇ m.
  • the maximum width W6 in the second-second axis direction (Y2-axis direction) between the center point of the exposed second electrode 152 and the edge of the second electrode 152 in the second-second axis direction (Y2-axis direction). ) May be 5.5 ⁇ m to 7.5 ⁇ m. However, it is not limited to this length.
  • the insulating layer 160 may electrically separate the first conductive semiconductor layer 141 and the second conductive semiconductor layer 143 from the semiconductor structure 140.
  • the insulating layer 160 may be formed by selecting at least one selected from the group consisting of SiO 2, SixOy, Si 3 N 4, SixNy, SiO x Ny, Al 2 O 3, TiO 2, AlN, and the like, but is not limited thereto.
  • 14A to 14F are flowcharts illustrating a method of manufacturing a semiconductor device according to the fourth embodiment.
  • ions may be implanted into the donor substrate S.
  • the donor substrate S may include an ion layer I.
  • the donor substrate S may include an intermediate layer 170 disposed on one side and a first layer 171 disposed on the other side.
  • the intermediate layer 170 may be a layer disposed on the bonding layer 130 of the semiconductor device in FIG. 13.
  • the donor substrate S may include an intermediate layer 170 and a first layer 171.
  • the ions implanted into the donor substrate S may include hydrogen (H) ions, but are not limited thereto.
  • the ion layer I may be spaced apart from a surface of the donor substrate S by a predetermined distance.
  • the ion layer I may be 2 ⁇ m or less from one side of the donor substrate S.
  • the ion layer I may be formed to be 2um apart from one side of the donor substrate S. That is, the thickness of the intermediate layer 170 may be 2um.
  • the thickness of the intermediate layer 170 may be 0.4 ⁇ m to 0.6 ⁇ m.
  • the sacrificial layer 120 may be disposed between the substrate 110 and the bonding layer 130.
  • the separation layer 180 may be disposed between the substrate 110 and the sacrificial layer 120.
  • the substrate 110 may be a transparent substrate including sapphire (Al 2 O 3), glass, or the like. Accordingly, the substrate 110 may transmit the laser light radiated from the bottom. As a result, the laser light may be absorbed by the sacrificial layer 120 during the laser lift-off.
  • the separation layer 180 may improve the regeneration of the substrate 110, for example, a sapphire substrate.
  • the separation layer 180 also facilitates transfer by laser lift off (LLO) described in FIGS. 15A to 15E.
  • LLO laser lift off
  • the separation layer 180 may be made of the same material as the bonding layer 130.
  • the separation layer 180 may include SiO 2.
  • the substrate 110, the separation layer 180, the sacrificial layer 120, and the bonding layer 130 may be stacked in this order.
  • the bonding layer 130 may include SiO 2
  • the bonding layer 130 disposed on the sacrificial layer 120 may include the bonding layer 130 and the O 2 plasma disposed below the intermediate layer 170.
  • the present invention is not limited thereto, and cutting may be performed by a material other than oxygen.
  • the bonding layer 130 disposed on the sacrificial layer 120 and the bonding layer 130 disposed below the intermediate layer 170 may be subjected to an etching process such as polishing and annealing on surfaces facing each other.
  • the intermediate layer 180 is disposed on the substrate 110, the sacrificial layer 120 is disposed on the intermediate layer 180, the bonding layer 130 is disposed on the sacrificial layer 120, and the bonding layer (
  • the donor substrate S may be disposed spaced apart from the upper portion 130.
  • the intermediate layer 170 is disposed on the bonding layer 130 and the bonding layer 130 disposed at the lowermost portion, and the ion layer I and the first layer 171 are disposed on the intermediate layer 170. May be arranged in order.
  • the intermediate layer 170 separated from the donor substrate may be disposed on the bonding layer 130.
  • the ion layer I of FIG. 14B may be removed by fluid jet cleaving so that the first layer 171 may be separated from the intermediate layer 170.
  • the first layer separated from the donor substrate may be reused as the substrate.
  • the separated first layer can be used as a donor substrate in FIGS. 14A-14C.
  • the separated first layer may be newly formed as a donor substrate including a first layer, an ion layer, and an intermediate layer. This can provide the effect of manufacturing cost and cost reduction.
  • the intermediate layer 170 may be disposed on the bonding layer 130.
  • the semiconductor structure 140 may be disposed on the intermediate layer 170.
  • the intermediate layer 170 may contact the semiconductor structure 140. Since the intermediate layer 170 may have a bad roughness of the upper surface due to voids generated by the ion implantation process, defects may be generated during red epi deposition, and thus the upper surface of the intermediate layer 170 may be flattened by polishing. For example, chemical mechanical planarization may be performed on the upper surface of the intermediate layer 170, and the semiconductor structure 140 may be disposed on the upper surface of the intermediate layer 170 after the planarization. By such a configuration, the semiconductor structure 140 may have improved electrical characteristics.
  • the semiconductor structure 140 may be disposed on the intermediate layer 170.
  • the semiconductor structure 140 is on the first conductive semiconductor layer 141 disposed on the intermediate layer 170, the first cladding layer 144 and the first cladding layer 144 disposed on the first conductive semiconductor layer.
  • the active layer 142 may be disposed on the active layer 142, and the second conductive semiconductor layer 143 may be disposed on the active layer 142.
  • the semiconductor structure 140 may be applied in the same manner as described above with reference to FIG. 13.
  • primary etching may be performed from a portion of the semiconductor structure 140 to a portion of the first conductivity-type semiconductor layer 141.
  • Primary etching may be by wet etching or dry etching, but is not limited thereto, and various methods may be applied.
  • the second electrode 152 of FIG. 14E may be disposed on the second conductive semiconductor layer 143 and patterned as shown in FIG. 14E. However, it is not limited to this method.
  • a second electrode 152 may be disposed on the semiconductor structure 140.
  • the second electrode 152 may be electrically connected to the second-second conductive semiconductor layer 143b.
  • An area of a lower surface of the second electrode 152 may be smaller than an upper surface of the second conductive semiconductor layer 143.
  • the edge of the second electrode 152 may be disposed 1 ⁇ m to 3 ⁇ m from an edge of the second conductive semiconductor layer 143.
  • the first electrode 151 and the second electrode 152 may be applied to all of the electrode forming methods commonly used, such as stuffing, coating, and deposition. However, the present invention is not limited thereto.
  • the second electrode 152 is formed before the primary etching, and the first electrode 151 is etched after the primary etching to be disposed on the exposed top surface of the first conductive semiconductor layer 41. Can be.
  • the first electrode 151 and the second electrode 152 may be disposed at different positions from the substrate 110.
  • the first electrode 151 may be disposed on the first conductivity type semiconductor layer 141.
  • the second electrode 152 may be disposed on the second conductivity type semiconductor layer 143. Accordingly, the second electrode 152 may be disposed above the first electrode 151.
  • the present invention is not limited thereto.
  • the first electrode 151 may be disposed above the second electrode 152.
  • the first electrode 151 may be disposed on the first conductive semiconductor layer 141 and electrically connected to the first conductive semiconductor layer 141. This may be equally applicable to the description of FIG. 13.
  • secondary etching may be performed to the upper surface of the substrate 110. Secondary etching may be by wet etching or dry etching, but is not limited thereto. In the semiconductor device, the secondary etching may have a thickness greater than that of the primary etching.
  • the semiconductor device disposed on the substrate through secondary etching may be isolated in the form of a plurality of chips.
  • two semiconductor devices may be disposed on the substrate 110 through secondary etching in FIG. 14F.
  • the number of semiconductor devices may be set variously according to the size of the substrate and the size of the semiconductor device.
  • the insulating layer 160 may be disposed to cover the sacrificial layer 120, the coupling layer 130, the intermediate layer 170, and the semiconductor structure 140.
  • the insulating layer 160 may cover side surfaces of the sacrificial layer 120, the coupling layer 130, the intermediate layer 170, and the semiconductor structure 140.
  • the insulating layer 160 may cover a portion of the upper surface of the first electrode 151. A portion of the upper surface of the first electrode 151 may be exposed. An upper surface of the exposed first electrode 151 may be electrically connected to an electrode pad or the like to inject current.
  • the insulating layer 160 may cover a portion of the upper surface of the second electrode 152. A portion of the upper surface of the second electrode 152 may be exposed.
  • the exposed upper surface of the second electrode 152 may be electrically connected to an electrode pad or the like to inject current.
  • a portion of the insulating layer 160 may be disposed on the upper surface of the substrate.
  • the insulating layer 160 disposed between the adjacent semiconductor chips may be in contact with the substrate 110.
  • 15A to 15E are flowcharts illustrating a process of transferring a semiconductor device to a display device according to a fourth embodiment.
  • a method of manufacturing a display device separates a semiconductor device from a substrate by selectively irradiating a laser to a semiconductor device including a plurality of semiconductor devices disposed on the substrate 110. And disposing the separated semiconductor device on the panel substrate.
  • the semiconductor device before the transfer is a separation layer disposed on the substrate 110, a sacrificial layer disposed on the separation layer, a bonding layer disposed on the sacrificial layer, and disposed on the bonding layer as shown in FIGS. 14A to 14F. It may include a semiconductor structure, a first electrode, a second electrode and an insulating layer.
  • the semiconductor structure may include a first conductive semiconductor layer, a second conductive semiconductor layer, and an active layer disposed between the first conductive semiconductor layer and the second conductive semiconductor layer.
  • the substrate 110 may be the same as the substrate 110 described with reference to FIGS. 14A to 14F.
  • a plurality of semiconductor devices may be disposed on the substrate 110.
  • the plurality of semiconductor devices may include a first semiconductor device 10-1, a second semiconductor device 10-2, a third semiconductor device 10-3, and a fourth semiconductor device 10-4. have.
  • the present invention is not limited thereto, and the semiconductor device may have various numbers.
  • the conveyance mechanism 210 may include the first bonding layer 211 and the conveyance frame 212 disposed below.
  • the carrier frame 212 may have an uneven structure, and may easily bond the semiconductor element and the first bonding layer 211 to each other.
  • the first semiconductor element 10-1 and the third semiconductor element 10-3 may be separated from the transfer mechanism 210. have.
  • coupling between the second bonding layer 310, the first semiconductor device 10-1, and the third semiconductor device 10-3 may be performed.
  • the selected semiconductor device may be separated from the substrate 110 by irradiating a laser under the selected semiconductor device.
  • the transfer mechanism 210 moves upward, and the semiconductor element can move along the movement of the transfer mechanism 210.
  • the substrate 110 and the first semiconductor device 10-1 are irradiated with a laser under a region where the first semiconductor device 10-1 and the third semiconductor device 10-3 are disposed on the substrate 110.
  • the third semiconductor device 10-3 may be separated.
  • the transport mechanism 210 may be formed such that the bonding layer 211 bonds with one semiconductor element so as to separate one semiconductor element at a time.
  • a laser lift-off (LLO) using a photon beam having a specific wavelength band may be applied to the method of separating the semiconductor device from the substrate 110.
  • the center wavelength of the irradiated laser may be 266 nm, 532 nm, or 1064 nm, but is not limited thereto.
  • the separation layer 180 and the bonding layer 130 disposed between the semiconductor device and the substrate 110 may prevent physical damage between the semiconductor devices due to laser lift-off (LLO).
  • the sacrificial layer may be separated from the semiconductor device by laser lift-off (LLO).
  • LLO laser lift-off
  • the sacrificial layer may be partially removed due to separation and the remaining sacrificial layer may be separated together with the bonding layer.
  • the sacrificial layer and the bonding layer, the semiconductor structure, the first electrode, and the second electrode, which are layers disposed on the sacrificial layer may be separated into the substrate 110.
  • the separation layer 180 may be left on the substrate 110.
  • a portion of the sacrificial layer may be left on the separation layer, but is not shown below.
  • the plurality of semiconductor devices separated by the substrate 110 may have a predetermined distance from each other.
  • the first semiconductor device 10-1 and the third semiconductor device 10-3 are separated from the growth substrate, and the first semiconductor device 10-1 and the third semiconductor device 10-3 are separated from each other.
  • the second semiconductor device 10-2 and the fourth semiconductor device 10-4 having the same separation distance from each other may be separated in the same manner. As a result, semiconductor devices having the same separation distance may be transferred to the display panel.
  • the selected semiconductor device may be disposed on the panel substrate.
  • the first semiconductor element 10-1 and the third semiconductor element 10-3 may be disposed on the panel substrate 300.
  • the second bonding layer 310 may be disposed on the panel substrate 300, and the first semiconductor element 10-1 and the third semiconductor element 10-3 may be disposed on the second bonding layer 310. It can be placed on. Accordingly, the first semiconductor device 10-1 and the third semiconductor device 10-3 may be in contact with the second bonding layer. In this manner, semiconductor devices having spaced intervals may be disposed on the panel substrate to improve the efficiency of the transfer process.
  • a laser may be irradiated to separate the first bonding layer 211 and the selected semiconductor device.
  • the laser may be irradiated onto the transfer mechanism 210 to physically separate the first bonding layer 211 and the selected semiconductor device.
  • the first semiconductor element 10-1 and the third semiconductor element 10-3 may be separated from the transfer mechanism 210. have.
  • coupling between the second bonding layer 310, the first semiconductor device 10-1, and the third semiconductor device 10-3 may be performed.
  • 16 is a graph illustrating transmittance for each wavelength according to a thickness of a sacrificial layer of a semiconductor device according to an embodiment.
  • the semiconductor device according to the embodiment when there is no sacrificial layer (A), when the sacrificial layer is 10 nm thick (B), when the sacrificial layer is 20 nm thick (C), the sacrificial layer has a thickness of In the case of 30 nm (D), when the thickness of the sacrificial layer was 40 nm (E), each transmittance was measured.
  • the semiconductor device can provide a transmittance of 80% or more in most wavelength bands. Accordingly, there is a limit in which the laser injected through the substrate is difficult to transmit and thus cause laser lift-off (LLO).
  • LLO laser lift-off
  • the semiconductor element can transmit the laser at 60% or less in the wavelength band of 310 nm or less.
  • the semiconductor device absorbs 40% or more of the laser injected through the substrate in the sacrificial layer, it may be difficult to separate the semiconductor device disposed on the sacrificial layer from the substrate.
  • the semiconductor element can transmit the laser at 50% or less in the wavelength band of 310 nm or less.
  • the laser beam may be further transmitted in the wavelength band of 310 nm or less.
  • the semiconductor device may transmit the laser at about 40% or less in the wavelength band of 310 nm or less. That is, the sacrificial layer may absorb light at 60% or more. Accordingly, the semiconductor device disposed above the sacrificial layer can be easily separated from the substrate.
  • the semiconductor device according to the embodiment can be manufactured by irradiating laser light of 266 nm having a small central wavelength.
  • the sacrificial layer of the semiconductor device according to the embodiment may have a thickness of 20 nm or more.
  • 50% or more of lasers having a wavelength band of 310 nm or less can be easily absorbed.
  • the sacrificial layer of the semiconductor device according to the embodiment may have a thickness of 40 nm or more.
  • the thickness of the sacrificial layer may be 1: 1.5 to 1:50 thickness and thickness ratio of the bonding layer.
  • the laser having a wavelength band of 310 nm or less can be absorbed mostly through a transmittance of 40% or less, so that physical separation from the substrate can be easily performed.
  • the thickness of the sacrificial layer is less than 1: 1.5, the thickness of the sacrificial layer may be difficult to separate from the growth substrate by the laser lift-off (LLO). If the ratio is greater than 1:50, the stress is severe due to the difference in coefficient of thermal expansion between the intermediate layer and the growth substrate, and there is a limit that epitaxial growth is difficult on the separation layer.
  • the separation layer, the sacrificial layer and the bonding layer may have a total thickness of 3 ⁇ m or less.
  • 17 is a graph illustrating transmittance for each wavelength of a bonding layer of a semiconductor device according to an embodiment.
  • the bonding layer of the semiconductor device according to the embodiment may provide a high transmittance (%) in most wavelength ranges.
  • the semiconductor device according to the embodiment may transmit 90% or more of light in a wavelength band between 0 nm and 800 nm.
  • the laser injected through the substrate may pass through the separation layer and be absorbed in the sacrificial layer.
  • the sacrificial layer may be partially separated by a laser.
  • the sacrificial layer may be separated by absorbing a laser at a portion adjacent to the separation layer.
  • the sacrificial layer, the bonding layer, and the semiconductor structure may be separated from the substrate as one semiconductor device.
  • FIG. 18 is a photograph of a sacrificial layer and a bonding layer of a semiconductor device according to an embodiment.
  • the semiconductor device may be inverted.
  • the sacrificial layer 120 may be combined with the bonding layer 130, and the coupling layer 130 may be disposed between the intermediate layer and the sacrificial layer 120.
  • the intermediate layer and the semiconductor structure may be disposed on the bonding layer 130 and the haen layer 120.
  • the thickness of the sacrificial layer 120 may be 33 nm.
  • the thickness of the bonding layer 130 may be 189 nm.
  • the sacrificial layer 120 may be removed by a thickness of about 20 nm due to laser lift off (LLO) by the laser.
  • LLO laser lift off
  • the semiconductor device may have a structure in which a sacrificial layer and a bonding layer are disposed below the intermediate layer due to laser lift off (LLO).
  • FIG. 19 is a modification of FIG. 13.
  • a semiconductor device may include a sacrificial layer 120, a coupling layer 130 disposed on the sacrificial layer 120, and an intermediate layer 170 disposed on the coupling layer 130.
  • the semiconductor structure 140 may be disposed on the intermediate layer 170.
  • the semiconductor structure 140 is formed between the first conductivity type semiconductor layer 141, the second conductivity type semiconductor layer 143, and the first conductivity type semiconductor layer 141 and the second conductivity type semiconductor layer 143b. It may include an active layer 142 disposed.
  • the second conductive semiconductor layer 143 may include a 2-1 conductive semiconductor layer 143a disposed adjacent to the active layer and a 2-2 conductive semiconductor layer 143b disposed adjacent to the intermediate layer. have.
  • the sacrificial layer 120, the bonding layer 130, and the intermediate layer 170 may be applied in the same manner as described with reference to FIG. 13.
  • the second-2 conductivity type semiconductor layer 143b may be disposed on the intermediate layer 170.
  • the thickness of the second-2 conductive semiconductor layer 143b may be 3.15 ⁇ m to 3.85 ⁇ m.
  • the present invention is not limited thereto.
  • the 2-2 conductivity type semiconductor layer 143b may be disposed on the 2-1 conductivity type semiconductor layer 143a.
  • the second-second conductive semiconductor layer 143b may include a p-type GaP-based layer.
  • the second-second conductivity type semiconductor layer 143b may include a superlattice structure of a GaP layer / InxGa1-xP layer (where 0 ⁇ x ⁇ 1).
  • the second electrode 152 may be disposed on the second-second conductive semiconductor layer 143b.
  • the second-second conductive semiconductor layer 143b may be electrically connected to the second electrode 152.
  • the second electrode 152 may be disposed on one side of the top surface of the 2-2 conductivity type semiconductor layer 143b. The second electrode 152 may be located below the first electrode 151.
  • the 2-1 conductive semiconductor layer 143a may be disposed on the 2-2 conductive semiconductor layer 143b.
  • the 2-1 conductive semiconductor layer 143a may be disposed between the 2-2 conductive semiconductor layer 143b and the active layer 142.
  • the thickness of the 2-1 conductive semiconductor layer 143a may be 0.57 ⁇ m to 0.69 ⁇ m. However, the present invention is not limited thereto.
  • the 2-1 conductive semiconductor layer 143a may have InxAlyGa1-x-yP (0 ⁇ x ⁇ 1, 0 ⁇ y ⁇ 1, 0 ⁇ x + y ⁇ 1) or InxAlyGa1-x-yN (0 ⁇ x ⁇ 1 , 0 ⁇ y ⁇ 1, 0 ⁇ x + y ⁇ 1).
  • the p-type dopant may include Mg, Zn, Ca, Sr, Ba, or the like.
  • the 2-1 conductive semiconductor layer 143a may be a p-type semiconductor layer when the 2-1 conductive semiconductor layer 143a doped with the second dopant is doped.
  • the 2-1 conductive semiconductor layer 143a may include TSBR and AlInP.
  • the active layer 142 may be disposed on the 2-1 conductive semiconductor layer 143a.
  • the active layer 142 is a layer where electrons (or holes) injected through the first conductivity type semiconductor layer 141 and holes (or electrons) injected through the 2-1 conductivity type semiconductor layer 143a meet each other.
  • the active layer 142 transitions to a low energy level as electrons and holes recombine, and may generate light having an ultraviolet wavelength.
  • the active layer 142 may have any one of a single well structure, a multi well structure, a single quantum well structure, a multi quantum well (MQW) structure, a quantum dot structure, or a quantum line structure, and the active layer 142. ) Is not limited thereto.
  • the active layer 142 may be formed of a pair structure of any one or more of GaInP / AlGaInP, GaP / AlGaP, InGaP / AlGaP, InGaN / GaN, InGaN / InGaN, GaN / AlGaN, InAlGaN / GaN, GaAs / AlGaAs, InGaAs / AlGaAs.
  • the present invention is not limited thereto.
  • the thickness d9 of the active layer 142 may be 0.54 ⁇ m to 0.66. However, the present invention is not limited thereto.
  • the first clad layer 144 may be disposed on the active layer 142.
  • the first clad may be disposed between the active layer 142 and the first conductive semiconductor layer 141.
  • the first clad layer 144 may include AlInP.
  • the thickness of the first cladding layer 144 may be 0.45 ⁇ m to 0.55 ⁇ m.
  • the present invention is not limited thereto.
  • the first conductivity type semiconductor layer 141 may be disposed on the first cladding layer 144.
  • the first conductive semiconductor layer 141 may be formed of a compound semiconductor such as a group III-V group or a group II-VI, and may be doped with a first dopant.
  • the first conductive semiconductor layer 141 may have InxAlyGa1-x-yP (0 ⁇ x ⁇ 1, 0 ⁇ y ⁇ 1, 0 ⁇ x + y ⁇ 1) or InxAlyGa1-x-yN (0 ⁇ x ⁇ 1, 0 It may include a semiconductor material having a composition formula of ⁇ y ⁇ 1, 0 ⁇ x + y ⁇ 1).
  • the first dopant may be an n-type dopant such as Si, Ge, Sn, Se, or Te.
  • the first conductive semiconductor layer 141 doped with the first dopant may be an n-type semiconductor layer.
  • the first conductive semiconductor layer 141 may include at least one of AlGaP, InGaP, AlInGaP, InP, GaN, InN, AlN, InGaN, AlGaN, InAlGaN, AlInN, AlGaAs, InGaAs, AlInGaAs, and GaP.
  • the first conductive semiconductor layer 141 may be formed using a chemical vapor deposition method (CVD), molecular beam epitaxy (MBE), sputtering or hydroxide vapor phase epitaxy (HVPE), but is not limited thereto.
  • CVD chemical vapor deposition method
  • MBE molecular beam epitaxy
  • HVPE hydroxide vapor phase epitaxy
  • the thickness of the first conductive semiconductor layer 141 may be 0.45 ⁇ m to 5.5 ⁇ m. However, the present invention is not limited thereto.
  • the first electrode 151 may be disposed on the first conductivity type semiconductor layer 141.
  • the first electrode 151 may be electrically connected to the first conductivity type semiconductor layer 141.
  • the first electrode 151 may be located above the second electrode 152.
  • the insulating layer 160 may cover the sacrificial layer 120, the coupling layer 130, and the semiconductor structure 140.
  • the insulating layer 160 may cover side surfaces of the sacrificial layer 120, the coupling layer 130, and the semiconductor structure 140.
  • the insulating layer 160 may cover a portion of the upper surface of the first electrode 151. A portion of the upper surface of the first electrode 151 may be exposed.
  • the insulating layer 160 may cover a portion of the upper surface of the second electrode 152. A portion of the upper surface of the second electrode 152 may be exposed.
  • a semiconductor device may include a sacrificial layer 120 and a sacrificial layer.
  • the bonding layer 130 disposed on the layer 120, the intermediate layer 170 disposed on the bonding layer 130, the reflective layer 190 disposed on the intermediate layer 170, and the agent disposed on the reflective layer 190.
  • the first conductive semiconductor layer 141, the first cladding layer 144 disposed on the first conductive semiconductor layer, the active layer 142 disposed on the first cladding layer 144, and the active layer 142 disposed on the active layer A second conductive semiconductor layer 143, a first electrode 151 electrically connected to the first conductive semiconductor layer, a second electrode 152 and a sacrificial layer electrically connected to the second conductive semiconductor layer.
  • An insulating layer 160 surrounding the coupling layer 130, the first conductive semiconductor layer 141, the first cladding layer 144, the active layer 142, and the second conductive semiconductor layer 142. include can do.
  • the sacrificial layer 120 may be a layer disposed on the bottom of the semiconductor device according to the embodiment. That is, the sacrificial layer 120 may be a layer disposed on the outermost side in the first-second direction (X2 axis direction). The sacrificial layer 120 may be disposed on a substrate (not shown).
  • the maximum width W1 in the second direction (Y-axis direction) of the sacrificial layer 120 may be 30 ⁇ m to 60 ⁇ m.
  • the first direction includes a first-first direction (X1 axis direction) and a first-second direction (X2 axis direction) in the thickness direction of the semiconductor structure 140.
  • the first-first direction (X1 axis direction) is a direction from the first conductive semiconductor layer 141 toward the second conductive semiconductor layer 143 in the thickness direction of the semiconductor structure 140.
  • the first-second direction (X2-axis direction) is a direction from the second conductive semiconductor layer 143 toward the first conductive semiconductor layer 141 in the thickness direction of the semiconductor structure 140.
  • the second direction (Y-axis direction) may be a direction perpendicular to the first direction (X-axis direction).
  • the second direction (Y-axis direction) includes a second-first direction (Y1-axis direction) and a second-second direction (Y2-axis direction).
  • the sacrificial layer 120 may be a layer left while transferring the semiconductor device to the display device as shown in FIG. 23C.
  • the sacrificial layer 120 may be partially removed by the laser irradiated for the transfer when the semiconductor device is transferred to the display device, and the other part may be left.
  • the sacrificial layer 120 may include a material that can be separated from the wavelength of the irradiated laser.
  • the wavelength of the laser may be any one of 266 nm, 532 nm, and 1064 nm, but is not limited thereto.
  • the sacrificial layer 120 may include oxide or nitride. However, the present invention is not limited thereto.
  • the sacrificial layer 120 may include an oxide-based material as a material having less deformation generated during epitaxial growth.
  • the sacrificial layer 120 may be formed of indium tin oxide (ITO), indium zinc oxide (IZO), indium zinc tin oxide (IZTO), indium aluminum zinc oxide (IZAZO), indium gallium zinc oxide (IGZO), and indium gallium tin oxide (IGTO).
  • ITO indium tin oxide
  • IZO indium zinc oxide
  • IZTO indium zinc tin oxide
  • IZAZO indium aluminum zinc oxide
  • IGZO indium gallium zinc oxide
  • IGTO indium gallium tin oxide
  • the sacrificial layer 120 may have a thickness d20 of 20 nm or more in the first direction (X-axis direction).
  • the sacrificial layer 120 may have a thickness d20 of 40 nm or more in the first direction (X-axis direction).
  • the sacrificial layer 120 may be formed by an E-beam evaporator, a thermal evaporator, a metal organic chemical vapor deposition (MOCVD), a sputtering and a pulsed laser deposition (PLD) method. It is not limited to this.
  • the bonding layer 130 may be disposed on the sacrificial layer 120.
  • the bonding layer 130 may include a material such as SiO 2, SiN x, TiO 2, polyimide, resin, or the like.
  • the thickness d21 of the bonding layer 130 may be 30 nm to 1 ⁇ m. However, the present invention is not limited thereto. Here, the thickness may be a length in the X-axis direction.
  • the bonding layer 130 may be annealed to bond the sacrificial layer 120 and the intermediate layer 170 to each other. This will be described below with reference to FIGS. 21B to 2C. And, in the bonding, peeling may occur while the hydrogen ions in the bonding layer 130 is discharged. Thus, the bonding layer 130 may have a surface roughness of 1 nm or less. By such a configuration, the separation layer and the bonding layer can be easily bonded.
  • the bonding layer 130 and the sacrificial layer 120 may be interchanged with each other.
  • the intermediate layer 170 may be disposed on the bonding layer 130.
  • the intermediate layer 170 may include GaInP and GaAs.
  • the intermediate layer 170 may be combined with the sacrificial layer 120 through the bonding layer 130.
  • the intermediate layer 170 may have a structure in which n-GaAs and GaAs are stacked.
  • the intermediate layer 170 may include a first layer (not shown) including GaAs and a second layer (not shown) including n-GaAs.
  • the reflective layer 190 may be disposed on the intermediate layer 170.
  • the reflective layer 190 may contact the semiconductor structure 140 and the intermediate layer 170.
  • the reflective layer 190 may have a distributed bragg reflector (DBR) structure and may include, for example, AlGaAs.
  • the reflective layer 190 may have a structure in which a plurality of materials having different composition ratios of Al and Ga are alternately stacked in multiple layers.
  • the reflective layer 190 may reflect light of a predetermined wavelength.
  • the reflective layer 190 may reflect red light. That is, the reflective layer 190 may provide the effect of increasing the reflectance and improving the luminous flux by increasing the bandwidth of the stop band by applying multiple DBR instead of a single DBR.
  • the reflective layer 190 may be formed of a plurality of layers having different refractive indices.
  • the reflective layer 190 may reflect light generated by the semiconductor structure 140 upward. As a result, the amount of light provided to the upper portion of the semiconductor structure 140 may be increased. In addition, the reflective layer 190 may block the light generated by the semiconductor structure 140 from being provided to the intermediate layer 170 disposed under the reflective layer 190. As a result, the intermediate layer 170 disposed below the reflective layer 190 may not absorb the light generated by the semiconductor structure 140, and the light generated by the semiconductor structure 140 may be provided mostly upward. As a result, the semiconductor device according to the embodiment may have improved optical performance. The semiconductor structure 140 may be disposed on the reflective layer 190.
  • the semiconductor structure 140 is on the first conductive semiconductor layer 141 disposed on the reflective layer 190, the first cladding layer 144 and the first cladding layer 144 disposed on the first conductive semiconductor layer.
  • the active layer 142 may be disposed on the active layer 142, and the second conductive semiconductor layer 143 may be disposed on the active layer 142.
  • the thickness d22 of the reflective layer 190 may be 3um to 4um, but is not limited thereto.
  • the first conductivity type semiconductor layer 141 may be disposed on the reflective layer 190.
  • the thickness d23 + d24 of the first conductive semiconductor layer 141 may be 1.8 ⁇ m to 2.2 ⁇ m.
  • the present invention is not limited thereto.
  • the first conductive semiconductor layer 141 may be formed of a compound semiconductor such as a III-V group or a II-VI group, and may be doped with a first dopant.
  • the first conductive semiconductor layer 141 may have InxAlyGa1-x-yP (0 ⁇ x ⁇ 1, 0 ⁇ y ⁇ 1, 0 ⁇ x + y ⁇ 1) or InxAlyGa1-x-yN (0 ⁇ x ⁇ 1, 0 It may include a semiconductor material having a composition formula of ⁇ y ⁇ 1, 0 ⁇ x + y ⁇ 1).
  • the first dopant may be an n-type dopant such as Si, Ge, Sn, Se, or Te.
  • the first conductive semiconductor layer 141 doped with the first dopant may be an n-type semiconductor layer.
  • the first conductive semiconductor layer 141 may include at least one of AlGaP, InGaP, AlInGaP, InP, GaN, InN, AlN, InGaN, AlGaN, InAlGaN, AlInN, AlGaAs, InGaAs, AlInGaAs, and GaP.
  • the first conductivity type semiconductor layer 141 may have a doping concentration of 1.00E + 19 or more.
  • the first conductive semiconductor layer 141 may be easily in ohmic contact with the first electrode 151 by the doping concentration. In this configuration, the first conductivity-type semiconductor layer 141 may improve luminous efficiency by improving current injection between the first electrodes 151.
  • the first conductive semiconductor layer 141 may be formed using a chemical vapor deposition method (CVD) or a molecular beam epitaxy (MBE) or a method such as sputtering or hydroxide vapor phase epitaxy (HVPE), but is not limited thereto. .
  • CVD chemical vapor deposition method
  • MBE molecular beam epitaxy
  • HVPE hydroxide vapor phase epitaxy
  • the first clad layer 144 may be disposed on the first conductive semiconductor layer 141.
  • the first clad layer 144 may be disposed between the first conductivity type semiconductor layer 141 and the active layer 142.
  • the first clad layer 144 may include a plurality of layers.
  • the first clad layer 144 may include an AlInP-based layer / AlInGaP-based layer. However, it is not limited to this kind.
  • the thickness d25 of the first clad layer 144 may be 0.45 ⁇ m to 0.55 ⁇ m. However, the present invention is not limited thereto.
  • the active layer 142 may be disposed on the first clad layer 144.
  • the active layer 142 may be disposed between the first conductive semiconductor layer 141 and the second conductive semiconductor layer 143.
  • the active layer 142 is a layer where electrons (or holes) injected through the first conductive semiconductor layer 141 meet holes (or electrons) injected through the second conductive semiconductor layer 143.
  • the active layer 142 transitions to a low energy level as electrons and holes recombine, and may generate light having a red wavelength.
  • the active layer 142 may have any one of a single well structure, a multi well structure, a single quantum well structure, a multi quantum well (MQW) structure, a quantum dot structure, or a quantum line structure, and the active layer 142. ) Is not limited thereto.
  • the active layer 142 may be formed of a pair structure of any one or more of GaInP / AlGaInP, GaP / AlGaP, InGaP / AlGaP, InGaN / GaN, InGaN / InGaN, GaN / AlGaN, InAlGaN / GaN, GaAs / AlGaAs, InGaAs / AlGaAs.
  • the present invention is not limited thereto.
  • the thickness d26 of the active layer 142 may be 0.54 ⁇ m to 0.66 ⁇ m. However, the present invention is not limited thereto.
  • Electrons are cooled in the first cladding layer 144 so that the active layer 142 may generate more radiation recombination.
  • the second conductivity type semiconductor layer 143 may be disposed on the active layer 142.
  • the second conductive semiconductor layer 143 may include a 2-1 conductive semiconductor layer 143a and a 2-2 conductive semiconductor layer 143b.
  • the 2-1 conductivity type semiconductor layer 143a may be disposed on the active layer 142.
  • the 2-2 conductivity type semiconductor layer 143b may be disposed on the 2-1 conductivity type semiconductor layer 143a.
  • the 2-1 conductive semiconductor layer 143a may include TSBR and P-AllnP.
  • the thickness d27 of the 2-1 conductive semiconductor layer 143a may be 0.57 ⁇ m to 0.70 ⁇ m.
  • the present invention is not limited thereto.
  • the 2-1 conductive semiconductor layer 143a may be formed of a compound semiconductor, such as a III-V group or a II-VI group.
  • the second dopant may be doped in the 2-1 conductive semiconductor layer 143a.
  • the 2-1 conductive semiconductor layer 143a may have InxAlyGa1-x-yP (0 ⁇ x ⁇ 1, 0 ⁇ y ⁇ 1, 0 ⁇ x + y ⁇ 1) or InxAlyGa1-x-yN (0 ⁇ x ⁇ 1 , 0 ⁇ y ⁇ 1, 0 ⁇ x + y ⁇ 1).
  • the p-type dopant may include Mg, Zn, Ca, Sr, Ba, or the like.
  • the 2-1 conductive semiconductor layer 143a may be a p-type semiconductor layer when the 2-1 conductive semiconductor layer 143a doped with the second dopant is doped.
  • the 2-2 conductivity type semiconductor layer 143b may be disposed on the 2-1 conductivity type semiconductor layer 143a.
  • the second-second conductive semiconductor layer 143b may include a p-type GaP-based layer.
  • the second-second conductivity type semiconductor layer 143b may include a superlattice structure of a GaP layer / InxGa1-xP layer (where 0 ⁇ x ⁇ 1).
  • the second conductive semiconductor layer 143b may be formed of a plurality of layers, Mg may be doped only in some layers, but is not limited thereto.
  • the thickness d28 of the second-2 conductive semiconductor layer 143b may be 0.9 ⁇ m to 1.1 ⁇ m. However, the present invention is not limited thereto.
  • the first electrode 151 may be disposed on the first conductivity type semiconductor layer 141.
  • the first electrode 151 may be electrically connected to the first conductivity type semiconductor layer 141.
  • the first electrode 151 may be disposed on a portion of the upper surface on which mesa etching is performed in the first conductivity type semiconductor layer 141. Accordingly, the first electrode 151 may be disposed below the second electrode 152 disposed on the upper surface of the second conductive semiconductor layer 143.
  • the first electrode 151 may be in ohmic contact with the first conductivity type semiconductor layer 141. Accordingly, the current may be injected into the first conductive semiconductor layer 141 through the first electrode 151.
  • the first electrode 151 may be indium tin oxide (ITO), indium zinc oxide (IZO), indium zinc tin oxide (IZTO), indium aluminum zinc oxide (IZAZO), indium gallium zinc oxide (IGZO), or indium gallium tin (IGTO).
  • ITO indium tin oxide
  • IZO indium zinc oxide
  • IZTO indium zinc tin oxide
  • IZAZO indium aluminum zinc oxide
  • IGZO indium gallium zinc oxide
  • IGTO indium gallium tin
  • At least one of Au, Hf, and the like may be formed, but is not limited thereto.
  • the first electrode 151 may be applied to all of the electrode forming methods commonly used, such as stuffing, coating, and deposition.
  • the second electrode 152 may be disposed on the second-second conductive semiconductor layer 143b.
  • the second electrode 152 may be electrically connected to the second-second conductive semiconductor layer 143b.
  • the second electrode 152 includes indium tin oxide (ITO), indium zinc oxide (IZO), indium zinc tin oxide (IZTO), indium aluminum zinc oxide (IZAO), indium gallium zinc oxide (IGZO), and indium gallium tin (IGTO) oxide), aluminum zinc oxide (AZO), antimony tin oxide (ATO), gallium zinc oxide (GZO), IZO (IZO Nitride), AGZO (Al-Ga ZnO), IGZO (In-Ga ZnO), ZnO, IrOx, RuOx, NiO, RuOx / ITO, Ni / IrOx / Au, or Ni / IrOx / Au / ITO, Ag, Ni, Cr, Ti, Al, Rh, Pd, Ir, Sn, In, Ru, Mg, Zn, Pt At least one of Au, Hf, and the like may be formed, but is not limited thereto.
  • the second electrode 152 may be applied to all of the electrode forming methods commonly used, such as stuffing, coating, and deposition.
  • the first electrode 151 may have a larger width in the second direction (Y-axis direction) than the second electrode 152. However, it is not limited to this length.
  • the insulating layer 160 may include the sacrificial layer 120, the coupling layer 130, the intermediate layer 170, the reflective layer 190, the first conductive semiconductor layer 141, the active layer 143, and the second conductive semiconductor layer ( 143, on the first electrode 151 and the second electrode 152.
  • the shortest width W2 in the second-second direction (Y2-axis direction) between the edge and the second electrode 152 in the second-second direction (Y2-axis direction) of the insulating layer 160 is 2.5 ⁇ m to 3.5 ⁇ m.
  • the shortest width W6 in the 2-1 direction (Y1 axis direction) between the edge and the first electrode 151 in the 2-1 direction (Y1 axis direction) of the insulating layer 160 is 2.5 ⁇ m to 3.5 ⁇ m.
  • the insulating layer 160 may partially cover the first electrode 151 and the second electrode 152. As a result, the first electrode 151 and the second electrode 152 may be partially exposed. In addition, the insulating layer 160 may cover the side of the sacrificial layer 120 and the side of the bonding layer 130. The insulating layer 160 may cover a portion of the upper surface of the first electrode 151. By such a configuration, the first electrode 151 may be electrically connected to the electrode or the pad through the exposed upper surface to inject the current. Similarly, the second electrode 152 may include an exposed upper surface like the first electrode 151. The insulating layer 160 may cover the coupling layer 130 and the sacrificial layer 120, and the sacrificial layer 120 and the coupling layer 130 may not be exposed to the outside.
  • the insulating layer 160 may cover a portion of the upper surface of the first electrode 151. In addition, the insulating layer 160 may cover a portion of the upper surface of the second electrode 152. A portion of the upper surface of the first electrode 151 may be exposed. A portion of the upper surface of the second electrode 152 may be exposed.
  • the top surface of the exposed first electrode 151 and the top surface of the exposed second electrode 152 may be circular, but are not limited thereto.
  • the distance W4 in the second direction (Y-axis direction) between the center point of the exposed upper surface of the first electrode 151 and the center point of the upper surface of the second electrode 152 may be 20 ⁇ m to 30 ⁇ m.
  • the center point refers to a point that bisects the width of each of the exposed first electrode and the exposed second electrode in the second direction (Y-axis direction).
  • the maximum width W5 is in the 2-1 axis direction (Y1 axis direction) between the center point of the exposed first electrode 151 and the edge of the first electrode 151 in the 2-1 axis direction (Y1 axis direction). 5.5 ⁇ m to 7.5 ⁇ m.
  • the maximum width W6 in the second-second axis direction (Y2-axis direction) between the center point of the exposed second electrode 152 and the edge of the second electrode 152 in the second-second axis direction (Y2-axis direction). ) May be 5.5 ⁇ m to 7.5 ⁇ m. However, it is not limited to this length.
  • the insulating layer 160 may electrically separate the first conductive semiconductor layer 141 and the second conductive semiconductor layer 143 from the semiconductor structure 140.
  • the insulating layer 160 may be formed by selecting at least one selected from the group consisting of SiO 2, SixOy, Si 3 N 4, SixNy, SiO x Ny, Al 2 O 3, TiO 2, AlN, and the like, but is not limited thereto.
  • the reflective layer 190 may be disposed on the intermediate layer 170.
  • the reflective layer 190 may be in contact with the semiconductor structure 140.
  • the reflective layer 190 may have a structure in which a plurality of materials having different composition ratios of Al and Ga are alternately stacked in multiple layers.
  • the reflective layer 190 may reflect light of a predetermined wavelength.
  • the reflective layer 190 may reflect red light. That is, the reflective layer 190 may provide the effect of increasing the reflectance and improving the luminous flux by increasing the bandwidth of the stop band by applying multiple DBR instead of a single DBR.
  • the reflective layer 190 may be formed of a plurality of layers having different refractive indices.
  • the reflective layer 190 may include a first layer 191 having a first refractive index and a second layer 192 having a second refractive index different from the first refractive index. That is, the 'reflection layer 190 may have a structure in which layers 191 and 192 having different refractive indices are alternately stacked. For example, the refractive index of the first layer 191 may be smaller than the refractive index of the second layer 192. However, it is not limited to these functions.
  • the Reflection layer 190 is formed with the first layer 191 at a thickness of m ⁇ / 4n.
  • the reflective layer 190 may reflect 95% or more of light having a center wavelength of 620 nm.
  • the first layer 191 and the second layer 192 may have a thickness of ⁇ / 4 times the reference wavelength, and each layer 191 and 192 may have a thickness of 40 nm to 50 nm. In addition, the thickness of the first layer 191 may be greater than that of the second layer 192.
  • the first layer 191 may have a higher Al composition than the second layer 192.
  • the first layer 191 may be Al 0.9 Ga 0.1 As and the second layer may be Al 0.5 Ga 0.5 As.
  • the band reflection layer 190 has a band gap energy larger than the oscillation wavelength, absorption of light does not occur well, and thus the reflectance of light may be improved.
  • a bandgap buffer layer (not shown) may be disposed on the reflective layer 190.
  • the bandgap buffer layer may include (Al0.85Ga0.15) 0.5In0.5P.
  • the bandgap buffer layer (not shown) may have a thickness of 180 nm to 220 nm.
  • the band gap buffer layer (not shown) may have an energy band gap greater than that of the active layer 142. By such a configuration, the bandgap buffer layer (not shown) may be in contact with the upper first conductive semiconductor layer 141 while transmitting the light generated by the active layer 142.
  • the chip when the height difference dh between the first upper surface K1 and the second upper surface K2 is greater than 2 ⁇ m, the chip is horizontally aligned in the transfer process as shown in FIGS. 23 and 25. Can lose.
  • the transfer process may refer to the operation of moving the chip from the growth substrate. That is, the larger the step, the more difficult the chip is to keep horizontal.
  • the height difference dh between the first upper surface K1 and the second upper surface K2 may be 350 nm or more and 2.0 ⁇ m or less. If the height difference dh is larger than 2.0 ⁇ m, a distortion occurs during transfer of the semiconductor device, which makes it difficult to transfer the semiconductor device to a desired position. In addition, when the height difference dh is smaller than 350 nm, the first conductive semiconductor layer 141 may not be partially exposed.
  • the upper surface of the semiconductor element is substantially flat, which facilitates transfer and suppresses crack generation.
  • the height difference dh between the first upper surface K1 and the second upper surface K2 may be 0.6 ⁇ m ⁇ 0.2 ⁇ m, but is not limited thereto.
  • the first upper surface K1 may be defined as a surface where the first conductive semiconductor layer 141 is exposed after the first etching (see FIG. 21D), and the second upper surface K2 may be the second conductive type. It may be defined as an upper surface of the semiconductor layer 143.
  • 21A to 21F are flowcharts illustrating a method of manufacturing a semiconductor device according to the fifth embodiment.
  • ions may be implanted into the donor substrate S.
  • the donor substrate S may include an ion layer I.
  • the donor substrate S may include an intermediate layer 170 disposed on one side and a first layer 171 disposed on the other side.
  • the intermediate layer 170 may be a layer disposed on the bonding layer 130 of the semiconductor device in FIG. 20A.
  • the donor substrate S may include an intermediate layer 170 and a first layer 171.
  • the ions implanted into the donor substrate S may include hydrogen (H) ions, but are not limited thereto.
  • the ion layer I may be spaced apart from a surface of the donor substrate S by a predetermined distance.
  • the ion layer I may be 2 ⁇ m or less from one side of the donor substrate S.
  • FIG. For example, the ion layer I may be formed spaced apart from one side of the donor substrate S by 2 ⁇ m or less. That is, the thickness of the intermediate layer 170 may be 2um or less.
  • the thickness of the intermediate layer 170 may be 0.4 ⁇ m to 0.6 ⁇ m, but is not limited thereto.
  • the sacrificial layer 120 may be disposed between the substrate 110 and the bonding layer 130.
  • the separation layer 180 may be disposed between the substrate 110 and the sacrificial layer 120.
  • the substrate 110 may be a transparent substrate including sapphire (Al 2 O 3), glass, or the like. Accordingly, the substrate 110 may transmit the laser light radiated from the bottom. As a result, the sacrificial layer 120 may absorb the laser light and may be separated from the substrate 110 during the laser lift-off.
  • the separation layer 180 may improve regeneration of the substrate 110, for example, a sapphire substrate. Although the separation layer 180 is not disposed on the substrate 110, laser lift off may be performed by laser light emitted from the lower portion of the substrate 110 toward the sacrificial layer 120.
  • the separation layer 180 also facilitates transfer by laser lift off (LLO) described in FIGS. 23A to 23C.
  • LLO laser lift off
  • the separation layer 180 may be made of the same material as the bonding layer 130.
  • the separation layer 180 may include SiO 2.
  • the substrate 110, the separation layer 180, the sacrificial layer 120, and the bonding layer 130 may be stacked in this order.
  • the bonding layer 130 is disposed on the sacrificial layer 120, and the bonding layer 130 disposed below the intermediate layer 170 disposed on one side of the donor substrate S is disposed on the sacrificial layer 120. It may be disposed to face adjacent to the bonding layer 130 disposed.
  • the bonding layer 130 may include SiO 2
  • the bonding layer 130 disposed on the sacrificial layer 120 may include the bonding layer 130 and the O 2 plasma disposed below the intermediate layer 170.
  • the present invention is not limited thereto, and cutting may be performed by a material other than oxygen.
  • the bonding layer 130 disposed on the sacrificial layer 120 and the bonding layer 130 disposed below the intermediate layer 170 may be polished, annealed, or otherwise processed on surfaces facing each other. ) And the intermediate layer 170 may be combined.
  • the separation layer 180 is disposed on the substrate 110, the sacrificial layer 120 is disposed on the separation layer 180, the bonding layer 130 is disposed on the sacrificial layer 120, and the bonding is performed.
  • the donor substrate S may be spaced apart from the upper layer 130.
  • the intermediate layer 170 is disposed on the bonding layer 130 and the bonding layer 130 disposed at the lowermost portion, and the ion layer I and the first layer 171 are disposed on the intermediate layer 170. May be arranged in order.
  • the intermediate layer 170 separated from the donor substrate may be disposed on the bonding layer 130.
  • fluid jet cleaving may be performed on the ion layer I from one side P of the ion layer I.
  • the ion layer I may be removed by fluid jet cleaving, so that the first layer 171 may be separated from the intermediate layer 170.
  • the first layer 171 separated from the donor substrate S may be reused as a substrate.
  • the separated first layer 171 may be used again as a donor substrate in FIGS. 21A to 21C.
  • the separated first layer 171 may be newly formed as a first layer, an ion layer, and an intermediate layer as a donor substrate. This approach can provide manufacturing cost and cost savings.
  • the intermediate layer 170 may be disposed on the bonding layer 130.
  • the intermediate layer 170 may contact the reflective layer 190.
  • the intermediate layer 170 has a roughness of the upper surface due to voids generated by the ion implantation process, and when the semiconductor structure 140 is deposited, defect epitaxial deposition may occur.
  • the intermediate layer 170 may be polished on the top surface.
  • the upper surface of the intermediate layer 170 may be planarized to reduce roughness, thereby reducing the occurrence of defects in the semiconductor structure 140.
  • chemical mechanical planarization may be performed on the upper surface of the intermediate layer 170, and the semiconductor structure 140 may be disposed on the upper surface of the intermediate layer 170 after the planarization.
  • the semiconductor structure 140 may have improved electrical characteristics.
  • the reflective layer 190 may be disposed on the intermediate layer 170.
  • the reflective layer 190 may contact the semiconductor structure 140.
  • the reflective layer 190 may have a distributed bragg reflector (DBR) structure and may include, for example, AlGaAs.
  • the reflective layer 190 may have a structure in which a plurality of materials having different composition ratios of Al and Ga are alternately stacked in multiple layers.
  • the reflective layer 190 may reflect light of a predetermined wavelength.
  • the reflective layer 190 may reflect red light. That is, the reflective layer 190 may provide the effect of increasing the reflectance and improving the luminous flux by increasing the bandwidth of the stop band by applying multiple DBR instead of a single DBR.
  • the reflective layer 190 may be formed of a plurality of layers having different refractive indices.
  • the reflective layer 190 may reflect light generated by the semiconductor structure 140 upward. As a result, the amount of light provided to the upper portion of the semiconductor structure 140 may be increased. In addition, the reflective layer 190 may block the light generated by the semiconductor structure 140 from being provided to the intermediate layer 170 disposed under the reflective layer 190. As a result, the intermediate layer 170 disposed below the reflective layer 190 may not absorb the light generated by the semiconductor structure 140, and the light generated by the semiconductor structure 140 may be provided mostly upward. As a result, the semiconductor device according to the embodiment may have improved optical performance.
  • the semiconductor structure 140 may be disposed on the reflective layer 190.
  • the semiconductor structure 140 is on the first conductive semiconductor layer 141 disposed on the reflective layer 190, the first cladding layer 144 and the first cladding layer 144 disposed on the first conductive semiconductor layer.
  • the active layer 142 may be disposed on the active layer 142, and the second conductive semiconductor layer 143 may be disposed on the active layer 142.
  • the semiconductor structure 140 may be applied in the same manner as described above with reference to FIG. 20A.
  • primary etching may be performed from a portion of the semiconductor structure 140 to a portion of the first conductivity-type semiconductor layer 141.
  • Primary etching may be by wet etching or dry etching, but is not limited thereto, and various methods may be applied.
  • the second electrode 152 of FIG. 21E may be disposed on the second conductive semiconductor layer 143 and patterned as shown in FIG. 21E. However, it is not limited to this method.
  • a second electrode 152 may be disposed on the semiconductor structure 140.
  • the second electrode 152 may be electrically connected to the second-second conductive semiconductor layer 143b.
  • An area of a lower surface of the second electrode 152 may be smaller than an upper surface of the second conductive semiconductor layer 143.
  • the edge of the second electrode 152 may be disposed 1 ⁇ m to 3 ⁇ m from an edge of the second conductive semiconductor layer 143.
  • the first electrode 151 and the second electrode 152 may be applied to all of the electrode forming methods commonly used, such as stuffing, coating, and deposition. However, the present invention is not limited thereto.
  • the second electrode 152 is formed before the primary etching, and the first electrode 151 is etched after the primary etching to be disposed on the exposed top surface of the first conductive semiconductor layer 41. Can be.
  • the first electrode 151 and the second electrode 152 may be disposed at different positions from the substrate 110.
  • the first electrode 151 may be disposed on the first conductivity type semiconductor layer 141.
  • the second electrode 152 may be disposed on the second conductivity type semiconductor layer 143. Accordingly, the second electrode 152 may be disposed above the first electrode 151.
  • the present invention is not limited thereto.
  • the first electrode 151 may be disposed above the second electrode 152.
  • the first electrode 151 may be disposed on the first conductive semiconductor layer 141 and electrically connected to the first conductive semiconductor layer 141. This may be the same as described in FIG. 20A.
  • secondary etching may be performed to the top surface of the substrate 110 or the bottom surface of the sacrificial layer 120. Secondary etching may be by wet etching or dry etching, but is not limited thereto. In the semiconductor device, the secondary etching may be performed while having a thickness greater than that of the primary etching.
  • a plurality of semiconductor devices may be disposed on the substrate through secondary etching. That is, the plurality of semiconductor devices may be isolated in a chip form. For example, two semiconductor devices may be disposed on the substrate 110 through secondary etching in FIG. 21F. The number of semiconductor devices may be set variously according to the size of the substrate and the size of the semiconductor device.
  • the insulating layer 160 may be disposed to cover the sacrificial layer 120, the coupling layer 130, the intermediate layer 170, the reflective layer 190, and the semiconductor structure 140.
  • the insulating layer 160 may cover side surfaces of the sacrificial layer 120, the coupling layer 130, the intermediate layer 170, the reflective layer 190, and the semiconductor structure 140.
  • the insulating layer 160 may cover a portion of the upper surface of the first electrode 151.
  • a portion of the upper surface of the first electrode 151 may be exposed.
  • the exposed upper surface of the first electrode 151 may be electrically connected to an electrode pad or the like to inject current.
  • the insulating layer 160 may cover a portion of the upper surface of the second electrode 152. A portion of the upper surface of the second electrode 152 may be exposed. Like the first electrode 151, the exposed upper surface of the second electrode 152 may be electrically connected to an electrode pad or the like to inject current. A portion of the insulating layer 160 may be disposed on the upper surface of the substrate. The insulating layer 160 disposed between the adjacent semiconductor chips may be in contact with the substrate 110.
  • FIGS. 22A to 22B are views illustrating a process of transferring a semiconductor device of a wafer onto a donor substrate
  • FIGS. 23A to 23C are flowcharts illustrating a process of transferring a semiconductor device from a wafer to a donor substrate.
  • the plurality of semiconductor devices 10 described above may be disposed on one wafer 1.
  • the plurality of semiconductor devices 10 on the wafer 1 may be primarily transferred to the plurality of donor substrates 210.
  • the wafer 1 may be 6 inches in size, but is not limited thereto.
  • the semiconductor device 10 may have a size of 21 ⁇ m ⁇ 45 ⁇ m, respectively, but is not limited thereto.
  • a plurality of semiconductor devices 10 may be disposed between the first widths P1.
  • a plurality of semiconductor devices 10 may be disposed between the second widths P2.
  • the first width P1 may be a length in one direction in which a plurality of semiconductor elements are disposed
  • the second width P2 may be a length in a direction perpendicular to the one direction.
  • the first width P1 may be a longitudinal length on the wafer 1
  • the second width P2 may be a horizontal length on the wafer 1.
  • the first width P1 and the second width P2 may have the same length.
  • the first width P1 and the second width P2 may be arrangement intervals between a plurality of semiconductor elements disposed on a panel substrate, which will be described later.
  • the first width P1 and the second width P2 may be 834 ⁇ m, but may be changed according to an interval in which the semiconductor elements are disposed on the panel substrate.
  • the semiconductor device 10 disposed in the predetermined region K of the wafer 1 may be transferred to the donor substrate 210 in FIG. 22B.
  • the predetermined area K may have the same size as that of the donor substrate 210, but is not limited thereto.
  • the plurality of semiconductor devices 10 disposed at predetermined intervals in the predetermined region K may be transferred to the donor substrate 210.
  • the donor substrate 210 and the plurality of semiconductor elements 10 disposed on the donor substrate 210 may be referred to as a semiconductor module.
  • the number of donor substrates 210 generated from one wafer 1 may vary depending on the size of the wafer 1 and the donor substrate 210. For example, when the size of the wafer 1 is 6 inches, 5.4 million semiconductor devices may be disposed on the wafer 1. In addition, when the size of the donor substrate 210 is 100.8 mm ⁇ 100.8 mm, 375 donor substrates 210 may be generated per one wafer 1. However, as described above, the number of donor substrates may be variously changed according to the size of the wafer and the size of the donor substrate.
  • the donor substrate 210 may have a fourth width P4 having a length in a direction different from a third width P3 having a length in one direction.
  • the third width P3 and the fourth width P4 may be the same length.
  • a wafer including a semiconductor device for generating red light, a wafer including a semiconductor device for generating green light, and a wafer including a semiconductor device for generating blue light may be a semiconductor for generating red light, green light, or blue light.
  • Each device may be transferred to the donor substrate 210.
  • the semiconductor device generating red light, the semiconductor device generating green light, and the semiconductor device generating blue light may be repeatedly transferred on the donor substrate 210 in order.
  • the present invention is not limited to this order, and a semiconductor device that generates red light, blue light, and green light may be disposed on one wafer.
  • the plurality of semiconductor devices 10 disposed on the donor substrate 210 may provide red (R, red), green (G, green), and blue (B, blue) light. 22A and 22B, the semiconductor device 10 may look like a single chip, but the present invention is not limited thereto, and the red, green, and blue semiconductor devices may form one semiconductor device 10. In addition, the semiconductor device 10 may be designed to provide all of the red, green, and blue colors as a single chip.
  • the plurality of semiconductor devices 10 disposed on the wafer 1 may be transferred to the donor substrate 210 in a state in which the plurality of semiconductor devices 10 are spaced apart by a predetermined distance in one direction and another direction.
  • the semiconductor devices disposed on the donor substrate 210 may be spaced apart from each other.
  • the separation distance between the semiconductor devices disposed on the wafer 1 and the semiconductor devices disposed on the donor substrate 210 may be different from each other.
  • the separation distance between the semiconductor devices disposed on the wafer 1 may be smaller than the separation distance between the semiconductor devices disposed on the donor substrate 210.
  • a plurality of semiconductor elements disposed in the same region of the wafer 1 may be transferred to the panel substrate through the donor substrate 210 to have a predetermined interval. Accordingly, the plurality of semiconductor elements transferred to the panel substrate may provide the same characteristics, such as a wavelength change, of the semiconductor elements having the plurality of regions disposed in the same region of the wafer.
  • a substrate disposed on a wafer and a plurality of semiconductor elements may be transferred to a donor substrate. (Primary transfer)
  • the substrate 110 may be the same as the substrate 110 described above with reference to FIGS. 21A through 21F.
  • the plurality of semiconductor devices 10-1 to 10-4 may be disposed on the substrate 110.
  • the plurality of semiconductor devices 10-1 to 10-4 may include a first semiconductor device 10-1, a second semiconductor device 10-2, a third semiconductor device 10-3, and a fourth semiconductor device. (10-4).
  • the present invention is not limited thereto, and the semiconductor device may have various numbers.
  • At least one semiconductor device selected from the plurality of semiconductor devices 10-1, 10-2, 10-3, and 10-4 may be separated into the substrate 110 using the donor substrate 210.
  • semiconductor devices spaced apart by a predetermined interval may be selected and transferred to the donor substrate 210.
  • the donor substrate 210 may include a first bonding layer 211 and a carrier frame 212 disposed below.
  • the carrier frame 212 may have an uneven structure, and may easily bond the semiconductor element and the first bonding layer 211 to each other. However, it is not limited to this shape. As described with reference to FIGS.
  • only a semiconductor device disposed at a predetermined distance W5 among the plurality of semiconductor devices disposed on the wafer may be transferred to the donor substrate 210.
  • the separation distance between the semiconductor elements transferred to the donor substrate may be equal to the first width P1 or the second width P2 described above.
  • the first semiconductor device 10-1 and the third semiconductor device 10-3 may be separated from the donor substrate 210. have.
  • coupling between the second bonding layer 310, the first semiconductor device 10-1, and the third semiconductor device 10-3 may be performed.
  • the selected semiconductor devices 10-1 and 10-3 may be separated from the substrate 110 by irradiating a laser beam passing through the substrate 110 under the selected semiconductor devices 10-1 and 10-3.
  • the donor substrate 210 may move upward, and the selected semiconductor devices 10-1 and 10-3 may also move along the movement of the donor substrate 210.
  • the substrate 110 and the first semiconductor device 10-1 are irradiated with a laser under a region where the first semiconductor device 10-1 and the third semiconductor device 10-3 are disposed on the substrate 110. And the third semiconductor device 10-3 may be separated.
  • the donor substrate 210 and the bonding layer 211 may be formed to be bonded to one semiconductor device when the semiconductor device is separated at one time.
  • a laser lift-off (LLO) using a photon beam having a specific wavelength band may be applied to the method of separating the semiconductor device from the substrate 110.
  • the center wavelength of the irradiated laser may be 266 nm, 532 nm, or 1064 nm, but is not limited thereto.
  • the plurality of semiconductor devices separated from the substrate 110 may have a predetermined distance from each other.
  • the first semiconductor device 10-1 and the third semiconductor device 10-3 are separated from the substrate 110, and the first semiconductor device 10-1 and the third semiconductor device 10-are separated from each other.
  • the second semiconductor device 10-2 and the fourth semiconductor device 10-4 having the same separation distance as that of 3) may be separated in the same manner. As a result, semiconductor devices having the same separation distance may be transferred to the display panel.
  • FIGS. 25A to 25B are flowcharts illustrating a process of transferring a semiconductor element to a panel substrate of a display device.
  • a plurality of semiconductor devices 10 primarily transferred from the wafer 1 may be disposed on the donor substrate 210.
  • a plurality of donor substrates 210 transferred from the wafer 1 may be provided.
  • the plurality of semiconductor devices 10 disposed on the donor substrate 210 may be secondarily transferred onto the panel substrate 300.
  • the panel substrate 300 may include a plurality of regions.
  • each region formed on the panel substrate 300 is a region where the semiconductor element is transferred by being secondarily transferred from one donor substrate.
  • the panel substrate 300 may have a rectangular shape as a panel of the display device, but may have various shapes, which will be described below with reference to the rectangular shape.
  • the panel substrate 300 may include twelve regions S1 to S12.
  • the panel substrate 300 may include the first region S1 to the twelfth region S12.
  • the first region S1 to the twelfth region S12 may be partitioned by the first line L1 to the fifth line L5.
  • the first line L1 to the third line L3 may divide the first surface E1 of the panel substrate 300 into four parts.
  • the fourth line L4 to the fifth line L5 may divide the second surface E2 of the panel substrate 300 into three parts.
  • the first surface E1 and the second surface E2 may be any one of edges of the panel substrate 300, respectively.
  • the first surface E1 and the second surface E2 may be surfaces adjacent to each other.
  • the first region S1 to the twelfth region S12 may have the same size as that of the donor substrate 210.
  • the first region S1 to the twelfth region S12 may each include an alignment mark.
  • the plurality of donor substrates 210 may be disposed in the first area S1 to the twelfth area S12 along the alignment marks included in the first area S1 to the twelfth area S12, respectively.
  • the semiconductor device 10 disposed on the donor substrate 210 may be a semiconductor device 10 manufactured from one region of the same wafer 1.
  • the alignment mark may be formed in the same manner for each region of the donor substrate 210 and the panel substrate during the manufacturing process, and the second transfer may be performed along the alignment mark during the process.
  • the plurality of semiconductor devices 10 disposed on the panel substrate 300 may have a predetermined distance dw2. Since the semiconductor elements 10 of the donor substrate 210 are transferred to the panel substrate 300 along the alignment mark, the plurality of semiconductor elements 10 disposed on the donor substrate 210 may also be disposed on the panel substrate 300.
  • the plurality of semiconductor devices 10 disposed in the may have a separation distance dw1 equal to the predetermined separation distance dw2.
  • the separation distance dw2 between the adjacent semiconductor elements 10 on the panel substrate 300 and the separation distance dw1 between the adjacent semiconductor elements 10 on the donor substrate 210 are provided in the plurality of adjacent semiconductors disposed on the wafer 1. It may be greater than the separation distance between the devices.
  • the plurality of semiconductor elements 10 disposed in a predetermined region of the wafer 1 may be transferred to the plurality of donor substrates 210 with a predetermined distance.
  • the semiconductor device selected in FIG. 23B may be disposed on a panel substrate.
  • the first semiconductor element 10-1 and the third semiconductor element 10-3 may be disposed on the panel substrate 300.
  • the second bonding layer 310 may be disposed on the panel substrate 300, and the first semiconductor element 10-1 and the third semiconductor element 10-3 may be disposed on the second bonding layer 310. It can be placed on. Accordingly, the first semiconductor device 10-1 and the third semiconductor device 10-3 may be bonded to the second bonding layer 310. In this manner, the semiconductor devices 10-1 and 10-3 having spaced apart intervals may be disposed on the panel substrate to improve the efficiency of the transfer process.
  • a laser may be irradiated to separate the first bonding layer 211 and the selected semiconductor device.
  • the laser may be irradiated onto the transfer mechanism 210 to physically separate the first bonding layer 211 and the selected semiconductor device.
  • the transfer mechanism 210 when the transfer mechanism 210 is moved upward after laser irradiation, the first semiconductor element 10-1 and the third semiconductor element 10-3 may be separated from the transfer mechanism 210. have. In addition, coupling between the second bonding layer 310, the first semiconductor device 10-1, and the third semiconductor device 10-3 may be performed. Thus, the plurality of semiconductor elements on the donor substrate can be transferred (secondary transfer) to the panel substrate.
  • FIG. 26 is a modification of FIG. 20A.
  • a semiconductor device may include a sacrificial layer 120, a bonding layer 130 disposed on the sacrificial layer 120, and an intermediate layer 170 disposed on the bonding layer 130.
  • the semiconductor device may include a reflective layer 190 disposed on the intermediate layer 170, a semiconductor structure 140 disposed on the reflective layer 190, a first electrode 151, and a second electrode 152.
  • the semiconductor structure 140 may include the first conductive semiconductor layer 141, the second conductive semiconductor layer 143, the first conductive semiconductor layer 141, and the second-conductive semiconductor layer 143b. It may include an active layer 142 disposed between).
  • the second conductive semiconductor layer 143 may include a 2-1 conductive semiconductor layer 143a disposed adjacent to the active layer and a 2-2 conductive semiconductor layer 143b disposed adjacent to the intermediate layer. have.
  • the sacrificial layer 120, the coupling layer 130, the intermediate layer 170, and the reflective layer 190 may be applied in the same manner as described with reference to FIG. 20A.
  • the second-2 conductivity type semiconductor layer 143b may be disposed on the intermediate layer 170.
  • the thickness of the second-2 conductive semiconductor layer 143b may be 3.15 ⁇ m to 3.85 ⁇ m.
  • the present invention is not limited thereto.
  • the 2-2 conductivity type semiconductor layer 143b may be disposed on the 2-1 conductivity type semiconductor layer 143a.
  • the second-second conductive semiconductor layer 143b may include a p-type GaP-based layer.
  • the second-second conductivity type semiconductor layer 143b may include a superlattice structure of a GaP layer / InxGa1-xP layer (where 0 ⁇ x ⁇ 1).
  • the second electrode 152 may be disposed on the second-second conductive semiconductor layer 143b.
  • the second-second conductive semiconductor layer 143b may be electrically connected to the second electrode 152.
  • the second electrode 152 may be disposed on one side of the top surface of the 2-2 conductivity type semiconductor layer 143b. The second electrode 152 may be located below the first electrode 151.
  • the 2-1 conductive semiconductor layer 143a may be disposed on the 2-2 conductive semiconductor layer 143b.
  • the 2-1 conductive semiconductor layer 143a may be disposed between the 2-2 conductive semiconductor layer 143b and the active layer 142.
  • the thickness of the 2-1 conductive semiconductor layer 143a may be 0.57 ⁇ m to 0.69 ⁇ m. However, the present invention is not limited thereto.
  • the 2-1 conductive semiconductor layer 143a may have InxAlyGa1-x-yP (0 ⁇ x ⁇ 1, 0 ⁇ y ⁇ 1, 0 ⁇ x + y ⁇ 1) or InxAlyGa1-x-yN (0 ⁇ x ⁇ 1 , 0 ⁇ y ⁇ 1, 0 ⁇ x + y ⁇ 1).
  • the p-type dopant may include Mg, Zn, Ca, Sr, Ba, or the like.
  • the 2-1 conductive semiconductor layer 143a may be a p-type semiconductor layer when the 2-1 conductive semiconductor layer 143a doped with the second dopant is doped.
  • the 2-1 conductive semiconductor layer 143a may include TSBR and AlInP.
  • the active layer 142 may be disposed on the 2-1 conductive semiconductor layer 143a.
  • the active layer 142 is a layer where electrons (or holes) injected through the first conductivity type semiconductor layer 141 and holes (or electrons) injected through the 2-1 conductivity type semiconductor layer 143a meet each other.
  • the active layer 142 transitions to a low energy level as electrons and holes recombine, and may generate light having a red wavelength.
  • the active layer 142 may have any one of a single well structure, a multi well structure, a single quantum well structure, a multi quantum well (MQW) structure, a quantum dot structure, or a quantum line structure, and the active layer 142. ) Is not limited thereto.
  • the active layer 142 may be formed of a pair structure of any one or more of GaInP / AlGaInP, GaP / AlGaP, InGaP / AlGaP, InGaN / GaN, InGaN / InGaN, GaN / AlGaN, InAlGaN / GaN, GaAs / AlGaAs, InGaAs / AlGaAs.
  • the present invention is not limited thereto.
  • the thickness of the active layer 142 may be 0.54 ⁇ m to 0.66. However, the present invention is not limited thereto.
  • the first clad layer 144 may be disposed on the active layer 142.
  • the first clad may be disposed between the active layer 142 and the first conductive semiconductor layer 141.
  • the first clad layer 144 may include AlInP.
  • the thickness of the first cladding layer 144 may be 0.45 ⁇ m to 0.55 ⁇ m.
  • the present invention is not limited thereto.
  • the first conductivity type semiconductor layer 141 may be disposed on the first cladding layer 144.
  • the first conductive semiconductor layer 141 may be formed of a compound semiconductor such as a group III-V group or a group II-VI, and may be doped with a first dopant.
  • the first conductive semiconductor layer 141 may have InxAlyGa1-x-yP (0 ⁇ x ⁇ 1, 0 ⁇ y ⁇ 1, 0 ⁇ x + y ⁇ 1) or InxAlyGa1-x-yN (0 ⁇ x ⁇ 1, 0 It may include a semiconductor material having a composition formula of ⁇ y ⁇ 1, 0 ⁇ x + y ⁇ 1).
  • the first dopant may be an n-type dopant such as Si, Ge, Sn, Se, or Te.
  • the first conductive semiconductor layer 141 doped with the first dopant may be an n-type semiconductor layer.
  • the first conductive semiconductor layer 141 may include at least one of AlGaP, InGaP, AlInGaP, InP, GaN, InN, AlN, InGaN, AlGaN, InAlGaN, AlInN, AlGaAs, InGaAs, AlInGaAs, and GaP.
  • the first conductive semiconductor layer 141 may be formed using a chemical vapor deposition method (CVD), molecular beam epitaxy (MBE), sputtering or hydroxide vapor phase epitaxy (HVPE), but is not limited thereto.
  • CVD chemical vapor deposition method
  • MBE molecular beam epitaxy
  • HVPE hydroxide vapor phase epitaxy
  • the thickness of the first conductive semiconductor layer 141 may be 0.45 ⁇ m to 5.5 ⁇ m. However, the present invention is not limited thereto.
  • the first electrode 151 may be disposed on the first conductivity type semiconductor layer 141.
  • the first electrode 151 may be electrically connected to the first conductivity type semiconductor layer 141.
  • the first electrode 151 may be located above the second electrode 152.
  • the insulating layer 160 may cover the sacrificial layer 120, the coupling layer 130, the intermediate layer 170, the reflective layer 190, and the semiconductor structure 140.
  • the insulating layer 160 may cover side surfaces of the sacrificial layer 120, the coupling layer 130, the intermediate layer 170, the reflective layer 190, and the semiconductor structure 140.
  • the insulating layer 160 may cover a portion of the upper surface of the first electrode 151. A portion of the upper surface of the first electrode 151 may be exposed.
  • the insulating layer 160 may cover a portion of the upper surface of the second electrode 152. A portion of the upper surface of the second electrode 152 may be exposed.
  • FIG. 27 is a sectional view of a semiconductor device according to the sixth embodiment.
  • a semiconductor device may include a bonding layer 130 ′, an intermediate layer 170 disposed on the coupling layer 130 ′, a reflective layer 190 disposed on the intermediate layer 170, The first conductive semiconductor layer 141 disposed on the reflective layer 190, the first cladding layer 144 disposed on the first conductive semiconductor layer, and the active layer disposed on the first cladding layer 144 ( 142, a second conductive semiconductor layer 143 disposed on the active layer, a first electrode 151 electrically connected to the first conductive semiconductor layer, and an electrical connection with the second conductive semiconductor layer.
  • the second electrode 152 and the insulating layer 160 may be included.
  • the intermediate layer 170, the reflective layer 190, the first conductive semiconductor layer 141, the first cladding layer 144, the active layer 142, the second conductive semiconductor layer 143, and the first electrode 151 ) And the second electrode 152 and the insulating layer 160 may be the same as described above.
  • the bonding layer 130 ′ may include a material such as SiO 2, SiN x, TiO 2, polyimide, resin, or the like as the bonding layer 130.
  • the present invention is not limited thereto, and the sacrificial layer 120 and the coupling layer 130 may be disposed as shown in FIG. 20A.
  • the bonding layer 130 ′ may be removed during the laser lift-off (LLO).
  • 28A to 28H are flowcharts illustrating a method of manufacturing a semiconductor device according to the sixth embodiment.
  • the first substrate P may be disposed at the lowermost portion.
  • the first substrate P may use at least one of GaAs, sapphire (Al 2 O 3), SiC, Si, GaN, ZnO, GaP, InP, Ge, and Ga203.
  • An uneven structure may be formed on the first substrate P, but is not limited thereto. Impurities on the surface may be removed by wet cleaning the first substrate P. Referring to FIG.
  • the bonding layer 130 ′ may be disposed on the first substrate P. FIG.
  • the bonding layer 130 ′ may be removed while transferring the semiconductor device to the display device.
  • the bonding layer 130 ′ may be separated by a laser irradiated during the transfer.
  • the bonding layer 130 ′ may be formed to be separated at the wavelength of the irradiated laser.
  • the wavelength of the laser may be 532 nm or 1064 nm, but is not limited to this wavelength.
  • the bonding layer 130 ′ may be partially present under the intermediate layer 170 when transferred.
  • the bonding layer 130 ′ may include any one of C, O, N, and H, and the bonding layer 130 ′ may include a resin, but is not limited thereto.
  • the thickness of the bonding layer 130 ′ may be 6 ⁇ m to 8 ⁇ m. However, the present invention is not limited thereto. Here, the thickness may be a length in the stacking direction of each layer in the semiconductor device.
  • the intermediate layer 170 may be formed on the bonding layer 130 ′.
  • the reflective layer 190 may be sequentially formed on the intermediate layer 170.
  • first conductive semiconductor layer may be disposed on the reflective layer 190, and the first cladding layer 144, the active layer 142, and the second conductive semiconductor layer 143 may be formed in this order.
  • the first conductivity type semiconductor layer 141 may be disposed on the reflective layer 190.
  • the first conductive semiconductor layer 141 may be formed using a chemical vapor deposition method (CVD) or a molecular beam epitaxy (MBE) or a method such as sputtering or hydroxide vapor phase epitaxy (HVPE), but is not limited thereto. .
  • CVD chemical vapor deposition method
  • MBE molecular beam epitaxy
  • HVPE hydroxide vapor phase epitaxy
  • the first clad layer 144 may be disposed on the first conductive semiconductor layer 141.
  • the first clad layer 144 may be disposed between the first conductivity type semiconductor layer 141 and the active layer 142.
  • the first clad layer 144 may include a plurality of layers.
  • the first clad layer 144 may include an AlInP-based layer / AlInGaP-based layer.
  • the active layer 142 may be disposed on the first clad layer 144.
  • the active layer 142 may be disposed between the first conductivity type semiconductor layer 141 and the second conductivity type semiconductor layer 143b.
  • the active layer 142 is a layer where electrons (or holes) injected through the first conductivity type semiconductor layer 141 and holes (or electrons) injected through the 2-1 conductivity type semiconductor layer 143a meet each other.
  • the active layer 142 may transition to a low energy level as electrons and holes recombine, and may generate red light.
  • the active layer 142 may have any one of a single well structure, a multi well structure, a single quantum well structure, a multi quantum well (MQW) structure, a quantum dot structure, or a quantum line structure, and the active layer 142. ) Is not limited thereto.
  • the second conductivity type semiconductor layer 143 may be disposed on the active layer 142.
  • the second conductive semiconductor layer 143 may include a 2-1 conductive semiconductor layer 143a and a 2-2 conductive semiconductor layer 143b.
  • the second-second conductivity type semiconductor layer 143b may include a superlattice structure of a GaP layer / InxGa1-xP layer (where 0 ⁇ x ⁇ 1).
  • Mg having a concentration of about 10 ⁇ 10 18 may be doped into the 2-2 conductivity type semiconductor layer 143b, but is not limited thereto.
  • the second conductive semiconductor layer 143b may be formed of a plurality of layers, Mg may be doped only in some layers, but is not limited thereto.
  • the second substrate 2 may be disposed on the second conductive semiconductor layer 143.
  • the second substrate 2 may be disposed on the second-second conductive semiconductor layer 143b.
  • An adhesive layer may be disposed between the second substrate 2 and the second conductive semiconductor layer 143 so that the second substrate 2 may be connected to the second conductive semiconductor layer 143.
  • the second substrate 2 may be a conductive substrate and / or an insulating substrate.
  • the second substrate 2 may include a sapphire substrate, but is not limited thereto.
  • the first substrate P may be separated from the semiconductor device.
  • the first substrate P may be removed by a process such as laser lift-off.
  • the bonding layer 170 and the substrate 110 may be disposed on the intermediate layer 170.
  • the bonding layer 170 may be partially disposed on the intermediate layer 170, and may be partially disposed below the substrate 110, and then may be bonded to each other by the intermediate layer 170 and the substrate 110 by annealing or the like. However, it is not limited to this method.
  • the substrate 110 may be a sapphire substrate, and a laser beam emitted when the substrate 110 is transferred to the display device may be transmitted.
  • a laser beam emitted when the substrate 110 is transferred to the display device may be transmitted.
  • the irradiated laser wavelength is 532 nm or 1064 nm
  • the laser of 532 nm or 1064 nm wavelength may be transmitted through the substrate 110 and absorbed by the bonding layer 130 ′.
  • the bonding layer 130 ′ may be separated by the irradiated laser.
  • the second substrate 2 may be removed by laser lift off (LLO).
  • LLO laser lift off
  • primary etching may be performed from a portion of the semiconductor device to a portion of the first conductive semiconductor layer 141.
  • the primary etching may be by wet etching or dry etching, but is not limited thereto.
  • a portion of an upper surface of the first conductivity type semiconductor layer 141 may be exposed by primary etching.
  • the second electrode 152 may be disposed on the semiconductor device.
  • the second electrode 152 may be electrically connected to the second-second conductive semiconductor layer 143b.
  • the first electrode 151 may be disposed on the first conductive semiconductor layer 141.
  • the first electrode 151 and the second electrode 152 may be applied to all of the electrode forming methods commonly used, such as stuffing, coating, and deposition. However, the present invention is not limited thereto.
  • the first electrode 151 and the second electrode 152 may be disposed at different positions from the substrate 110.
  • the second electrode 152 may be disposed above the first electrode 151.
  • the present invention is not limited thereto.
  • the first electrode 151 is disposed above the second electrode 152.
  • Secondary etching may be performed to the upper surface of the substrate 110. Secondary etching may be by wet etching or dry etching, but is not limited thereto.
  • the secondary etching may etch a thickness larger than the primary etching, but is not limited thereto.
  • secondary etching may be performed up to the bonding layer 130 ′.
  • the semiconductor device disposed on the substrate 110 through secondary etching may be isolated in the form of a plurality of chips.
  • the protective layer 160 may be disposed on the protective layer 160.
  • the protective layer 160 includes a bonding layer 130 ′, an intermediate layer 170, a reflective layer 190, and a first conductive semiconductor layer 141, a first cladding layer 144, an active layer 142, and a second conductive type.
  • the side surface of the semiconductor layer 143 may be covered.
  • the protective layer 160 may cover up to a portion of the upper surface of the first electrode 151. A portion of the upper surface of the first electrode 151 may be exposed.
  • the protective layer 160 may cover a portion of the upper surface of the second electrode 152. A portion of the upper surface of the second electrode 152 may be exposed.
  • a portion of the protective layer 160 may be disposed on the top surface of the substrate 110. A portion of the protective layer 160 may be disposed between adjacent semiconductor chips. As described above, the protective layer 160 may be an insulating layer.
  • the protective layer 160 may be formed by selecting at least one selected from the group consisting of SiO 2, SixOy, Si 3 N 4, SixNy, SiO x Ny, Al 2 O 3, TiO 2, AlN, and the like, but is not limited thereto.
  • FIG. 29 is a modification of FIG. 27.
  • the semiconductor device may have a shape in which positions of the first conductive semiconductor layer and the second conductive semiconductor layer are changed in FIG. 28.
  • the first electrode 151 may be disposed below the second electrode 152.
  • the semiconductor device according to the modified example is disposed on the coupling layer 130 ′, the intermediate layer 170 disposed on the coupling layer 130 ′, the reflective layer 190 disposed on the intermediate layer 170, and the reflective layer 190.
  • the semiconductor structure 140 may include a first electrode 151 and a second electrode 152.
  • the semiconductor structure 140 is disposed between the first conductivity type semiconductor layer 141, the second conductivity type semiconductor layer 143, and the first conductivity type semiconductor layer 141 and the second conductivity type semiconductor layer 143b.
  • the active layer 142 may be included.
  • the second conductive semiconductor layer 143 may include a 2-1 conductive semiconductor layer 143a disposed adjacent to the active layer and a 2-2 conductive semiconductor layer 143b disposed adjacent to the intermediate layer. have.
  • the first electrode 151 connected to the first conductive semiconductor layer 141 and the second electrode 152 and the coupling layer 130 ′ connected to the second-second conductive semiconductor layer 143b and the semiconductor It may include an insulating layer 160 covering the structure 140.
  • the bonding layer 130 ′, the intermediate layer 170, and the reflective layer 190 may be applied in the same manner as described with reference to FIG. 27.
  • the second-2 conductivity type semiconductor layer 143b may be disposed on the intermediate layer 170.
  • the 2-2 conductivity type semiconductor layer 143b may be disposed on the 2-1 conductivity type semiconductor layer 143a.
  • the second-second conductive semiconductor layer 143b may include a p-type GaP-based layer.
  • the second-second conductivity type semiconductor layer 143b may include a superlattice structure of a GaP layer / InxGa1-xP layer (where 0 ⁇ x ⁇ 1).
  • the second electrode 152 may be disposed on the second-second conductive semiconductor layer 143b.
  • the second-second conductive semiconductor layer 143b may be electrically connected to the second electrode 152.
  • the second electrode 152 may be disposed on one side of the top surface of the 2-2 conductivity type semiconductor layer 143b. The second electrode 152 may be located below the first electrode 151.
  • the 2-1 conductive semiconductor layer 143a may be disposed on the 2-2 conductive semiconductor layer 143b.
  • the 2-1 conductive semiconductor layer 143a may be disposed between the 2-2 conductive semiconductor layer 143b and the active layer 142.
  • the 2-1 conductive semiconductor layer 143a may have InxAlyGa1-x-yP (0 ⁇ x ⁇ 1, 0 ⁇ y ⁇ 1, 0 ⁇ x + y ⁇ 1) or InxAlyGa1-x-yN (0 ⁇ x ⁇ 1 , 0 ⁇ y ⁇ 1, 0 ⁇ x + y ⁇ 1).
  • the p-type dopant may include Mg, Zn, Ca, Sr, Ba, or the like.
  • the 2-1 conductive semiconductor layer 143a may be a p-type semiconductor layer when the 2-1 conductive semiconductor layer 143a doped with the second dopant is doped.
  • the 2-1 conductive semiconductor layer 143a may include TSBR and AlInP.
  • the active layer 142 may be disposed on the 2-1 conductive semiconductor layer 143a.
  • the active layer 142 is a layer where electrons (or holes) injected through the first conductivity type semiconductor layer 141 and holes (or electrons) injected through the 2-1 conductivity type semiconductor layer 143a meet each other.
  • the active layer 142 may transition to a low energy level as electrons and holes recombine, and may generate red light.
  • the active layer 142 may have any one of a single well structure, a multi well structure, a single quantum well structure, a multi quantum well (MQW) structure, a quantum dot structure, or a quantum line structure, and the active layer 142. ) Is not limited thereto.
  • the active layer 142 may be formed of a pair structure of any one or more of GaInP / AlGaInP, GaP / AlGaP, InGaP / AlGaP, InGaN / GaN, InGaN / InGaN, GaN / AlGaN, InAlGaN / GaN, GaAs / AlGaAs, InGaAs / AlGaAs.
  • the present invention is not limited thereto.
  • the first clad layer 144 may be disposed on the active layer 142.
  • the first clad may be disposed between the active layer 142 and the first conductive semiconductor layer 141.
  • the first clad layer 144 may include AlInP.
  • the first conductivity type semiconductor layer 141 may be disposed on the first cladding layer 144.
  • the first conductive semiconductor layer 141 may be formed of a compound semiconductor such as a group III-V group or a group II-VI, and may be doped with a first dopant.
  • the first conductive semiconductor layer 141 may have InxAlyGa1-x-yP (0 ⁇ x ⁇ 1, 0 ⁇ y ⁇ 1, 0 ⁇ x + y ⁇ 1) or InxAlyGa1-x-yN (0 ⁇ x ⁇ 1, 0 It may include a semiconductor material having a composition formula of ⁇ y ⁇ 1, 0 ⁇ x + y ⁇ 1).
  • the first dopant may be an n-type dopant such as Si, Ge, Sn, Se, or Te.
  • the first conductive semiconductor layer 141 doped with the first dopant may be an n-type semiconductor layer.
  • the first conductive semiconductor layer 141 may include at least one of AlGaP, InGaP, AlInGaP, InP, GaN, InN, AlN, InGaN, AlGaN, InAlGaN, AlInN, AlGaAs, InGaAs, AlInGaAs, and GaP.
  • the first conductive semiconductor layer 141 may be formed using a chemical vapor deposition method (CVD), molecular beam epitaxy (MBE), sputtering or hydroxide vapor phase epitaxy (HVPE), but is not limited thereto.
  • CVD chemical vapor deposition method
  • MBE molecular beam epitaxy
  • HVPE hydroxide vapor phase epitaxy
  • the first electrode 151 may be disposed on the first conductivity type semiconductor layer 141.
  • the first electrode 151 may be electrically connected to the first conductivity type semiconductor layer 141.
  • the first electrode 151 may be located above the second electrode 152.
  • the insulating layer 160 may cover the coupling layer 130 ′, the intermediate layer 170, the reflective layer 190, and the semiconductor structure 140.
  • the insulating layer 160 may cover side surfaces of the coupling layer 130 ′, the intermediate layer 170, the reflective layer 190, and the semiconductor structure 140.
  • the insulating layer 160 may cover a portion of the upper surface of the first electrode 151. A portion of the upper surface of the first electrode 151 may be exposed. The insulating layer 160 may cover a portion of the upper surface of the second electrode 152. A portion of the upper surface of the second electrode 152 may be exposed.
  • FIG. 30 is a conceptual diagram of a display device to which a semiconductor device is transferred according to an exemplary embodiment.
  • a display device including a semiconductor device includes a second panel substrate 410, a driving thin film transistor T2, a planarization layer 430, a common electrode CE, and a pixel electrode AE. And a semiconductor device 10.
  • the driving thin film transistor T2 includes a gate electrode GE, a semiconductor layer SCL, an ohmic contact layer OCL, a source electrode SE, and a drain electrode DE.
  • the driving thin film transistor is a driving device and is electrically connected to the semiconductor device 10 to drive the semiconductor device.
  • the gate electrode GE may be formed together with the gate line.
  • the gate electrode GE may be covered with the gate insulating layer 440.
  • the gate insulating layer 440 may be formed of a single layer or a plurality of layers made of an inorganic material, and may be formed of silicon oxide (SiOx), silicon nitride (SiNx), or the like.
  • the semiconductor layer SCL may be disposed on the gate insulating layer 440 in a predetermined pattern (or island) form so as to overlap the gate electrode GE.
  • the semiconductor layer SCL may be formed of a semiconductor material including any one of amorphous silicon, polycrystalline silicon, oxide, and organic material, but is not limited thereto.
  • the ohmic contact layer OCL may be disposed on the semiconductor layer SCL in a predetermined pattern (or island) form.
  • the ohmic contact layer PCL may be for an ohmic contact between the semiconductor layer SCL and the source / drain electrodes SE and DE.
  • the source electrode SE is formed on one side of the ohmic contact layer OCL to overlap one side of the semiconductor layer SCL.
  • the drain electrode DE may be formed on the other side of the ohmic contact layer OCL to be spaced apart from the source electrode SE while overlapping the other side of the semiconductor layer SCL.
  • the drain electrode DE may be formed together with the source electrode SE.
  • the planarization layer may be disposed on an entire surface of the second panel substrate 410.
  • the driving thin film transistor T2 may be disposed in the planarization layer.
  • the planarization layer according to an embodiment may include an organic material such as benzocyclobutene or photo acryl, but is not limited thereto.
  • the groove 450 may be a predetermined emission region, and a semiconductor device may be disposed.
  • the light emitting area may be defined as a remaining area of the display apparatus except for a circuit area.
  • the groove 450 may be concave in the planarization layer 430, but is not limited thereto.
  • the semiconductor device 10 may be disposed in the groove 450.
  • the first and second electrodes of the semiconductor device may be connected to a circuit (not shown) of the display device.
  • the semiconductor device 10 may be attached to the groove 450 through the adhesive layer 420.
  • the adhesive layer 420 may be the second bonding layer, but is not limited thereto.
  • the second electrode 152 of the semiconductor device 10 may be electrically connected to the source electrode SE of the driving thin film transistor T2 through the pixel electrode AE.
  • the first electrode 151 of the semiconductor device 10 may be connected to the common power line CL through the common electrode CE.
  • the first and second electrodes 151 and 152 may be stepped with each other, and the electrode 151 at a relatively lower position among the first and second electrodes 151 and 152 may be the same as the top surface of the planarization layer 430. It can be located on a horizontal line. However, the present invention is not limited thereto.
  • the pixel electrode AE may electrically connect the source electrode SE of the driving thin film transistor T2 and the second electrode of the semiconductor device.
  • the common electrode CE may electrically connect the common power line CL and the first electrode of the semiconductor device.
  • the pixel electrode AE and the common electrode CE may each include a transparent conductive material.
  • the transparent conductive material may include a material such as indium tin oxide (ITO) or indium zinc oxide (IZO), but is not limited thereto.
  • SD standard definition
  • HD high definition
  • HD full HD
  • UH. Ultra HD
  • the display device may be a display panel or a TV having a diagonal size of 100 inches or more, and the pixel may be implemented as a light emitting diode (LED).
  • LED light emitting diode
  • the embodiment implements an image and an image by using a semiconductor device, color purity and color reproduction are excellent.
  • an image and an image are implemented using a semiconductor device package having excellent linearity, thereby enabling a clear large display device of 100 inches or more.
  • the embodiment can realize a high resolution 100 inch or larger display device at low cost.
  • the semiconductor device according to the embodiment may further include an optical member such as a light guide plate, a prism sheet, and a diffusion sheet to function as a backlight unit.
  • the semiconductor device of the embodiment may be further applied to a display device, a lighting device, and a pointing device.
  • the display device may include a bottom cover, a reflector, a light emitting module, a light guide plate, an optical sheet, a display panel, an image signal output circuit, and a color filter.
  • the bottom cover, the reflector, the light emitting module, the light guide plate, and the optical sheet may form a backlight unit.
  • the reflecting plate is disposed on the bottom cover, and the light emitting module emits light.
  • the light guide plate is disposed in front of the reflective plate to guide light emitted from the light emitting module to the front, and the optical sheet includes a prism sheet or the like and is disposed in front of the light guide plate.
  • the display panel is disposed in front of the optical sheet, the image signal output circuit supplies the image signal to the display panel, and the color filter is disposed in front of the display panel.
  • the lighting apparatus may include a light source module including a substrate and a semiconductor device of an embodiment, a heat dissipation unit for dissipating heat of the light source module, and a power supply unit for processing or converting an electrical signal provided from the outside and providing the light source module to the light source module.
  • the lighting device may include a lamp, a head lamp, a street lamp or the like.
  • the camera flash of the mobile terminal may include a light source module including the semiconductor device of the embodiment.
  • SD standard definition
  • HD high definition
  • HD full HD
  • UH. Ultra HD
  • the display device may be a display panel or a TV having a diagonal size of 100 inches or more, and the pixel may be implemented as a light emitting diode (LED).
  • LED light emitting diode
  • the embodiment implements an image and an image by using a semiconductor chip, color purity and color reproduction are excellent.
  • the embodiment implements an image and an image by using a light emitting device package having excellent linearity, thereby enabling a clear large display device of 100 inches or more.
  • the embodiment can realize a high resolution 100 inch or larger display device at low cost.
  • the semiconductor chip according to the embodiment may further include an optical member such as a light guide plate, a prism sheet, and a diffusion sheet to function as a backlight unit.
  • the semiconductor chip of the embodiment may be further applied to a display device, a lighting device, and a pointing device.
  • the display device may include a bottom cover, a reflector, a light emitting module, a light guide plate, an optical sheet, a display panel, an image signal output circuit, and a color filter.
  • the bottom cover, the reflector, the light emitting module, the light guide plate, and the optical sheet may form a backlight unit.
  • the reflecting plate is disposed on the bottom cover, and the light emitting module emits light.
  • the light guide plate is disposed in front of the reflective plate to guide light emitted from the light emitting module to the front, and the optical sheet includes a prism sheet or the like and is disposed in front of the light guide plate.
  • the display panel is disposed in front of the optical sheet, the image signal output circuit supplies the image signal to the display panel, and the color filter is disposed in front of the display panel.
  • the lighting apparatus may include a light source module including a substrate and a semiconductor chip of an embodiment, a heat dissipation unit for dissipating heat of the light source module, and a power supply unit for processing or converting an electrical signal provided from the outside and providing the light source module to the light source module.
  • the lighting device may include a lamp, a head lamp, a street lamp or the like.
  • the camera flash of the mobile terminal may include a light source module including the semiconductor chip of the embodiment.

Landscapes

  • Led Devices (AREA)
  • Control Of El Displays (AREA)
  • Burglar Alarm Systems (AREA)

Abstract

Dans un mode de réalisation, l'invention concerne un dispositif à semiconducteur comprenant : un substrat; une couche de couplage disposée sur le substrat; une structure semiconductrice qui comprend une première couche semiconductrice conductrice, une seconde couche semiconductrice conductrice, et une couche active disposée entre la première couche semiconductrice conductrice et la seconde couche semiconductrice conductrice et qui est disposée sur la couche de couplage; une première électrode connectée à la première couche semiconductrice conductrice; une seconde électrode connectée à la seconde couche semiconductrice conductrice; et une couche d'isolation pour recouvrir la couche de couplage et la structure semiconductrice.
PCT/KR2018/001518 2017-02-06 2018-02-05 Dispositif à semiconducteur et dispositif d'affichage le comprenant WO2018143751A1 (fr)

Applications Claiming Priority (6)

Application Number Priority Date Filing Date Title
KR10-2017-0016228 2017-02-06
KR1020170016228A KR102633028B1 (ko) 2017-02-06 2017-02-06 반도체 소자 및 이를 포함하는 디스플레이 장치
KR1020170106702A KR102332450B1 (ko) 2017-08-23 2017-08-23 반도체 소자
KR10-2017-0106702 2017-08-23
KR1020170145897A KR102385209B1 (ko) 2017-11-03 2017-11-03 반도체 소자
KR10-2017-0145897 2017-11-03

Publications (1)

Publication Number Publication Date
WO2018143751A1 true WO2018143751A1 (fr) 2018-08-09

Family

ID=63040912

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/KR2018/001518 WO2018143751A1 (fr) 2017-02-06 2018-02-05 Dispositif à semiconducteur et dispositif d'affichage le comprenant

Country Status (2)

Country Link
TW (1) TWI767986B (fr)
WO (1) WO2018143751A1 (fr)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111580289A (zh) * 2020-05-22 2020-08-25 联合微电子中心有限责任公司 制作半导体器件的方法、半导体器件和半导体集成电路
US11522112B2 (en) * 2019-02-01 2022-12-06 Lextar Electronics Corporation Light emitting diode and manufacturing method thereof

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP7312056B2 (ja) * 2019-01-07 2023-07-20 日機装株式会社 半導体発光素子および半導体発光素子の製造方法
TWI685162B (zh) * 2019-05-30 2020-02-11 宏捷科技股份有限公司 面射型雷射的製造方法
US10971650B2 (en) * 2019-07-29 2021-04-06 Lextar Electronics Corporation Light emitting device
JP7472354B1 (ja) * 2023-04-04 2024-04-22 日機装株式会社 半導体発光素子および半導体発光素子の製造方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009277898A (ja) * 2008-05-15 2009-11-26 Hitachi Cable Ltd 半導体発光素子及び半導体発光素子の製造方法
JP2014056984A (ja) * 2012-09-13 2014-03-27 Stanley Electric Co Ltd 半導体発光素子、車両用灯具及び半導体発光素子の製造方法
US20140252388A1 (en) * 2013-03-06 2014-09-11 Kabushiki Kaisha Toshiba Semiconductor light emitting element and method for manufacturing same
KR20150142373A (ko) * 2014-06-11 2015-12-22 엘지이노텍 주식회사 발광 소자 및 그를 포함하는 발광소자 패키지
KR20160014263A (ko) * 2014-07-29 2016-02-11 엘지이노텍 주식회사 발광 소자 및 발광 소자 패키지

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009277898A (ja) * 2008-05-15 2009-11-26 Hitachi Cable Ltd 半導体発光素子及び半導体発光素子の製造方法
JP2014056984A (ja) * 2012-09-13 2014-03-27 Stanley Electric Co Ltd 半導体発光素子、車両用灯具及び半導体発光素子の製造方法
US20140252388A1 (en) * 2013-03-06 2014-09-11 Kabushiki Kaisha Toshiba Semiconductor light emitting element and method for manufacturing same
KR20150142373A (ko) * 2014-06-11 2015-12-22 엘지이노텍 주식회사 발광 소자 및 그를 포함하는 발광소자 패키지
KR20160014263A (ko) * 2014-07-29 2016-02-11 엘지이노텍 주식회사 발광 소자 및 발광 소자 패키지

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11522112B2 (en) * 2019-02-01 2022-12-06 Lextar Electronics Corporation Light emitting diode and manufacturing method thereof
CN111580289A (zh) * 2020-05-22 2020-08-25 联合微电子中心有限责任公司 制作半导体器件的方法、半导体器件和半导体集成电路
CN111580289B (zh) * 2020-05-22 2023-07-18 联合微电子中心有限责任公司 制作半导体器件的方法、半导体器件和半导体集成电路

Also Published As

Publication number Publication date
TWI767986B (zh) 2022-06-21
TW201836143A (zh) 2018-10-01

Similar Documents

Publication Publication Date Title
WO2019103566A1 (fr) Unité de del pour affichage et appareil d'affichage doté de celle-ci
WO2018143751A1 (fr) Dispositif à semiconducteur et dispositif d'affichage le comprenant
WO2019135606A1 (fr) Dispositif électroluminescent avec empilement de del pour afficheur et appareil d'affichage le comprenant
WO2019117656A1 (fr) Structure empilée électroluminescente et dispositif d'affichage la comprenant
WO2011083923A2 (fr) Diodes électroluminescentes comportant des pastilles d'électrodes
WO2017160119A1 (fr) Dispositif à semi-conducteurs et dispositif d'affichage le comprenant
WO2017222279A1 (fr) Dispositif semi-conducteur
WO2017191923A1 (fr) Diode électroluminescente
WO2019054547A1 (fr) Boîtier de dispositif électroluminescent et appareil d'éclairage le comprenant
WO2017183944A1 (fr) Dispositif électroluminescent et afficheur le comprenant
WO2019004518A1 (fr) Boîtier de dispositif électroluminescent et appareil source de lumière
WO2018048275A1 (fr) Dispositif semi-conducteur
WO2016129873A2 (fr) Élément électroluminescent et diode électroluminescente
WO2013141561A1 (fr) Procédé de séparation de couches épitaxiales et de substrats de croissance, et dispositif semi-conducteur l'utilisant
WO2018164371A1 (fr) Dispositif à semi-conducteur et boîtier de dispositif à semi-conducteur
WO2015190817A1 (fr) Élément électroluminescent à semi-conducteur
WO2018139877A1 (fr) Dispositif à semiconducteur
WO2019074149A1 (fr) Boîtier d'élément électroluminescent et élément de source de lumière
WO2019054793A1 (fr) Boîtier de dispositif électroluminescent
WO2019045513A1 (fr) Boîtier d'élément électroluminescent et dispositif d'éclairage le comprenant
WO2017026753A1 (fr) Diode électroluminescente et boîtier de diode électroluminescente
WO2018139770A1 (fr) Dispositif à semi-conducteur et boîtier de dispositif à semi-conducteur
WO2019132490A1 (fr) Dispositif à semi-conducteurs
WO2019045166A1 (fr) Boîtier de dispositif électroluminescent
WO2019054548A1 (fr) Boîtier de dispositif électroluminescent

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 18747278

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 18747278

Country of ref document: EP

Kind code of ref document: A1