WO2018149109A1 - Multi-layer one-time programmable permanent memory unit and preparation method therefor - Google Patents

Abstract

Disclosed are a multi-layer one-time programmable permanent memory unit and a preparation method therefor, relating to memory technology. Provided is the multi-layer one-time programmable permanent memory unit, including: at least two layers of one-time programmable permanent memory modules, with one layer being stacked on the other layer, wherein each layer of the at least two layers of one-time programmable permanent memory modules includes M rows and N columns made of reversely doped semiconductor materials; M and N are positive integers greater than 1; thin insulating dielectric materials are arranged at the intersections of the M rows and the N columns of each layer of the at least two layers of one-time programmable permanent memory modules and between the M rows and the N columns; and the thin insulating dielectric materials are arranged on either the top face or the bottom face of each one of the M rows and the N columns. The multi-layer OTP permanent memory unit of the present invention has a high memory density.

Description

Multi-layer one-time programmable permanent memory unit and preparation method thereof Technical field

The present invention relates to memory technology.

Background technique

The memory device and method of fabrication disclosed herein are related to mass data storage. More particularly, the memory devices and methods of fabrication disclosed herein relate to one time programmable (OTP) persistent memory technology.

Includes Erasable Programmable Read Only Memory (EPROM), EEPROM, Flash, NAND-Flash, Hard Disk, CD, Digital Versatile Disc (DVD), Blu-ray Disc Various digital storage technologies, such as Blu-ray Discs registered by the Association, have been widely used for data storage for more than 50 years. However, the life of a storage medium is typically less than 5 to 10 years. Anti-fuse storage technology developed for big data storage, because it is very expensive and has low storage density, cannot meet the demand for massive data storage.

Therefore, for mass data storage, there is a need for a high-density, low-cost multi-layer one-time programmable (OTP) permanent storage unit that can store data for a relatively long period of time under harsh environmental conditions. In addition, there is a need for a method of fabricating a multilayer OTP permanent memory cell in which an inversely doped semiconductor layer (eg, polysilicon, single crystal silicon, or amorphous silicon, etc.) is stacked on both sides of a thin dielectric layer to form an antifuse. Programmable diode storage array.

Summary of the invention

This section is a summary of the summary of the invention, and the basic concepts of the invention are described in a simplified form and are further disclosed in the detailed description of the invention. This abstract is not intended to identify the scope of the subject matter of the claims.

The memory device disclosed by the present invention relates to the above-described high-density, high-reliability and low-cost multi-layer one-time programmable (OTP) permanent memory unit for mass data storage, which can store data for a relatively long period of time under harsh environmental conditions. . In addition, the present invention discloses a method for preparing the above-mentioned multilayer OTP permanent memory cell, in which a reverse-doped semiconductor material (for example, polysilicon, single crystal silicon, etc.) is superposed on both sides of a thin dielectric layer to form an anti-fuse. Program the diode storage array.

The disclosed multi-layer one-time programmable (OTP) permanent memory cell includes at least two layers of OTP permanent memory modules stacked one on top of the other and a layer of insulating dielectric material. Each layer of OTP permanent memory module includes M rows and N columns made of a counter-doped semiconductor material, where M and N are positive integers greater than one. In one embodiment, the disclosed one-time programmable (OTP) permanent memory module of a multi-layer OTP permanent memory includes M rows and N columns of conductors. A thin insulating dielectric material is located at the intersection of the M rows and N columns of each OTP permanent memory module, and the top or bottom surface of each M row and each N column of each OTP permanent memory module. In addition, a thin insulating dielectric material is located between the M rows and the N columns of each OTP permanent memory module. The M rows of each layer of OTP permanent memory modules are made of p-type semiconductor material or n-type semiconductor material, while the N columns of each layer of OTP permanent memory modules are made of oppositely doped semiconductor materials. That is, if the M rows of each layer of the OTP permanent memory module are made of a p-type semiconductor material, the N columns of each layer of the OTP permanent memory module are made of an n-type semiconductor material, and vice versa.

Each layer of OTP persistent memory modules is stacked bottom-up, connected at the intersection between the OTP permanent memory modules and the intersection between the M rows and N columns of the various layers of OTP permanent memory modules. The M rows of each layer of OTP permanent memory modules are located at the top or bottom of the N columns. The multi-layered OTP persistent memory unit disclosed herein also includes a plurality of OTP programmable memory cells formed at the intersection between the intersection of M rows and N columns of the OTP permanent memory module and the OTP programmable permanent memory module. Each of the OTP memory cells includes a p-type semiconductor region, an n-type semiconductor region, and a thin insulating dielectric region between the p-type semiconductor region and the n-type semiconductor region. Each of the OTP memory cells further includes at least two connection terminals located in the p-type semiconductor region and the n-type semiconductor region of each of the OTP memory cells. The connection terminals of each OTP memory cell are connected to each other using conductive vias (made of metal or doped polysilicon or other conductive material). A predetermined value of the thickness of the thin insulating dielectric material forming the thin insulating dielectric region of each OTP memory cell corresponds to the breakdown voltage of each OTP memory cell. A thin insulating dielectric material, exemplified by silicon dioxide (SiO2), has a thickness ranging from 0.5 nanometers (nm) to 4 nm corresponding to a breakdown voltage of about 3 volts to 10 volts.

The present invention also discloses a method of fabricating a multilayer one-time programmable (OTP) permanent memory cell using planar deposition and etching of a semiconductor such as polysilicon or silicon. The method of the present invention includes using a deposition process or an epitaxial process to dispose a semiconductor material on a top planar surface of a wafer containing completed memory peripheral circuits; forming an inversely doped p-type or n-type semiconductor using an ion implantation process or a diffusion process Material Removing a redundant portion of the reverse-phase doped semiconductor material using a photolithography mask process and an etching process to form a strip-shaped semiconductor for forming M rows or N columns of the OTP permanent memory; using a planarization process, filling with an insulating dielectric material has been formed a strip-shaped semiconductor material of M rows or columns of OTP permanent memory modules; using a chemical mechanical polishing process to remove excess portions of strip-shaped semiconductors filled with insulating dielectric material overflowing M rows or columns of OTP permanent memory modules; using a thermal oxidation process, A low temperature chemical vapor deposition process or an atomic layer deposition (ALD) process, creating a thin insulating dielectric film, such as silicon dioxide (SiO2), on top of the already filled OTP permanent memory module M rows or N columns of strip semiconductor material. The above method is repeated to a predetermined number of times, and each layer of OTP permanent memory modules built up from the bottom up is stacked symmetrically up and down to form a multi-layer OTP permanent memory unit.

Another method of making a multi-layer one-time programmable (OTP) permanent memory cell is also disclosed. The method includes: depositing a thick insulating dielectric material on a flat top surface of a wafer containing completed memory peripheral circuits; using a mask etching process, a plasma etching process, and depositing a thick insulating dielectric material Forming a trench on the layer as the row or column of the OTP permanent memory module; depositing a semiconductor material in the trench being constructed; using a diffusion or ion implantation process to invert the p-type or n-type impurity in the deposited semiconductor material Doping; using a conventional planarization process to remove excess deposited doped semiconductor material from the inversely doped semiconductor material to form M rows or N columns of the OTP permanent memory module; using a thermal oxidation process or a thermal deposition process or An ALD (Atomic Layer Deposition) process is used to create an insulating dielectric film on M rows or N columns of the OTP permanent memory module; the above method is repeated a predetermined number of times, using each layer of OTP permanent memory modules built up from the bottom up, Stacked symmetrically to form a multi-layer OTP permanent memory cell. A thin insulating dielectric film on the M or N columns of the OTP permanent memory module is used as a programmable dielectric material.

The method disclosed herein forms a multilayer one-time programmable (OTP) permanent memory cell using an anti-fuse mechanism such as "poly/thin oxide/poly", where "poly" refers to polysilicon and thin oxide refers to thin Insulated dielectric material. The methods disclosed herein, such as stacking p-poly/thin oxide/n-poly/thin oxide/p-poly/thin oxide, form a vertical multilayer high density memory, where "p-poly" refers to p-type Doped polysilicon and "n-poly" refer to n-type doped polysilicon. In one embodiment, the doped polysilicon is replaced by silicon (Si). In one embodiment, the thin oxide is thermally grown or deposited over the bottom polysilicon layer. Thin oxides can also be replaced by other dielectric films, such as nitrides or combinations of oxides and nitrides. Each layer of a multi-layer OTP permanent memory cell consisting of inverted doped polysilicon or silicon at the bottom and top Programmable p-n junction diodes significantly increase stack storage density at low cost. A multi-layer memory array in a multi-layer OTP permanent memory cell, including a programmable diode. N-channel metal oxide semiconductor (NMOS) transistors and P-channel metal oxide semiconductor (PMOS) transistors are used for programming circuits, detection circuits, and decoding circuits. For example, a programmable diode defined by a p-poly/thin oxide/n-poly block reverse current from biased to unselected and unselected columns. P-type polysilicon and n-type polysilicon are also used as row and column connections, eliminating the need for expensive metal lines on top of each polysilicon for increased storage density.

The multi-layer one-time programmable (OTP) permanent memory unit disclosed by the present invention is an OTP permanent memory unit with high density and low cost. The prepared multilayer OTP permanent memory cell has a high storage density. For example, the method disclosed herein can produce a 10 terabyte (TB) multilayer OTP permanent memory using a 10 nanometer (nm) silicon process on a 25 mm by 25 mm area chip. The resulting multi-layer OTP permanent memory cell has a very small form factor and a permanent data retention lifetime, for example, greater than 100 years.

In one or more embodiments, the related system includes circuitry for implementing the methods disclosed herein. The circuit can be any combination of hardware and/or firmware to configure the disclosed method in accordance with the design choices of the system designer. In addition, various structural elements can be used depending on the design choice of the system designer.

DRAWINGS

The above summary of the invention, as well as the following detailed description, In order to explain the present invention, an exemplary structure of the present invention is shown in the accompanying drawings. However, the invention is not limited to the specific methods and components disclosed herein. The description of the method steps or components in the figures, which are referenced in the figures, are applied to the description of the method steps or components in the subsequent figures.

Figure 1 illustrates a perspective view of a single layer one time programmable memory module in a multi-layer, one time programmable permanent memory unit.

2 illustrates a perspective view of a multi-layer, one-time programmable permanent memory unit stacked from two layers of one-time programmable permanent memory modules.

Figure 3 illustrates a block diagram of a one-time programmable memory unit.

FIG. 4 illustrates a circuit diagram of the one-time programmable memory cell shown in FIG.

Figure 5 illustrates a perspective view of a single layer one-time programmable permanent memory module embodiment of a one-time programmable memory cell formed at the intersection of rows and columns of a one-time programmable permanent memory module.

Figure 6 illustrates a one-time programmable memory cell formed at the intersection of rows and columns of a one-time programmable permanent memory module as shown in Figure 5.

Figure 7 illustrates a partial front view of a multi-layer, one-time programmable permanent memory unit.

Figure 8 illustrates a circuit diagram of a multi-layer one-time programmable permanent memory cell as shown in Figure 7.

Figure 9 illustrates a partial side view of one embodiment of a multi-layer disposable programmable memory cell.

Figure 10 illustrates a circuit diagram of one embodiment of the multi-layer one-time programmable permanent memory unit of Figure 9.

Figure 11 illustrates a top view of a multi-layer disposable programmable permanent memory unit.

Figure 12 illustrates a front view of a plurality of one time programmable permanent memory module layers stacked in a bottom-up direction to form a multi-layer disposable programmable memory unit.

Figure 13 illustrates a side view showing one embodiment of a one-time programmable permanent memory module stacked in a bottom-up direction to form a multi-layer disposable programmable memory cell.

Figure 14 illustrates a top view of an embodiment showing a plurality of one-time programmable permanent memory module layers adjacent to each other, the rows and columns being constructed of oppositely doped semiconductor materials interconnected by conductive vias.

Figure 15 illustrates a cross-sectional view of a multi-layer, one-time programmable permanent memory cell showing the doped semiconductor material lines on different layers of a multi-layer, one-time programmable memory cell formed by stacking a plurality of one-time programmable permanent memory module layers interconnection.

16 illustrates a cross-sectional view of a multi-layer, one-time programmable permanent memory cell showing different layers of inverted doped semiconductor material columns on different layers of a plurality of one-time programmable memory module stacks The interconnection of lines.

17 through 19 illustrate circuit diagrams of memory array circuits of various embodiments in which a plurality of one-time programmable permanent memory modules are stacked to form a multi-layer, one-time programmable permanent memory unit.

Figure 20 illustrates a method of fabricating a multilayer one-time programmable permanent memory cell using a planar deposition process and a semiconductor material etch process.

Figure 21 illustrates a method of preparing a multilayer one-time programmable permanent memory cell by constructing a trench in an insulating dielectric material and filling the trench with a semiconductor material.

Figure 22 is a partial schematic view of a Schottky contact embodiment.

detailed description

The single layer OTP permanent memory module 101 shown in FIG. 1 constitutes one layer of the multi-layer OTP memory unit 100. The OTP permanent memory module 101 includes an inverted doped semiconductor material M row 102 and an N column 103, where M and N are positive integers greater than one. For example, the OTP persistent storage module 101 illustrated in FIG. 1 includes at least two rows 102 and at least two columns 103. The OTP permanent memory module 101 includes a first row A11 and a second row A12 at the top of the first column B11 and the second column B12, as shown in FIG. M and N can be any integer between 1 and 1024 x 1204. Row 102 is made of a p-type semiconductor material or an n-type semiconductor material, while column 103 is composed of an inverted p-type or n-type semiconductor material. For example, if the first row A11 and the second row A12 are p-type semiconductor materials, the first column B11 and the second column B12 are n-type semiconductor materials, and vice versa.

Row 102 and column 103 of one-time programmable (OTP) permanent memory module 101 are arranged in a line such that row 102 and column 103 intersect perpendicularly to each other for optimal results. In one embodiment, row 102 and column 103 are in different configurations, such as non-linear, in a non-vertical direction, or in a curved manner, and the like. The different configurations of row 102 and column 103 produce different results. Row 102 may be referred to as a word line, and column 103 may be referred to as a bit line, respectively. Alternatively, row 102 is referred to as a bit line and column 103 is referred to as a word line.

The one-time programmable (OTP) permanent memory module 101 also includes a thin layer of insulating dielectric material 105, such as silicon dioxide (SiO2), located on the top surface 102a of the row 102 and the top surface 103a of the column 103, respectively. In one embodiment (not shown), an insulating dielectric material layer 105 (e.g., SiO2) is located on the bottom surface 102b of row 102 and bottom surface 103b of column 103, respectively. In Figure 1, insulating dielectric material 105 is designated as a shaded area. The excess insulating dielectric material 105 outside the intersection 104 of row 102 and column 103 is removed using an etch process. In the subsequent planarization process, row 102 and column 103 are filled with a layer of insulating dielectric material 105. In Figure 1, the filled insulating dielectric layers are designated as non-shaded areas above the upper surface of the shaded areas 102a and 103a.

2 illustrates a perspective view of a multi-layer one-time programmable (OTP) permanent memory cell 100 stacked from 101 and 106 two-layer OTP permanent memory modules. The multi-layer OTP permanent memory cell 100 disclosed herein includes at least two layers of stacked OTP permanent memory modules 101 and 106 and an insulating dielectric material 105. Each layer of OTP permanent memory modules 101 and 106 includes M rows 102 and 107, respectively, comprising N columns 103 and 108, respectively, and the rows and columns are comprised of an invertically doped semiconductor material, where M and N are positive integers greater than one. For example, the first layer of OTP permanent memory module 101 includes two rows 102 and two columns 103 of inversely doped semiconductor material, and the second layer of OTP permanent memory module 106 includes two rows 107 and two columns of inversely doped semiconductor material. 108. As shown in FIG. 2, rows 102 and 107 belonging to OTP permanent memory modules 101 and 106, respectively, are located at the top of column 103 and column 108, respectively. In one embodiment (not shown), rows 102 and 107 belonging to OTP permanent memory modules 101 and 106, respectively, are located at the bottom of column 103 and column 108, respectively. In order to obtain optimal data storage, rows 102 and 107 belonging to OTP permanent memory modules 101 and 106, respectively, column 103 and column 108 are straight and perpendicular to each other.

As shown in FIG. 2, each of the one-time programmable (OTP) persistent memory modules 101 and 106 are stacked in a bottom-up direction belonging to rows 102 and 107, columns 103 and columns of OTP permanent memory modules 101 and 106, respectively. 108 is connected at intersections 104 and 109, respectively, and the intersection between OTP permanent memory modules 101 and 106 is 110. For example, the second OTP persistent storage module 106 includes a first row A21, a second row A22, a first column B21, and a second column B22. The module 106 is stacked on top of the first OTP persistent storage module 101, and the module 101 includes One row A11, second row A12, first column B11 and second column B12. The insulating dielectric material 105 is located at the intersection 104 of the row 102 and the column 103 of the OTP permanent memory module 101, respectively, between 102 and 103, at the intersection 109 of the row 107 of the module 106 and the column 108, between 107 and 108, Also located on the top surface 102a of the M row 102 of the OTP permanent memory module 101, and the top surface 103a of the N column 103, are located on the top surface 107a of the M row 107 of the module 106, and the top surface 108a of the N column 108. In one embodiment (not shown), the insulating dielectric material 105 is located at the intersection 102 of the OTP permanent memory modules 101, 106, the intersections 104, 109 of the rows 107 and the columns 103, 108, respectively, between 102, 103 and 107, 108 are also located on the bottom surfaces 102b, 107b of the M rows 102, 107 of the OTP permanent memory modules 101, 106, and the bottom surfaces 103b, 108b of the N columns 103, 108, respectively.

The intersections between rows 102, 107 and columns 103, 108 of one-time programmable (OTP) persistent memory modules 101, 106 are 104 and 109, respectively, and OTP in multi-layer OTP persistent memory unit 100 The intersection between the persistent storage modules 101 and 106 is 110. Figure 1 shows that the OTP memory cells are located at intersections A11-B11, A11-B12, A12-B12, and A12-B11, respectively. In addition, the OTP memory unit is also located at the intersection of A11-B21, A11-B22, A12-B21, A12-B22, A21-B21, A21-B22, A22-B22, and A22-B21, as shown in FIG. Each layer of OTP permanent memory modules 101 and 106 includes four OTP memory cells. For example, the OTP persistent storage module 101 includes four OTP memory units 111a, 111b, 111c, and 111d, as shown in FIG. A multi-layer OTP permanent memory unit 100 having at least two layers of OTP persistent memory modules 101 and 106, including twelve OTP memory units. Each OTP memory cell includes a p-type semiconductor region 112, an n-type semiconductor region 114, and a thin insulating dielectric region 113 between the p-type semiconductor region 112 and the n-type semiconductor region 114, as shown in FIG. The thin insulating dielectric region 113 separates the p-type semiconductor region 112 and the n-type semiconductor region 114. Each of the OTP memory cells further includes at least two terminals, 116a and 116b disposed on each of the OTP memory cell p-type semiconductor region 112 and the n-type semiconductor region 114, as shown in FIG. The terminals of each OTP memory cell, such as 116a and 116b, are interconnected using conductive vias 1501, such as the metal vias of Figures 15-16. Consider rows A11, A12 and A21, A22 of the multilayer OTP permanent memory cell 100 shown in Figure 2, which are p-type semiconductor materials placed on top of columns B11, B12 and B21, B22 of the n-type semiconductor material, respectively. The row of p-type semiconductor material rows A11, A12, A21, A22 and n-type semiconductor material columns B11, B12, B21, B22 form a p-type semiconductor region 112 and an n-type semiconductor region 114 of each OTP memory cell, respectively.

FIG. 3 illustrates a block diagram of a one-time programmable (OTP) memory unit 111. The OTP memory cell 111 includes a p-type semiconductor region 112, an n-type semiconductor region 114, and a thin insulating dielectric region 113 between the p-type semiconductor region 112 and the n-type semiconductor region 114. The thickness of the thin insulating dielectric material 105 forming the thin insulating dielectric region 113 of each OTP memory cell 111 has a predetermined value corresponding to the breakdown voltage of each OTP memory cell. Because a thick dielectric material requires a higher programming voltage, and a too thin dielectric material causes unwanted breakdown and leakage, a thin insulating dielectric material 105 that will form a thin insulating dielectric region 113 in each OTP memory cell 111 will be formed. The thickness is set to suit both the programming voltage and leakage. Insulating dielectric material 105, e.g., the thickness of the silicon dioxide (SiO2) of about 0.5 nanometers (nm) to 4nm, (Si ₃ N ₄₎ of silicon nitride is greater than a thickness of 4nm. In one embodiment, other insulating dielectric materials having a thickness of less than 0.5 nanometers are used. The positions of the p-type semiconductor region 112 and the n-type semiconductor region 114 are interchanged, and the directions of the OTP memory cells 111 can be interchanged.

FIG. 4 illustrates an equivalent circuit diagram 115 of the one-time programmable (OTP) memory cell 111 shown in FIG. OTP memory cell 111 is electrically represented as a diode in series with a programmable anti-fuse capacitor. The direction of the OTP memory cell 111 shown in FIG. 4 corresponds to the OTP memory cell 111 of FIG. 3 in the order of the p-type semiconductor region 112, the insulating dielectric region 113, and the n-type semiconductor region 114. OTP memory unit 111 blocks reverse current from other programmed bits.

Figure 5 illustrates a perspective view of an embodiment of a single layer one-time programmable (OTP) persistent memory module 101 with corresponding OTP memory cells 111a, 111b, 111c, and 111d as shown in Figure 6, formed in an OTP permanent The intersection 104 of row 102 of memory module 101 and column 103. In this embodiment, the OTP permanent memory module 101 includes M rows 102 and N columns 103 of conductors, where M and N are positive integers greater than one. The conductor is such as a metal silicide, or doped polysilicon, or other electrically conductive material. Polysilicon is a combination of polycrystalline silicon and silicide. In one example shown in FIG. 5, the OTP persistent storage module 101 includes at least two rows 102 and at least two columns 103. Row 102 and column 103 of OTP persistent memory module 101 intersect at 104, forming a plurality of OTP memory cells 111a, 111b, 111c and 111d as shown in FIG. 6, a detailed description of which has been disclosed in FIG. The shaded area of intersection 104 of row 102 and column 103 of OTP permanent memory module 101 shown in Figure 5 represents the insulating dielectric region 113 of each OTP memory cell 111a, 111b, 111c, and 111d.

Figure 6 illustrates one-time programmable (OTP) memory cells 111a, 111b, 111c, and 111d formed at the intersection 104 of row 102 and column 103 of the OTP permanent memory module 101 shown in Figure 5. The OTP permanent memory module 101 includes at least two rows 102 and two columns 103 made of conductors. At four intersections 104, four OTP memory cells 111a, 111b, 111c, and 111d are formed, which are shown as four in FIG. Independent block. The top connection terminals 116a, 116c and 116e, 116g of the four OTP memory cells 111a, 111b, 111c and 111d are connected by two row lines 117a and 117c, respectively. The bottom connection terminals 116b, 116h and 116d, 116f of the four OTP memory cells 111a, 111b, 111c and 111d are connected by two column lines 117d and 117b, respectively.

In Figures 7-13 and 15-19 disclosed hereinafter, "1", a lowercase L, represents an OTP persistent storage module (e.g., 101 or 106) that constitutes the multi-layer OTP persistent storage unit 100 shown in Figure 2. The layer number or module number, which may be any integer between 1 and 1024; "R" represents a row line on a layer or an OTP permanent memory module (eg 101 or 106); "C" represents a column line; "x" indicates the column line number; "y" indicates the line number.

FIG. 7 illustrates a partial front view of the multi-layer one-time programmable (OTP) permanent memory cell 100 of FIG. As illustrated in Figure 7, the row line layer (R _l , y) is located at the top of the column line layer represented by (C _l , x-1), (C _l , x) and (C _l , x+1). (C _l , x) denotes the first layer of column lines whose column line number is x. Similarly, (C _l , x-1) and (C _l , x+1) are two column lines on either side of the column line (C _l , x). As shown in FIG. 7, the row line layer is composed of a p-type semiconductor material, such as p-type doped polysilicon (p-poly), in which case the column line layer is made of an n-type semiconductor material, such as n-type doped polysilicon (n- Poly) constitutes. Line layer (R _l , y) and column line (C _l+1 , x-1), (C _l , x-1), (C _l+1 , x), (C _l , x), (C _{l + 1, x + 1)} , and _{(C 1, x + 1)} , and an insulating dielectric material 105 intersect at an intersection. When the programming voltage is applied, the insulating dielectric material 105 at the intersection of the row line (R ₁ , y) and the column line (C ₁ , x) is broken down, at the intersection of the row and column lines of the layer A pn junction diode is formed. The p-poly and n-poly materials diffuse through the broken dielectric dielectric material 105 to form a pn junction diode. The distance between adjacent row lines and adjacent columns remains at the lowest value in the process design rules to adequately achieve good storage density. In order to achieve better storage density, the distance between adjacent row lines and adjacent column lines on each layer is optimized to be greater than the lowest value of the process design rule.

Figure 8 illustrates a circuit diagram of a multi-layer one time programmable (OTP) permanent memory cell memory array as shown in Figure 7. The circuit diagram is shown in each column line (C _l+1 , x-1), (C _l , x-1), (C _l+1 , x), (C _l , x), (C _l+1 , x+ 1), at the intersection of (C _l , x+1) and the row line (R _l , y), the pn junction diode 801 formed by breaking through the insulating dielectric material 105 is disclosed in detail in FIG.

FIG. 9 illustrates a partial side view of one embodiment of a multi-layer one-time programmable (OTP) permanent memory unit 100 as shown in FIG. 2. In this embodiment, the column lines (Cl, x) of a layer of OTP permanent memory modules are placed in the same layer row line (R _l , y-1), (R _l , y), (R _l , y+1) Between the underlying row lines (R _l-1 , y-1), (R _l-1 , y), (R _l-1 , y+1). The row line (R _l , y) indicates that the serial number is y on the first layer. Similarly, (R _l , y-1) and (R _l , y+1) are on either side of the row line (R _l , y). As illustrated in FIG. 9, the top and bottom row lines of the layer are both p-type semiconductor materials, such as p-type doped polysilicon (p-poly), and the layer line is made of an n-type semiconductor material, for example, n. Type doped polysilicon (n-poly). The layer column line (C _l , x) and the row line (R _l , y-1), (R _l , y), (R _l , y+1) (R _l-1 , y-1), (R _L-1 , y), (R _l-1 , y+1), and the insulating dielectric material 105 intersect at the intersection. Upon application of a programming voltage, the column lines (C _1, x) and row lines (R _1, y) an insulating dielectric material at the intersection 105 is broken, a pn junction at the intersection of the layer of row and column lines diode. The p-poly material and the n-poly material diffuse through the insulating dielectric material 105 that has been broken down to form a pn junction diode.

Figure 10 illustrates a circuit diagram of a memory array of one embodiment of the multi-layer one time programmable (OTP) permanent memory cell of Figure 9. The circuit diagram shows that in each row line ((R _l , y-1), (R _l , y), (R _l , y+1), (R _l-1 , y-1), (R _l-1 , y), at the intersection of (R _l-1 , y+1) and the column line (C _l , x), a pn junction diode 1001 formed by breaking through the insulating dielectric material 105, as disclosed in detail in FIG.

FIG. 11 illustrates a top view of a multi-layer one-time programmable (OTP) permanent memory cell 100. As shown in FIG. 11, the column lines are composed of an n-type semiconductor material such as n-type doped polysilicon (n-poly), and the row lines are composed of a p-type semiconductor material such as p-type doped polysilicon (p-poly). . In one embodiment (not shown), the column lines are p-poly and the row lines are n-poly. The row lines of the OTP permanent memory module intersect the column lines of the OTP permanent memory module, forming an OTP permanent memory cell at the intersection of the row and column lines. (C _l , x) denotes a column line numbered x on the first layer. Similarly, (C _l , x-1) and (C _l , x+1) are two column lines on either side of the column line (C _l , x). (R _l , y) denotes a row line numbered y on the first layer. Similarly, (R _l , y-1) and (R _l , y+1) are two row lines on either side of the row line (R _l , y).

Figure 12 shows a front view of a multi-layer OTP permanent memory cell 100 formed by stacking a plurality of one-time programmable (OTP) permanent memory modules in a bottom-up direction. In the OTP permanent memory module shown in FIG. 12, the column lines are placed below the row lines to form a multi-layer OTP permanent memory cell 100. The front view shown in Figure 12 shows the intersection of the column lines of a plurality of OTP permanent memory modules with the row lines of a plurality of OTP permanent memory modules. The first (first) layer containing the row lines (R ₁ , y) and the column lines (C ₁ , x) stacked on the _0th line including the row lines (R ₀ , y) and the column lines (C ₀ , x) Above the layer. Similarly, the "1+1" layer containing the row lines (R _l+1 , y) and the column lines (C _l+1 , x) is symmetrically stacked with row lines (R ₁ , y) and column lines ( Above the first layer of C ₁ , x). The multi-layer OTP permanent memory unit 100 is obtained by analogy.

A row line made of a p-type semiconductor material is stacked on a column line made of an n-type semiconductor material, and a column line layer is stacked on top of the row line to obtain a "row/column/row/column" Symmetrical layout, ie P/N/P/N. Therefore, in order to add one layer to the one-time programmable (OTP) permanent memory cell 100, it is necessary to add a thin insulating dielectric material 105 and a layer of inversely doped semiconductor material (e.g., polysilicon). On the OTP permanent memory cell 100, a new layer of OTP permanent memory is created for each additional thin insulating dielectric material 105 and counter-doped semiconductor material. The stacked layers, that is, the plurality of OTP permanent memory module layers, operate over a silicon (Si) substrate 1201 and a gate oxide 1202 deposited as an insulating dielectric layer. The logic and programming circuit 1203 is configured to arrange the programming voltage to insulate the intersection of the row and column lines in the OTP permanent memory module of the multi-layer OTP permanent memory cell 100. The dielectric material 105 breaks down. For example, when programming or reading a multi-layer OTP permanent memory cell 100, a positive voltage is applied to selected row lines and selected column lines in the memory module layer so that current can be made from p-type semiconductor material. The line flows to the column lines of the n-type semiconductor material to obtain a positive pn junction conductance.

Figure 13 illustrates a side view of an embodiment of a one-time programmable (OTP) permanent memory module stacked in a bottom-up direction to form a multi-layer OTP permanent memory cell 100. In the OTP permanent memory module shown in FIG. 13, the column lines are located below the row lines to form a multi-layer OTP permanent memory cell 100. The row and column lines of the OTP permanent memory module are respectively made of a p-type semiconductor material (eg, boron doped polysilicon, p-poly or P-type copper oxide) and an n-type semiconductor material (eg, phosphorus doped or arsenic doped polysilicon, n -poly, or N-type indium zinc oxide). Figure 13 is a side elevational view showing the intersection of the column lines of the OTP permanent memory module with the row lines of the plurality of OTP permanent memory modules. The first (1) layer including the row lines (R ₁ , y) and the column lines (C1, x) is stacked on the _0th layer including the row lines (R ₀ , y) and the column lines (C ₀ , x) on. Similarly, the "l"+1 layer containing the row lines (R _l +1, y) and the column lines (C _l +1, x) ("l" is a lowercase L), stacked in a row containing lines (R _l , y) and the "1" layer of the column line (C _l , x), and so on, thereby obtaining the multi-layer OTP permanent memory cell 100. A plurality of layers stacked symmetrically, or a plurality of OTP permanent memory module layers, are run on a silicon substrate 1201 on which a gate oxide layer 1202 of an insulating dielectric layer is deposited. The logic and programming circuit 1203 is configured to align the programming voltage to insulate the dielectric dielectric material 105 at the intersection of the row and column lines in the OTP permanent memory module of the multi-layer OTP permanent memory cell 100.

Figure 14 illustrates a top view of a plurality of one-time programmable (OTP) permanent memory modules 101, 106, 118, and 119 showing layers adjacent to each other in an embodiment, wherein the reverse phase doped semiconductor material is formed The row and column lines are connected to each other by conductive vias such as metal or doped polysilicon holes. The row and column lines of the OTP permanent memory modules (e.g., 101 and 118) are interconnected with the row and column lines of the OTP permanent memory modules (e.g., 106 and 119) of adjacent layers using the conductive vias described above.

Figure 15 illustrates a multilayer one-time programmable (OTP) permanent memory cell, in a row-wise cross-sectional view, illustrating the doped semiconductor material (e.g., p-type) on different layers of a stacked multi-layer OTP permanent memory cell Interconnection of row lines between semiconductor materials). Conductive vias 1501 are used to connect the row lines on the different layers that are stacked to form a multi-layer OTP permanent memory cell.

Figure 16 illustrates a multilayer one-time programmable (OTP) permanent memory cell, sectioned along the column line, illustrating the different layers of the stacked multi-layer OTP permanent memory cell, doped half Interconnection between column lines of a conductor material, such as an n-type semiconductor material. Conductive vias 1501 are used to form the columns on the different layers of the multi-layer OTP permanent memory cell.

17-19 illustrate circuit diagrams of memory arrays of embodiments of a multi-layer OTP memory cell 100 formed by one-time programmable (OPT) permanent memory module layer stacking. Figure 17 illustrates a circuit diagram of a memory array of a multi-layer OTP permanent memory cell 100 showing a layer of word lines, i.e., row lines (R _l , y+1), (R _l , y), on the same OTP permanent memory module, (R _l , y-1), the bit line connected to the top layer is the column line (C _l+1 , x-1), (C _l+1 , x), (C _l+1 , x+1) and the bottom layer Bit lines (C _l , x-1), (C _l , x), (C _l , x+1). The top and bottom OTP memory cells are connected to bit lines C _l+1 and C _l and share a common word line R _l .

Figure 18 illustrates a circuit diagram of a multi-layer OTP permanent memory cell 100 memory array circuit showing a column line (C _l , x-1), (C _l , x), (C _l , x+1), Connect to adjacent top and bottom row lines ((R _l+1 , y+1), (R _l , y+1), (R _l+1 , y), (R _l , y), (R _L+1 , y-1), (R _l , y-1). The OTP memory unit formed by the top layer R _l+1 and the OTP memory unit formed by the bottom layer R _l share the same bit line C _l .

Figure 19 illustrates a circuit diagram of a memory array of a multi-layer OTP permanent memory cell 100 showing row lines (R _l+1 , y), (R _l , y) and (R _l-1 , y on three layers ) is connected to the column lines on the adjacent four layers, namely: the top column line (C _l+1 , x-1), (C _l+1 , x) and (C _l+1 , x+1), Sub-top column lines (C _l , x-1), (C _l , x) and (C _l , x+1), sub-lower column lines (C _l-1 , x-1), (C _l-1 , x) and (C _l-1 , x+1), the underlying column lines (C _l-2 , x-1), (C _l-2 , x) and (C _l-2 , x+1).

The multi-layer one-time programmable (OTP) persistent memory unit 100 further includes a multi-stage decoding circuit (not shown), at least two M rows of lines 102 in the OTP permanent memory modules 101 and 106 shown in FIG. 2 or 107 and at least two N column lines 103 or 108 are implemented. The multi-level decoding circuit can be shared by the upper and lower stacked OTP permanent memory modules 101 and 106. Multi-layer memory arrays typically include multiple stages of decoders, such as layer decoders, segment decoders, row decoders, column decoders, and the like. A multi-layer OTP permanent memory unit 100 having a plurality of row lines 102, 107, column lines 103, 108, employing a multi-stage decoder system, such as a layer decoder, a page decoder, a segment decoder, a row decoder, and a column decoding The addresses of the row lines 102, 107 and the column lines 103, 108 are decoded, allowing the programming and/or reading system to access the data stored in the multi-layer OTP persistent memory unit 100.

The operating voltmeter of the multi-layer one-time programmable (OTP) permanent memory cell 100 as shown in FIG. 2 is exemplified by the following Tables 1 to 4. It gives the user the operating voltage according to the position of the line (R _l) and columns (C _l) the definition of programming and / or reading data in the persistent storage unit 100 in the multilayer OTP. The programming voltage (Vpp), the half programming voltage (Vphf), and the read voltage (Vrd) are selected in accordance with the process technology, electrical performance and reliability requirements of the multi-layer OTP permanent memory cell 100. The user can assign different voltages to the selected row (SR) of the row line (R _l ) and the column line (C _l ) when programming and/or reading data to the multi-layer OTP permanent memory cell 100, respectively. Line selection (UR), selected column (SC) and unselected column (UC) are shown in Tables 1 to 4. When programming, Vphf (1/2Vpp) on unselected and unselected columns is used to reduce voltage stress, thereby avoiding unnecessary programming or oxide layer reliability issues. In addition, the voltages on R _l and/or C _l can be charged to Vphf and allowed to float, as represented by "Vphf &Float" in the table.

Table 1 above illustrates the multi-layer one-time programmable (OTP) permanent memory cell 100 shown in FIG. 2. According to the operating voltage meter of Option 1, the corresponding memory array circuit is as shown in FIG. 8, FIG. 10 and FIG. 17-19. Show. The user can set the row line (R _l ) voltage to the programming voltage (Vpp), the column line (C _l ) voltage to zero, and the selected row line (SR) to the multi-layer OTP permanent memory cell 100. / or the OTP memory cell of the selected column line (SC) is programmed. The user can set the voltage of R _l to Vpp, the voltage of C _l is set to half programming voltage (Vphf) and floating (represented by "Vphf &Float"), so that unselected OTP with SR and / or unselected column (UC) is selected. The storage unit is not programmed. The user can set the voltage of R _l to zero, the voltage of C _l to zero, programming unselected rows (UR) and/or selected columns SC. The user can set the voltage of R _l to zero, the voltage of C _l to Vphf & Float, and the programming UR and / or UC. Similarly, the user can set the R _l voltage to the circuit read voltage (Vrd) and connect C _l to the sense circuit (Sensing) to read the SR and/or SC. The user can set the R _l voltage to Vrd and set the C _l voltage to Vrd to read SR and/or UC. The user can set the voltage of R _l to zero, and connect C _l to the detection circuit (Sensing) to read UR and/or SC. The user can set R _l to zero voltage and set C _l to Vrd to read UR and/or UC.

Table 2 above illustrates a multi-layer one-time programmable (OTP) permanent memory cell 100 as shown in FIG. 2. According to the operating voltage meter of option 2, the corresponding memory array circuit is as shown in FIG. 8, FIG. 10 and FIG. 17-19. . The user can set the voltage of the row line (R _l ) to zero, the column line voltage to the programming voltage (Vpp), and the selected row line (SR) and/or the selected column line (SC) to the multi-layer OTP permanent memory cell 100. The OTP memory cell is programmed. The user can set the voltage of R _l to zero and the voltage of C _l to be zero, so that unselected OTP memory cells containing SR and / or unselected columns (UC) are not programmed. The user can set the R _l voltage to a half programming voltage (Vphf) and float (indicated by Vphf & Float), set the voltage of C _l to Vpp, and program unselected lines (UR) and/or SC. The user can set R _l to Vphf & Float, set C _{l to} zero voltage, and program UR and / or UC. Similarly, the user can set the voltage of R _l to the read voltage (Vrd) and connect C _l to the detection circuit to read SR and/or SC. The user can set R _l to Vrd and set C _l to Vrd to read SR and/or UC. The user can set the R _l voltage to zero and connect C _l to the detection circuit to read UR and/or SC. The user can set R _{l to} zero voltage, set the C _l voltage to Vrd, and read UR and / or UC.

Table 3 above illustrates a multi-layer one-time programmable (OTP) permanent memory cell 100 as shown in FIG. 2. According to the operating voltage meter of option 3, the corresponding memory array circuit is as shown in FIG. 8, FIG. 10 and FIG. 17-19. . The user can set the voltage of the row line (R _l ) to a half programming voltage (Vphf), the column line voltage to a negative programming voltage (-Vpp), and the selected row line (SR) and/or to the multi-layer OTP permanent memory cell 100. Or select the OTP memory cell of the column line (SC) for programming. The user can set R _l to Vphf and C _{l to} be floating (Float) so that unselected OTP memory cells containing SR and/or unselected columns (UC) are not programmed. The user can set the R _l voltage to zero, the voltage of C _l to be negative Vphf, and the unselected line (UR) and/or SC. The user can set the voltage of R _l to zero and the voltage of C _{l to} be floating (Float), programmed UR and / or UC. Similarly, the user can set the R _l voltage to the read voltage (Vrd) and connect C _l to the detection circuit (Sensing) to read the SR and/or SC. The user can set R _l to Vrd and set C _l to Vrd to read SR and/or UC. The user can set the voltage of R _l to zero and the voltage of C _{l to} zero, reading UR and / or SC. The user can set R _{l to} zero voltage and C _l to Vrd to read UR and/or UC.

Table 4 above illustrates a multi-layer one-time programmable (OTP) permanent memory cell 100 as shown in FIG. 2. According to the operating voltage meter of option 4, the corresponding memory array circuit is as shown in FIG. 8, FIG. 10 and FIG. 17-19. . The user can set the row lines (R _l) the programming voltage is negative voltage half (Vphf) and column lines (C _l) voltage Vphf, 100 of the multilayered OTP persistent storage unit contains the selected row (SR) and / or is selected from The OTP memory cell of the fixed column (SC) is programmed. The user can set a negative voltage Vphf R _l and C _l is the voltage of the floating (Float), such that the selected OTP memory cell is not programmed and containing SR / or unselected column (UC) is. The user can set the R _l voltage to zero, the C _l voltage to be negative Vphf, and the unselected line (UR) and/or SC to be programmed. The user can set the R _l voltage to zero and the C _l voltage to float (Float), programming UR and / or UC. Similarly, the user can set the voltage of R _l to the read voltage (Vrd) and connect C _l to the detection circuit (Sensing) to read SR and/or SC. The user can set the R _l voltage to Vrd, the C _l voltage to Vrd, and read SR and/or UC. The user can set the voltage of R _l to zero and connect C _l to the detection circuit to read UR and / or SC. The user can set the R _l voltage to zero and the C _l voltage to Vrd to read UR and/or UC. In one embodiment, the detection circuit is connected to the row lines instead of the column lines.

Figure 20 shows an example of a method for preparing a multilayer one-time programmable (OTP) permanent memory cell 100 as shown in Figure 2 using a planar deposition process and a semiconductor material etch process. In the method disclosed herein, step 2001 is to place a semiconductor material (eg, polysilicon, silicon, etc.) on a top planar surface of a wafer containing completed memory peripheral circuitry using a deposition process or an epitaxial process. The memory peripheral circuitry provides access to the multi-layer OTP persistent memory unit 100. Step 2002 is to inversely dope the semiconductor material with a p-type dopant or an n-type dopant using an ion implantation process or a diffusion process. Step 2003 is to remove excess portions of the reverse-phase doped semiconductor material using a photolithography mask and an etching process, and to form a strip-shaped semiconductor material using the reverse-phase doped semiconductor material to form an OTP permanent memory module 101 as shown in FIG. M row 102 or N column 103, M and N are positive integers greater than one. The OTP permanent memory module 101 constitutes one of the layers of the multi-layer OTP permanent memory unit 100. Step 2004 is to fill the insulating dielectric material 105 with a planarization process on the M rows 102 or N columns 103 strip of semiconductor material in the formed OTP permanent memory module 101. Step 2005 is to remove excess insulating dielectric material 105 that overflows or fills the strip of semiconductor material above M rows 102 or N columns 103 using chemical and mechanical polishing processes. Step 2006 is to form a thin layer on top of the M row 102 or the N column 103 of the already filled OTP permanent memory module 101 by a thermal oxidation process, or a low temperature chemical vapor deposition process, or an atomic layer deposition (ALD) process. Insulated dielectric film. Step 2007 is to repeat the above method to a predetermined number of times, creating each layer of OTP permanent memory module 106 (shown in FIG. 2) from the lower vertical direction, symmetrically stacking the OTP permanent memory module 106, and generating a multi-layer OTP permanent memory. Unit 100. A plurality of OTP memory cells, such as 111a, 111b, 111c, and 111d in FIG. 6, are formed at the intersection 104 of the M row 102 or the N column 103 of the OTP persistent memory module 101, and the OTP persistent memory module 101 is located thereon The intersection of another layer of OTP permanent memory modules 106 is 110. Create another thin insulating dielectric film on top of the topmost OTP permanent memory module 106 and stack in reverse The M rows or N columns of the doped semiconductor material (p-type semiconductor material or n-type semiconductor material) are so repeated that the OTP memory cells in the multi-layer OTP permanent memory cell 100 can be improved, such as 111a, 111b, 111c, and 111d. Storage capacity.

Figure 21 shows an example of a method for fabricating a multilayer one-time programmable (OTP) permanent memory cell 100 as shown in Figure 2 for a trench formed on an insulating dielectric material and filling the trench with a semiconductor material. In the method disclosed herein, step 2101 is to deposit a layer of thick insulating dielectric material on the top planar surface of the wafer containing the completed memory peripheral circuitry. Step 2102 is to use a mask etch process to construct trenches on the deposited thick insulating dielectric material for locating a row or column of a layer of permanent memory modules. Step 2103 is to deposit a semiconductor material on the trench being constructed. Step 2104 is to inversely dope the deposited semiconductor material with a p-type or n-type dopant using a diffusion process or an ion implantation process. In one embodiment, the in situ deposition method is used to achieve high concentration doping, and steps 2103 and 2104 are combined into a single step. Step 2105 is to remove the over-deposited reverse-doped semiconductor material using a common planarization process to form M rows 102 or N columns 103 of the OTP permanent memory module 101, where M and N are positive integers greater than one. Following step 2106, a layer of thick insulating dielectric material is deposited on the top planar surface of the wafer. Step 2107 uses a mask etch process to construct trenches on the thick insulating dielectric material for locating rows or columns of OTP permanent memory modules. The etching process is terminated after reaching the last deposited semiconductor material. Step 2108 is to create a thin insulating dielectric film on M row 102 or N column 103 of OTP permanent memory module 101 using a thermal oxidation process or a thermal deposition process or an atomic layer deposition (ALD) process. As shown in FIG. 2, a thin insulating dielectric film on each M row 102 or N column 103 of the OTP permanent memory module 101 is used as a programmable dielectric material. Step 2109 is to repeat the above-mentioned 2103, 2104, 2105, 2106, 2107, and 2108 methods to a predetermined number of times, and create each layer of the OTP permanent memory module 106 as shown in FIG. 2 in a direction from the lower vertical direction, symmetrically stacking the OTP permanent. The memory module 106 generates a multi-layer OTP permanent memory unit 100. The storage capacity of the generated OTP memory cells, such as 111a, 111b, 111c, and 111d shown in FIG. 6, can be improved, and a detailed description thereof is disclosed in FIG.

An example of a Schottky contact:

A multi-layer, one-time programmable permanent memory unit containing:

At least two layers of one-time programmable permanent memory modules, one layer stacked on top of another layer; each of the at least two layers of one-time programmable permanent memory modules comprising M row lines and N column lines, wherein M and N are greater than 1 positive integer;

At each intersection, the material of row line M and column line N are respectively required to conform to the two materials required to create a Schottky contact at the intersection, for example, the row line material is available and forms a Schottky tube. Metals such as Al, Ag, Au, Pt, and columnar N materials are N-type semiconductor materials such as N-Poly, N-Si, N-IZO (N-type indium zinc oxide) and the like. Between the material intersections of row line M and column line N is a thin medium such as SiO ₂ or other material that can be used for the antifuse mentioned in this patent.

Specifically, for the intersection of a particular row and column line, the structure is "row line material - insulating medium - column line material", and the foregoing "row line and column line materials are respectively in accordance with the intersection The two materials required to create a Schottky contact at the point means that the line material and the line material should be capable of forming a Schottky contact in the event of breakdown of the dielectric. Figure 22 shows the structure. Wherein, 2201 is a metal that can be used to form a Schottky contact, such as Al, Ag, Au, Pt, 2202 is a thin dielectric layer, and 2203 is an N-type semiconductor material, such as N-Poly, N-Si, N-IZO (N Type indium zinc oxide).

The examples have been provided above for illustrative purposes only and do not pose any limitation to the multilayer one-time programmable (OTP) permanent memory cell 100 and its method of fabrication as disclosed herein as disclosed herein. Although the multi-layered OTP persistent memory unit 100 and method have been described in terms of various embodiments, the description and description of the embodiments are not to be construed as limiting. Moreover, although a particular manner, materials, and embodiments are employed to describe the multi-layer OTP permanent memory cell 100 and its method of fabrication, the multi-layered OTP permanent memory cell 100 and methods of making the same are not limited to the disclosures herein. It is intended to extend to all functionally equivalent structures, methods and applications, such as the scope of the appended claims. Skilled and skilled artisan, many modifications and changes may be made thereto without departing from the scope and spirit of the multi-layered OTP permanent memory unit 100 disclosed herein and its method of preparation.

Claims (17)

1. Multi-layer, one-time programmable permanent memory unit with:

   At least two layers of one-time programmable permanent memory modules stacked one on top of the other; each of the at least two layers of one-time programmable permanent memory modules comprising M made of a reverse phase doped semiconductor material Rows and N columns, where M and N are greater than 1 positive integer;

   a thin insulating dielectric material disposed between the M rows and N columns of each of the at least two layers of one-time programmable permanent memory modules, between the M rows and the N columns; the thin insulating dielectric material being One of the top and bottom surfaces of each of the M rows and N columns.
2. The multi-layer, one-time programmable permanent memory unit of claim 1 wherein each of said one-time programmable permanent memory modules is stacked in a bottom-up direction in said M rows and N columns The intersections are connected, and the M rows in each of the one-time programmable permanent memory modules are disposed on one of the top and bottom of the N columns.
3. The multi-layer, one-time programmable permanent memory unit of claim 1 further comprising a plurality of disposables formed at the intersection of M rows and N columns of said one-time programmable permanent memory module of each layer A programmable persistent memory unit and a plurality of one-time programmable permanent memory units formed at intersections between the one-time programmable permanent memory modules.
4. The multi-layer, one-time programmable permanent memory unit of claim 3 wherein said one-time programmable memory cell comprises a p-type semiconductor region, an n-type semiconductor region, and said p-type semiconductor region and said A thin insulating dielectric region between the n-type semiconductor regions.
5. A multi-layer, one-time programmable permanent memory unit according to claim 4, wherein each of said one-time programmable memory cells further comprises at least two connection terminals located in said p-type semiconductor region and said n Type semiconductor region.
6. A multi-layer, one-time programmable permanent memory unit according to claim 5, wherein said at least two of said one-time programmable memory cells are connected to each other using conductive vias.
7. A multi-layer, one-time programmable permanent memory unit according to claim 4, wherein a thickness of said thin insulating dielectric material forming said thin insulating dielectric region of said one-time programmable memory cell is predetermined, corresponding A breakdown voltage for each of the one-time programmable memory cells.
8. The multi-layer, one-time programmable permanent memory unit of claim 1 further comprising said M-row and N-column multi-level decoder circuits for said one-time programmable permanent memory module The multi-level decoder circuit is shared by the one-time programmable permanent memory modules stacked on top of each other at least two levels.
9. The multi-layer, one-time programmable permanent memory unit of claim 1 wherein said M rows of said one-time programmable permanent memory module of each layer are comprised of one of a p-type semiconductor material and an n-type semiconductor material In the configuration, the N columns are formed by inversion of one of the p-type semiconductor material and the n-type semiconductor material.
10. A multi-layer, one-time programmable permanent memory unit containing:

    At least two layers of one-time programmable permanent memory modules stacked one on top of the other, each layer of the at least two layers of one-time programmable permanent memory modules comprising M rows and N columns of useful conductors, Where M and N are greater than 1 positive integer;

    a plurality of one-time programmable permanent memory cells formed at the intersection of M rows and N columns of each of said one-time programmable permanent memory modules, and a plurality of intersecting one-time programmable permanent memory modules formed therebetween A one-time programmable permanent memory unit.
11. A multi-layer, one-time programmable permanent memory unit containing:

    At least two layers of one-time programmable permanent memory modules, one layer stacked on top of another layer; each of the at least two layers of one-time programmable permanent memory modules comprising M row lines and N column lines, wherein M and N are greater than 1 positive integer;

    At each intersection, the material of row line M and column line N are respectively the two materials required to produce a Schottky contact at the intersection;

    A thin insulating dielectric material is disposed at the intersection of M rows and N columns of each of the at least two layers of one-time programmable permanent memory modules.
12. A method of fabricating a multilayer one-time programmable permanent memory cell, the method comprising:

    Providing a semiconductor material on a top planar surface of the wafer containing the completed memory peripheral circuit using one of a deposition process and an epitaxial process;

    The semiconductor material is inversely doped with a dopant using one of an ion implantation process and a diffusion process, the dopant being one of a p-type dopant and an n-type dopant;

    Removing the excess portion of the doped semiconductor material using a photolithographic mask process and an etch process to form the strip of doped semiconductor material into strips of strip of semiconductor material to form a one-time programmable permanent memory module One of M rows and N columns of hetero semiconductor materials, wherein M and N are positive integers greater than one;

    Filling a strip of semiconductor material constituting one of the M rows and N columns of the one-time programmable permanent memory module with an insulating dielectric material using a planarization process;

    Excessively filling the insulating dielectric material in a strip of semiconductor material constituting one of M rows and N columns of the one-time programmable permanent memory module using a chemical mechanical polishing process;

    Using a thermal oxidation process, or a low temperature chemical vapor deposition process, or an atomic layer deposition process, on top of the already filled semiconductor material strips constituting one of the M rows and N columns of the one time programmable permanent memory module a thin insulating dielectric film;

    The method is repeated in a downward vertical direction for a predetermined number of times, and the one-time programmable permanent memory module produced by each iteration is symmetrically stacked to produce the multi-layer one-time programmable permanent memory unit.
13. The method of claim 12 further characterized by forming an intersection between an M-row and an N-column of said one-time programmable persistent memory module and an intersection between said one-time programmable persistent memory module Many one-time programmable memory cells.
14. The method of claim 12 further comprising iteratively adding another layer of said thin insulating dielectric film over said topmost one of said one time programmable permanent memory modules, in said additional Stacking one of the M rows and N columns made of a reverse phase doped semiconductor material on a thin insulating dielectric to add a one-time programmable permanent memory cell in the multilayer one-time programmable permanent memory cell; The reverse phase doped semiconductor material is one of a p-type semiconductor material and an n-type semiconductor material.
15. A method of fabricating a multilayer one-time programmable permanent memory cell, the method comprising:

    Depositing a thick insulating dielectric material on a top planar surface of the wafer containing the completed memory peripheral circuitry;

    Constructing a trench on the deposited thick dielectric layer using a mask etch process for locating one of the rows and columns of the one-time programmable permanent memory module;

    Depositing a semiconductor material on the trench;

    The doped semiconductor material is inversely doped using a dopant process using a diffusion process or an ion implantation process, the dopant being one of a p-type dopant and an n-type dopant;

    Excessively deposited the counter-doped semiconductor material is removed using a conventional planarization process to form one of M rows and N columns of the one-time programmable permanent memory module, M and N being positive integers greater than one;

    Depositing a layer of insulating dielectric material on the top planar surface of the wafer;

    A trench is formed on the deposited thick dielectric layer using a mask etch process for locating one of the rows and columns of the one-time programmable permanent memory module; the etch process will continue until the last deposited semiconductor material until;

    Depositing a thin insulating dielectric film on one of the M rows and N columns of the one-time programmable permanent memory module using a thermal oxidation process, or a thermal deposition process, or an atomic layer deposition process, The thin insulating dielectric film on one of the M rows and N columns of the secondary programmable permanent memory module is used as a programmable dielectric material;

    The method is repeated in a downward vertical direction for a predetermined number of times, and the one-time programmable permanent memory module produced by each iteration is symmetrically stacked to produce the multi-layer one-time programmable permanent memory unit.
16. The method of claim 15 further comprising at an intersection of M rows and N columns of said one time programmable persistent memory module and at an intersection between said one time programmable persistent memory modules, A number of one-time programmable memory cells are formed.
17. The method of claim 16 further comprising iteratively adding another layer of said thin insulating dielectric film over said topmost one-time programmable permanent memory module, in said additional One of the M rows and N columns made of a reverse phase doped semiconductor material is stacked over a thin insulating dielectric film to increase the one-time programmable permanent memory in the multilayer one-time programmable permanent memory cell The reverse phase doped semiconductor material is one of a p-type semiconductor material and an n-type semiconductor material.

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