[go: up one dir, main page]

WO2018157573A1 - Structure d'électrode de grille et procédé de fabrication de celle-ci, et dispositif d'affichage - Google Patents

Structure d'électrode de grille et procédé de fabrication de celle-ci, et dispositif d'affichage Download PDF

Info

Publication number
WO2018157573A1
WO2018157573A1 PCT/CN2017/100441 CN2017100441W WO2018157573A1 WO 2018157573 A1 WO2018157573 A1 WO 2018157573A1 CN 2017100441 W CN2017100441 W CN 2017100441W WO 2018157573 A1 WO2018157573 A1 WO 2018157573A1
Authority
WO
WIPO (PCT)
Prior art keywords
gate electrode
buffer layer
layer
photoresist
insulating layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2017/100441
Other languages
English (en)
Chinese (zh)
Inventor
简重光
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
HKC Co Ltd
Chongqing HKC Optoelectronics Technology Co Ltd
Original Assignee
HKC Co Ltd
Chongqing HKC Optoelectronics Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by HKC Co Ltd, Chongqing HKC Optoelectronics Technology Co Ltd filed Critical HKC Co Ltd
Priority to US15/578,435 priority Critical patent/US10388678B2/en
Publication of WO2018157573A1 publication Critical patent/WO2018157573A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0312—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/23—Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
    • H10D64/251—Source or drain electrodes for field-effect devices
    • H10D64/258—Source or drain electrodes for field-effect devices characterised by the relative positions of the source or drain electrodes with respect to the gate electrode
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0212—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or coating of substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/411—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs characterised by materials, geometry or structure of the substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/431—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having different compositions, shapes, layouts or thicknesses of gate insulators in different TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H10D86/443—Interconnections, e.g. scanning lines adapted for preventing breakage, peeling or short circuiting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/471—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having different architectures, e.g. having both top-gate and bottom-gate TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/10—Integrated devices
    • H10F39/12—Image sensors
    • H10F39/15—Charge-coupled device [CCD] image sensors
    • H10F39/151—Geometry or disposition of pixel elements, address lines or gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/80—Constructional details of image sensors
    • H10F39/803—Pixels having integrated switching, control, storage or amplification elements
    • H10F39/8037—Pixels having integrated switching, control, storage or amplification elements the integrated elements comprising a transistor
    • H10F39/80373—Pixels having integrated switching, control, storage or amplification elements the integrated elements comprising a transistor characterised by the gate of the transistor
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/6736—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes characterised by the shape of gate insulators
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines

Definitions

  • the present application relates to the field of display technologies, and in particular, to a gate electrode structure, a method of manufacturing the same, and a display device.
  • TFT-LCD Thin Film Transistor-Liquid Crystal Display
  • TFTs Thin Film Transistors glass substrates for TFT-LCD displays are widely used.
  • the circuit layout on the screen usually has a gate electrode (also known as a scan line or GATE) and a data line (also known as DATA), which cross each other.
  • the purpose of the present application is to provide a gate electrode structure, a manufacturing method thereof and a display panel, which aim to solve the problem that the data line is easily broken at the intersection of the gate electrode and the data line in the prior art.
  • the application provides a method for manufacturing a gate electrode structure, comprising the following steps:
  • a data line partially overlapping the semiconductor layer is formed on an upper surface of the semiconductor layer and/or an upper surface of the insulating layer.
  • the recess is formed by a photolithography process.
  • the step of photolithography comprises:
  • the light source emitting light through the reticle to expose a portion of the photoresist
  • the substrate is cleaned, and the photoresist and the buffer layer are removed.
  • the method for manufacturing the gate electrode structure further includes the following steps:
  • the photoresist is peeled off.
  • the photoresist is stripped by etching the photoresist using a photoresist.
  • the buffer layer, the insulating layer, and the semiconductor layer are formed by a chemical vapor deposition process.
  • the buffer layer and the insulating layer are made of a material comprising: silicon nitride.
  • the material used for the gate electrode and the data line comprises: aluminum or molybdenum.
  • the application also provides a gate electrode structure, including:
  • a buffer layer is formed on a side surface of the substrate, and the buffer layer is provided with a groove penetrating the buffer layer;
  • a gate electrode formed in the recess, and an upper surface of the buffer layer and a top surface of the gate electrode are in the same plane;
  • a semiconductor layer formed on an upper surface of the insulating layer and disposed opposite to the gate electrode;
  • a data line is formed on an upper surface of the insulating layer and/or an upper surface of the semiconductor layer, and partially overlaps the semiconductor layer.
  • the recess is formed by a photolithography process.
  • the photoresist and the upper surface of the recess are deposited to form a gate electrode conductive layer.
  • the buffer layer, the insulating layer, and the semiconductor layer are formed by a chemical vapor deposition process.
  • the buffer layer and the insulating layer are made of a material comprising: silicon nitride.
  • the material used for the gate electrode and the data line comprises: aluminum or molybdenum.
  • the application also provides a display device comprising:
  • the gate electrode structure comprising:
  • a buffer layer is formed on a side surface of the substrate, and the buffer layer is provided with a groove penetrating the buffer layer;
  • a gate electrode formed in the recess, and an upper surface of the buffer layer and a top surface of the gate electrode are in the same plane;
  • a semiconductor layer formed on an upper surface of the insulating layer and disposed opposite to the gate electrode;
  • a data line formed on an upper surface of the insulating layer and/or an upper surface of the semiconductor layer and partially overlapping the semiconductor layer;
  • the gate electrode structure is electrically connected to the plurality of pixels
  • the recess is formed by a photolithography process; the photoresist and the upper surface of the recess are deposited to form a gate electrode conductive layer; and the buffer layer, the insulating layer and the semiconductor layer are formed by chemical vapor deposition Process.
  • the gate electrode structure and the manufacturing method thereof and the display device proposed in the present application have a buffer layer formed on the substrate, a groove formed on the buffer layer, and a gate electrode formed in the groove And the upper surface of the gate electrode is on the same plane as the upper surface of the buffer layer.
  • An insulating layer is further formed on the upper surface of the gate electrode and the upper surface of the buffer layer, and a semiconductor layer and a data line are further formed on the insulating layer, so that the insulating layer is formed on one plane without being subjected to the gate electrode profile angle
  • the effect of this greatly reduces the probability of disconnection at the intersection of the data line and the gate electrode, thereby improving the yield of the product.
  • FIG. 1 is a schematic diagram of a buffer layer according to an embodiment of the present application.
  • FIG. 2 is a schematic view showing a coating photoresist according to an embodiment of the present application.
  • FIG. 3 is a schematic diagram of photolithography proposed in the embodiment of the present application.
  • FIG. 4 is a schematic diagram of forming a gate electrode according to an embodiment of the present application.
  • FIG. 5 is a schematic diagram of removing photoresist from an embodiment of the present application.
  • FIG. 6 is a schematic diagram of forming an insulating layer according to an embodiment of the present application.
  • FIG. 7 is a schematic structural view of a gate electrode according to an embodiment of the present application.
  • FIG. 8 is a flow chart of manufacturing an embodiment of a method for fabricating a gate electrode structure according to the present application.
  • FIG. 9 is a flow chart of manufacturing an embodiment of a photolithography method according to the present application.
  • FIG. 10 is a flow chart showing the fabrication of an embodiment of a method for forming a gate electrode according to the present application.
  • the present application provides a gate electrode structure and a method of fabricating the same.
  • the gate electrode manufacturing method is: in step S1, the substrate 1 is prepared, and a buffer is formed on a substrate side surface 11 of the substrate 1.
  • Layer 2 in step S2, a groove 3 is formed on the upper surface 21 of the buffer layer, the groove 3 extends through the buffer layer 2, in step S3, the gate electrode 5 is formed in the groove 3, and the upper surface 51 of the gate electrode is The buffer layer upper surface 21 is on the same plane P.
  • an insulating layer 6 is formed on the gate electrode upper surface 51 and the buffer layer upper surface 21, and in step S5, on the insulating layer upper surface 61 of the insulating layer 6.
  • the semiconductor layer 8 opposed to the gate electrode 5 is formed with a data line 71 crossing the gate electrode 5 on the semiconductor layer 8 and/or the insulating layer 6 in step S6.
  • the gate electrode upper surface 51 and the buffer layer upper surface 21 are on the same plane P, and the insulating layer 6 can be formed on one plane P, thereby eliminating the problem that the gate electrode 5 is inferior to the insulating layer 6 due to its own height, shape or profile angle of the gate electrode 5.
  • the influence of the coverage at the edge of the gate electrode 5 greatly reduces the occurrence of disconnection at the intersection of the gate electrode 5 and the data line 71 when the data line 71 is formed. Improve the pass rate of the product.
  • the buffer layer 2 is formed on one side surface of the substrate 1. In other embodiments, the buffer layer 2 may be on both sides of the substrate 1 or other positions, which are not limited herein.
  • the buffer layer 2 for forming the gate electrode 5 and the periphery of the gate electrode 5 is formed by first forming the buffer layer 2, and then forming the above-mentioned groove 3 on the buffer layer 2, wherein the groove 3 is buffered. Layer 2, and forming the gate electrode 5 in the recess 3. In other embodiments, other sequences may be employed, such as forming the gate electrode 5 first, and then forming a buffer layer on the same side substrate 11 around the gate electrode 5. 2, or the buffer layer 2 and the gate electrode 5 are directly formed on the substrate 1 in separate sub-regions, which are not limited herein.
  • the gate electrode upper surface 51 and the buffer layer upper surface 21 are on the same plane P.
  • the insulating layer 6 may be formed on a plane P to make the semiconductor layer 8 and the data line.
  • the 71 can be formed directly on one plane, reducing the influence of the shape or profile angle of the gate electrode 5 on the data line 71.
  • the gate electrode upper surface 51 and the buffer layer upper surface 21 are not necessarily completely on one plane P, and may have a certain relative height difference, for example, the distance from the upper surface 51 of the gate electrode 5 to the substrate 1 is smaller than the buffer layer.
  • the distance from the upper surface 21 to the substrate 1 is formed into a "concave” shape, and the semiconductor layer 8 is formed in a concave shape of a "concave” shape (not shown in the drawing), if the distance from the upper surface 83 of the semiconductor layer to the substrate 1 is as described above
  • the distance from the upper surface 61 of the insulating layer on the buffer layer 2 to the substrate 1 is the same, so that the upper surface 83 of the semiconductor layer and the upper surface 61 of the insulating layer on the buffer layer 2 are on one plane, and thus, the data line 71 is formed at On one plane, the disconnection of the data line 71 at the intersection of the gate electrode 5 is also reduced; likewise, the distance from the upper surface 51 of the gate electrode 5 to the substrate 1 is greater than the distance from the upper surface 21 of the buffer layer to the substrate 1.
  • a "convex" shape is formed, and the semiconductor layer 8 is formed in the convex shape of the convex shape, which is not limited herein.
  • the insulating layer 6 is formed on the gate electrode upper surface 51 and the buffer layer upper surface 21, and thus functions as an insulating layer and also serves as a base of the semiconductor layer 8 and the data line 71.
  • the insulating layer 6 can also It is only deposited on the upper surface 51 of the gate electrode, and the buffer layer 2 is used to realize the insulating function in a region other than the gate electrode.
  • other methods may be used for the insulation as long as the gate electrode 5 and the semiconductor layer 8 can be made. The purpose of insulation is achieved. This is not a single limitation.
  • the semiconductor layer 8 includes a first semiconductor layer 81 and a second semiconductor layer 82, wherein the material deposited by the first semiconductor layer 81 is amorphous silicon, and the material deposited by the second semiconductor layer 82 is highly concentrated.
  • the N-type amorphous silicon is mixed, and at the same time, the semiconductor layer 8 partially overlaps with the gate electrode 5, so that the gate electrode can control the on and off of the current between the data line 71 and the source 72 in the semiconductor layer.
  • other materials may be used to form the semiconductor layer, as long as the switching function of the gate electrode 5 can be realized, which is not limited herein.
  • the data line 71 and the source 72 are formed on the upper surface 61 of the insulating layer 6 or the upper surface 83 of the semiconductor layer 8, and intersect the gate electrode 5.
  • the region where the data line 71 and the source 72 intersect the gate electrode 5 is the position at which the gate electrode 5 controls the current between the data line 71 and the source 72.
  • the recess 3 is formed by photolithography, and thus the recess 3 for the gate electrode 5 can be formed on the buffer layer 2 by using photolithography. Simple and low cost.
  • other methods of forming the recess 3 on the buffer layer 2, such as laser engraving and the like, may be used, which are not limited herein.
  • the method of photolithography can also be used in the process of generating the data line 71.
  • the step of forming the data line 71 includes: first step: forming a conductive layer of the data line 71; and second step: removing the conductive layer other than the data line 71 and the source 72 by photolithography. Also, as long as the data line 71 can be formed, it is not limited to the use of photolithography, and is not limited herein.
  • the step of photolithography includes: applying a photoresist F to the upper surface 21 of the buffer layer 2 in step S10; and providing a photomask over the photoresist F in step S20 ( The drawing is not shown) and the light source (not shown in the drawing); in step S30, the light source is turned on, the light source is exposed to a portion of the photoresist F through the reticle; in step S40, the exposed photoresist F is developed; In step S50, the portion of the photoresist F that is exposed and developed is etched away and the buffer layer 2 between the exposed photoresist F and the substrate 1 is etched; in step S60, the substrate 1 is cleaned, and the photoresist is etched.
  • the corroded buffer layer 2 is removed.
  • the photoresist F is uniformly coated on the buffer layer 2, the photomask is disposed above the photoresist F, and after being developed and etched, the buffer layer 2 at the recess 3 is etched away, and finally the substrate 1 is cleaned, thereby forming The groove 3 is.
  • the exposed photoresist F region may be etched, and the exposed photoresist region F may not be etched.
  • other types of photoresist may also be selected, such as photoresist F regions that are not exposed may be etched.
  • the steps in the above lithography may be reduced or some other steps may be added as long as the groove 3 is formed on the buffer layer 2, which is not limited herein.
  • the step of forming the gate electrode 5 includes: forming the gate electrode 5 and the conductive layer 4 on the upper surface of the photoresist F and the recess 3 in step S100; In step S200, the photoresist F is peeled off. Its In the upper surface of the photoresist F and the recess 3, the conductive layer 4 is formed, and the recess 3 is filled with a conductive layer to serve as the gate electrode 5.
  • the photoresist F is peeled off, the conductive layer 4 on the photoresist F can be peeled off together, thereby achieving the purpose of removing the conductive layer 4 on the photoresist F.
  • the gate electrode 5 can be formed by other methods.
  • a conductive layer is directly deposited on the substrate 1, and then a conductive layer other than the gate electrode 5 is etched away by photolithography, and then a buffer layer 2 is formed on the same side substrate 11 around the conductive layer.
  • the buffer layer 2 may be formed on the same side substrate 11 around the gate electrode 5 as long as other methods are available, and is not limited herein.
  • the method of peeling off the photoresist F is: etching the photoresist F using a photoresist. After the photoresist F is removed by using the photoresist, the conductive layer 4 deposited on the photoresist F is also removed, which is convenient and quick. Of course, in other embodiments, other methods for removing the photoresist F and the conductive layer 4 deposited on the upper surface of the photoresist F may be used, which are not limited herein.
  • the method of forming the buffer layer 2, the insulating layer 6 and the semiconductor layer 8 is chemical vapor deposition, and the buffer layer 2 and the insulating layer 6 are formed by chemical vapor deposition in a relatively simple and inexpensive manner. And a semiconductor layer 8.
  • the buffer layer 2, the insulating layer 6, and the semiconductor layer 8 may be deposited in other manners, which are not limited herein.
  • the material used for the buffer layer 2 and the insulating layer 6 comprises: silicon nitride.
  • silicon nitride In this way, an effective insulation effect can be obtained.
  • other materials may also be used.
  • the switching function of the gate electrode 5 can be realized as long as the effect of the insulation can be obtained and the voltage is applied or removed from the gate electrode 5.
  • the material used for the gate electrode 5 and the data line 71 includes: aluminum or molybdenum.
  • Aluminum and molybdenum have good electrical conductivity and are easy to deposit, which can reduce production cost and production difficulty.
  • the gate electrode 5 and the data line 71 are not limited to aluminum or molybdenum as long as the gate electrode 5 and the data line 71 having good conductivity can be formed.
  • the gate electrode 5 and the data line 71 are not limited to being deposited of only one material, and may be multiple or multiple layers.
  • the gate electrode 5 may deposit aluminum first and then deposit molybdenum
  • the data line 71 may deposit molybdenum first, and then Aluminum is deposited, and finally molybdenum is deposited as long as the gate electrode 5 and the data line 71 are easily electrically conductive, and the order of deposition is not limited herein.
  • the embodiment of the present application further provides a gate electrode structure (not shown in the drawings), comprising: a substrate 1; a buffer layer 2 formed on the side surface 11 of the substrate 1, and the buffer layer 2 is provided with a recess penetrating through the buffer layer 2.
  • a trench 3 a gate electrode 5 formed in the recess 3, and the upper surface 21 of the buffer layer 2 is located on the same plane P as the upper surface 51 of the gate electrode 5; formed on the upper surface 21 of the buffer layer 2 and the gate electrode 5
  • a gate electrode 5 is formed on the substrate 1, and a buffer layer 2 is formed on the same substrate side surface 11 around the gate electrode 5, and the buffer layer upper surface 21 and the gate electrode upper surface 51 are in the same plane P, and the insulating layer 6 can be disposed.
  • the data line 71 is formed on the upper surface 61 of the insulating layer and the upper surface 83 of the semiconductor layer, the shape of the gate electrode 5 and the outer contour angle have no influence on the data line 71.
  • Embodiments of the present application also provide a display device (not shown in the drawings), the display device including a gate electrode structure.
  • a gate electrode 5 is formed on the substrate 1, and a buffer layer 2 is formed on the same substrate side surface 11 around the gate electrode 5, and the buffer layer upper surface 21 and the gate electrode upper surface 51 are in the same plane P, and the insulating layer 6 can be disposed.
  • Deposited on a plane P since the semiconductor layer 8 is deposited on the insulating layer 6 of the plane P, and the data line 71 is formed on the insulating layer upper surface 61 and the semiconductor layer upper surface 83, the shape of the gate electrode 5, the outer contour angle There is no effect on the data line 71.
  • the display device further includes a plurality of pixels (not shown in the drawing), and the gate electrode structure is electrically connected to the plurality of pixels.
  • the display device may be a liquid crystal display.
  • the liquid crystal display is provided with a gate electrode structure and a plurality of pixel electrodes.
  • the gate electrode structure is electrically connected to the plurality of pixel electrodes.
  • other display devices may be used. This is not a single limitation.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Thin Film Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

La présente invention se rapporte au domaine technique de l'affichage, et concerne une structure d'électrode de grille et un procédé de fabrication de celle-ci. Le procédé consiste à : former une couche tampon sur la surface d'un côté d'un substrat ; former une rainure dans la couche tampon, la rainure pénétrant à travers la couche tampon ; former une électrode de grille dans la rainure, une surface supérieure de l'électrode de grille et une surface supérieure de la couche tampon se trouvant sur le même plan ; former une couche isolante sur la surface supérieure de l'électrode de grille et la surface supérieure de la couche tampon ; former une couche de semi-conducteur en face de l'électrode de grille sur une surface supérieure de la couche isolante ; et former une ligne de données chevauchée partiellement par la couche de semi-conducteur sur la surface supérieure de la couche de semi-conducteur et/ou la surface supérieure de la couche isolante. L'invention concerne aussi un dispositif d'affichage comprenant la structure d'électrode de grille.
PCT/CN2017/100441 2017-03-03 2017-09-05 Structure d'électrode de grille et procédé de fabrication de celle-ci, et dispositif d'affichage Ceased WO2018157573A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US15/578,435 US10388678B2 (en) 2017-03-03 2017-09-05 Gate structure, method for manufacturing gate structure, and display device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201710123214.1 2017-03-03
CN201710123214.1A CN106876260B (zh) 2017-03-03 2017-03-03 一种闸电极结构及其制造方法和显示装置

Publications (1)

Publication Number Publication Date
WO2018157573A1 true WO2018157573A1 (fr) 2018-09-07

Family

ID=59169858

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2017/100441 Ceased WO2018157573A1 (fr) 2017-03-03 2017-09-05 Structure d'électrode de grille et procédé de fabrication de celle-ci, et dispositif d'affichage

Country Status (3)

Country Link
US (1) US10388678B2 (fr)
CN (1) CN106876260B (fr)
WO (1) WO2018157573A1 (fr)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106876260B (zh) 2017-03-03 2020-03-27 惠科股份有限公司 一种闸电极结构及其制造方法和显示装置
CN108172584A (zh) * 2017-12-26 2018-06-15 深圳市华星光电半导体显示技术有限公司 阵列基板及其上电极线图案的制备方法和液晶显示面板
CN109683740B (zh) * 2018-12-17 2021-06-01 武汉华星光电半导体显示技术有限公司 显示面板
US11488985B2 (en) * 2019-11-06 2022-11-01 Innolux Corporation Semiconductor device
CN113809095B (zh) * 2020-05-27 2024-12-31 京东方科技集团股份有限公司 阵列基板及其制备方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03159174A (ja) * 1989-11-16 1991-07-09 Sanyo Electric Co Ltd 液晶表示装置
CN1489790A (zh) * 2001-02-19 2004-04-14 �Ҵ���˾ 薄膜晶体管结构及其制造方法和使用它的显示器件
CN1652003A (zh) * 2005-03-22 2005-08-10 广辉电子股份有限公司 一种薄膜晶体管与液晶显示器的制造方法
CN1740882A (zh) * 2005-09-27 2006-03-01 广辉电子股份有限公司 液晶显示器的阵列基板及其制造方法
CN106876260A (zh) * 2017-03-03 2017-06-20 惠科股份有限公司 一种闸电极结构及其制造方法和显示装置

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5214858B2 (ja) * 2006-06-22 2013-06-19 三菱電機株式会社 Ｔｆｔアレイ基板及びその製造方法
CN101677058B (zh) * 2008-09-19 2012-02-29 北京京东方光电科技有限公司 薄膜构造体的制造方法
KR101820326B1 (ko) * 2010-11-30 2018-01-22 삼성디스플레이 주식회사 표시 기판 및 이의 제조 방법

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03159174A (ja) * 1989-11-16 1991-07-09 Sanyo Electric Co Ltd 液晶表示装置
CN1489790A (zh) * 2001-02-19 2004-04-14 �Ҵ���˾ 薄膜晶体管结构及其制造方法和使用它的显示器件
CN1652003A (zh) * 2005-03-22 2005-08-10 广辉电子股份有限公司 一种薄膜晶体管与液晶显示器的制造方法
CN1740882A (zh) * 2005-09-27 2006-03-01 广辉电子股份有限公司 液晶显示器的阵列基板及其制造方法
CN106876260A (zh) * 2017-03-03 2017-06-20 惠科股份有限公司 一种闸电极结构及其制造方法和显示装置

Also Published As

Publication number Publication date
CN106876260B (zh) 2020-03-27
US20180301475A1 (en) 2018-10-18
US10388678B2 (en) 2019-08-20
CN106876260A (zh) 2017-06-20

Similar Documents

Publication Publication Date Title
US8692258B2 (en) Array substrate of TFT-LCD including a black matrix and method for manufacturing the same
US6337284B1 (en) Liquid crystal display device and method of manufacturing the same
US9716110B2 (en) Array substrate, method for manufacturing the same, and display device
WO2017054384A1 (fr) Substrat matriciel, son procédé de fabrication et écran d'affichage
WO2018157573A1 (fr) Structure d'électrode de grille et procédé de fabrication de celle-ci, et dispositif d'affichage
US10566458B2 (en) Array substrate and method for manufacturing the same
CN106024813B (zh) 一种低温多晶硅tft阵列基板的制作方法及相应装置
CN106847836B (zh) Tft基板及其制作方法
CN106847830A (zh) 阵列基板及其制作方法、显示面板
WO2018120691A1 (fr) Substrat de matrice et son procédé de fqabrication, et dispositif d'affichage
CN105810695B (zh) 阵列基板及显示装置
CN103676375A (zh) 阵列基板及其制作方法
CN107221501A (zh) 垂直型薄膜晶体管及其制备方法
WO2020133651A1 (fr) Structure d'électrode de pixel et son procédé de fabrication
CN107293556A (zh) 一种显示面板及显示装置
CN104934443A (zh) 阵列基板及其制造方法、显示装置
US7485907B2 (en) Array substrate for liquid crystal display device and the seal pattern in the periphery of the display
CN110854205A (zh) 一种薄膜晶体管及制作方法、显示面板及显示装置
WO2019100494A1 (fr) Substrat de réseau de transistors en couches minces de type ips et son procédé de fabrication
CN105448936B (zh) 一种阵列基板及其制作方法、显示装置
WO2016201778A1 (fr) Substrat de matrice et procédé de fabrication associé
US10651205B2 (en) Array substrate, display panel and display device
WO2015180357A1 (fr) Substrat de matrice et son procédé de fabrication et dispositif d'affichage
CN101017832A (zh) 薄膜晶体管基板及其制造方法以及具有该基板的显示面板
CN105789121A (zh) 全反射阵列基板及其制备方法、显示器件

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 15578435

Country of ref document: US

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 17899161

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

32PN Ep: public notification in the ep bulletin as address of the adressee cannot be established

Free format text: NOTING OF LOSS OF RIGHTS PURSUANT TO RULE 112(1) EPC (EPO FORM 1205A DATED 16/12/2019)

122 Ep: pct application non-entry in european phase

Ref document number: 17899161

Country of ref document: EP

Kind code of ref document: A1