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WO2018163985A1 - Circuit d'attaque de ligne de balayage et dispositif d'affichage équipé dudit circuit - Google Patents

Circuit d'attaque de ligne de balayage et dispositif d'affichage équipé dudit circuit Download PDF

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Publication number
WO2018163985A1
WO2018163985A1 PCT/JP2018/007958 JP2018007958W WO2018163985A1 WO 2018163985 A1 WO2018163985 A1 WO 2018163985A1 JP 2018007958 W JP2018007958 W JP 2018007958W WO 2018163985 A1 WO2018163985 A1 WO 2018163985A1
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Prior art keywords
voltage
node
transistor
scanning line
driving circuit
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PCT/JP2018/007958
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English (en)
Japanese (ja)
Inventor
晶 田川
泰章 岩瀬
洋平 竹内
卓哉 渡部
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シャープ株式会社
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Publication of WO2018163985A1 publication Critical patent/WO2018163985A1/fr

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements

Definitions

  • the present invention relates to a scanning line driving circuit provided in a display device such as a liquid crystal display device, and a display device including the scanning line driving circuit.
  • Liquid crystal display devices are widely used as thin, lightweight, and low power consumption display devices.
  • a scanning line driving circuit and a thin film transistor (hereinafter referred to as TFT) along with a pixel circuit are provided on one substrate of the liquid crystal panel.
  • TFT thin film transistor
  • Such a scanning line driving circuit is called a monolithic gate driver circuit.
  • the TFT included in the scanning line driving circuit is configured using, for example, amorphous silicon or an oxide semiconductor.
  • the conductivity type of the TFT is an n-channel type.
  • the TFT included in the scanning line driving circuit is formed using low-temperature polysilicon or low-temperature CG (Continuous Grain) silicon.
  • the conductivity type of the TFT may be a p-channel type or an n-channel type.
  • the depletion type TFT has, for example, voltage-current characteristics shown in FIG. As shown in FIG. 16, in the depletion type TFT, even when the gate-source voltage Vgs is 0, a current Ids (> 0) flows between the drain and the source. The depletion type TFT is not completely turned off even when the gate terminal and the source terminal are equipotential. For this reason, in a scanning line driving circuit including a depletion type TFT, an output signal may become unstable. In addition, since a through current flows through the scanning line driving circuit, current supply from a control circuit that controls the scanning line driving circuit is insufficient, and the scanning line driving circuit may malfunction.
  • Patent Document 1 describes a scanning line driving circuit using a depletion type TFT having a configuration in which unit circuits shown in FIG. 17 are connected in multiple stages and operating according to a timing chart shown in FIG. Yes. Three types of low level voltages VGL1 to VGL3 are supplied to the unit circuit shown in FIG.
  • the scanning line driving circuit described in Patent Document 1 is supplied with clock signals CK1 to CK3 whose voltage level changes between VGH and VGL1, and clock signals CK1a to CK3a whose voltage level changes between VGH and VGL3. (See FIG. 18).
  • the amplitude differs between these two systems of clock signals. For this reason, the configuration of the control circuit for controlling the scanning line driving circuit becomes complicated, and the cost of the display device increases. In addition, it is necessary to adjust the timing between the two clock signals.
  • the scanning line driving circuit described in Patent Document 1 has a problem that the configuration of the control circuit becomes complicated and the cost of the display device increases.
  • each of the unit circuits includes a first conduction terminal connected to the clock terminal, a control terminal connected to the first node, and a second conduction terminal connected to the first output terminal for outputting a signal for the scanning line.
  • a second output terminal for outputting a signal to a unit circuit in another stage, a first conduction terminal connected to the clock terminal, a control terminal connected to the first node, A second output transistor having a second conduction terminal connected to the first node, a first node set transistor for applying the on-voltage to the first node according to the potential of the set terminal, and the potential according to the potential of the control terminal.
  • a first node reset transistor that applies a second off voltage to the first node
  • a second output reset transistor that applies a third off voltage to the second output terminal according to the potential of the second node.
  • the second off voltage is a voltage farther from the on voltage than the first off voltage
  • the third off voltage is a voltage farther from the on voltage than the second off voltage. It is.
  • the first to third off voltages having the above-described magnitude relationship are applied to the first output terminal, the first node, and the second node of the unit circuit, respectively.
  • a voltage at which the transistor is turned off (difference between the second off voltage and the first off voltage) is applied between the control terminal and the second conduction terminal of the first output transistor
  • a voltage at which the transistor is turned off (difference between the third off voltage and the second off voltage) is also applied between the control terminal and the second conduction terminal of the first node set transistor.
  • the scanning line driving circuit operates in accordance with a clock signal that changes between two voltage levels. Therefore, a scan line driver circuit using a depletion type transistor that can be controlled more easily than in the past can be provided.
  • FIG. 1 is a block diagram illustrating a configuration of a scanning line driving circuit according to a first embodiment.
  • FIG. FIG. 2 is a circuit diagram of a unit circuit of the scanning line driving circuit shown in FIG. 1.
  • 2 is a timing chart of the scanning line driving circuit shown in FIG. It is a block diagram which shows the structure of the scanning line drive circuit which concerns on a comparative example.
  • It is a circuit diagram of a unit circuit of a scanning line driving circuit according to a comparative example.
  • 6 is a timing chart of a scanning line driving circuit according to a comparative example. It is a figure which shows the electric potential of the terminal of the transistor in a non-selection period about the scanning line drive circuit which concerns on a comparative example.
  • FIG. 2 is a diagram showing a potential of a transistor in a non-selection period for the scanning line driving circuit shown in FIG.
  • FIG. 6 is a circuit diagram of a unit circuit of a scanning line driving circuit according to a second embodiment. It is a block diagram which shows the structure of the scanning-line drive circuit which concerns on 3rd Embodiment. 13 is a timing chart of the scanning line driving circuit shown in FIG.
  • FIG. 15 is a timing chart of the scanning line driving circuit shown in FIG. It is a figure which shows the example of the voltage-current characteristic of a depletion type TFT. It is a circuit diagram of a unit circuit of a conventional scanning line driving circuit. It is a timing chart of the conventional scanning line drive circuit.
  • the scanning line driving circuit according to each embodiment has a configuration in which n (n is an integer of 1 or more) unit circuits are connected in multiple stages, and operates according to a multiphase clock signal.
  • n unit circuits included in the scanning line driving circuit are referred to as SR1, SR2,.
  • the horizontal direction of the drawing is referred to as the row direction, and the vertical direction of the drawing is referred to as the column direction.
  • a voltage that turns on the transistor when applied to the control terminal is referred to as an on-voltage
  • a voltage that turns off the transistor when applied to the control terminal is referred to as an off-voltage.
  • the high level voltage is an on voltage and the low level voltage is an off voltage.
  • the p-channel transistor the low level voltage is an on voltage and the high level voltage is an off voltage.
  • FIG. 1 is a block diagram illustrating a configuration of a scanning line driving circuit according to the first embodiment.
  • the scanning line driving circuit 10 shown in FIG. 1 is formed together with the display unit 5 on one substrate of a liquid crystal panel (not shown).
  • the display unit 5 is also called an active area, and the scanning line driving circuit 10 is also called a monolithic gate driver circuit.
  • the display unit 5 and the scanning line driving circuit 10 constitute a liquid crystal display device together with a data line driving circuit (not shown).
  • n is a multiple of 8
  • i is an integer of 1 to n
  • k is an integer of 1 to (n / 8).
  • the display unit 5 includes n scanning lines G1 to Gn (not shown) extending in the row direction, a plurality of data lines (not shown) extending in the column direction, and a plurality of data including the scanning lines G1 to Gn.
  • a plurality of pixel circuits (not shown) arranged corresponding to the intersections of the lines are included.
  • the scanning line drive circuit 10 includes a first drive unit 12 disposed on the left side of the display unit 5 and a second drive unit 13 disposed on the right side of the display unit 5.
  • Each of the first and second drive units 12 and 13 has a configuration in which (n / 2) unit circuits 11 are connected in multiple stages.
  • the first drive unit 12 includes odd-numbered unit circuits SR1, SR3,..., SRn-1, and the second drive unit 13 includes even-numbered unit circuits SR2, SR4,.
  • the unit circuit 11 has a clock terminal CK, a set terminal S, a reset terminal R, a first output terminal G, and a second output terminal Q.
  • the first output terminal G of the odd-numbered unit circuits SR1, SR3,..., SRn-1 is connected to the left end of the odd-numbered scanning lines G1, G3,.
  • the first output terminals G of the even-numbered unit circuits SR2, SR4,..., SRn are connected to the right ends of the even-numbered scanning lines G2, G4,.
  • the first driving unit 12 drives odd-numbered scanning lines G1, G3,..., Gn ⁇ 1, and the second driving unit 13 drives even-numbered scanning lines G2, G4,.
  • Such a driving method of the scanning lines G1 to Gn is also called comb driving (interlace driving).
  • the scanning line driving circuit 10 is supplied with 8-phase clock signals CK1 to CK8, two gate start pulses GSP1 and GSP2, and four clear signals CLR1 to CLR4.
  • the clock signals CK1 to CK8 are supplied to the clock terminals CK of the unit circuits 11 in the (8k-7) to 8k stages, respectively.
  • the gate start pulses GSP1 and GSP2 are supplied to the set terminals S of the first and second stage unit circuits SR1 and SR2, respectively.
  • the set terminals S of the unit circuits SR3 to SRn at the third to nth stages are connected to the second output terminal Q of the unit circuit at the second stage.
  • the clear signals CLR1 to CLR4 are supplied to the reset terminals R of the (n-3) to n-th unit circuits SRn-3 to SRn, respectively.
  • the reset terminals R of the unit circuits SR1 to SRn-4 in the 1st to (n-4) stages are connected to the second output terminal Q of the unit circuit in the 4th stage.
  • FIG. 2 is a circuit diagram of the unit circuit 11.
  • the unit circuit 11 includes nine transistors M1, M5, M6, M8 to M10, M14, M10B, M14B, and a capacitor C10.
  • the transistors included in the unit circuit 11 are all n-channel and depletion type TFTs.
  • the transistor included in the unit circuit 11 is, for example, a TFT having a semiconductor layer formed using an oxide semiconductor.
  • the transistor included in the unit circuit 11 may be an IGZO-TFT having a semiconductor layer formed using indium gallium zinc oxide (Indium Gallium Zinc Oxide: IGZO).
  • the high level voltage VGH is applied to the drain terminals of the transistors M1 and M5 and the gate terminal of the transistor M5.
  • the source terminal of the transistor M1, the drain terminals of the transistors M8 and M9, and the gate terminals of the transistors M6, M10, and M10B are connected to the node Na.
  • the source terminal of the transistor M5, the drain terminal of the transistor M6, and the gate terminals of the transistors M8, M14, and M14B are connected to the node Nb.
  • the gate terminal of the transistor M1 is connected to the set terminal S.
  • the gate terminal of the transistor M9 is connected to the reset terminal R.
  • the drain terminals of the transistors M10 and M10B are connected to the clock terminal CK.
  • the source terminal of the transistor M10 and the drain terminal of the transistor M14 are connected to the first output terminal G.
  • the source terminal of the transistor M10B and the drain terminal of the transistor M14B are connected to the second output terminal Q.
  • the capacitor C10 is provided between the gate and source of the transistor M10.
  • a low level voltage VSS1 is applied to the source terminals of the transistors M6 and M14.
  • a low level voltage VSS2 is applied to the source terminals of the transistors M8 and M9.
  • the low level voltage VSS3 is applied to the source terminal of the transistor M14B.
  • the low level voltage VSS2 is lower than the low level voltage VSS1, and the low level voltage VSS3 is lower than the low level voltage VSS2. That is, the low level voltages VSS1 to VSS3 satisfy the following expression (1).
  • the low level voltage VSS2 is a voltage farther from the high level voltage VGH than the low level voltage VSS1
  • the low level voltage VSS3 is a voltage farther from the high level voltage VGH than the low level voltage VSS2.
  • FIG. 3 is a timing chart of the scanning line driving circuit 10.
  • one cycle of the clock signal CK1 is referred to as T.
  • the clock signal CK1 becomes a high level in a quarter period of one period and becomes a low level in the remaining 3/4 period.
  • the clock signals CK2 to CK8 are signals delayed by T / 8, T / 4, 3T / 8, T / 2, 5T / 8, 3T / 4, and 7T / 8 from the clock signal CK1, respectively.
  • the high level voltage of the clock signals CK1 to CK8 is VGH
  • the low level voltage of the clock signals CK1 to CK8 is VSS1.
  • the scanning line driving circuit 10 operates in accordance with 8-phase clock signals CK1 to CK8 that change between the high level voltage VGH and the low level voltage VSS1.
  • FIG. 3 shows changes in the potentials of the clock signals CK1 to CK8 and changes in the potentials of the nodes and terminals of the unit circuit 11 in the (8k-7) stage.
  • the scanning line driving circuit 90 includes a first driving unit in which (n / 2) unit circuits 91 are connected in multiple stages, and a second driving unit having the same configuration as the first driving unit. As shown in FIG. 5, the unit circuit 91 does not include the transistors M10B and M14B and does not have the second output terminal Q. In the unit circuit 91, the low level voltage VSS1 is applied to the source terminals of the transistors M8 and M9.
  • the output signal of the i-th stage unit circuit 91 (the signal output from the output terminal G) is supplied to the scanning line Gi, and the set terminal S of the unit circuit 91 after the second stage and the unit circuit 91 before the fourth stage. To the reset terminal R.
  • FIG. 6 is a timing chart of the scanning line driving circuit 90.
  • FIG. 6 shows changes in the potentials of the clock signals CK1 to CK8 and changes in the potentials of the nodes and terminals of the unit circuit 91 in the (8k-7) stage, as in FIG. With reference to FIG. 6, the operation of the unit circuit 91 in the (8k-7) stage will be described.
  • the potential of the set terminal S (the output signal of the unit circuit 91 two stages before) changes to high level
  • the transistor M1 is turned on and the potential of the node Na becomes high level.
  • the transistors M6 and M10 are turned on, the potential of the node Nb becomes low level, and the transistors M8 and M14 are turned off.
  • the potential of the clock terminal CK clock signal CK1
  • the potential of the output terminal G (the output signal of the unit circuit 91) is at a low level.
  • the potential of the clock terminal CK changes to a high level. While the potential of the clock terminal CK is at a high level, the potential of the node Na is raised to a higher level than usual due to the push-up. Further, since the transistor M10 is in the on state, the potential of the output terminal G is high while the potential of the clock terminal CK is high. At this time, since the gate potential of the transistor M10 is higher than usual, the potential of the output terminal G becomes high level (VGH) with no threshold drop.
  • the potential of the clock terminal CK changes to the low level
  • the potential of the output terminal G changes to the low level
  • the potential of the node Na returns to the normal high level.
  • the transistor M9 is turned on
  • the potential of the node Na becomes a low level
  • the transistor M6 is turned off.
  • the potential of the node Nb becomes high level by the action of the transistor M5, and the transistors M8 and M14 are turned on.
  • the transistor M8 applies the low level voltage VSS1 to the node Na
  • the transistor M14 applies the low level voltage VSS1 to the output terminal G.
  • FIG. 7 is a diagram showing the potential of the terminal of the transistor M10 in the non-selection period for the scanning line driving circuit 90.
  • the gate-source voltage Vgs of the transistor M10 is zero.
  • the current Ix (> 0) flows between the drain and the source.
  • the potential of the output terminal G rises and the output signal of the unit circuit 91 rises unnecessarily.
  • the potentials of the output terminal G, the set terminal S, and the reset terminal R rise unnecessarily at the timing indicated by the arrows in FIG.
  • the scanning line driving circuit 90 malfunctions, and the display quality of the display device including the scanning line driving circuit 90 may deteriorate.
  • a method of lowering the gate potential of the transistor M10 during the non-selection period than the source potential (hereinafter referred to as the first method) can be considered.
  • a low level voltage VSS2 ( ⁇ VSS1) lower than the low level voltage VSS1 may be applied to the source terminals of the transistors M8 and M9.
  • FIG. 8 is a diagram illustrating the potentials of the terminals of the transistors M1 and M8 in the non-selection period when the first method is applied to the scanning line driving circuit 90.
  • the gate potential of the transistor M1 in the non-selection period is VSS1
  • the source potential is VSS2. Since the gate-source voltage Vgs of the transistor M1 is positive, the transistor M1 is turned on.
  • the gate potential of the transistor M8 is (VGH ⁇ Vth) (where Vth is the threshold voltage of the transistor M5), and the source potential is VSS2.
  • the transistor M8 Since VGH ⁇ Vth> VSS1, since the gate-source voltage Vgs of the transistor M8 is positive, the transistor M8 is also turned on. As described above, when the first method is applied to the scanning line driving circuit 90, the transistors M1 and M8 are turned on and the high-level voltage VGH is supplied in the non-selection period, the transistors M1, M8, and low Leakage current ILa flows through a path passing through a power supply line that supplies level voltage VSS2.
  • FIG. 9 is a diagram illustrating the potentials of the terminals of the transistors M1 and M8 in the non-selection period when the second method is applied to the scanning line driving circuit 90.
  • the gate-source voltage Vgs of the transistor M1 in the non-selection period is zero.
  • the leakage current ILb flows through the same path as when the first method is applied. Note that the leakage current ILb in this case is smaller than the leakage current ILa when the first method is applied.
  • the unit circuit 11 included in the scanning line driving circuit 10 is different from the unit circuit 91 included in the scanning line driving circuit 90 in the following points.
  • the unit circuit 11 includes transistors M10B and M14B and has a second output terminal Q.
  • the drain terminal of the transistor M10B is connected to the clock terminal CK
  • the gate terminal of the transistor M10B is connected to the node Na
  • the source terminal of the transistor M10B is connected to the second output terminal Q.
  • the drain terminal of the transistor M14B is connected to the second output terminal Q
  • the gate terminal of the transistor M14B is connected to the node Nb.
  • the low level voltage VSS2 is applied to the source terminals of the transistors M8 and M9
  • the low level voltage VSS3 is applied to the source terminal of the transistor M14B.
  • the low level voltages VSS1 to VSS3 satisfy Expression (1).
  • the operation of the unit circuit 11 at the (8k-7) stage will be described with reference to FIG.
  • the transistors M10B and M14B are turned on / off at the same timing as the transistors M10 and M14, respectively.
  • the potential of the first output terminal G is VGH when the potential of the clock terminal CK is at a high level within the selection period, and is VSS1 otherwise.
  • the potential of the terminal of the second output terminal Q is VGH when the potential of the clock terminal CK is high in the selection period, VSS1 when the potential of the clock terminal CK is low during the selection period, and VSS3 in the non-selection period. .
  • the potential of the set terminal S (the output signal from the second output terminal Q of the unit circuit 11 two stages before) changes ahead of the potential of the second output terminal Q by T / 4.
  • the potential of the reset terminal R (the output signal from the second output terminal Q of the unit circuit 11 after four stages) changes with a delay of T / 2 from the potential of the second output terminal Q.
  • the transistor M1 When the potential of the set terminal S changes to high level, the transistor M1 is turned on and the potential of the node Na becomes high level. Accordingly, the transistors M6, M10, and M10B are turned on, the potential of the node Nb becomes low level, and the transistors M8 and M14 are turned off. At this time, since the potential of the clock terminal CK is VSS1, the potentials of the first and second output terminals G and Q are VSS1.
  • the potential of the clock terminal CK changes to a high level. While the potential of the clock terminal CK is at a high level, the potential of the node Na is raised to a higher level than usual due to the push-up. Since the transistors M10 and M10B are on, the potentials of the first and second output terminals G and Q are high while the potential of the clock terminal CK is high. At this time, since the gate potentials of the transistors M10 and M10B are at a higher level than usual, the potentials at the first and second output terminals G and Q are at a high level (VGH) with no threshold drop.
  • VGH high level
  • the transistor M8 applies the low level voltage VSS2 to the node Na
  • the transistor M14 applies the low level voltage VSS1 to the first output terminal G
  • the transistor M14B applies the low level voltage VSS3 to the second output terminal Q. For this reason, the electric potential of the 2nd output terminal Q falls to VSS3.
  • the transistor M10 includes a first terminal having a drain terminal connected to the clock terminal CK, a gate terminal connected to the node Na, and a source terminal connected to the first output terminal G for outputting a signal for the scanning line. Functions as an output transistor.
  • the transistor M10B includes a drain terminal connected to the clock terminal CK, a gate terminal connected to the node Na, and a source terminal connected to the second output terminal Q for outputting a signal to the unit circuit 11 in the other stage. It functions as a second output transistor having
  • the transistor M1 functions as a first node set transistor that applies the high level voltage VGH to the node Na according to the potential of the set terminal S.
  • the transistor M9 functions as a first node reset transistor that applies the low level voltage VSS2 to the node Na according to the potential of the reset terminal R (the potential of the gate terminal).
  • the transistor M8 functions as a first node auxiliary reset transistor that applies the low level voltage VSS2 to the node Na according to the potential of the node Nb.
  • the transistor M14 functions as a first output reset transistor that applies the low-level voltage VSS1 to the first output terminal G according to the potential of the node Nb.
  • the transistor M14B functions as a second output reset transistor that applies the low-level voltage VSS3 to the second output terminal Q in accordance with the potential of the node Nb.
  • the transistor M5 functions as a voltage continuous application transistor that applies a high level voltage to the node Nb in a fixed manner.
  • the transistor M6 functions as a second node reset transistor that applies the low level voltage VSS1 to the node Nb in accordance with the potential of the node Na.
  • the transistors M5 and M6 constitute a second node control unit that controls the potential of the node Nb to a potential of a logic level opposite to the potential of the node Na.
  • the unit circuit 11 includes a transistor M10B sharing a drain terminal and a gate terminal with the transistor M10. Therefore, the output signals for the scanning lines G1 to Gn (signals output from the first output terminal G) and the output signals for the other unit circuits 11 (signals output from the second output terminal Q) are separated. Can do. Therefore, the low level voltage VSS3 of the latter output signal can be set separately from the low level voltage VSS1 of the former output signal.
  • the low level voltage VSS3 is set so as to satisfy Expression (1).
  • FIG. 10A is a diagram showing the potential of the terminal of the transistor M10 during the non-selection period for the scanning line driving circuit 10.
  • FIG. 10A in the non-selection period, the gate potential of the transistor M10 is VSS2, and the source potential is VSS1. From equation (1), the gate-source voltage Vgs of the transistor M10 is negative. Therefore, even when the transistor M10 is a depletion type, no current flows between the drain and source of the transistor M10. Thus, in the scanning line driving circuit 10, the current Ix shown in FIG. 7 does not flow during the non-selection period.
  • FIG. 10B is a diagram showing the potentials of the terminals of the transistors M1 and M8 in the non-selection period for the scanning line driving circuit 10.
  • the gate potential of the transistor M1 is VSS3 and the source potential is VSS2.
  • the gate-source voltage Vgs of the transistor M1 is negative. Therefore, even when the transistor M1 is a depletion type, no current flows between the drain and source of the transistor M1. Therefore, in the scanning line driving circuit 10, the leakage currents ILa and ILb shown in FIGS. 8 and 9 do not flow during the non-selection period.
  • the scanning line driving circuit 10 it is necessary to set the low level voltages VSS1 to VSS3 so as to satisfy the expression (1).
  • the current flowing through the TFT in the off state when the drain-source voltage Vds is 10 V should be 1 ⁇ 10 ⁇ 9 A or less per unit channel length and unit channel width. It is enough. Therefore, based on the characteristics of the TFT, the gate-source in which the current (drain-source current) flowing through the TFT when the drain-source voltage Vds is 10 V is 1 ⁇ 10 ⁇ 9 A per unit channel length and unit channel width.
  • the inter-level voltage (hereinafter referred to as Va) is obtained, and the low-level voltages VSS2 and VSS3 are set so as to satisfy VSS1-VSS2> (absolute value of Va) and VSS2-VSS3> (absolute value of Va).
  • the scanning line driving circuit 10 In the scanning line driving circuit 10, during the non-selection period, the current Ix shown in FIG. 7 does not flow, and the leakage currents ILa and ILb shown in FIGS. 8 and 9 do not flow. Therefore, malfunction of the scanning line driving circuit 10 can be prevented, and power consumption in the control circuit of the scanning line driving circuit 10 can be reduced. Further, the scanning line driving circuit 10 operates in accordance with 8-phase clock signals CK1 to CK8 that change between two voltage levels VGH and VSS1. Therefore, according to the scanning line driving circuit 10, it is possible to provide a scanning line driving circuit that uses a depletion type transistor and can be controlled more easily than in the past.
  • the scanning line driving circuit 10 has a configuration in which a plurality of unit circuits 11 are connected in multiple stages, and an on voltage (high level voltage VGH) and a first off voltage (low level voltage VSS1). ) And the multi-phase (eight-phase) clock signals CK1 to CK8.
  • Each unit circuit 11 outputs a signal to the first conduction terminal (drain terminal) connected to the clock terminal CK, a control terminal (gate terminal) connected to the first node (node Na), and the scanning line.
  • a first output transistor (transistor M10) having a second conduction terminal (source terminal) connected to the first output terminal G, a first conduction terminal connected to the clock terminal CK, and a first node.
  • a second output transistor (transistor M10B) having a control terminal and a second conduction terminal connected to a second output terminal Q for outputting a signal to the unit circuit 11 in the other stage;
  • a first node set transistor (transistor M1) that applies an on voltage to the first node, and a second off voltage (low level) at the first node according to the potential of the control terminal.
  • a first node reset transistor (transistor M9) that applies a voltage VSS2), and a second output reset transistor that applies a third off voltage (low level voltage VSS3) to the second output terminal Q in accordance with the potential of the second node.
  • the second off voltage is a voltage farther from the on voltage than the first off voltage
  • the third off voltage is a voltage farther from the on voltage than the second off voltage.
  • the first to third off voltages having the above-described magnitude relationship are applied to the first output terminal G, the first node, and the second node of the unit circuit 11, respectively. Is done.
  • a voltage at which the transistor is turned off (difference between the second off voltage and the first off voltage) is applied between the control terminal and the second conduction terminal of the first output transistor,
  • a voltage at which the transistor is turned off (difference between the third off voltage and the second off voltage) is also applied between the control terminal and the second conduction terminal of the first node set transistor.
  • the scanning line driving circuit 10 operates according to a clock signal that changes between two voltage levels. Therefore, a scan line driver circuit using a depletion type transistor that can be controlled more easily than in the past can be provided.
  • Each unit circuit 11 includes a second node control unit that controls the potential of the second node to a potential of a logic level opposite to the potential of the first node.
  • a second node control unit that controls the potential of the second node to a potential of a logic level opposite to the potential of the first node.
  • the first node reset transistor applies a second off voltage to the first node according to the potential of the reset terminal R. Therefore, the second off voltage can be applied to the first node according to the potential of the reset terminal using the first node reset transistor.
  • Each unit circuit 11 includes a first node auxiliary reset transistor (transistor M8) that applies a second off voltage to the first node according to the potential of the second node. By providing the first auxiliary reset transistor, the second off voltage can be applied to the first node together with the first node reset transistor.
  • Each unit circuit 11 includes a first output reset transistor (transistor M14) that applies a first off voltage to the first output terminal G in accordance with the potential of the second node. By providing the first output reset transistor, the first off voltage can be applied to the first output terminal.
  • the second node control unit applies a voltage continuous application transistor (transistor M5) that applies an on-voltage to the second node in a fixed manner and a first off-voltage to the second node according to the potential of the first node.
  • a second node reset transistor transistor M6. Therefore, the second node control unit that controls the potential of the second node to the potential of the logic level opposite to the potential of the first node can be configured by using the voltage continuous application transistor and the second node reset transistor.
  • the difference between the first off-voltage and the second off-voltage (VSS1-VSS2) and the difference between the second off-voltage and the third off-voltage (VSS2-VSS3) are set based on the characteristics of the transistors included in the unit circuit 11. ing.
  • the difference between the first off-voltage and the second off-voltage and the difference between the second off-voltage and the third off-voltage are the voltage between the first and second conduction terminals of the transistor (the drain-source voltage Vds of the TFT).
  • Is 10 V the current flowing between the transistors (drain-source current) is 1 ⁇ 10 ⁇ 9 A per unit channel length and unit channel width. It is set larger than the absolute value of the gate-source voltage.
  • the first to third off-voltages are set in consideration of the transistor characteristics, so that current flows through the first output transistor and the first node set transistor in the non-selection period. Can be prevented. Therefore, the output signal of the scanning line driving circuit 10 can be stabilized and the malfunctioning of the scanning line driving circuit 10 can be prevented.
  • the plurality of clock signals CK1 to CK8 have the same amplitude, and one clock signal selected from the plurality of clock signals CK1 to CK8 is input to each unit circuit 11 via the clock terminal CK. . Therefore, it is possible to provide a scanning line driving circuit that operates based on multiphase clock signals having the same amplitude and can be controlled more easily than in the past.
  • the transistor included in the unit circuit 11 is a thin film transistor having a semiconductor layer formed using an oxide semiconductor. Therefore, leakage current in the scanning line driving circuit 10 can be reduced, and malfunctioning of the scanning line driving circuit 10 can be prevented.
  • the conductivity type of the transistor included in the unit circuit 11 is an n-channel type, the ON voltage is a high level voltage VGH, the first OFF voltage is a low level voltage VSS1, and the second OFF voltage is a low level voltage lower than the first OFF voltage.
  • VSS2 and the third off voltage are the low level voltage VSS3 lower than the second off voltage. Therefore, it is possible to provide the scanning line driving circuit 10 that uses an n-channel type and depletion type transistor and can be controlled more easily than in the past.
  • a display device including a display unit 5 including a plurality of scanning lines, a plurality of data lines, and a plurality of pixel circuits, and a scanning line driving circuit 10 that drives the scanning lines can be configured.
  • a low-cost display device can be provided by using the scanning line driving circuit 10 that uses a depletion type transistor and can be controlled more easily than in the past.
  • the scanning line driving circuit 10 is formed on the display panel (liquid crystal panel) together with the display unit 5. Therefore, the width of the peripheral part of the display screen can be reduced.
  • the scanning line driving circuit according to the second embodiment has the same configuration as the scanning line driving circuit 10 according to the first embodiment (see FIG. 1).
  • the scanning line driving circuit according to the present embodiment is formed together with the display unit 5 on one substrate of a liquid crystal panel (not shown) (gate driver monolithic configuration).
  • gate driver monolithic configuration the same constituent elements as those of the above-described embodiments are denoted by the same reference numerals and description thereof is omitted.
  • the scanning line driving circuit according to this embodiment has a configuration in which unit circuits 21 shown in FIG. 11 are connected in multiple stages instead of the unit circuit 11 shown in FIG.
  • the unit circuit 21 is obtained by connecting the source terminal of the transistor M9 to the node Nb in the unit circuit 11.
  • the transistor M9 is turned on and the potential of the node Nb becomes high level.
  • the transistors M8, M14, and M14B are turned on.
  • the transistor M8 applies the low level voltage VSS2 to the node Na
  • the transistor M14B applies the low level voltage VSS1 to the first output terminal G
  • the transistor M14B applies the low level voltage VSS3 to the second output terminal Q.
  • the scanning line driving circuit according to the present embodiment operates in the same manner as the scanning line driving circuit 10 according to the first embodiment.
  • the transistors M10, M10B, M1, M14, M14B, M5, and M6 are respectively a first output transistor, a second output transistor, a first node set transistor, and a first output reset. It functions as a transistor, a second output reset transistor, a voltage continuous application transistor, and a second node reset transistor, and the transistors M5 and M6 constitute a second node control unit.
  • the transistor M9 functions as a second node set transistor that applies the high level voltage VGH to the node Nb according to the potential of the reset terminal R.
  • the transistor M8 functions as a first node reset transistor that applies the low-level voltage VSS2 to the node Na in accordance with the potential of the node Nb (gate terminal potential).
  • the scanning line driving circuit according to the present embodiment the same effect as the scanning line driving circuit 10 according to the first embodiment can be obtained.
  • the drain terminal of the transistor M9 is not connected to the node Na.
  • the scanning line driving circuit according to the present embodiment also has an advantage that there is no leakage current path from the node Na through the transistor M9.
  • each unit circuit 21 applies the ON voltage (high level voltage VGH) to the second node (node Nb) according to the potential of the reset terminal R.
  • a second node set transistor (transistor M9) is included.
  • the first node reset transistor (transistor M8) applies the second off voltage (low level voltage VSS2) to the first node (node Na) according to the potential of the second node.
  • the second off voltage can be applied to the first node according to the potential of the second node using the first node reset transistor.
  • the scanning line driving circuit according to the present embodiment it is possible to provide a scanning line driving circuit that uses a depletion type transistor and can be controlled more easily than in the past, as in the first embodiment.
  • FIG. 12 is a block diagram illustrating a configuration of a scanning line driving circuit according to the third embodiment.
  • the scanning line driving circuit 30 shown in FIG. 12 is formed together with the display unit 5 on one substrate of a liquid crystal panel (not shown) (gate driver monolithic configuration).
  • the display unit 5 and the scanning line driving circuit 30 constitute a liquid crystal display device together with a data line driving circuit (not shown).
  • n is a multiple of 24, and k is an integer of 1 to (n / 8).
  • the scanning line driving circuit 30 includes a first driving unit 32 disposed on the left side of the display unit 5 and a second driving unit 33 disposed on the right side of the display unit 5.
  • Each of the first and second drive units 32 and 33 has a configuration in which (n / 2) unit circuits 21 (FIG. 11) are connected in multiple stages.
  • the first driving unit 32 includes odd-numbered unit circuits SR1, SR3,..., SRn ⁇ 1, and the second driving unit 33 includes even-numbered unit circuits SR2, SR4,.
  • the first and second drive units 32 and 33 are connected to the display unit 5 in the same manner as in the first embodiment.
  • the scanning line driving circuit 30 performs comb driving.
  • the scanning line driving circuit 30 is supplied with eight-phase clock signals CK1 to CK8, four gate start pulses GSP1 to GSP4, and six clear signals CLR1 to CLR6.
  • the clock signals CK1 to CK8 are supplied to the clock terminals CK of the unit circuits 11 in the (8k-7) to 8k stages, respectively.
  • the gate start pulses GSP1 to GSP4 are supplied to the set terminals S of the first to fourth stage unit circuits SR1 to SR4, respectively.
  • the set terminals S of the fifth to nth stage unit circuits SR5 to SRn are connected to the second output terminal Q of the unit circuit four stages before.
  • the clear signals CLR1 to CLR6 are respectively supplied to the reset terminals R of the (n-5) to n-th unit circuits SRn-5 to SRn.
  • the reset terminals R of the unit circuits SR1 to SRn-6 in the 1st to (n-6) stages are connected to the second output terminal Q of the unit circuit in the 6th stage.
  • FIG. 13 is a timing chart of the scanning line driving circuit 30.
  • the clock signal CK1 becomes high level in 1/2 cycle of one cycle and becomes low level in the remaining 1/2 cycle.
  • the clock signals CK2 to CK8 are signals delayed by T / 8, T / 4, 3T / 8, T / 2, 5T / 8, 3T / 4, and 7T / 8 from the clock signal CK1, respectively.
  • the high level voltage of the clock signals CK1 to CK8 is VGH
  • the low level voltage of the clock signals CK1 to CK8 is VSS1.
  • the scanning line driving circuit 30 operates in accordance with 8-phase clock signals CK1 to CK8 that change between the high level voltage VGH and the low level voltage VSS1.
  • FIG. 13 shows changes in the potentials of the clock signals CK1 to CK8 and changes in the potentials of the nodes and terminals of the unit circuit 21 in the (8k-7) stage.
  • the scanning line driving circuit 30 it is possible to provide a scanning line driving circuit that uses a depletion type transistor and can be controlled more easily than in the past, as in the first and second embodiments. .
  • a circuit including two driving units arranged on both sides of the display unit 5 is considered as one scanning line driving circuit, but is arranged on both sides of the display unit 5.
  • the two driving units thus formed may be considered as separate scanning line driving circuits.
  • FIG. 14 is a block diagram showing a configuration of a scanning line driving circuit according to the fourth embodiment. 14 is formed together with the display unit 5 on one substrate of a liquid crystal panel (not shown) (gate driver monolithic configuration).
  • the display unit 5 and the scanning line driving circuit 40 constitute a liquid crystal display device together with a data line driving circuit (not shown).
  • n is a multiple of 12
  • k is an integer of 1 or more (n / 4) or less.
  • the scanning line driving circuit 40 is arranged on one side (left side in the drawing) of the display unit 5.
  • the scanning line driving circuit 40 has a configuration in which n unit circuits 21 (FIG. 11) are connected in multiple stages.
  • the first output terminals G of the unit circuits SR1 to SRn at the 1st to nth stages are connected to the left ends of the scanning lines G1 to Gn, respectively.
  • the scanning line driving circuit 40 drives the scanning lines G1 to Gn.
  • the scanning line driving circuit 40 is supplied with four-phase clock signals CK1 to CK4, two gate start pulses GSP1 and GSP2, and three clear signals CLR1 to CLR3.
  • the clock signals CK1 to CK4 are supplied to the clock terminals CK of the unit circuits 21 in the (4k-3) to 4k stages, respectively.
  • the gate start pulses GSP1 and GSP2 are supplied to the set terminals S of the first and second stage unit circuits SR1 and SR2, respectively.
  • the set terminals S of the unit circuits SR3 to SRn at the third to nth stages are connected to the second output terminal Q of the unit circuit at the second stage.
  • the clear signals CLR1 to CLR3 are respectively supplied to the reset terminals R of the (n-2) to n-th unit circuits SRn-2 to SRn.
  • the reset terminals R of the unit circuits SR1 to SRn-3 at the 1st to (n-3) th stages are connected to the second output terminal Q of the unit circuit at the 3rd stage.
  • FIG. 15 is a timing chart of the scanning line driving circuit 40.
  • the clock signal CK1 becomes high level in 1/2 cycle of one cycle and becomes low level in the remaining 1/2 cycle.
  • the clock signals CK2 to CK4 are signals delayed by T / 4, T / 2, and 3T / 4 from the clock signal CK1, respectively.
  • the high level voltage of the clock signals CK1 to CK4 is VGH
  • the low level voltage of the clock signals CK1 to CK4 is VSS1.
  • the scanning line driving circuit 40 operates according to four-phase clock signals CK1 to CK4 that change between the high level voltage VGH and the low level voltage VSS1.
  • FIG. 15 shows changes in the potentials of the clock signals CK1 to CK4 and changes in the potentials of the nodes and terminals of the unit circuit 21 in the (4k-3) stage.
  • the scanning line driving circuit 40 it is possible to provide a scanning line driving circuit that uses a depletion type transistor and can be controlled more easily than in the prior art, as in the first to third embodiments. .
  • the scanning line driving circuit according to the embodiment can be configured as follows.
  • the scanning line driving circuit 30 according to the third embodiment has a configuration in which the unit circuits 21 are connected in multiple stages as shown in FIG. 12, and the scanning line driving circuit 40 according to the fourth embodiment illustrates the unit circuit 21. 14 has a multi-stage connection configuration.
  • the scanning line driving circuit according to the modification may have a configuration in which the unit circuits 11 are connected in multiple stages as shown in FIG.
  • the scanning line driving circuit according to the modified example includes a unit circuit in which one or both of the transistors M8 and M14 are deleted from the unit circuit 11, a unit circuit in which the transistor M14 is deleted from the unit circuit 21, or the unit circuits 11 and 21.
  • a unit circuit in which the drain terminal of the transistor M1 is connected to the set terminal S may be provided.
  • the scanning line driving circuit according to the modification may be a multi-stage connection of an arbitrary number of unit circuits.
  • the unit circuits 11 and 21 are configured using n-channel TFTs.
  • the unit circuit may be configured using an n-channel TFT.
  • the n-channel transistor included in the unit circuit is replaced with a p-channel transistor. The polarity of the voltage applied to the power supply wiring and the control wiring may be reversed.
  • the conductivity type of the transistor included in the unit circuit is a p-channel type
  • the on voltage is a low level voltage
  • the first off voltage is a high level voltage
  • the second off voltage is a high level voltage higher than the first off voltage.
  • the third off voltage is a high level voltage higher than the second off voltage. Accordingly, it is possible to provide a scanning line driver circuit using a p-channel type and a depletion type transistor that can be controlled more easily than in the past.
  • the scanning line driving circuit According to the scanning line driving circuit according to the embodiment and the modification thereof, it is possible to provide a scanning line driving circuit that uses a depletion type transistor and can be controlled more easily than in the past.
  • the scanning line driving circuit has a configuration in which a plurality of unit circuits are connected in multiple stages, and operates in accordance with a multiphase clock signal that changes between an on-voltage and a first off-voltage.
  • Each of the unit circuits includes a first conduction terminal connected to the clock terminal, a control terminal connected to the first node, and a second conduction terminal connected to the first output terminal for outputting a signal for the scanning line.
  • a second output terminal for outputting a signal to a unit circuit in another stage, a first conduction terminal connected to the clock terminal, a control terminal connected to the first node, A second output transistor having a second conduction terminal connected to the first node, a first node set transistor for applying the on-voltage to the first node according to the potential of the set terminal, and the potential according to the potential of the control terminal.
  • a first node reset transistor that applies a second off voltage to the first node
  • a second output reset transistor that applies a third off voltage to the second output terminal according to the potential of the second node.
  • the second off voltage is a voltage farther from the on voltage than the first off voltage
  • the third off voltage is a voltage farther from the on voltage than the second off voltage.
  • Each of the unit circuits may include a second node control unit that controls the potential of the second node to a potential of a logic level opposite to the potential of the first node (second aspect).
  • the first node reset transistor may apply the second off voltage to the first node according to a potential of a reset terminal (third aspect).
  • Each of the unit circuits may further include a first node auxiliary reset transistor that applies the second off voltage to the first node according to the potential of the second node (fourth aspect).
  • Each of the unit circuits further includes a second node set transistor that applies the on-voltage to the second node according to a potential of a reset terminal, and the first node reset transistor corresponds to the potential of the second node.
  • the second off voltage may be applied to the first node (fifth aspect).
  • Each of the unit circuits may further include a first output reset transistor that applies the first off voltage to the first output terminal in accordance with the potential of the second node (sixth aspect).
  • the second node control unit applies a voltage continuous application transistor that applies the on voltage to the second node in a fixed manner, and applies the first off voltage to the second node according to the potential of the first node.
  • a second node reset transistor may be included (seventh aspect).
  • the difference between the first off-voltage and the second off-voltage, and the difference between the second off-voltage and the third off-voltage may be set based on characteristics of transistors included in the unit circuit (first 8 aspects).
  • the difference between the first off voltage and the second off voltage, and the difference between the second off voltage and the third off voltage are units when the voltage between the first and second conduction terminals of the transistor is 10V.
  • the absolute value of the voltage between the control terminal and the second conduction terminal of the transistor having a channel length and a current per unit channel width of 1 ⁇ 10 ⁇ 9 A may be greater (9th aspect).
  • the amplitudes of the plurality of clock signals are the same, and one clock signal selected from among the plurality of clock signals may be input to each unit circuit via the clock terminal (first). 10 aspects).
  • the transistor included in the unit circuit may be a thin film transistor having a semiconductor layer formed using an oxide semiconductor (eleventh aspect).
  • the transistor included in the unit circuit is an n-channel conductivity type, the on voltage is a high level voltage, the first off voltage is a low level voltage, and the second off voltage is a low level lower than the first off voltage.
  • the level voltage and the third off voltage may be a low level voltage lower than the second off voltage (a twelfth aspect).
  • the transistor included in the unit circuit is a p-channel type, the on voltage is a low level voltage, the first off voltage is a high level voltage, and the second off voltage is higher than the first off voltage.
  • the level voltage and the third off voltage may be a high level voltage higher than the second off voltage (a thirteenth aspect).
  • the display device includes a display unit including a plurality of scanning lines, a plurality of data lines, and a plurality of pixel circuits, and the scanning line according to any one of the first to thirteenth aspects that drives the scanning lines. And a drive circuit (fourteenth aspect).
  • the scanning line driving circuit may be formed on a display panel together with the display unit (fifteenth aspect).
  • the first to third off voltages having the above-described magnitude relationship are applied to the first output terminal, the first node, and the second node of the unit circuit, respectively.
  • a voltage at which the transistor is turned off (difference between the second off voltage and the first off voltage) is applied between the control terminal and the second conduction terminal of the first output transistor
  • a voltage at which the transistor is turned off (difference between the third off voltage and the second off voltage) is also applied between the control terminal and the second conduction terminal of the first node set transistor. For this reason, even when a depletion type transistor is used, no current flows through the first output transistor and the first node set transistor in the non-selection period.
  • the output signal of the scan line driver circuit can be stabilized and malfunction of the scan line driver circuit can be prevented. Further, the scanning line driving circuit operates in accordance with a clock signal that changes between two voltage levels. Therefore, a scan line driver circuit using a depletion type transistor that can be controlled more easily than in the past can be provided.
  • the second output terminal is controlled based on the potential of the second node by controlling the potential of the second node to the potential of the logic level opposite to that of the first node using the second node control unit. And the like can be controlled.
  • the second off voltage can be applied to the first node according to the potential of the reset terminal using the first node reset transistor.
  • the second off voltage can be applied to the first node together with the first node reset transistor.
  • the second node set transistor by providing the second node set transistor, it is possible to apply the second off voltage to the first node according to the potential of the second node using the first node reset transistor.
  • the first output reset transistor by providing the first output reset transistor, the first off voltage can be applied to the first output terminal.
  • the second node control unit that controls the potential of the second node to the potential of the logic level opposite to the potential of the first node by using the voltage continuous application transistor and the second node reset transistor. Can be configured.
  • the first to third off voltages are set in consideration of the characteristics of the transistor, so that the first output transistor It is possible to prevent a current from flowing through the first node set transistor. Therefore, the output signal of the scan line driver circuit can be stabilized and malfunction of the scan line driver circuit can be prevented.
  • the scanning line driving circuit is configured by using the thin film transistor having the semiconductor layer formed using the oxide semiconductor, thereby reducing the leakage current in the scanning line driving circuit, and the scanning line driving circuit. Can be prevented from malfunctioning.
  • a low-cost display device can be provided by using a scanning line driving circuit that uses a depletion type transistor and can be controlled more easily than in the past.
  • the width of the peripheral portion of the display screen can be narrowed by forming the scanning line driving circuit on the display panel together with the display portion.

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Abstract

Selon l'invention, un circuit d'attaque de ligne de balayage (10), construit à partir d'une cascade de circuits uniques (11), fonctionne selon huit phases de signaux d'horloge CK1 à CK8 qui varient entre une tension de haut niveau VGH et une tension de faible niveau VSS1. Un circuit unique (11) comprend : un transistor M10B qui comprend une borne de drain connectée à une borne d'horloge CK, une borne de grille connectée à un nœud Na et une borne de source connectée à une seconde borne de sortie Q pour transférer un signal à des circuits uniques dans d'autres blocs ; un transistor M9 qui applique une tension de faible niveau VSS2 au nœud Na en fonction du potentiel au niveau d'un terminal de réinitialisation R ; et un transistor M14B qui applique une tension de faible niveau VSS3 à la seconde borne de sortie Q en fonction du potentiel au niveau d'un nœud Nb. La tension de faible niveau satisfait VSS1 > VSS2 > VSS3. Ainsi, l'invention concerne un circuit d'attaque de ligne de balayage qui peut être commandé plus facilement à l'aide d'un transistor de type à appauvrissement.
PCT/JP2018/007958 2017-03-10 2018-03-02 Circuit d'attaque de ligne de balayage et dispositif d'affichage équipé dudit circuit WO2018163985A1 (fr)

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2010067641A1 (fr) * 2008-12-10 2010-06-17 シャープ株式会社 Circuit de commande de ligne de signal de balayage, registre à décalage et procédé de commande d'un registre à décalage
JP2012257211A (ja) * 2011-05-13 2012-12-27 Semiconductor Energy Lab Co Ltd 半導体装置
JP2014026258A (ja) * 2012-07-24 2014-02-06 Samsung Display Co Ltd 表示装置
US20140267214A1 (en) * 2013-03-13 2014-09-18 Samsung Display Co., Ltd. Display panel
JP2015033026A (ja) * 2013-08-05 2015-02-16 株式会社ジャパンディスプレイ 薄膜トランジスタ回路およびそれを用いた表示装置

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2010067641A1 (fr) * 2008-12-10 2010-06-17 シャープ株式会社 Circuit de commande de ligne de signal de balayage, registre à décalage et procédé de commande d'un registre à décalage
JP2012257211A (ja) * 2011-05-13 2012-12-27 Semiconductor Energy Lab Co Ltd 半導体装置
JP2014026258A (ja) * 2012-07-24 2014-02-06 Samsung Display Co Ltd 表示装置
US20140267214A1 (en) * 2013-03-13 2014-09-18 Samsung Display Co., Ltd. Display panel
JP2015033026A (ja) * 2013-08-05 2015-02-16 株式会社ジャパンディスプレイ 薄膜トランジスタ回路およびそれを用いた表示装置

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