[go: up one dir, main page]

WO2018165817A1 - Procédé de fabrication de circuit - Google Patents

Procédé de fabrication de circuit Download PDF

Info

Publication number
WO2018165817A1
WO2018165817A1 PCT/CN2017/076433 CN2017076433W WO2018165817A1 WO 2018165817 A1 WO2018165817 A1 WO 2018165817A1 CN 2017076433 W CN2017076433 W CN 2017076433W WO 2018165817 A1 WO2018165817 A1 WO 2018165817A1
Authority
WO
WIPO (PCT)
Prior art keywords
chip
substrate
layer
circuit
metal layer
Prior art date
Application number
PCT/CN2017/076433
Other languages
English (en)
Chinese (zh)
Inventor
胡川
刘俊军
Original Assignee
深圳修远电子科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 深圳修远电子科技有限公司 filed Critical 深圳修远电子科技有限公司
Priority to PCT/CN2017/076433 priority Critical patent/WO2018165817A1/fr
Publication of WO2018165817A1 publication Critical patent/WO2018165817A1/fr

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern

Definitions

  • the invention belongs to the field of electronics, and in particular relates to a circuit manufacturing method.
  • the photocatalytic method requires a photosensitive material, many process steps have a heat treatment, and the material no longer has photosensitivity after these steps, and the photocatalytic method has limited use conditions; the photocatalytic method also has a problem of inaccurate positioning. All of these reasons will reduce interconnect density and limit chip communication speed.
  • the present invention overcomes the defects of the prior art, and provides a circuit manufacturing method for fabricating a connection hole on a circuit board, the connection hole is positioned accurately and the aperture is small, and a fine circuit with a small line width can be fabricated, and the interconnection line can be improved. Density, chip transfer speed is increased.
  • a circuit manufacturing method includes: a substrate is provided with a first metal layer, the first metal layer is provided with a first guiding hole; a chip is provided with a chip pin; a dielectric layer is disposed between the chip and the substrate, and the chip passes The dielectric layer is disposed on a top surface of the substrate such that the first guiding hole corresponds to the chip pin; and a particle beam or a photon beam is emitted from the bottom of the substrate toward the chip: a particle beam or a photon beam Not passing through the first metal layer; a particle beam or a photon beam passing through the first guiding hole and the substrate, and engraving a connecting through hole in the dielectric layer, the first guiding hole, passing through The through hole of the substrate and the connecting through hole communicate with each other to form a connection channel, and the chip pin is in communication with the connection channel.
  • a conductor layer is disposed in the connecting channel, the conductor layer will be The chip pins are electrically connected to the first metal layer.
  • the conductor layer is a metal layer coated on an inner wall of the connecting channel.
  • the chips are two or more, and at least two of the chips are directly electrically connected through the first metal layer.
  • the bottom surface of the substrate is provided with the first metal layer
  • the top surface of the substrate is provided with a second metal layer
  • the second metal layer is located between the substrate and the chip
  • the second metal layer is provided with a second guiding hole corresponding to the first guiding hole and the chip pin, and the particle beam or photon beam passes through the second guiding hole
  • the first guiding hole engraves the connecting through hole in the dielectric layer, the through hole passing through the substrate, the first guiding hole, the second guiding hole, and the connecting through are mutually connected
  • the connection channel is formed.
  • a conductor layer is disposed within the connection channel, the conductor layer electrically connecting the chip lead to the first metal layer or the second metal layer.
  • the thickness of the first metal layer is greater than or equal to the thickness of the second metal layer.
  • the diameter of the second guiding hole is less than or equal to the diameter of the first guiding hole.
  • the first metal layer is made into a first circuit layer, and the chip pins are electrically connected to the first circuit layer; or Prior to the chip, the second metal layer is formed into a second circuit layer, and the chip pins and the second circuit layer are electrically connected.
  • the second circuit layer comprises a circuit pattern or a fine line, the circuit pattern or the fine line having a line width of less than 10 microns.
  • the substrate is disposed on a carrier, a second circuit layer is formed on a top surface of the substrate, and the chip is placed on the substrate to electrically connect the chip to the second circuit layer.
  • the second circuit layer is provided with a second guiding hole corresponding to the first guiding hole and the chip pin; detaching the carrier from the substrate, in the The first metal layer is formed on the bottom surface of the substrate.
  • an encapsulation layer is disposed on the substrate before the carrier is detached from the substrate, and the chip is located between the encapsulation layer and the substrate to cure the encapsulation layer The chip is fixed.
  • the second circuit layer comprises a fine connection
  • the chip is at least two, and at least two of the chips are directly electrically connected by the second circuit layer.
  • the fine lines have a line width of less than 10 microns.
  • an encapsulation layer is disposed on the substrate before engraving the connection via, and the chip is located between the encapsulation layer and the substrate, and curing the encapsulation layer to fix the chip .
  • the encapsulation layer, the chip, the substrate, and the first metal layer constitute a package board. After the connection via is formed, the package board is cut into at least two circuit boards. .
  • the particle beam is a plasma beam or an electron beam; or the photon beam is a laser beam.
  • the chip is bonded to the top surface of the substrate by the dielectric layer.
  • the dielectric layer is a viscous material and the chip is affixed to the substrate by the dielectric layer.
  • the first guiding holes are at least two, and the chip pins are two corresponding ones, and the particle beam or the photon beam is used to simultaneously illuminate at least two first guiding holes, and at least Two of the connecting channels.
  • the particle beam or photon beam has an illumination range greater than a cross-sectional area of the first guiding aperture.
  • the circuit manufacturing method includes: a substrate is provided with a first metal layer, a first metal layer is provided with a first guiding hole; a chip is provided with a chip pin; a dielectric layer is disposed between the chip and the substrate, and the chip passes through the medium
  • the layer is disposed on a top surface of the substrate such that the first guiding hole corresponds to the chip pin; the particle beam or the photon beam is emitted from the bottom of the substrate toward the chip: the particle beam or the photon beam cannot pass through the first metal layer; the particle beam or The photon beam passes through the first guiding hole and the substrate, and a connecting through hole is engraved in the dielectric layer, through the through hole of the substrate,
  • the first guiding hole and the connecting through hole communicate with each other to form a connecting channel, and the chip pin is in communication with the connecting channel.
  • the particle beam or photon beam used cannot pass through the first metal layer and can only be perforated through the first guiding hole, and the first metal layer provides a positional positioning and a hole size limitation for the connecting through hole, and the first guiding hole serves as
  • the perforated guiding pattern can engrave the connecting through hole only at the position where the first guiding hole is provided, and the aperture of the first guiding hole limits the diameter of the connecting through hole, and therefore, the aperture can be made by designing the diameter of the first guiding hole Small enough through-holes (less than 10 microns), the diameter of the connecting channels can be made small enough to increase the density of the interconnects.
  • the first metal layer may be disposed on the top surface or the bottom surface of the substrate, or may be disposed in the substrate.
  • the position corresponding to the first guiding hole on the substrate may be preset with a through hole, or the connection may be engraved by a particle beam or a photon beam.
  • a through hole is engraved on the substrate at the same time. After the engraving is completed, the through hole, the first guiding hole and the connecting through hole on the substrate are connected to each other to form a connecting channel, and the chip pin is exposed by the connecting channel, and the connecting channel can be connected through the connecting channel.
  • the chip is connected to a circuit, an electronic component, or a device to implement fan-out of the chip.
  • the first guiding hole corresponds to the chip pin, and when the particle beam or the photon beam passes through the first guiding hole and the substrate reaches the chip pin, it is blocked by the chip pin, and cannot continue to advance, and the dielectric layer that blocks the chip pin is separated by the particle.
  • the beam or photon beam is removed to form a connection via, and the connection via exposes the chip pins.
  • the through hole, the first guiding hole, and the connection through the substrate are utilized by the characteristics of linear propagation of the particle beam or the photon beam.
  • the vias are automatically aligned and interconnected to automatically form a connection channel, and the connection channels are aligned with the chip pins.
  • a first guiding hole may be disposed at an appropriate position of the first metal layer as needed, and one or two or more first guiding holes may be disposed, the primary particle
  • the shooting of the beam or the photon beam can simultaneously engrave a plurality of connecting through holes, thereby achieving fan-out of a plurality of chip pins, and the efficiency is high.
  • the top surface and the bottom surface of the substrate are only for the sake of brevity. Referring to the position where the substrate is placed in FIG. 1, the upward side is the top surface and the downward side is the bottom surface, but this does not limit the spatial orientation of the actual substrate.
  • the substrate can be turned over. As shown in FIG. 5, the bottom side of the substrate is the top surface, and the upward side is the bottom surface.
  • the side on which the chip is mounted can be the top surface, and the opposite side is the bottom surface.
  • a conductor layer is disposed in the connection channel, and the conductor layer electrically connects the chip pin and the first metal layer.
  • the electrical connection between the chip and the first metal layer is realized through the connection channel, and no additional space is occupied, and more connection nodes and interconnection lines can be obtained in the same space, thereby improving data transmission speed.
  • the direct size of the connection channel for example, the diameter of the connection channel is made as small as possible, the density of the connection node and the interconnection line can be obtained, and the data transmission speed is greatly improved.
  • the conductor layer is a metal layer coated on an inner wall of the connecting channel. Electroplating or other processes can be used to simultaneously form a metal layer on the inner walls of all the connecting channels, and the production efficiency is high.
  • the chip is at least two, and at least two chips are directly electrically connected through the first metal layer.
  • the chip has a fast computing speed, has a high-density chip pin, requires a high-speed data transmission channel, requires more connection nodes, and the chip pins escape through the conductor layer in the connection via hole, thereby avoiding the chip chip of the chip itself.
  • the block of the foot is electrically connected to the first metal layer to obtain a connection node and an interconnect line with higher density, and directly transmit data directly between the chips, thereby greatly improving the data transmission speed and efficiency.
  • the bottom surface of the substrate is provided with a first metal layer
  • the top surface of the substrate is provided with a second metal layer
  • the second metal layer is located between the substrate and the chip
  • the second metal layer is provided with a second guiding hole
  • the second guiding hole is Corresponding to the first guiding hole and the chip lead, the particle beam or the photon beam passes through the second guiding hole and the first guiding hole to engrave the connecting through hole in the dielectric layer, the through hole of the substrate, the first guiding hole, and the second guiding
  • the holes and the connection lines communicate with each other to form a connection channel.
  • the first metal layer is a positioning layer for making a connection through hole
  • the first guiding hole is equivalent to a mold for making a connecting through hole, and the position of the first guiding hole defines a position of the connecting through hole, and the diameter of the first guiding hole defines the connection.
  • the second metal layer can assist in making the connection via hole, and the second guiding hole can pass the particle beam or the photon beam to prevent the second metal layer from being damaged by the particle beam or the photon beam, especially when the second metal layer is small in thickness and connected.
  • the line width is narrow, the low-intensity particle beam or the photon beam hits the second metal layer, and it is possible to burn the second metal layer, so that the second guiding hole is provided to protect the second metal layer.
  • a conductor layer is disposed in the connection channel, and the conductor layer electrically connects the chip pin to the first metal layer or the second metal layer.
  • the chip pins may be connected to any one of the metal layers on the substrate as needed, or may be electrically connected to the two metal layers at the same time to form a 3D circuit.
  • the thickness of the first metal layer is greater than or equal to the thickness of the second metal layer, and a tight circuit pattern or fine wiring can be formed on the thin second metal layer to obtain higher connection node density and higher transmission speed.
  • the thicker first metal layer acts as a positioning layer for making the connection vias, preventing the particle beam or photon beam from damaging the first metal layer.
  • the diameter of the second guiding hole is smaller than or equal to the diameter of the first guiding hole, which facilitates the correspondence between the second guiding hole and the chip pin, and ensures that the second guiding hole corresponds to the first guiding hole, and is beneficial when the conductor layer is disposed in the connecting channel.
  • the conductor layer is electrically connected to the chip pins.
  • the connection via is formed, the first metal layer is made into the first circuit layer, and the chip pins are electrically connected to the first circuit layer; since the first metal layer is made into the first circuit layer, the first metal is reduced.
  • the shielding range of the layer so that the connection hole is formed before the first metal layer is formed into the first circuit layer.
  • the particle beam or the photon beam can be irradiated to the substrate in a wide range, one time.
  • the production of all the connection vias in the range of the particle beam or the photon beam irradiation is completed, and the production efficiency is higher; however, the connection via holes can also be formed after the first circuit layer is fabricated. Also.
  • the first metal layer does not necessarily completely cover the surface of the substrate, and a plurality of first metal layers may be disposed on the substrate at the same time.
  • the range of the first metal layer may be designed according to the irradiation range of the particle beam or the photon beam, as needed.
  • the second metal layer is formed into a second circuit layer before the chip is placed, and the chip pins and the second circuit layer are electrically connected.
  • the second circuit layer may be a circuit pattern having a circuit function, or may be an interconnection line, or the second circuit layer itself may constitute an electronic original. Since the first metal layer has been positioned for making the connection via hole, the second metal layer only serves as an auxiliary function, and the second metal layer is made into the second circuit layer, and then the connection via hole is formed, which does not affect the connection through hole. Production.
  • the second circuit layer comprises a circuit pattern or a fine wiring, and the circuit pattern or the fine wiring has a line width of less than 10 micrometers.
  • the line width of the wiring and circuit pattern obtained by the conventional method is about 60 micrometers. Due to the limitation of the process itself, the line width cannot be further reduced and the transmission speed is increased. In the method of the present invention, the line width obtained is less than 10 micrometers, and a high-density circuit pattern or fine wiring can be fabricated in the second metal layer to obtain a higher connection node density and a higher transmission speed.
  • the substrate is disposed on the carrier, the second circuit layer is formed on the top surface of the substrate, the chip is placed on the substrate, the chip is electrically connected to the second circuit layer, and the second circuit layer is provided with a second guiding hole, second Guide hole and The first guiding hole corresponds to the chip pin; the carrier is detached from the substrate, and the first metal layer is formed on the bottom surface of the substrate.
  • the substrate may be deformed or the like, and the misalignment caused by the deformation of the substrate can be dealt with only by increasing the line width and the gap of the circuit pattern, thereby limiting the circuit pattern density and the connection density.
  • the carrier plate provides a supporting function, and the substrate can be kept flat during the process of fabricating the second circuit layer on the basis of the carrier board, and the line width and the gap of the circuit pattern and the fine wiring can be made smaller and more precise.
  • the circuit pattern and the fine wiring (the second circuit layer may include a circuit pattern, fine wiring).
  • it is suitable for ultra-thin substrates (thickness less than ? micron) or flexible substrates such as flexible substrates, and the support provided by the carrier can keep the substrate flat and facilitate the fabrication of the second circuit layer.
  • an encapsulation layer is disposed on the substrate, and the chip is located between the encapsulation layer and the substrate, and the curing encapsulation layer fixes the chip.
  • the chip is fixed by the encapsulation layer under the support of the carrier board. At this time, the positional relationship between the chip and the chip, between the chip and the second circuit layer is fixed, and the connection relationship is fixed, and the subsequent production process will not affect the chip. Positional relationship and connection relationship between the chip and the chip and the second circuit layer.
  • the second circuit layer comprises fine wiring, the chip is at least two, at least two chips are directly electrically connected through the second circuit layer, the transmission line between the chips is increased, and the transmission does not need to pass through other circuits.
  • the device can increase the transmission speed.
  • the line width of fine wiring is less than 10 microns.
  • the traditional method of fabricating the circuit layer limits the reduction of the line width and the increase of the connection density due to the inaccurate positioning.
  • the method of the present invention locates the position of the through hole by the diameter of the first guiding hole of the first metal layer, and the positioning is accurate, and the fine wire with a small line width can be used, so that the connection density can be increased, thereby increasing the transmission rate.
  • an encapsulation layer is disposed on the substrate, and the chip is located between the encapsulation layer and the substrate, and the curing encapsulation layer fixes the chip.
  • the substrate may be deformed or the like, and the misalignment caused by the deformation of the substrate can be dealt with only by increasing the line width and the gap of the circuit pattern, thereby limiting the circuit pattern density and the connection density.
  • the invention always fixes the positional relationship between the chip and the first metal layer and the substrate through the encapsulation layer before engraving the connection via hole, thereby avoiding the subsequent process to change the positional relationship between the chip and the first metal layer and the substrate.
  • the encapsulation layer, the chip, the substrate, and the first metal layer constitute a package board, and after the connection through hole is made,
  • the package board is cut into at least two boards.
  • the traditional method of manufacturing a circuit board because the positioning is not accurate enough, and the substrate will be deformed, can only make a small area of the circuit board (20cm ⁇ 2), is not suitable for large-scale, high-efficiency production.
  • the method of the invention has the advantages of accurate positioning, firstly fixing the chip with the encapsulation layer in the subsequent process, and avoiding deformation of the substrate, and capable of fabricating a large flat panel level (greater than 20 cm ⁇ 2) of the circuit board at one time, and after the completion of the production, the large flat panel is prepared.
  • the board is cut into small boards as needed. These small boards can be used directly, resulting in high production efficiency and further cost reduction.
  • the particle beam is a plasma beam or an electron beam; or, the photon beam is a laser beam.
  • the factors to be considered include, but are not limited to: production cost, energy level of particle beam or photon beam, cost, technical requirements of the production workshop. .
  • the chip is bound to the top surface of the substrate by the dielectric layer, so that the position of the chip is fixed to the substrate by the dielectric layer, and the position of the chip is changed in a subsequent process such as making a connection channel and making a conductive layer for electrical connection.
  • the operation precision of the chip is improved, so that a higher density chip pin and a first guiding hole can be set, and a high-density connection node is set on the chip to improve the data transmission speed of the chip.
  • the dielectric layer is a viscous material
  • the chip is bonded to the substrate by the dielectric layer.
  • the first guiding holes are at least two, and the chip pins are corresponding to two, and the particle beam or the photon beam is used to simultaneously illuminate at least two first guiding holes, and at least two of the connections are made. aisle. It is possible to simultaneously manufacture a plurality of connection channels on the substrate, even all the connection channels on the substrate, and the production efficiency is high.
  • the irradiation range of the particle beam or the photon beam is greater than a cross-sectional area of the first guiding hole. Only the particle beam or photon beam irradiated into the first guiding hole can reach the dielectric layer and penetrate the connecting through hole on the dielectric layer, and the particle beam or photon beam irradiated outside the cross section of the first guiding hole is first The metal layer blocks and cannot penetrate, and does not break other circuit structures. In this way, the shape and size of the cross section of the connecting through hole are the same as those of the first guiding hole. By setting the position and the aperture of the first guiding hole, the position and the aperture of the connecting through hole can be easily determined, and the connecting channel and the chip lead can be realized. The positioning of the foot is accurate, you can also The control of a pilot hole is set to be smaller and finer, and more connection nodes are implemented.
  • FIG. 1 is a schematic diagram of a chip fanout method according to an embodiment of the present invention.
  • FIG. 2 is a schematic diagram of steps of mounting a chip according to an embodiment of the present invention.
  • FIG. 3 is a schematic diagram of a connection procedure according to an embodiment of the present invention.
  • FIG. 4 is a schematic diagram of a packaging step according to an embodiment of the present invention.
  • FIG. 5 is a schematic diagram 1 of a punching step according to an embodiment of the present invention.
  • FIG. 6 is a second schematic diagram of a punching step according to an embodiment of the present invention.
  • FIG. 7 is a second schematic diagram of a connection procedure according to an embodiment of the present invention.
  • FIG. 8 is a schematic diagram of a punching step according to Embodiment 2 of the present invention.
  • FIG. 9 is a schematic diagram 1 of the steps of installing a chip according to Embodiment 3 of the present invention.
  • FIG. 10 is a second schematic diagram of the steps of installing a chip according to Embodiment 3 of the present invention.
  • FIG. 11 is a schematic diagram of a packaging step according to Embodiment 3 of the present invention.
  • FIG. 12 is a schematic diagram of a step of detaching according to Embodiment 3 of the present invention.
  • FIG. 13 is a schematic diagram of a third drilling step according to an embodiment of the present invention.
  • FIG. 14 is a schematic view showing the steps of providing a conductor layer according to Embodiment 3 of the present invention.
  • FIG. 15 is a schematic diagram showing the steps of fabricating a circuit pattern in a first conductor layer according to Embodiment 3 of the present invention.
  • the circuit manufacturing method includes the following.
  • a first metal layer 100 is provided on the top surface of the substrate 300, and a second metal layer 200 is provided on the bottom surface of the substrate 300.
  • the top surface and the bottom surface of the substrate 300 are only for the sake of brevity. Referring to the position of the substrate 300 in FIG. 1 , the upper side is the top surface and the lower side is the bottom surface, but this does not limit the space of the substrate 300 in practice. Orientation, in practice, the substrate 300 can be flipped, and one side of the mounting chip 400 can be selected as a top surface, and the opposite side is a bottom surface.
  • a via hole is formed on the entire substrate 300, the first metal layer 100, and the second metal layer 200, and then a first guiding hole 110 is formed on the first metal layer 100, and the second metal layer 200 is formed.
  • a second guiding hole 210 is formed on the substrate 300, and a through hole is formed on the substrate 300, and the first guiding hole 110 and the second guiding hole 210 correspond to the through hole obtained on the substrate 300.
  • the first guiding hole 110 and the second guiding hole 210 may be formed without forming a through hole in the substrate 300 in advance.
  • the first guiding hole 110 and the second guiding hole 210 are preset.
  • the second metal layer 200 may be formed into a second circuit layer, and the second circuit layer may be a circuit pattern having a circuit function, or may be an interconnection line, or the second circuit layer itself may constitute an electronic original.
  • the chip 400 is provided with a chip lead 410.
  • a dielectric layer 500 is disposed between the chip 400 and the substrate 300, and the chip 400 is placed on the top surface of the substrate 300, so that the first guiding hole 110 and the chip lead The foot 410 corresponds.
  • the dielectric layer 500 is a viscous material, and the chip 400 is bonded to the substrate 300 by the dielectric layer 500, and the chip 400 can be fixed on the substrate 300 by means of bonding.
  • an encapsulation layer 600 is disposed on the substrate 300, and the chip 400 is located between the encapsulation layer 600 and the substrate 300, and the cured encapsulation layer 600 fixes the chip 400.
  • the misalignment caused by the deformation of the substrate 300 can be dealt with only by increasing the line width and the gap of the circuit pattern, thereby limiting the circuit pattern density and the connection density.
  • the present invention always fixes the positional relationship between the chip 400 and the first metal layer 100 and the substrate 300 through the encapsulation layer 600 before engraving the connection via 510, thereby avoiding subsequent processes such that the chip 400 and the first metal layer 100 and the substrate 300 are The positional relationship has changed.
  • the first metal layer 100 is a positioning layer for forming the connection via 510.
  • the first guiding hole 110 is equivalent to a mold for making the connection via 510.
  • the position of the first guiding hole 110 defines the connecting via 510.
  • Position, the diameter of the first guiding hole 110 defines the diameter of the connecting through hole 510.
  • the second metal layer 200 can assist in making the connection vias 510, and the second guiding holes 210 can pass the particle beam or the photon beam 610 to prevent the second metal layer 200 from being damaged by the particle beam or the photon beam 610.
  • a particle beam or photon beam 610 is emitted from the bottom of the substrate 300 toward the chip 400: the particle beam or photon beam 610 cannot pass through the first metal layer 100; the particle beam or photon beam 610 passes through the first guiding hole 110, the substrate 300, and the Two guiding holes 210, and a connecting through hole 510 is engraved in the dielectric layer 500, through the first guiding hole 110, the through hole of the substrate 300, the second guiding hole 210, and the connecting through hole 510 are connected to each other to form a connecting channel 700, the chip
  • the pin 410 is in communication with the connection channel 700, and the connection channel 700 is shown in FIG.
  • the particle beam or photon beam 610 passes through the first guiding hole 110, the substrate 300, the second guiding hole 210, and the dielectric layer 500 to reach the chip pin 410, it is blocked by the chip pin 410 and cannot continue to advance, and at this time, the chip is blocked.
  • the dielectric layer 500 of the pin 410 is removed by the particle beam or the photon beam 610 to form a connection via 510, and the connection via 510 exposes the chip pin 410, so that the chip pin 410 is used by the first guiding hole 110 and the substrate 300.
  • the through hole, the second guiding hole 210, and the connecting via 700 formed by the connecting via 510 are exposed, and the chip 400 can be connected to the circuit, the electronic component, or the device through the connecting channel 700 to realize fan-out of the chip 400.
  • the particle beam or photon beam 610 used cannot pass through the first metal layer 100 and can only be perforated through the first guiding hole 110, and the first metal layer 100 provides a positional positioning and a hole size limitation for the connecting through hole 510.
  • the first guiding hole 110 serves as a guiding pattern for punching, and the connecting through hole 510 can be engraved only at a position where the first guiding hole 110 is provided.
  • the aperture of the first guiding hole 110 limits the diameter of the connecting through hole 510, and therefore,
  • the diameter of the first guiding hole 110 can be made into a connecting through hole 510 (less than 10 micrometers) having a sufficiently small aperture. Accordingly, the diameter of the connecting channel 700 can also be made small enough to increase the density of the interconnecting wire.
  • the particle beam is a plasma beam or an electron beam; or, the photon beam 610 is a laser beam.
  • a suitable particle beam or photon beam 610 can be selected, and factors to be considered include, but are not limited to, production cost, energy level of the particle beam or photon beam 610, cost, and technology of the production plant. Claim.
  • a conductor layer 630 is disposed in the connection channel 700, including but not limited to evaporation, sputtering, electroplating, solder ball soldering, filling, etc., and the conductor layer 630 places the chip leads 410 and the first metal layer 100. Or the second metal layer 200 is electrically connected.
  • the chip pins 410 may be connected to any one of the metal layers on the substrate 300 as needed, or may be electrically connected to the two metal layers at the same time to form a 3D circuit.
  • At least two chips 400 may be disposed on the substrate 300, and at least two chips 400 are directly electrically connected through the first metal layer 100 or the second metal layer 200.
  • the chip 400 has a fast operation speed, has a high-density chip pin 410, requires a high-speed data transmission channel, requires more connection nodes, and the chip pin 410 escapes through the conductor layer 630 in the connection via 510, which can be avoided.
  • the blocking of the chip pins 410 of the chip 400 itself is electrically connected to the other chip 400, thereby obtaining a connection node and an interconnection line with higher density, and directly transmitting data directly between the chips 400, thereby greatly improving data transmission speed and efficiency.
  • the first metal layer 100 is formed into a first circuit layer, and the chip pins 410 are electrically connected to the first circuit layer; Since the first metal layer 100 is made into the first circuit layer, the shielding range of the first metal layer 100 is reduced. Therefore, the connection via 510 is formed before the first metal layer 100 is formed into the first circuit layer.
  • the shielding effect of the metal layer 100 can illuminate the substrate 300 with the particle beam or the photon beam 610 over a wide range, and complete the fabrication of all the connection vias 510 in the range of irradiation of the particle beam or the photon beam 610 at one time, and the production efficiency is high. Also.
  • the first metal layer 100 does not necessarily completely cover the surface of the substrate 300.
  • a plurality of first metal layers 100 may be disposed on the substrate 300 at the same time.
  • the first metal layer 100 may be designed according to the irradiation range of the particle beam or the photon beam 610, as needed. geographic range.
  • the encapsulation layer 600, the chip 400, the substrate 300, and the first metal layer 100 constitute a package board, and the package board is cut into at least two circuit boards.
  • the method of the present invention is accurate in positioning.
  • the chip 400 is first fixed by the encapsulation layer 600 to perform subsequent processes, and the deformation of the substrate 300 can be avoided, and the circuit board of a large flat panel level (greater than 20 cm 2 ) can be fabricated at one time.
  • the large flat circuit board is cut into several small circuit boards as needed, and these small circuit boards can be directly used, and the production efficiency is very high and the cost is further reduced.
  • the first guiding holes 110 are at least two, and the chip pins 410 are two corresponding ones. At least two connecting channels 700 are synchronously formed by using a particle beam or a photon beam, and a plurality of connecting channels 700 on the substrate 300 can be simultaneously fabricated, and even It is all the connection channels 700 on the substrate, and the production efficiency is high. Forming a first guiding hole 110 on the first metal layer 100, forming a second guiding hole 210 on the second metal layer 200, and forming a through hole on the substrate 300, so that all the first guiding holes 110 are needed in the range of the large flat plate, The position of the second guiding hole 210 is synchronously produced;
  • the chip 400 is mounted on the substrate 300 by means of pasting, and the plurality of chips 400 can be extracted at one time and the plurality of chips 400 can be mounted simultaneously;
  • the first guiding hole 110 may be disposed at an appropriate position of the first metal layer 100, and one or more first guiding holes 110 may be disposed, and the shooting of the primary particle beam or the photon beam 610 may simultaneously engrave a plurality of connecting through holes. 510, implementing fanout of the plurality of chip pins 410;
  • a conductor layer 630 is disposed in the connection channel 700 to electrically connect the chip lead 410 and the first metal layer 100 or the second metal layer 200, wherein the conductor layer 630 is formed by crystal growth or the like, and the conductor can be synchronously grown in the entire large flat plate.
  • the entire package board can be divided into several circuit boards, each of which can be used separately, and the steps of mounting the chip 400, packaging, punching, wiring, and making circuit patterns are uniformly performed on the package board, and finally cutting is performed, and the package is packaged.
  • the board is cut into several separate boards.
  • the top surface of the substrate 300 is provided with a first metal layer 100, and the bottom surface of the substrate 300 is not provided with a second metal layer 200.
  • the particle beam (or photon beam 610) employed can penetrate the substrate 300 but cannot penetrate the metal, the particle beam (or photon beam 610) can be divided into several beams, initially defining each beam of particles (or photon beam 610).
  • the beam 610) engraves the connection via 510 on the dielectric layer 500 through the first guiding hole 110. Since the laser light cannot penetrate the first metal layer 100, only the portion of the laser light passing through the connection via 510 can engrave the connection via 510.
  • the diameter of the through hole on the substrate 300 is larger than the diameter of the connection through hole 510, and the diameter of the connection through hole 510 is limited by the diameter of the first guiding hole 110.
  • the particle beam (or photon beam 610) may not be divided into several beams, and the engraved connection vias 510 may be directly irradiated.
  • the substrate 300 is adhered to the carrier 800 through the adhesive layer 810, the second metal layer 200 is formed on the top surface of the substrate 300, and the second metal layer 200 is formed into a second circuit layer, and the second circuit layer is formed.
  • a second guiding hole 210 is disposed, and a viscous dielectric layer 500 is disposed between the chip 400 and the substrate 300.
  • the chip 400 is mounted on the top surface of the substrate 300 through the dielectric layer 500, so that the chip pins 410 and 200 of the chip 400 are provided.
  • the guiding holes 210 correspond to each other, and at the same time, the chip 400 is electrically connected to the second circuit layer.
  • the second circuit layer includes a circuit pattern or a fine wiring, and the circuit pattern or fine wiring has a line width of less than 10 micrometers.
  • the line width of the wiring and circuit pattern obtained by the conventional method is about 60 micrometers, and the line width and the transmission speed cannot be further reduced.
  • the line width obtained is less than 10 micrometers, and a high-density circuit pattern or fine wiring can be formed in the second metal layer 200 to obtain a higher connection node density and a higher transmission speed.
  • the encapsulation layer 600 is disposed on the substrate 300, and the chip 400 is disposed between the encapsulation layer 600 and the substrate 300, and the cured encapsulation layer 600 fixes the chip 400.
  • the chip 400 is fixed by the encapsulation layer 600 under the support of the carrier 800. At this time, the positional relationship between the chip 400 and the chip 400, between the chip 400 and the second circuit layer is fixed, the connection relationship is fixed, and thereafter the production is completed. The process will not affect the positional relationship and connection relationship between the chip 400 and the chip 400, between the chip 400 and the second circuit layer.
  • the carrier 800 is detached from the substrate 300, and a first metal layer 100 is formed on the bottom surface of the substrate 300.
  • the first metal layer 100 is provided with a first guiding hole 110, a second guiding hole 210, a first guiding hole 110, and a chip lead
  • the foot 410 corresponds.
  • the carrier plate 800 is preferably a glass or metal material, and the metal material is preferably stainless steel.
  • the glass is transparent, and the adhesive layer 810 can be a photosensitive material.
  • the light conditions can be changed to disable the adhesive layer 810, and the carrier 800 can be released from the substrate 300.
  • the metal material is a good conductor of heat, and the adhesive layer 810 can be hot.
  • the sensitive material changing its temperature, can disable the adhesion of the adhesive layer 810 and release the carrier 800 from the substrate 300.
  • the thickness of the first metal layer 100 is greater than or equal to the thickness of the second metal layer 200, and a tight circuit pattern or fine wiring can be formed in the thin second metal layer 200 to obtain higher connection node density and higher transmission.
  • Speed on the other hand, the thicker first metal layer 100 acts as a positioning layer for the connection vias 510, preventing the particle beam or photon beam 610 from damaging the first metal layer 100.
  • the diameter of the second guiding hole 210 is less than or equal to the diameter of the first guiding hole 110, which facilitates the second guiding hole corresponding to the 210 chip pin 410, and ensures that the second guiding hole 210 corresponds to the first guiding hole 110,
  • the conductor layer 630 is disposed in the connection channel 700, it is advantageous to ensure electrical connection between the conductor layer 630 and the chip pins 410.
  • the chip 400 is at least two, at least two chips 400 are directly electrically connected through the second circuit layer, the transmission line between the chips 400 is increased, and the transmission does not need to pass other devices on the circuit, and the transmission speed can be improved.
  • the carrier 800 provides a supporting function and can be based on the carrier 800.
  • the substrate 300 is kept flat, and the line width and the gap of the circuit pattern and the fine wiring can be made smaller, and a more precise circuit pattern and fine wiring can be obtained (the second circuit layer can include the circuit pattern). , fine connection).
  • the support provided by the carrier 800 can maintain the flatness of the substrate 300 to facilitate the fabrication of the second circuit layer.

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

L'invention concerne un procédé de fabrication de circuit, consistant : en ce qu'un substrat comporte une première couche de métal, et en ce que la première couche de métal comporte un premier trou de guide ; en ce qu'une puce comporte une broche de puce ; en ce qu'une couche diélectrique est agencée entre la puce et le substrat, et en ce que la puce est placée sur une surface supérieure du substrat, de sorte que le premier trou de guide corresponde à la broche de puce ; et en ce qu'un faisceau de particules ou un faisceau de photons est émis par une surface inférieure du substrat vers la puce, le faisceau de particules ou le faisceau de photons ne pouvant traverser la première couche de métal ; et le faisceau de particules ou le faisceau de photons traversant le premier trou de guide et le substrat, et un trou traversant connecteur étant gravé dans la couche diélectrique. Ainsi, un trou traversant passant à travers le substrat, le premier trou de guide et le trou traversant connecteur communiquent entre eux pour former un canal connecteur, et la broche de puce communique de manière correspondante avec le canal connecteur. Un trou connecteur est fabriqué sur une carte de circuit imprimé et a un petit orifice, de sorte qu'un circuit fin à faible largeur de raie peut être fabriqué, accroissant ainsi la densité de lignes d'interconnexion, et accroissant la vitesse de transmission de la puce.
PCT/CN2017/076433 2017-03-13 2017-03-13 Procédé de fabrication de circuit WO2018165817A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
PCT/CN2017/076433 WO2018165817A1 (fr) 2017-03-13 2017-03-13 Procédé de fabrication de circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2017/076433 WO2018165817A1 (fr) 2017-03-13 2017-03-13 Procédé de fabrication de circuit

Publications (1)

Publication Number Publication Date
WO2018165817A1 true WO2018165817A1 (fr) 2018-09-20

Family

ID=63521799

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2017/076433 WO2018165817A1 (fr) 2017-03-13 2017-03-13 Procédé de fabrication de circuit

Country Status (1)

Country Link
WO (1) WO2018165817A1 (fr)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1344483A (zh) * 1999-03-16 2002-04-10 西门子公司 在双侧设有金属层的电绝缘基板材料上引入接触孔的方法
CN1812689A (zh) * 2005-01-26 2006-08-02 松下电器产业株式会社 多层电路基板及其制造方法
CN105070671A (zh) * 2015-09-10 2015-11-18 中芯长电半导体（江阴）有限公司 一种芯片封装方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1344483A (zh) * 1999-03-16 2002-04-10 西门子公司 在双侧设有金属层的电绝缘基板材料上引入接触孔的方法
CN1812689A (zh) * 2005-01-26 2006-08-02 松下电器产业株式会社 多层电路基板及其制造方法
CN105070671A (zh) * 2015-09-10 2015-11-18 中芯长电半导体（江阴）有限公司 一种芯片封装方法

Similar Documents

Publication Publication Date Title
CN101499445B (zh) 半导体器件及其制造方法
KR840002470B1 (ko) 요업체회로기판(窯業體回路基板) 제조방법
US20060003495A1 (en) Method for fabricating an electronic component embedded substrate
CN102376687A (zh) 半导体元件封装结构及其制造方法
JPH05206645A (ja) 多層プリント配線板の製造方法
CN109003959B (zh) 一种焊线预成型的高导热封装结构及其制造方法
US11039535B2 (en) Manufacturing holes in component carrier material
CN103474361A (zh) 一种嵌入式有源埋入功能基板的封装工艺及封装结构
CN104025728A (zh) 元器件内置基板的制造方法及使用该方法制造的元器件内置基板
TW201446084A (zh) 電路板及其製作方法
KR101874992B1 (ko) 부품 내장형 인쇄회로기판 및 이의 제조방법
CN108882558A (zh) 金手指的镀金方法及金手指电路板
JP2008263188A (ja) 回路基板の製造方法
TW202008527A (zh) 印刷電路板結構及其製造方法
JPH04150033A (ja) 電子回路基板のバンプ並びに電子回路基板のバンプ及び回路パターンの形成方法
CN114927493A (zh) 嵌埋封装基板的制作方法及嵌埋封装基板
CN103762205A (zh) 兼容pcb工艺的多功能基板及其制作方法
WO2018165817A1 (fr) Procédé de fabrication de circuit
WO2018219220A1 (fr) Structure de substrat de circuit semi-intégré et son procédé de fabrication
CN106373939B (zh) 一种封装基板的结构及其封装方法
KR20070115785A (ko) 빌드업 기판, 그것을 갖는 전자 부품 및 전자 기기
TW201417663A (zh) 承載板的製作方法
KR20060070930A (ko) 패키지 기판의 제조 방법
JP2018019111A (ja) 電子部品パッケージの製造方法
CN114423177A (zh) 一种mini LED电路板制作方法及mini LED电路板

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 17901121

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

32PN Ep: public notification in the ep bulletin as address of the adressee cannot be established

Free format text: NOTING OF LOSS OF RIGHTS PURSUANT TO RULE 112(1) EPC (EPO FORM 1205A DATED 06/12/2019)

122 Ep: pct application non-entry in european phase

Ref document number: 17901121

Country of ref document: EP

Kind code of ref document: A1