[go: up one dir, main page]

WO2018166020A1 - 芯片加密方法 - Google Patents

芯片加密方法 Download PDF

Info

Publication number
WO2018166020A1
WO2018166020A1 PCT/CN2017/080020 CN2017080020W WO2018166020A1 WO 2018166020 A1 WO2018166020 A1 WO 2018166020A1 CN 2017080020 W CN2017080020 W CN 2017080020W WO 2018166020 A1 WO2018166020 A1 WO 2018166020A1
Authority
WO
WIPO (PCT)
Prior art keywords
chip
value
algorithm
fuse
encryption method
Prior art date
Application number
PCT/CN2017/080020
Other languages
English (en)
French (fr)
Inventor
王波
毛宏程
段维虎
Original Assignee
广州众诺电子技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 广州众诺电子技术有限公司 filed Critical 广州众诺电子技术有限公司
Priority to US15/764,323 priority Critical patent/US10664623B2/en
Publication of WO2018166020A1 publication Critical patent/WO2018166020A1/zh

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
    • G06F21/71—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
    • G06F21/76—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information in application-specific integrated circuits [ASIC] or field-programmable devices, e.g. field-programmable gate arrays [FPGA] or programmable logic devices [PLD]
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/60—Protecting data
    • G06F21/602—Providing cryptographic facilities or services
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
    • G06F21/71—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
    • G06F21/72—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information in cryptographic circuits

Definitions

  • the present invention relates to the field of security chip technologies, and in particular, to a chip encryption method.
  • cryptographic security chips have developed into embedded systems with complete functions and complex hardware and software architectures.
  • cryptographic security chips generally have security problems.
  • Password security chips involve cryptographic algorithms and secrets. Key information, attackers can read, analyze, dissect and other attacks, such as ultra-high or ultra-low clock frequency attacks, physical detection attacks, energy attacks, side channel attacks, DPA attacks, etc., which seriously threatens password security. The security of the chip.
  • the biggest problem with the prior art is that if the cracker cracks any of the parent chips, the key and application using the parent chip can be easily obtained, that is, the chip of the batch is cracked.
  • the cost of cracking is lower and the security is lower.
  • the present invention provides a chip encryption method with high security and high cost of cracking, which can make each chip key unique.
  • a chip encryption method comprising the following steps
  • the fuse value and the trim value are used as algorithm parameters, and the algorithm is used to calculate the secret key of each chip, wherein the secret key of each chip is unique;
  • the fuse value, trim value and secret key of each chip are written into the corresponding chip.
  • the trimming value is a trimming value of a current, a voltage or a resistance of an analog circuit of each chip during the test.
  • the analog circuit comprises one or more of an LDO, BRG or OSC circuit.
  • the fuse value is a fuse value of a fuse in each chip, and the fuse value is obtained during the test.
  • the chip encryption method further comprises the step of blowing the fuse after the test is completed.
  • the fuse is blown after the test is completed.
  • the fuse values of each chip are unique.
  • the trim value of each chip is unique.
  • each chip comprises an external memory and an internal memory, and the fuse value, the trim value and the secret key are stored in an internal memory of the chip.
  • the internal memory includes a chip memory and a last level cache of the processor, the external memory including volatile storage and non-volatile storage.
  • the algorithm is one or more of a symmetry algorithm, an asymmetric algorithm, a hash algorithm or a custom algorithm.
  • the chip encryption method provided by the present invention adjusts the parameters of the chip algorithm by writing the trimming value and the fuse value of the corresponding chip to each chip. Since the trimming value and the fuse value of each chip are slightly different in the actual production process, the trimming value and the fuse value are written into the inside of each chip as parameters of the calculation key algorithm. Thereby, the uniqueness of the key of each chip is ensured, and the chip encryption method provided by the invention is simple, safe and reliable.
  • the chip encryption method according to the present invention can ensure that the same parent adopts different keys in different applications or different chips of the same application in mass production.
  • the chip encryption method of the present invention makes the key of each chip different. It greatly increases the cost and difficulty of the attacker. Even if an attacker cracks a chip, he can only get the key and application of the chip, and can only copy the single chip. If you want to perform batch cracking, you need to crack each chip in the batch chip. Therefore, the cost and difficulty of the cracker are greatly increased, and thus the meaning of the crack is lost.
  • FIG. 1 is a flowchart of a chip encryption method in an embodiment of the present invention.
  • a chip encryption method is provided, and the method includes the following steps:
  • step S1 the fuse value (fuse value) and the trim value (trim value) of each chip are obtained, and an algorithm is set.
  • the fuse value and the trim value can be tested or calculated by an external device, and the algorithm can be designed according to actual needs.
  • the fuse value and the trim value can be obtained by the device being tested.
  • the test device is an existing device, so its function and working principle are not described in this embodiment.
  • step S2 the fuse value and the trim value are used as algorithm parameters, and the algorithm is used to calculate the secret key of each chip, wherein the secret key of each chip is unique. Since the chip is usually affected by the production equipment and the production environment during the actual production process, the fuse value and the trimming value of each chip will be different from the fuse values and trim values of other chips, so the fuse will be melted.
  • the line value and the trim value are parameters of the corresponding chip secret key algorithm, so that the secret key of each chip is different from the key of other chips, that is, the secret keys of each chip are unique.
  • the production environment may be an environmental factor such as temperature or humidity.
  • step S3 the fuse value, the trim value and the secret key of each chip are written into the corresponding chip.
  • Each chip can store its own fuse value, trim value and the key corresponding to the two values. It should be noted that the order of step S1, step S2, and step S3 is not solid. set.
  • the trimming value is a trimming value of a current, a voltage, or a resistance of an analog circuit of each chip during the test.
  • Each chip needs to test the function of the chip after completing the package, such as CP test (ie, mid-test) or other functional tests such as FT test.
  • the analog circuit may include one or more of an LDO (Low Dropout Regulator), a BGR (Bandgap Reference Circuits), or an OSC (Oscillating Circuit) circuit.
  • the fuse value is a fuse value of the chip fuse, and the fuse value is obtained during the test.
  • the chip encryption method may further include the following step S4: the fuse of the chip is blown after the test is completed, so that the test state is unrecoverable.
  • the fuse values of the respective chips are unique.
  • the trim value of each chip is unique. It can be understood that at least one value of the fuse value and the trim value of each chip is unique.
  • the fuse value and the trim value are physical characteristics generated during the production process of the chip. Due to the influence of the production environment and/or equipment, the two values are often difficult to repeat, and it is difficult to pass some kind of The law is calculated or derived, that is, the fuse value and the trim value are naturally unique. Therefore, the key calculated by using the two values as parameters is unique, so even if the key of one of the chips is cracked, only the key and application of the chip can be obtained, and the same batch as the chip cannot be cracked. The other chips increase the difficulty of cracking the chip.
  • Each chip includes an external memory and an internal memory.
  • the fuse value, the trim value and the secret key are stored in the internal memory of the chip in this embodiment. in.
  • the internal memory includes a chip memory and a last level cache of the processor, the external memory including volatile storage and non-volatile storage.
  • the trimming value, the fuse value and the secret key of the writing chip can be written by the memory random address.
  • the memory random address storage method can be realized by scrambling the bus. For example, for an N-bit bus, there can be a factorial N of N!
  • an 8-bit bus can have 40320 kinds of arrangement
  • the memory randomization rule can be arranged in any one of the arrangement manners, and the bus arranged by the memory randomization method is no longer increased or decreased.
  • the order is discharged bit by bit. For example, if the data to be stored is discharged in order, address 01 stores the trim value, address 02 stores the fuse value, and address 03 stores the secret key, and other addresses store other data, after the memory random address method (for example, mapping can be employed) After the function performs the calculation, address 03 stores the trim value, address 07 stores the fuse value, and address 05 stores the secret key, and other addresses store other data.
  • the algorithm is one or more of a symmetry algorithm, an asymmetric algorithm, a hash algorithm, a grouping algorithm, or a custom algorithm.
  • the symmetry algorithm includes a DES (Data Encryption Standard) algorithm or an AES (Advanced Encryption Standard) algorithm.
  • the asymmetry algorithm includes an RSA algorithm (a number-based asymmetry (public key) encryption algorithm proposed by Rivest, Shamir, and Adleman) or an ECC algorithm (Elliptic Curves Cryptography, a public key). Encryption algorithm) and so on.
  • the hash algorithm includes an MD5 algorithm (Message-Digest Algorithm 5) or a SHA-1 algorithm (Secure Hash Algorithm-1).
  • the algorithm in this embodiment is preferably an asymmetric algorithm. And different algorithms can be set for different purposes or different fields of chips as needed.
  • the chip encryption method according to the present invention can ensure that the same parent adopts different keys in different applications or different chips of the same application in mass production.
  • the chip encryption method of the present invention makes the key of each chip different. It greatly increases the cost and difficulty of the attacker. Even if an attacker cracks a chip, he can only get the key and application of the chip, and can only copy the single chip. It is necessary to crack each chip in the batch chip, thus greatly increasing the cost and difficulty of the cracker, thus losing the meaning of the crack. Thereby protecting the intellectual property of the user to the utmost extent.

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Computer Security & Cryptography (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Health & Medical Sciences (AREA)
  • Bioethics (AREA)
  • General Health & Medical Sciences (AREA)
  • Storage Device Security (AREA)

Abstract

一种芯片加密方法，包括如下步骤：获取各个芯片的熔线值及修调值，并设置算法（S1）；将熔线值、修调值作为算法参数，并利用算法计算得出各个芯片的秘钥，各个芯片的秘钥唯一（S2）；将各个芯片的熔线值、修调值及秘钥均写入相应的芯片内（S3）。所述的芯片加密方法，由于各个芯片的熔线值、修调值天然具有唯一性，因此能确保在批量生产时同一颗母体在不同的应用时或同一应用的不同芯片所采取的秘钥完全不同。即使攻击者破解一颗芯片，只能拿到该颗芯片的秘钥和应用，且只能复制该单颗芯片，若要进行批量破解，则要对批量芯片中的每个芯片分别进行破解，大大增加了破解者的成本及难度，就失去了破解的意义。从而最大限度上保护了使用者的知识产权。

Description

芯片加密方法 技术领域
本发明涉及安全芯片技术领域，具体涉及一种芯片加密方法。
背景技术
随着SOC设计水平的提升和技术的进步，密码安全芯片已经发展成为功能齐全，软硬件结构复杂的嵌入式系统，但同时密码安全芯片却普遍存在安全问题，密码安全芯片涉及到密码算法、密钥等信息，攻击者可以对其读取、分析、解剖等攻击，如超高或超低时钟的频率攻击、物理探测攻击、能量攻击、侧信道攻击、DPA攻击等等，严重威胁了密码安全芯片的安全。
现有的芯片通常采取固定的加密算法和秘钥，或者仅仅利用芯片的ID号来进行加密。在实际大批量生产中，破解者只需要破解同一个母体芯片或者通过软件修改去掉ID号的捆绑，便能获取使用该母体芯片采用的算法和秘钥，从而获取相应批次芯片秘钥。
现有的密码安全加密芯片大多数采取的是内置安全加密算法，设计硬件AES模块、3DES加密算法模块等。设计使用同一的秘钥，将秘钥固化到芯片里。同一颗晶元母体(市面上有不同型号的SOC芯片，虽然封装不同、容量等略有差异，但设计时采用的仍然是同一颗晶元母体)由于在设计时已经固化，采用的是同一种加密算法和秘钥。
然而在实际应用中，有可能同一颗晶元母体有着不同的应用，理 论上同一颗晶元母体有着无数多个不同的应用。因此，攻击者只需要破解任意一颗母体，就可以很快得到使用该母体的任何应用。
因此，现有技术存在的最大问题在于如果破解者破解其中的任意一颗母体芯片，则会轻松获取到使用该母体芯片的秘钥及应用，即破解该批次的芯片。对破解者来说，破解成本较低，安全性较低。
发明内容
为解决上述问题，本发明提供一种安全性高，破解成本高的芯片加密方法，该方法能使得各个芯片秘钥唯一。
一种芯片加密方法，包括如下步骤
获取各个芯片的熔线值及修调值，并设置算法；
将熔线值、修调值作为算法参数，并利用算法计算得出各个芯片的秘钥，其中各个芯片的秘钥唯一；
将各个芯片的熔线值、修调值及秘钥均写入相应的芯片内。
优选地，所述修调值为在测试过程中各芯片的模拟电路的电流、电压或者电阻的修调值。
优选地，所述模拟电路包括LDO、BRG或者OSC电路中的一种或者多种。
优选地，所述熔线值为各芯片中熔丝的熔断值，在测试过程中获取该熔线值。
优选地，芯片加密方法还包括如下步骤，在测试完成之后将熔丝熔断。在测试完成之后将熔丝熔断。
优选地，各芯片的熔线值唯一。
优选地，各芯片的修调值唯一。
优选地，各芯片包括外部存储器及内部存储器，所述熔线值、修调值及秘钥存储于芯片的内部存储器中。
优选地，所述内部存储器包括芯片内存及处理器的最后一级缓存，所外部存储器包括易失性存储及非易失性存储。
优选地，所述算法为对称性算法、非对称算法、杂凑算法或者自定义算法中的一种或者多种。
本发明的有益效果：
与现有技术，本发明提供的一种芯片加密方法通过向各个芯片内部写入相应的芯片的修调值和熔线值，来调整芯片算法的参数。由于在实际生产过程中每个芯片的修调值和熔线值有略微的差异，通过把修调值和熔线值作为计算秘钥算法的参数写入到每个芯片内部。从而保证了每个芯片的秘钥唯一性，本发明提供的芯片加密方法操作简单且安全可靠。
综上所述，应用本发明所述的芯片加密方法，能确保在批量生产时同一颗母体在不同的应用时或同一应用的不同芯片所采取的秘钥完全不同。本发明所述的芯片加密方法使得每个芯片的秘钥不同。大大增加了攻击者的成本及难度。即使攻击者破解一颗芯片，也只能拿到该颗芯片的秘钥和应用，只能复制该单颗芯片，若要进行批量破解，则需要对批量芯片中的每个芯片都进行破解，因此大大增加了破解者的成本及难度，这样也就失去了破解的意义。
附图说明
图1为本发明的实施例中一种芯片加密方法的流程图。
具体实施方式
下面，结合附图以及具体实施方式，对本发明做进一步描述：
参照图1，本实施例中提供一种芯片加密方法，该方法包括如下步骤：
步骤S1，获取各个芯片的熔线值(fuse值)及修调值(trim值)，并设置算法。其中所述熔线值及修调值可通过外部设备进行测试或者计算得出，所述算法可根据实际需要设计。例如所述熔线值及修调值可通过测试的设备获取。该测试设备为已有设备，因此其功能及工作原理在本实施例中不予赘述。
步骤S2，将熔线值、修调值作为算法参数，并利用算法计算得出各个芯片的秘钥，其中各个芯片的秘钥唯一。由于芯片在实际生产过程中通常会受到生产设备及生产环境的影响而导致每个芯片的熔线值及修调值都会与其他芯片的熔线值及修调值有一定的差别，因此将熔线值及修调值作为相应芯片秘钥算法的参数，可以使得每个芯片的秘钥均与其他芯片的秘钥不相同，即各个芯片的秘钥都是唯一的。所述生产环境可以是温度或者湿度等环境因素。
步骤S3，将各个芯片的熔线值、修调值及秘钥均写入相应的芯片内。每个芯片内均可存储其自身的熔线值、修调值及与该两种值对应的秘钥。需要说明的是步骤S1、步骤S2、步骤S3的顺序并非固 定。
所述修调值为在测试过程中各芯片的模拟电路的电流、电压或者电阻的修调值。各个芯片在完成封装之后都需要对芯片的功能进行测试，例如CP测试(即中测)或者FT测试等其他功能测试等。所述模拟电路可以包括LDO(Low Dropout Regulator，低压差线性稳压器)、BGR(Bandgap Reference Circuits，频带间隙参考电路)或者OSC(震荡电路)电路中的一种或者多种。所述熔线值为芯片熔丝的熔断值，在测试过程中获取该熔线值。
作为优选方案，为了提高芯片的安全性，芯片加密方法还可包括如下步骤S4：在测试完成之后将芯片的熔丝熔断，使得所述测试状态不可恢复。
作为优选的方案，各芯片的熔线值唯一。作为另一优选的方案，各芯片的修调值唯一。可以理解为，所述每个芯片的熔线值与修调值至少有一个值是唯一的。熔线值及修调值是在芯片生产过程中产生的一种物理特性，由于生产环境和/或设备的因素影响，导致该两种值通常很难出现重复的，并且也很难通过某种规律计算或者推导出来，也就是说熔线值及修调值天然具有唯一性。因此利用该两个值作为参数计算出来的秘钥具有唯一性，所以即使破解了其中一个芯片的秘钥，也只能得出该芯片的秘钥及应用，并不能破解与该芯片相同批次的其他芯片，从而增加了破解芯片的难度。
各芯片包括外部存储器及内部存储器。为了提高芯片的安全性，本实施例中将所述熔线值、修调值及秘钥存储于芯片的内部存储器 中。所述内部存储器包括芯片内存及处理器的最后一级缓存，所外部存储器包括易失性存储及非易失性存储。为了进一步提高芯片的安全性，本发明的实施例中，可通过存储器乱址来对写入芯片的修调值、熔线值及秘钥。例如可通过对总线进行搅乱来实现存储器乱址存储法，例如对于一个N位的总线，可以有N的阶乘N！种方式排列，例如对应一个8位的总线可以有40320种排列方式，存储器乱址法则是可以采取其中任意一种排列方式进行排列即可，并且存储器乱址法排列的总线不再按照增加或者减少的顺序逐位排放。例如若按照顺序排放所需要存储的数据时，地址01存储修调值，地址02存储熔线值，而地址03存储秘钥，其他地址存储其他数据，在经过存储器乱址法(例如可采用映射函数进行计算)之后，地址03存储修调值，地址07存储熔线值，而地址05存储秘钥，其他地址存储其他数据。因此安全芯片破解者若不知道相关的乱址所采用的函数时，要发现存储器实际上是如何编址是十分困难的，从而可以进一步提高芯片的安全性及破解的难度。当然也可以利用其他函数实现存储器地址进行重新编址。
所述算法为对称性算法、非对称算法、杂凑算法、分组算法或者自定义算法中的一种或者多种。所述对称性算法包括DES(Data Encryption Standard，数据加密标准)算法或AES(Advanced Encryption Standard,高级加密标准)算法等。所述非对称性算法包括RSA算法(是Rivest、Shamir和Adleman提出来的基于数论非对称性(公开钥)加密算法)或者ECC算法(Elliptic Curves Cryptography，公钥 加密算法)等。所述杂凑算法包括MD5算法(Message-Digest Algorithm 5，信息-摘要算法)或SHA-1算法(Secure Hash Algorithm-1，安全散列算法)等。作为优选的方案，本实施例中的算法优选非对称算法。并且可根据需要针对不同用途或者不同领域的芯片设置不同的算法。
秘钥加密实施例
以下通过具体实施例对本发明的方法进行说明：如采用AES加密算法，密码长度为192bit，其中熔线值取8bit，修调值取16bit，固定秘钥168bit。设熔线值为X，修调值为Y，固定秘钥Z，则秘钥计算的公式可为：K＝Z+X+Y①。
当A芯片的熔线值为X1，修调值为Y1，则根据公式①可得秘钥K1＝X1+Y1+Z。
当B芯片的熔线值为X2，修调值为Y2，则根据公式①秘钥K2＝X2+Y2+Z。
由于熔线值、修调值在生产过程中会存在差异，所每个芯片的熔线值、修调值是不同的，即X1≠X2；Y1≠Y2，所以必然存在K1一定不等于K2。
综上所述，应用本发明所述的芯片加密方法，能确保在批量生产时同一颗母体在不同的应用时或同一应用的不同芯片所采取的秘钥完全不同。本发明所述的芯片加密方法使得每个芯片的秘钥不同。大大增加了攻击者的成本及难度。即使攻击者破解一颗芯片，也只能拿到该颗芯片的秘钥和应用，只能复制该单颗芯片，若要进行批量破解， 则需要对批量芯片中的每个芯片都进行破解，因此大大增加了破解者的成本及难度，这样也就失去了破解的意义。从而最大限度上保护了使用者的知识产权。
对本领域的技术人员来说，可根据以上描述的技术方案以及构思，做出其它各种相应的改变以及形变，而所有的这些改变以及形变都应该属于本发明权利要求的保护范围之内。

Claims (10)

  1. 一种芯片加密方法，其特征在于，包括如下步骤：
    获取各个芯片的熔线值及修调值，并设置算法；
    将熔线值、修调值作为算法参数，并利用算法计算得出各个芯片的秘钥，其中各个芯片的秘钥唯一；
    将各个芯片的熔线值、修调值及秘钥均写入相应的芯片内。
  2. 根据权利要求1所述的芯片加密方法，其特征在于：所述修调值为在测试过程中各芯片的模拟电路的电流、电压或者电阻的修调值。
  3. 根据权利要求2所述的芯片加密方法，其特征在于：所述模拟电路包括LDO、BRG或者OSC电路中的一种或者多种。
  4. 根据权利要求1、2或3任一项所述的芯片加密方法，其特征在于：所述熔线值为各芯片中熔丝的熔断值，在测试过程中获取该熔线值。
  5. 根据权利要求4所述的芯片加密方法，其特征在于：还包括如下步骤，在测试完成之后将熔丝熔断。
  6. 根据权利要求1、2或3任一项所述的芯片加密方法，其特征在于：各芯片的熔线值唯一。
  7. 根据权利要求1、2或3任一项所述的芯片加密方法，其特征在于：各芯片的修调值唯一。
  8. 根据权利要求1、2或3任一项所述的芯片加密方法，其特征在于：各芯片包括外部存储器及内部存储器，所述熔线值、修调值及秘钥存储于芯片的内部存储器中。
  9. 根据权利要求8所述的芯片加密方法，其特征在于：所述内部存储器包括芯片内存及处理器的最后一级缓存，所外部存储器包括易失性存储及非易失性存储。
  10. 根据权利要求1、2或3任一项所述的芯片加密方法，其特征在于：所述算法为对称性算法、非对称算法、杂凑算法或者自定义算法中的一种或者多种。
PCT/CN2017/080020 2017-03-17 2017-04-11 芯片加密方法 WO2018166020A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US15/764,323 US10664623B2 (en) 2017-03-17 2017-04-11 Method for chip encryption

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201710160228.0 2017-03-17
CN201710160228.0A CN106991340B (zh) 2017-03-17 2017-03-17 芯片加密方法

Publications (1)

Publication Number Publication Date
WO2018166020A1 true WO2018166020A1 (zh) 2018-09-20

Family

ID=59411618

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2017/080020 WO2018166020A1 (zh) 2017-03-17 2017-04-11 芯片加密方法

Country Status (4)

Country Link
US (1) US10664623B2 (zh)
JP (1) JP2018157560A (zh)
CN (1) CN106991340B (zh)
WO (1) WO2018166020A1 (zh)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110395049A (zh) * 2018-04-25 2019-11-01 广州众诺电子技术有限公司 高容量芯片及耗材容器
CN110929271A (zh) * 2019-10-31 2020-03-27 苏州浪潮智能科技有限公司 一种芯片防篡改方法、系统、终端及存储介质
US11152052B1 (en) 2020-06-03 2021-10-19 Micron Technology, Inc. Apparatuses, systems, and methods for fuse array based device identification
CN112398641A (zh) * 2020-11-17 2021-02-23 上海桂垚信息科技有限公司 一种基于aes加密算法在加密芯片上的应用方法
US11856114B2 (en) 2021-02-12 2023-12-26 Taiwan Semiconductor Manufacturing Co., Ltd. Device signature based on trim and redundancy information

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140310800A1 (en) * 2012-10-19 2014-10-16 Atul Kabra Secure disk access control
CN104798338A (zh) * 2012-12-27 2015-07-22 英特尔公司 用于在集成电路制造期间保护密钥制备的熔丝认证
CN105575436A (zh) * 2016-02-23 2016-05-11 中国科学院半导体研究所 可编程控制多晶熔丝电路及包含该电路的集成电路
CN106443399A (zh) * 2016-09-08 2017-02-22 上海华岭集成电路技术股份有限公司 一种防止芯片熔丝误熔断的方法

Family Cites Families (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6635048B1 (en) * 1999-04-30 2003-10-21 Medtronic, Inc. Implantable medical pump with multi-layer back-up memory
US7840803B2 (en) * 2002-04-16 2010-11-23 Massachusetts Institute Of Technology Authentication of integrated circuits
US6801146B2 (en) * 2002-11-14 2004-10-05 Fyre Storm, Inc. Sample and hold circuit including a multiplexer
DK1572463T3 (da) * 2002-12-02 2011-07-25 Silverbrook Res Pty Ltd Kompensation for en død dyse
JP2005260614A (ja) * 2004-03-12 2005-09-22 Dainippon Printing Co Ltd 暗号装置
US8230326B2 (en) * 2004-12-17 2012-07-24 International Business Machines Corporation Method for associating annotations with document families
US8881246B2 (en) * 2006-12-29 2014-11-04 Taiwan Semiconductor Manufacturing Company, Ltd. System and method for providing secured integrated engineering analysis
US8290150B2 (en) * 2007-05-11 2012-10-16 Validity Sensors, Inc. Method and system for electronically securing an electronic device using physically unclonable functions
US20080320263A1 (en) * 2007-06-20 2008-12-25 Daniel Nemiroff Method, system, and apparatus for encrypting, integrity, and anti-replay protecting data in non-volatile memory in a fault tolerant manner
US8965956B2 (en) * 2007-10-09 2015-02-24 Cleversafe, Inc. Integrated client for use with a dispersed data storage network
US8379856B2 (en) * 2009-06-17 2013-02-19 Empire Technology Development Llc Hardware based cryptography
US20140193154A1 (en) * 2010-02-22 2014-07-10 Vello Systems, Inc. Subchannel security at the optical layer
GB2486635B (en) * 2010-12-14 2016-12-14 Stmicroelectronics (Research & Development) Ltd Detecting key corruption
CN102393890B (zh) * 2011-10-09 2014-07-16 广州大学 一种抗物理入侵和旁路攻击的密码芯片系统及其实现方法
US9459955B2 (en) * 2012-05-24 2016-10-04 Sandisk Technologies Llc System and method to scramble data based on a scramble key
JP5710561B2 (ja) * 2012-08-29 2015-04-30 株式会社東芝 半導体記憶装置
AP2015008555A0 (en) * 2012-11-26 2015-06-30 Irdeto Bv Obtaining a version of an item of content
TWI622969B (zh) * 2012-12-17 2018-05-01 印奈克斯托股份有限公司 用以使用物理特性來標記製造物品的方法及設備
US9390291B2 (en) * 2012-12-29 2016-07-12 Intel Corporation Secure key derivation and cryptography logic for integrated circuits
US9223674B2 (en) * 2013-03-11 2015-12-29 Wisconsin Alumni Research Foundation Computer system and method for runtime control of parallelism in program execution
US9533743B2 (en) * 2013-03-15 2017-01-03 Terry W. Cox Life saving apparatus
US9628086B2 (en) * 2013-11-14 2017-04-18 Case Western Reserve University Nanoelectromechanical antifuse and related systems
US9934411B2 (en) * 2015-07-13 2018-04-03 Texas Instruments Incorporated Apparatus for physically unclonable function (PUF) for a memory array
US9995789B2 (en) * 2015-12-22 2018-06-12 Intel IP Corporation Secure remote debugging of SoCs
US10128794B2 (en) * 2016-09-29 2018-11-13 Macronix International Co., Ltd. Feedback compensated oscillator

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140310800A1 (en) * 2012-10-19 2014-10-16 Atul Kabra Secure disk access control
CN104798338A (zh) * 2012-12-27 2015-07-22 英特尔公司 用于在集成电路制造期间保护密钥制备的熔丝认证
CN105575436A (zh) * 2016-02-23 2016-05-11 中国科学院半导体研究所 可编程控制多晶熔丝电路及包含该电路的集成电路
CN106443399A (zh) * 2016-09-08 2017-02-22 上海华岭集成电路技术股份有限公司 一种防止芯片熔丝误熔断的方法

Also Published As

Publication number Publication date
CN106991340A (zh) 2017-07-28
CN106991340B (zh) 2018-05-15
US20190156068A1 (en) 2019-05-23
JP2018157560A (ja) 2018-10-04
US10664623B2 (en) 2020-05-26

Similar Documents

Publication Publication Date Title
WO2018166020A1 (zh) 芯片加密方法
CN109005040B (zh) 动态多密钥混淆puf结构及其认证方法
US9992031B2 (en) Dark bits to reduce physically unclonable function error rates
US9483664B2 (en) Address dependent data encryption
US9875378B2 (en) Physically unclonable function assisted memory encryption device techniques
US11171793B2 (en) Method and system for detecting an attack on a physically unclonable function (PUF)
US11232718B2 (en) Methods and devices for protecting data
TW201141177A (en) Hardware attestation techniques
GB2513265A (en) Provisioning of security certificates
CN107430670A (zh) 用于存储器保护的柔性计数器系统
CN104243137B (zh) 数据处理系统以及初始化数据处理系统的方法
US11368319B2 (en) Integrated circuit performing authentication using challenge-response protocol and method of using the integrated circuit
CN110659506A (zh) 基于密钥刷新对存储器进行重放保护
CN105095097A (zh) 随机化的存储器访问
US20100011221A1 (en) Secured storage device with two-stage symmetric-key algorithm
JP5831203B2 (ja) 個体別情報生成装置、暗号化装置、認証システム、及び個体別情報生成方法
JP6054225B2 (ja) 構成情報管理装置および構成情報管理方法
US11734415B2 (en) Device and method for managing an encrypted software application
US20220284088A1 (en) Authentication of write requests
JP6284301B2 (ja) 保守作業判定装置および保守作業判定方法
US11531785B2 (en) PUF-based data integrity
JP2014155043A (ja) Ｉｃカード
CN114866228A (zh) 一种实现软密码模块的方法、系统、存储介质及终端
JP6007918B2 (ja) デバイス固有情報生成出力装置、デバイス固有情報生成方法および生成プログラム
CN104573754A (zh) 芯片标识符读写方法

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 17900637

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 17900637

Country of ref document: EP

Kind code of ref document: A1