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WO2018171160A1 - 快速放电电路、显示装置、快速放电方法和显示控制方法 - Google Patents

快速放电电路、显示装置、快速放电方法和显示控制方法 Download PDF

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Publication number
WO2018171160A1
WO2018171160A1 PCT/CN2017/104161 CN2017104161W WO2018171160A1 WO 2018171160 A1 WO2018171160 A1 WO 2018171160A1 CN 2017104161 W CN2017104161 W CN 2017104161W WO 2018171160 A1 WO2018171160 A1 WO 2018171160A1
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WO
WIPO (PCT)
Prior art keywords
discharge
level
display
unit
display device
Prior art date
Application number
PCT/CN2017/104161
Other languages
English (en)
French (fr)
Inventor
孙世成
王珍
丛乐乐
方业周
霍培荣
Original Assignee
京东方科技集团股份有限公司
鄂尔多斯市源盛光电有限责任公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司, 鄂尔多斯市源盛光电有限责任公司 filed Critical 京东方科技集团股份有限公司
Priority to US15/774,182 priority Critical patent/US10650719B2/en
Publication of WO2018171160A1 publication Critical patent/WO2018171160A1/zh
Priority to US16/844,430 priority patent/US11189216B2/en

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2085—Special arrangements for addressing the individual elements of the matrix, other than by driving respective rows and columns in combination
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2092—Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0248—Precharge or discharge of column electrodes before or after applying exact column voltages
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0251—Precharge or discharge of pixel before applying new pixel voltage
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/027—Arrangements or methods related to powering off a display

Definitions

  • the present disclosure relates to the field of discharge control technologies, and in particular, to a rapid discharge circuit, a display device, a rapid discharge method, and a display control method.
  • LTPS Low Temperature Poly-silicon
  • the LTPS shows that the leakage current Ioff is relatively small due to the process design and the double gate structure design. Therefore, when the display panel is powered off abnormally, the LTPS shows that the product has a small charge discharge process due to the small leakage current Ioff, and it is easy to generate charge residue. Therefore, after the display device is abnormally powered down, it is necessary to set a discharge unit to quickly release the pixel charge of the display panel.
  • a fast discharge circuit applied to a display device in the related art requires an additional design space for a discharge cell in a GOA (Gate On Array) circuit, and a modified Mask is required in the production of the display panel. The number is large and the cost is high.
  • the main purpose of the present disclosure is to provide a fast discharge circuit, a display device, a rapid discharge method, and a display control method, which need to additionally design a special space for a discharge unit on a display substrate in the related art, and need to adopt a display panel. There are many problems with the number of masks after the change, and the cost is high.
  • the present disclosure provides a fast discharge circuit applied to a display device, the fast discharge circuit including a discharge unit;
  • a control end of the discharge unit is connected to a driving integrated circuit, a first end of the discharge unit is connected to a gate line included in the display device, and a second end of the discharge unit and a display level end in the display device Connecting; the display level end is connected to the driving integrated circuit;
  • the discharge unit is configured to control the display level end to write a first level to the gate line when the display device is abnormally powered down.
  • the discharge unit includes a discharge transistor
  • a gate of the discharge transistor is connected to the driving integrated circuit, a first pole of the discharge transistor is connected to the gate line, and a second pole of the discharge transistor is connected to the display level end.
  • the present disclosure also provides a display device comprising a plurality of rows of gate lines, a plurality of columns of data lines, a data switch and a driving integrated circuit, the driving integrated circuit comprising a data voltage providing unit, the first end of the data switch The data voltage supply unit is connected, the second end of the data switch is connected to the data line, and the display device further comprises the fast discharge circuit described above;
  • the driving integrated circuit further includes a determining unit, a potential control unit and a data line control unit; the control end of the data switch is connected to the data line control unit;
  • the determining unit is configured to output an abnormal power-down indication signal when it is determined that the display device is abnormally powered down;
  • the potential control unit is respectively connected to the determining unit, the control end of the discharge unit, and the display level end, and is configured to output a discharge to the control end of the discharge unit when receiving the abnormal power-down indication signal Controlling a signal and controlling a potential of the display level terminal to be a first level;
  • the data line control unit is respectively connected to the determining unit, the control end of the data switch, and the data voltage providing unit, for controlling the data when receiving an abnormal power-down indication signal from the determining unit Switching to cause the data voltage supply unit to write a predetermined discharge level to the data line;
  • the discharge unit is configured to control the display level terminal to write a first level to the gate line when the control terminal thereof receives the discharge control signal.
  • the first level is a high level
  • the first level is a low level.
  • the discharge unit when the discharge unit includes a discharge transistor, a gate of the discharge transistor is connected to the potential control unit, a first pole of the discharge transistor is connected to the gate line, and a second of the discharge transistor The pole is connected to the display level terminal.
  • the potential control unit is further configured to: when the abnormal power-down indication signal is not received, control the discharge transistor to be turned on during a touch period, and control the display level end to write the second level into the Grid line.
  • the second level is a low level
  • the second level is a high level.
  • the display level end is a display low level end; the display low level end is not conductive to the low level end of the static electricity protection circuit applied to the static electricity protection circuit in the display device.
  • the display device further includes a gate driving circuit; the gate driving circuit is connected to the start signal input end, the clock signal input end, the first scan voltage output end, and the second scan voltage output end;
  • the discharge unit is further connected to the start signal input end, the clock signal input end, the first scan voltage output end and the second scan voltage output end, and is further configured to receive the abnormality Controlling the start signal input end, the clock signal input end, the first scan voltage output end, and the second scan voltage output end to be connected to a third level when the power down indication signal is used to control the
  • the gate drive circuit works normally.
  • the data voltage supply unit is a data driving circuit disposed in the driving integrated circuit
  • the determining unit is a comparator disposed in the driving integrated circuit
  • the potential control unit is disposed in the A register in the integrated circuit is driven, the data line control unit being a controller disposed in the drive integrated circuit.
  • the predetermined discharge level is a ground level.
  • the present disclosure also provides a fast discharge method applied to the above-described fast discharge circuit, the fast discharge method comprising: when the display device is abnormally powered down, the discharge unit controls the display level end to write the first level to the gate line .
  • the present disclosure also provides a display control method, which is applied to the above display device, and the display control method includes:
  • the determining unit determines that the display device is abnormally powered down, the determining unit outputs an abnormal power-down indication signal to the potential control unit and the data line control unit;
  • the data line control unit When the data line control unit receives the abnormal power down indication signal, the data line control unit controls the data switch to cause the data voltage supply unit to write a predetermined discharge level to the data line; when the potential control unit receives When the abnormal power-down indication signal is reached, the potential control unit outputs a discharge control signal to the control terminal of the discharge unit, and controls the potential of the display level terminal to be the first level;
  • the discharge unit controls the display level terminal to write a first level to the gate line to control the gate of the pixel region to be connected to the gate line.
  • the thin film transistor is turned on;
  • the residual charge on the pixel electrode is released to the data line through the open thin film transistor.
  • the display control method when connected to the display level end, the display control method further includes:
  • the potential control unit When the potential control unit does not receive the abnormal power-down indication signal, the potential control unit controls the discharge transistor to be turned on during the touch time period, and controls the display level end to write the second level Into the gate line.
  • the display control method when the display level end in the display device is the display low level end, the display control method further includes:
  • the control separates the display low-level terminal from the low-voltage terminal of the static electricity protection in the display device such that the display low-level terminal and the static electricity protection low-level terminal are not connected.
  • the predetermined discharge level is a ground level.
  • FIG. 1 is a structural diagram of a fast discharge circuit according to an embodiment of the present disclosure
  • FIG. 2 is a structural diagram of a specific embodiment of a discharge cell of a fast discharge circuit according to an embodiment of the present disclosure
  • FIG. 3 is a structural diagram of a display device according to an embodiment of the present disclosure.
  • FIG. 4 is a schematic diagram of a pixel area of a display device according to an embodiment of the present disclosure.
  • 5A is a structural diagram of a specific embodiment of a discharge cell of a fast discharge circuit in a display device according to an embodiment of the present disclosure
  • Figure 5B is a structural view of another embodiment of the discharge cell
  • 5C is a schematic diagram showing the connection between the low-level terminal VGL_GOA and the output terminal of the driving integrated circuit
  • FIG. 6 is a circuit diagram of still another embodiment of the discharge cell
  • FIG. 7 is a flowchart of a display control method according to an embodiment of the present disclosure.
  • Figure 8 is a schematic diagram showing the separation of VGL_GOA and VGL_ESD;
  • Figure 9 is a schematic view showing the connection and cutting of signal lines between the units shown in Figure 8.
  • FIG. 10A is a schematic diagram of a first DO (Data Output) side ESD (Electro-Static Discharge) unit sharing a VGL signal with a first GOA circuit area in the related art;
  • DO Data Output
  • ESD Electro-Static Discharge
  • 10B is a schematic diagram of the first DO-side ESD unit obtaining a low level VGL through the static-protection low-level terminal VGL_ESD in the embodiment of the present disclosure, the first GOA circuit region being connected to the display low-level terminal VGL_GOA;
  • 11A is a schematic diagram of a VGL signal shared by a first GOA circuit region and a first test board in the related art
  • FIG. 11B is a schematic diagram of the first test board obtaining a low level VGL through the electrostatic protection low level terminal VGL_ESD in the embodiment of the present disclosure, the first GOA circuit region being connected to the display low level terminal VGL_GOA.
  • the fast discharge circuit of the embodiment of the present disclosure is applied to a display device, as shown in FIG. 1, the fast discharge circuit includes a discharge unit 11;
  • the control end of the discharge unit 11 is connected to the driving integrated circuit 10, the first end of the discharge unit 11 is connected to the gate line Gate included in the display device, and the second end of the discharge unit is in the display device Display level end DLT connection; the display level end DLT is connected to the driving integrated circuit 10;
  • the discharge unit 11 is configured to control the display level terminal DLT to write a first level to the gate line Gate when the display device is abnormally powered down.
  • the determining unit in the display device when the determining unit in the display device is not within the predetermined voltage range according to the power source voltage outputted by the power source circuit in the display device and/or the external power source voltage received by the power source circuit, the determining unit determines The display device is abnormally powered down.
  • the driving integrated circuit 10 is a driving chip integrated with a data driving circuit, a timing controller, and a power supply circuit.
  • the discharge unit 11 included in the fast discharge circuit of the embodiment of the present disclosure is a circuit unit belonging to the related art in the display device, which is different from the related art in that when the display device is abnormally powered down,
  • the first level is supplied from the driving integrated circuit 10 to the display level terminal DLT, and the discharge unit 11 controls the display level terminal DLT to write a first level to the gate line Gate, thereby causing the gate in the pixel region to be
  • the thin film transistor connected to the gate line Gate is turned on.
  • the discharge unit 11 includes a discharge transistor Td;
  • a gate of the discharge transistor Td is connected to the driving integrated circuit 10, the discharge crystal
  • the source of the transistor Td is connected to the gate line Gate, and the drain of the discharge transistor Td is connected to the display level terminal DLT.
  • the Td is an n-type transistor as an example, but in actual operation, Td can also be replaced with a p-type transistor.
  • the display device of the embodiment of the present disclosure includes a plurality of rows of gate lines, a plurality of columns of data lines, a data switch MUX, and a driving integrated circuit;
  • the driving integrated circuit includes a data voltage providing unit 21, a first end of the data switch MUX is connected to the data voltage providing unit 21, and a second end of the data switch MUX is connected to the data line DL;
  • the driving integrated circuit further includes a determining unit 22, a potential control unit 23 and a data line control unit 24; the control end of the data switch MUX is connected to the data line control unit 24;
  • the display device further includes the above-described fast discharge circuit
  • the fast discharge circuit includes a discharge unit 11;
  • a control end of the discharge unit 11 is connected to the potential control unit 23, a first end of the discharge unit 11 is connected to a gate line Gate included in the display device, and a second end of the discharge unit is connected to the display a display level terminal DLT connection in the device; the display level terminal DLT is connected to the potential control unit 23;
  • the determining unit 22 is configured to output an abnormal power-down indication signal Spad when it is determined that the display device is abnormally powered down;
  • the potential control unit 23 is respectively connected to the determining unit 22, the control end of the discharge unit 11, and the display level terminal DLT, and is configured to send to the discharge unit when the abnormal power-down indication signal Spad is received.
  • the control terminal of 11 outputs a discharge control signal, and controls the potential of the display level terminal DLT to be a first level;
  • the data line control unit 24 is connected to the determining unit 22, the control end of the data switch MUX, and the data voltage providing unit 21, respectively, for receiving an abnormal power-down indication signal from the determining unit 22
  • the data switch MUX is controlled to cause the data voltage supply unit 21 to write a predetermined discharge level to the data line DL;
  • the discharge unit 11 is configured to control the display level terminal DLT to write a first level to the gate line Gate when its control terminal receives the discharge control signal.
  • the data voltage providing unit may be a data driving circuit in the driving integrated circuit
  • the determining unit may be a comparator disposed in the driving integrated circuit by comparing the power voltage received by the power circuit.
  • the power control unit may be a register disposed in the driving integrated circuit
  • the data line control unit may be a controller disposed in the driving integrated circuit.
  • a display device of an embodiment of the present disclosure includes a plurality of rows of gate lines and a plurality of columns of data lines; the gate lines and the data lines define a pixel region in which a thin film transistor and a pixel electrode are disposed, the thin film transistor a gate is connected to the gate line, a source of the thin film transistor is connected to the data line, and a drain of the thin film transistor is connected to the pixel electrode;
  • FIG. 3 does not show a plurality of rows of gate lines, a plurality of rows of data lines included in the display device, and thin film transistors and pixel electrodes disposed in the pixel regions defined by the gate lines and the data lines, the above components will be combined below Figure 4 illustrates.
  • the fast discharge circuit in the display device of the embodiment of the present disclosure includes a plurality of discharge cells, each of which is respectively connected to a row of gate lines for making the electrical position of the row of gate lines first when the power is abnormally powered down. a level such that a thin film transistor whose gate in the pixel region is connected to the row gate line is turned on, at which time the data line control unit controls the data switch to cause the data voltage supply unit to write a predetermined discharge level into the The data line is such that residual charge in the pixel electrode is released to the data line through the open thin film transistor.
  • the predetermined discharge level is a ground level.
  • the discharge effect is optimal.
  • the display device can control the residual charge in the pixel region to be released to the corresponding data line when the display device is abnormally powered down, by using the discharge unit and the display level terminal already included therein, and can utilize the related art.
  • the discharge unit and the display level realize rapid discharge, and save space for additional discharge in the display substrate for abnormal power failure compared with the related art, and the change of the original display product is small, and the Mask (mask) to be changed is small, and the cost is small. low.
  • the display device includes a plurality of rows of gate lines and a plurality of rows of data lines disposed in an AA (Active Area) area;
  • the gate line and the data line define a pixel region, and the pixel region is provided with a thin film crystal a transistor and a pixel electrode, a gate of the thin film transistor is connected to the gate line, a source of the thin film transistor is connected to the data line, and a drain of the thin film transistor is connected to the pixel electrode;
  • the labels are Gate1, Gate2, Gate3, and Gate4 are respectively the first row gate line, the second row gate line, the third row gate line, and the fourth row gate line; and the labels are Data1, Data2, Data3, and Data4.
  • Data5, Data6, Data7, and Data8 are the first column data line, the second column data line, the third column data line, the fourth column data line, the fifth column data line, the sixth column data line, and the seventh column, respectively.
  • the plurality of rows of data lines are connected to the data driving circuit.
  • the data driving circuit is provided in the above-described driving IC.
  • the first level is a high level
  • the first level is a low level.
  • the discharge unit may include a discharge transistor
  • a gate of the discharge transistor is connected to the potential control unit, a first pole of the discharge transistor is connected to a corresponding row gate line, and a second pole of the discharge transistor is connected to the display level terminal.
  • the gate of the discharge transistor Td is connected to the potential control unit 23, and the source and gate of the discharge transistor Td are gated. Connected, the drain of the discharge transistor Td is connected to the display level terminal DLT;
  • the potential control unit 23 is further configured to control the discharge transistor Td to be turned on during the touch time period and control the display level end DLT to write the second level when the abnormal power-down indication signal is not received.
  • the gate line Gate is inserted to disconnect the thin film transistor whose gate is connected to the gate line Gate in the pixel region of the touch period. That is, in this case, the touch control transistor in the related art is multiplexed into the discharge transistor Td, which controls the potential of the gate line during the touch period to control the gate in the pixel region. A transistor in which a thin film transistor connected to the gate line is disconnected. In actual operation, other transistors in the display device may be multiplexed into a discharge transistor, which is not limited herein.
  • the second level is a low level
  • the second level is a high level.
  • the display level end may be a low level terminal VGL_GOA for display
  • the potential control unit 23 is further configured to control the display low-level terminal VGL_GOA to output a first level when receiving the abnormal power-down indication signal;
  • the embodiment of the present disclosure can provide a high level for VGL_GOA through the output terminal of the driving IC, and the output terminal can output a high level, so that it can be realized. Pull the potential of VGL_GOA high to an abnormal power-down.
  • VGL_GOA is connected to the output terminal OUTP of the driving integrated circuit 10, and in the related art, VGL_GOA is connected to the power supply terminal Power_Pin.
  • a gate of the discharge transistor Td is connected to the touch enable terminal TX_EN, and the touch enable terminal TX_EN is connected to the potential control unit 23, and the first pole of the discharge transistor Td Connected to a corresponding row of gates Gate, the second pole of the discharge transistor Td is connected to the display low-level terminal VGL_GOA; that is, multiplexed by the touch control transistor into a discharge transistor Td;
  • the discharge transistor Td is an n-type transistor (in FIG. 6 , the Td is an n-type transistor as an example. In actual operation, Td may also be a p-type transistor, which is not limited herein);
  • the potential control unit controls the potential of TX_EN to be a high level, and the potential control unit controls the potential of VGL_GOA to also be a high level, so that Td is turned on, and the gate line Gate is controlled to be connected to a high level, thereby making a thin film transistor in which a gate electrode in the pixel region is connected to the gate line Gate is turned on, thereby discharging a charge remaining in a pixel electrode connected to a drain of the thin film transistor to a data line connected to a source of the thin film transistor, Thereby achieving a rapid discharge.
  • the display level terminal is the display low-level terminal VGL_GOA
  • the discharge transistor Both the Td and GOA circuits are connected to the low-level terminal VGL_GOA for display. Due to the structure of the ESD protection circuit, if VGL_GOA is connected to the low-voltage end of ESD protection as in the related art, it is impossible to achieve low-voltage ESD protection during the discharge phase. The potential of the flat VGL_ESD is pulled high, and it is impossible to increase the potential of the low-level terminal VGL_GOA during the discharge phase. Therefore, unlike the related art, it is necessary to separate the low-level terminal for display and the low-level terminal for electrostatic protection.
  • the display device further includes a gate driving circuit; the gate driving circuit is connected to the initial signal input end, the clock signal input end, the first scan voltage output end, and the second scan voltage output end;
  • the discharge unit is further connected to the start signal input end, the clock signal input end, the first scan voltage output end and the second scan voltage output end, respectively, to receive the abnormal power failure And controlling the start signal input end, the clock signal input end, the first scan voltage output end and the second scan voltage output end to be connected to a third level to control the gate
  • the drive circuit works normally.
  • the third level is a high level.
  • the first pole of the discharge transistor included in the discharge unit in the embodiment of the present disclosure is commonly connected with the output end of the gate driving circuit, so when the power is abnormally powered off, the gate driving circuit needs to be
  • the potential of the signal such as the clock signal is also set to a high level to set the electric position of the gate driving signal of the display area to a high level, thereby avoiding the potential of the gate driving signal outputted by the gate driving circuit being low.
  • the pixel region gate line cannot be pulled high during abnormal power-down, and rapid discharge is achieved.
  • the fast discharge method according to the embodiment of the present disclosure is applied to the above-described fast discharge circuit, and the fast discharge method includes: when the display device is abnormally powered down, the discharge unit controls the display level end to write the first level to the gate line .
  • the display control method according to the embodiment of the present disclosure is applied to the above display device. As shown in FIG. 7, the display control method includes:
  • S2 when the data line control unit receives the abnormal power-down indication signal, the data line control unit controls the data switch to cause the data voltage supply unit to write a predetermined discharge level to the data line; when the potential is controlled When the unit receives the abnormal power-down indication signal, the potential control unit outputs a discharge control signal to the control terminal of the discharge unit, and controls the potential of the display level terminal to be the first level;
  • S3 when the control of the discharge unit When the terminal receives the discharge control signal, the discharge unit controls the display level terminal to write the first level to the gate line to control the opening of the thin film transistor connected to the gate line in the pixel region;
  • the display control method when connected to the display level end, the display control method further includes:
  • the potential control unit When the potential control unit does not receive the abnormal power-down indication signal, the potential control unit controls the discharge transistor to be turned on during the touch time period, and controls the display level end to write the second level Into the gate line.
  • the display control method further includes:
  • the control separates the display low-level terminal from the low-voltage terminal of the static electricity protection in the display device such that the display low-level terminal and the static electricity protection low-level terminal are not connected.
  • the display low-level terminal VGL_GOA is separated from the static-protection low-level terminal VGL_ESD, and the potential of the VGL_ESD cannot be raised in the discharge phase due to the structure of the static electricity protection circuit. It is impossible to realize that the potential of the low-level terminal VGL_GOA is pulled high during the discharge phase, and therefore, unlike the related art, it is necessary to separate the low-level terminal for display and the low-level terminal for electrostatic protection.
  • Figure 8 is a schematic diagram showing the separation of VGL_GOA and VGL_ESD.
  • Fig. 8 is intended to express the area division of the VGL separation wiring in the display device.
  • a first GOA circuit region and a second GOA circuit region are respectively disposed on the left side and the right side of the AA area (effective display area), and the VGL_GOA wiring is disposed in the first GOA circuit area and the second GOA Inside the circuit area;
  • a first VGL_ESD (electrostatic protection) GOA circuit region is disposed on a left side of the first GOA circuit region, and a second VGL_ESD GOA circuit region is disposed on a right side of the second GOA circuit region;
  • the first VGL_ESD GOA circuit region and the second VGL_ESD GOA circuit region respectively include an ESD unit that protects the GOA and a VGL_ESD wiring that connects the DO-side ESD unit;
  • a first DO side (opposite side of the drive IC) ESD unit is disposed at the upper left of the AA area, and a second DO side ESD unit is disposed at the upper right of the AA area;
  • a first test board is disposed at the lower left of the AA area, and a second test board is disposed at the lower right of the AA area;
  • the first test board and the second test board are provided with test points for driving the integrated circuit input signals (including the clock signal, the high level signal VGH, the low level signal VGL, etc.), and the needle can be tested by using an oscilloscope or the like;
  • a driver integrated circuit and an FPC are disposed in this order directly below the AA area.
  • a first DO side ESD unit a second DO side ESD unit, a first VGL_ESD GOA circuit area, a second VGL_ESD GOA circuit area, a first test board, a second test board, a first GOA circuit area, and a
  • the two GOA circuit regions all acquire a low level through a VGL bus (that is, a line that provides a low level), however, in the technical solution of the embodiments of the present disclosure, the first GOA circuit region and the second GOA circuit The area needs to acquire a high level from the output terminal on the driver IC through VGL_GOA, so VGL_GOA and VGL_ESD need to be separated.
  • connection line between the units is a signal line
  • the cross mark is marked as a cut position.
  • the signal line added in the embodiment of the present disclosure is a signal line between the first GOA circuit area and the driving integrated circuit. And a signal line between the second GOA circuit region and the driver integrated circuit.
  • the first DO-side ESD unit shares a VGL signal with the first GOA circuit region, and the VGL signals are all supplied by the power supply terminal (not shown in FIG. 10A); as shown in FIG. 10B,
  • the first DO-side ESD unit obtains a low level VGL from the power supply terminal (not shown in FIG. 10B) through the static-protection low-level terminal VGL_ESD, and the first GOA circuit region passes the display low-voltage Flat-end VGL_GOA slave drive integrated circuit output ( Figure Not shown in 10B) Acquires a high level when the power is abnormally turned off.
  • both the first GOA circuit region and the first test board acquire the VGL signal through the power supply terminal (not shown in FIG. 11A).
  • the first GOA circuit region obtains high power from the output terminal of the driving integrated circuit (not shown in FIG. 11B) through the low-level terminal VGL_GOA for abnormal power failure.
  • the first test board still acquires the VGL signal from the power supply terminal (not shown in FIG. 11B) through the static protection low-level terminal VGL_ESD.

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Abstract

一种快速放电电路、显示装置、快速放电方法和显示控制方法。所述快速放电电路包括放电单元（11）；所述放电单元（11）的控制端与驱动集成电路（10）连接，所述放电单元（11）的第一端与显示装置包括的栅线（Gate）连接，所述放电单元（11）的第二端与所述显示装置中的显示电平端（DLT）连接；所述显示电平端（DLT）与所述驱动集成电路（10）连接；所述放电单元（11）用于在所述显示装置异常掉电时控制所述显示电平端（DLT）将第一电平写入所述栅线（Gate）。

Description

快速放电电路、显示装置、快速放电方法和显示控制方法
相关申请的交叉引用
本申请主张在2017年3月23日在中国提交的中国专利申请No.201710177793.8的优先权，其全部内容通过引用包含于此。
技术领域
本公开文本涉及放电控制技术领域，尤其涉及一种快速放电电路、显示装置、快速放电方法和显示控制方法。
背景技术
LTPS(Low Temperature Poly-silicon，低温多晶硅技术)显示产品因工艺设计与双栅的结构设计，漏电流Ioff比较小。所以在显示面板异常下电时，LTPS显示产品因漏电流Ioff较小的原因，电荷释放过程缓慢，易产生电荷残留。因此在显示装置异常掉电后，需要设置放电单元来快速释放显示面板像素区电荷。相关技术中的应用于显示装置的快速放电电路需要在GOA(Gate On Array，阵列基板行驱动)电路内为放电单元额外设计空间，在制作显示面板时需要采用变更后的Mask(掩膜)的数目多，费用高。
发明内容
本公开文本的主要目的在于提供一种快速放电电路、显示装置、快速放电方法和显示控制方法，解决相关技术中需要在显示基板上为放电单元额外设计专门的空间，在制作显示面板时需要采用变更后的掩膜的数目多，费用高的问题。
为了达到上述目的，本公开文本提供了一种快速放电电路，应用于显示装置，所述快速放电电路包括放电单元；
所述放电单元的控制端与驱动集成电路连接，所述放电单元的第一端与所述显示装置包括的栅线连接，所述放电单元的第二端与所述显示装置中的显示电平端连接；所述显示电平端与所述驱动集成电路连接；
所述放电单元用于在所述显示装置异常掉电时控制所述显示电平端将第一电平写入所述栅线。
实施时，所述放电单元包括放电晶体管；
所述放电晶体管的栅极与所述驱动集成电路连接，所述放电晶体管的第一极与所述栅线连接，所述放电晶体管的第二极与所述显示电平端连接。
本公开文本还提供了一种显示装置，包括多行栅线、多列数据线、数据开关和驱动集成电路，所述驱动集成电路包括数据电压提供单元，所述数据开关的第一端与所述数据电压提供单元连接，所述数据开关的第二端与所述数据线连接，所述显示装置还包括上述的快速放电电路；
所述驱动集成电路还包括判断单元、电位控制单元和数据线控制单元；所述数据开关的控制端与所述数据线控制单元连接；
所述判断单元用于当判断到所述显示装置异常掉电时输出异常掉电指示信号；
所述电位控制单元分别与所述判断单元、所述放电单元的控制端和所述显示电平端连接，用于当接收到所述异常掉电指示信号时向所述放电单元的控制端输出放电控制信号，并控制所述显示电平端的电位为第一电平；
所述数据线控制单元分别与所述判断单元、所述数据开关的控制端和所述数据电压提供单元连接，用于当接收到来自所述判断单元的异常掉电指示信号时控制所述数据开关以使得所述数据电压提供单元将预定放电电平写入所述数据线；
所述放电单元用于当其控制端接收到所述放电控制信号时控制所述显示电平端将第一电平写入所述栅线。
实施时，当像素区域中的栅极与所述栅线连接的薄膜晶体管为n型晶体管时，所述第一电平为高电平；
当像素区域中的栅极与所述栅线连接的薄膜晶体管为p型晶体管时，所述第一电平为低电平。
实施时，当所述放电单元包括放电晶体管时，所述放电晶体管的栅极与所述电位控制单元连接，所述放电晶体管的第一极与所述栅线连接，所述放电晶体管的第二极与所述显示电平端连接。
所述电位控制单元还用于在未接收到所述异常掉电指示信号时，在触控时间段控制所述放电晶体管导通，并控制所述显示电平端将第二电平写入所述栅线。
实施时，当像素区域中的栅极与所述栅线连接的薄膜晶体管为n型晶体管时，所述第二电平为低电平；
当像素区域中的栅极与所述栅线连接的薄膜晶体管为p型晶体管时，所述第二电平为高电平。
实施时，所述显示电平端为显示用低电平端；所述显示用低电平端与所述显示装置中的应用于静电防护电路中的静电防护用低电平端之间不导通。
实施时，所述显示装置还包括栅极驱动电路；所述栅极驱动电路与起始信号输入端、时钟信号输入端、第一扫描电压输出端和第二扫描电压输出端连接；
所述放电单元还分别与所述起始信号输入端、所述时钟信号输入端、所述第一扫描电压输出端和所述第二扫描电压输出端连接，还用于在接收到所述异常掉电指示信号时控制所述起始信号输入端、所述时钟信号输入端、所述第一扫描电压输出端和所述第二扫描电压输出端都接入第三电平，以控制所述栅极驱动电路正常工作。
实施时，所述数据电压提供单元为设置于所述驱动集成电路中的数据驱动电路，所述判断单元为设置于所述驱动集成电路中的比较器，所述电位控制单元为设置于所述驱动集成电路中的寄存器，所述数据线控制单元为设置于所述驱动集成电路中的控制器。
实施时，所述预定放电电平为地电平。
本公开文本还提供了一种快速放电方法，应用于上述的快速放电电路，所述快速放电方法包括：在显示装置异常掉电时，放电单元控制显示电平端将第一电平写入栅线。
本公开文本还提供了一种显示控制方法，应用于上述的显示装置，所述显示控制方法包括：
当判断单元判断到显示装置异常掉电时，判断单元向电位控制单元和数据线控制单元输出异常掉电指示信号；
当数据线控制单元接收到所述异常掉电指示信号时，所述数据线控制单元控制所述数据开关以使得所述数据电压提供单元将预定放电电平写入数据线；当电位控制单元接收到所述异常掉电指示信号时，所述电位控制单元向放电单元的控制端输出放电控制信号，并控制显示电平端的电位为第一电平；
当所述放电单元的控制端接收到所述放电控制信号时，所述放电单元控制所述显示电平端将第一电平写入栅线，以控制像素区域内栅极与该栅线连接的薄膜晶体管打开；
像素电极上的残留电荷通过打开的薄膜晶体管释放至所述数据线。
实施时，当所述放电单元包括放电晶体管，所述放电晶体管的栅极与所述电位控制单元连接，所述放电晶体管的第一极与相应行栅线连接，所述放电晶体管的第二极与所述显示电平端连接时，所述显示控制方法还包括：
在所述电位控制单元未接收到所述异常掉电指示信号时，在触控时间段，所述电位控制单元控制所述放电晶体管导通，并控制所述显示电平端将第二电平写入所述栅线。
实施时，当所述显示装置中的显示电平端为显示用低电平端时，所述显示控制方法还包括：
控制将显示用低电平端和所述显示装置中的静电防护用低电平端分离，以使得所述显示用低电平端和静电防护用低电平端不连接。
实施时，所述预定放电电平为地电平。
附图说明
为了更清楚地说明本申请实施例的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请中记载的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。以下附图并未刻意按实际尺寸等比例缩放绘制，重点在于示出本申请的主旨。
图1是本公开文本实施例所述的快速放电电路的结构图；
图2是本公开文本实施例所述的快速放电电路的放电单元的一具体实施例的结构图；
图3是本公开文本实施例所述的显示装置的结构图；
图4是本公开文本实施例所述的显示装置的像素区域的示意图；
图5A是本公开文本实施例所述的显示装置中的快速放电电路的放电单元的一具体实施例的结构图；
图5B是所述放电单元的另一具体实施例的结构图；
图5C是显示用低电平端VGL_GOA与驱动集成电路的输出端子之间的连接示意图；
图6是所述放电单元的又一具体实施例的电路图；
图7是本公开文本实施例所述的显示控制方法的流程图；
图8是VGL_GOA和VGL_ESD分离示意图；
图9是图8所示中各单元间的信号线的连接与切断示意图；
图10A是在相关技术中第一DO(Data Output，数据输出)侧ESD(Electro-Static Discharge，静电放电)单元与第一GOA电路区域共用VGL信号的示意图；
图10B是在本公开文本实施例中第一DO侧ESD单元通过静电防护低电平端VGL_ESD获得低电平VGL，第一GOA电路区域与显示用低电平端VGL_GOA连接的示意图；
图11A是在相关技术中第一GOA电路区域和第一测试板共用VGL信号的示意图；
图11B是在本公开文本实施例中第一测试板通过静电防护低电平端VGL_ESD获得低电平VGL，第一GOA电路区域与显示用低电平端VGL_GOA连接的示意图。
具体实施方式
下面将结合本公开文本实施例中的附图，对本公开文本实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开文本一部分实施例，而不是全部的实施例。基于本公开文本中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开文本保护的范围。
除非另作定义，此处使用的技术术语或者科学术语应当为本公开文本所属领域内具有一般技能的人士所理解的通常意义。本公开文本专利申请说明书以及权利要求书中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”或者“一”等类似词语也不表示数量限制，而是表示存在至少一个。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也相应地改变。
本公开文本实施例所述的快速放电电路，应用于显示装置，如图1所示，所述快速放电电路包括放电单元11；
所述放电单元11的控制端与驱动集成电路10连接，所述放电单元11的第一端与所述显示装置包括的栅线Gate连接，所述放电单元的第二端与所述显示装置中的显示电平端DLT连接；所述显示电平端DLT与所述驱动集成电路10连接；
所述放电单元11用于在所述显示装置异常掉电时控制所述显示电平端DLT将第一电平写入所述栅线Gate。
在具体实施例时，当显示装置中的判断单元根据显示装置中的电源电路输出的电源电压和/或所述电源电路接收到的外部电源电压不在预定电压范围内时，所述判断单元判断所述显示装置异常掉电。
在实际操作时，所述驱动集成电路10为集成有数据驱动电路、时序控制器和电源电路的驱动芯片。
在具体实施时，本公开文本实施例所述的快速放电电路包括的放电单元11即为显示装置中的属于相关技术的电路单元，与相关技术不同之处在于，在显示装置异常掉电时，由驱动集成电路10提供第一电平至所述显示电平端DLT，放电单元11控制显示电平端DLT将第一电平写入所述栅线Gate，从而使得像素区域中的栅极与所述栅线Gate连接的薄膜晶体管打开。
在实际操作时，如图2所示，所述放电单元11包括放电晶体管Td；
所述放电晶体管Td的栅极与所述驱动集成电路10连接，所述放电晶体 管Td的源极与栅线Gate连接，所述放电晶体管Td的漏极与所述显示电平端DLT连接。
在图2所示的实施例中，以Td为n型晶体管为例，但是在实际操作时，Td也可以被替换为p型晶体管。
如图3所示，本公开文本实施例所述的显示装置，包括多行栅线、多列数据线、数据开关MUX和驱动集成电路；
所述驱动集成电路包括数据电压提供单元21，所述数据开关MUX的第一端与所述数据电压提供单元21连接，所述数据开关MUX的第二端与数据线DL连接；
所述驱动集成电路还包括判断单元22、电位控制单元23和数据线控制单元24；所述数据开关MUX的控制端与所述数据线控制单元24连接；
所述显示装置还包括上述的快速放电电路；
所述快速放电电路包括放电单元11；
所述放电单元11的控制端与所述电位控制单元23连接，所述放电单元11的第一端与所述显示装置包括的栅线Gate连接，所述放电单元的第二端与所述显示装置中的显示电平端DLT连接；所述显示电平端DLT与所述电位控制单元23连接；
所述判断单元22用于当判断到所述显示装置异常掉电时输出异常掉电指示信号Spad；
所述电位控制单元23分别与所述判断单元22、所述放电单元11的控制端和所述显示电平端DLT连接，用于当接收到所述异常掉电指示信号Spad时向所述放电单元11的控制端输出放电控制信号，并控制所述显示电平端DLT的电位为第一电平；
所述数据线控制单元24分别与所述判断单元22、所述数据开关MUX的控制端和所述数据电压提供单元21连接，用于当接收到来自所述判断单元22的异常掉电指示信号Spad时控制所述数据开关MUX以使得所述数据电压提供单元21将预定放电电平写入所述数据线DL；
所述放电单元11用于当其控制端接收到所述放电控制信号时控制所述显示电平端DLT将第一电平写入所述栅线Gate。
在实际操作时，所述数据电压提供单元可以为所述驱动集成电路中的数据驱动电路，所述判断单元可以为设置于驱动集成电路中的比较器，通过比较电源电路接收到的电源电压而判断是否异常掉电，电位控制单元可以为设置于驱动集成电路中的寄存器，数据线控制单元可以为设置于驱动集成电路中的控制器。
本公开文本实施例的显示装置包括多行栅线和多列数据线；所述栅线和所述数据线限定出像素区域，所述像素区域内设有薄膜晶体管和像素电极，所述薄膜晶体管的栅极与所述栅线连接，所述薄膜晶体管的源极与所述数据线连接，所述薄膜晶体管的漏极与所述像素电极连接；
图3未示出显示装置包括的多行栅线、多行数据线，以及设置于所述栅线和所述数据线限定出的像素区域内的薄膜晶体管和像素电极，以上部件将在下面结合图4说明。
本公开文本实施例所述的显示装置中的快速放电电路包括多个放电单元，每一个放电单元分别与一行栅线连接，用于在异常掉电时将该行栅线的电位置为第一电平，从而使得像素区域中的栅极与该行栅线连接的薄膜晶体管打开，此时数据线控制单元控制所述数据开关以使得所述数据电压提供单元将预定放电电平写入所述数据线，从而使得像素电极中残留的电荷通过打开的薄膜晶体管释放至数据线。
可选地，该预定放电电平为地电平。
在具体实施时，当控制所述数据线置地(即接入地电平)时，放电效果最佳。
本公开文本实施例所述的显示装置利用其中已经包括的放电单元和显示电平端即可在显示装置异常掉电时控制像素区域中残留的电荷释放至相应的数据线，可以利用相关技术中的放电单元和显示电平实现快速放电，与相关技术相比节省显示基板中为异常掉电时放电额外设计的空间，对原有显示产品变更处小，需要变更的Mask(掩膜)少，费用低。
如图4所示，所述显示装置包括设置于AA(有效显示区，Active Area)区的多行栅线和多行数据线；
所述栅线和所述数据线限定出像素区域，所述像素区域内设有薄膜晶体 管和像素电极，所述薄膜晶体管的栅极与所述栅线连接，所述薄膜晶体管的源极与所述数据线连接，所述薄膜晶体管的漏极与所述像素电极连接；
在图4中，标号为Gate1、Gate2、Gate3、Gate4的分别为第一行栅线、第二行栅线、第三行栅线、第四行栅线；标号为Data1、Data2、Data3、Data4、Data5、Data6、Data7、Data8的分别为第一列数据线、第二列数据线、第三列数据线、第四列数据线、第五列数据线、第六列数据线、第七列数据线、第八列数据线；标号为TFT(Thin Film Transistor)的为薄膜晶体管，标号为PE(Pixel Electrode)的为像素电极。
在实际操作时，所述多行数据线都与数据驱动电路连接。所述数据驱动电路设置于上述的驱动IC中。
当像素区域中的栅极与所述栅线连接的薄膜晶体管为n型晶体管时，所述第一电平为高电平；
当像素区域中的栅极与所述栅线连接的薄膜晶体管为p型晶体管时，所述第一电平为低电平。
具体地，所述放电单元可以包括放电晶体管；
所述放电晶体管的栅极与所述电位控制单元连接，所述放电晶体管的第一极与相应行栅线连接，所述放电晶体管的第二极与所述显示电平端连接。
具体地，如图5A所示，当所述放电单元11包括放电晶体管Td时，所述放电晶体管Td的栅极与所述电位控制单元23连接，所述放电晶体管Td的源极与栅线Gate连接，所述放电晶体管Td的漏极与所述显示电平端DLT连接；
所述电位控制单元23还用于在未接收到所述异常掉电指示信号时，在触控时间段控制所述放电晶体管Td导通，并控制所述显示电平端DLT将第二电平写入所述栅线Gate，以使得在触控时间段像素区域中栅极与所述栅线Gate连接的薄膜晶体管断开。也即，在此种情况下，由相关技术中的触控控制晶体管复用为放电晶体管Td，该触控控制晶体管即为在触控时间段时控制栅线的电位以控制像素区域中的栅极与该栅线连接的薄膜晶体管断开的晶体管。在实际操作时，也可以采用显示装置中其他的晶体管复用为放电晶体管，在此不作限定。
当像素区域中的栅极与所述栅线连接的薄膜晶体管为n型晶体管时，所述第二电平为低电平；
当像素区域中的栅极与所述栅线连接的薄膜晶体管为p型晶体管时，所述第二电平为高电平。
在具体实施时，如图5B所示，所述显示电平端可以为显示用低电平端VGL_GOA；
所述电位控制单元23还用于当接收到所述异常掉电指示信号时控制所述显示用低电平端VGL_GOA输出第一电平；
在实际操作时，VGL_GOA原本的输出为低电平，无法拉高，因此本公开文本实施例可以通过驱动IC的输出端子为VGL_GOA提供高电平，该输出端子可以输出高电平，因此可以实现在异常掉电时将VGL_GOA的电位拉至高电平。
如图5C所示，VGL_GOA与驱动集成电路10的输出端子OUTP连接，而在相关技术中，VGL_GOA与电源端Power_Pin连接。
如图6所示，一所述放电晶体管Td的栅极与触控使能端TX_EN连接，所述触控使能端TX_EN与所述电位控制单元23连接，所述放电晶体管Td的第一极与相应的一行栅线Gate连接，所述放电晶体管Td的第二极与显示用低电平端VGL_GOA连接；也即由触控控制晶体管复用为放电晶体管Td；
所述放电晶体管Td为n型晶体管(在图6中以Td为n型晶体管为例，在实际操作时，Td也可以为p型晶体管，在此不作限定)；
在异常掉电时，电位控制单元控制TX_EN的电位为高电平，电位控制单元控制VGL_GOA的电位也为高电平，从而Td导通，控制该行栅线Gate接入高电平，从而使得像素区域中的栅极接入该行栅线Gate的薄膜晶体管都导通，从而将与该薄膜晶体管的漏极连接的像素电极中残留的电荷放电至该薄膜晶体管的源极连接的数据线，从而实现快速放电。
在实际操作时，当所述显示电平端为显示用低电平端VGL_GOA时，所述显示用低电平端VGL_GOA与所述显示装置中的应用于静电防护电路中的静电防护用低电平端之间不导通。
在实际操作时，当由触控控制晶体管复用作放电晶体管时，放电晶体管 Td和GOA电路都与显示用低电平端VGL_GOA连接，由于静电防护电路的结构，如果像相关技术中那样VGL_GOA与静电防护用低电平端连接的话，则无法实现在放电阶段将静电防护用低电平端VGL_ESD的电位拉高，而无法实现在放电阶段将显示用低电平端VGL_GOA的电位拉高，因此与相关技术不同，需要将显示用低电平端和静电防护用低电平端分离。
在具体实施时，所述显示装置还包括栅极驱动电路；所述栅极驱动电路与起始信号输入端、时钟信号输入端、第一扫描电压输出端和第二扫描电压输出端连接；
所述放电单元还分别与所述起始信号输入端、所述时钟信号输入端、所述第一扫描电压输出端和所述第二扫描电压输出端连接，以在接收到所述异常掉电指示信号时控制所述起始信号输入端、所述时钟信号输入端、所述第一扫描电压输出端和所述第二扫描电压输出端都接入第三电平，以控制所述栅极驱动电路正常工作。
当像素区域中设置的薄膜晶体管为n型晶体管时，所述第三电平为高电平。
在实际操作时，需要在放电时保证栅极驱动电路正常工作，以使得不影响TX_EN控制放电晶体管放电。
由于在具体实施时，本公开文本实施例中的放电单元包括的放电晶体管的第一极与栅极驱动电路的输出端是连接共通的，所以在异常下电时，需要将栅极驱动电路中的时钟信号等信号的电位同样置为高电平，以将显示区的栅极驱动信号的电位置为高电平，从而避免由于栅极驱动电路输出的栅极驱动信号的电位为低电平从而导致在异常掉电时无法将像素区栅线拉高，实现快速放电。
本公开文本实施例所述的快速放电方法，应用于上述的快速放电电路，所述快速放电方法包括：在显示装置异常掉电时，放电单元控制显示电平端将第一电平写入栅线。
本公开文本实施例所述的显示控制方法，应用于上述的显示装置，如图7所示，所述显示控制方法包括：
S1：当判断单元判断到显示装置异常掉电时，判断单元向电位控制单元 和数据线控制单元输出异常掉电指示信号；
S2：当数据线控制单元接收到所述异常掉电指示信号时，所述数据线控制单元控制所述数据开关以使得所述数据电压提供单元将预定放电电平写入数据线；当电位控制单元接收到所述异常掉电指示信号时，所述电位控制单元向放电单元的控制端输出放电控制信号，并控制显示电平端的电位为第一电平；S3：当所述放电单元的控制端接收到所述放电控制信号时，所述放电单元控制所述显示电平端将第一电平写入栅线，以控制像素区域内栅极与该栅线连接的薄膜晶体管打开；
S4：像素电极上的残留电荷通过打开的薄膜晶体管释放至所述数据线。
具体地，当所述放电单元包括放电晶体管，所述放电晶体管的栅极与所述电位控制单元连接，所述放电晶体管的第一极与相应行栅线连接，所述放电晶体管的第二极与所述显示电平端连接时，所述显示控制方法还包括：
在所述电位控制单元未接收到所述异常掉电指示信号时，在触控时间段，所述电位控制单元控制所述放电晶体管导通，并控制所述显示电平端将第二电平写入所述栅线。
具体地，当所述显示装置中的显示电平端为显示用低电平端时，所述显示控制方法还包括：
控制将显示用低电平端和所述显示装置中的静电防护用低电平端分离，以使得所述显示用低电平端和静电防护用低电平端不连接。
在本公开文本实施例所述的显示装置中，将显示用低电平端VGL_GOA与静电防护用低电平端VGL_ESD分离，由于静电防护电路的结构，无法实现在放电阶段将VGL_ESD的电位拉高，而无法实现在放电阶段将显示用低电平端VGL_GOA的电位拉高，因此与相关技术不同，需要将显示用低电平端和静电防护用低电平端分开。
图8为将VGL_GOA和VGL_ESD分离示意图。
图8意在表达显示装置中VGL分离布线的区域划分。
在图8中，在显示基板上，
在AA区(有效显示区)左侧、右侧分别设置有第一GOA电路区域、第二GOA电路区域，VGL_GOA布线设置于第一GOA电路区域和第二GOA 电路区域里面；
在第一GOA电路区域左侧设置有第一VGL_ESD(静电防护)GOA电路区域，在第二GOA电路区域右侧设置有第二VGL_ESD GOA电路区域；
所述第一VGL_ESD GOA电路区域和所述第二VGL_ESD GOA电路区域分别包括保护GOA的ESD单元和连接DO侧ESD单元的VGL_ESD布线；
在AA区的左上方设置有第一DO侧(Drive IC(驱动集成电路)的对侧)ESD单元，在AA区的右上方设置有第二DO侧ESD单元；
在AA区的左下方设置有第一测试板，在AA区的右下方设置有第二测试板；
第一测试板上和第二测试板上设置有一些驱动集成电路输入信号(包括时钟信号、高电平信号VGH、低电平信号VGL等)的测试点，可用示波器等探针进行扎针测试；
在AA区的正下方依次设置有驱动集成电路和FPC(Flexible Printed Circuit，柔性电路板)。
在相关技术中，第一DO侧ESD单元、第二DO侧ESD单元、第一VGL_ESD GOA电路区域、第二VGL_ESD GOA电路区域、第一测试板、第二测试板、第一GOA电路区域和第二GOA电路区域都通过一根VGL总线(该VGL总线即提供低电平的线)来获取低电平，然而在本公开文本实施例的技术方案中，第一GOA电路区域和第二GOA电路区域需要通过VGL_GOA从驱动集成电路上的输出端子获取高电平，因此需要将VGL_GOA和VGL_ESD分离开来。
在图9中，各单元间的连接线为信号线，叉号标示之处为切断位置，本公开文本实施例中新增的信号线为第一GOA电路区域与驱动集成电路之间的信号线，以及第二GOA电路区域与驱动集成电路之间的信号线。
如图10A所示，在相关技术中，第一DO侧ESD单元与第一GOA电路区域共用VGL信号，该VGL信号都由电源端(图10A中未示出)供应；如图10B所示，在本公开文本实施例中，第一DO侧ESD单元通过静电防护低电平端VGL_ESD从所述电源端(图10B中未示出)获得低电平VGL，第一GOA电路区域通过显示用低电平端VGL_GOA从驱动集成电路的输出端(图 10B中未示)在异常掉电时获取高电平。
如图11A所示，在相关技术中，第一GOA电路区域和第一测试板都通过电源端(图11A中未示出)获取VGL信号。而在本公开文本实施例中，如图11B所示，第一GOA电路区域通过显示用低电平端VGL_GOA从驱动集成电路的输出端(图11B中未示出)在异常掉电时获取高电平，第一测试板仍然通过静电防护低电平端VGL_ESD从电源端(图11B中未示出)获取VGL信号。
以上所述是本公开文本的优选实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本公开文本所述原理的前提下，还可以作出若干改进和润饰，这些改进和润饰也应视为本公开文本的保护范围。

Claims (15)

  1. 一种快速放电电路，应用于显示装置，其中，所述快速放电电路包括放电单元；
    所述放电单元的控制端与驱动集成电路连接，所述放电单元的第一端与所述显示装置包括的栅线连接，所述放电单元的第二端与所述显示装置中的显示电平端连接；所述显示电平端与所述驱动集成电路连接；
    所述放电单元用于在所述显示装置异常掉电时控制所述显示电平端将第一电平写入所述栅线。
  2. 如权利要求1所述的快速放电电路，其中，所述放电单元包括放电晶体管；
    所述放电晶体管的栅极与所述驱动集成电路连接，所述放电晶体管的第一极与所述栅线连接，所述放电晶体管的第二极与所述显示电平端连接。
  3. 一种显示装置，包括多行栅线、多列数据线、数据开关和驱动集成电路，所述驱动集成电路包括数据电压提供单元，所述数据开关的第一端与所述数据电压提供单元连接，所述数据开关的第二端与所述数据线连接，其中，所述显示装置还包括如权利要求1或2所述的快速放电电路；
    所述驱动集成电路还包括判断单元、电位控制单元和数据线控制单元；所述数据开关的控制端与所述数据线控制单元连接；
    所述判断单元用于当判断到所述显示装置异常掉电时输出异常掉电指示信号；
    所述电位控制单元分别与所述判断单元、所述放电单元的控制端和所述显示电平端连接，用于当接收到所述异常掉电指示信号时向所述放电单元的控制端输出放电控制信号，并控制所述显示电平端的电位为第一电平；
    所述数据线控制单元分别与所述判断单元、所述数据开关的控制端和所述数据电压提供单元连接，用于当接收到来自所述判断单元的异常掉电指示信号时控制所述数据开关以使得所述数据电压提供单元将预定放电电平写入所述数据线；
    所述放电单元用于当其控制端接收到所述放电控制信号时控制所述显示 电平端将第一电平写入所述栅线。
  4. 如权利要求3所述的显示装置，其中，当像素区域中的栅极与所述栅线连接的薄膜晶体管为n型晶体管时，所述第一电平为高电平；
    当像素区域中的栅极与所述栅线连接的薄膜晶体管为p型晶体管时，所述第一电平为低电平。
  5. 如权利要求3所述的显示装置，其中，当所述放电单元包括放电晶体管时，所述放电晶体管的栅极与所述电位控制单元连接，所述放电晶体管的第一极与所述栅线连接，所述放电晶体管的第二极与所述显示电平端连接。
    所述电位控制单元还用于在未接收到所述异常掉电指示信号时，在触控时间段控制所述放电晶体管导通，并控制所述显示电平端将第二电平写入所述栅线。
  6. 如权利要求5所述的显示装置，其中，当像素区域中的栅极与所述栅线连接的薄膜晶体管为n型晶体管时，所述第二电平为低电平；
    当像素区域中的栅极与所述栅线连接的薄膜晶体管为p型晶体管时，所述第二电平为高电平。
  7. 如权利要求5所述的显示装置，其中，所述显示电平端为显示用低电平端；所述显示用低电平端与所述显示装置中的应用于静电防护电路中的静电防护用低电平端之间不导通。
  8. 如权利要求6所述的显示装置，其中，所述显示装置还包括栅极驱动电路；所述栅极驱动电路与起始信号输入端、时钟信号输入端、第一扫描电压输出端和第二扫描电压输出端连接；
    所述放电单元还分别与所述起始信号输入端、所述时钟信号输入端、所述第一扫描电压输出端和所述第二扫描电压输出端连接，还用于在接收到所述异常掉电指示信号时控制所述起始信号输入端、所述时钟信号输入端、所述第一扫描电压输出端和所述第二扫描电压输出端都接入第三电平，以控制所述栅极驱动电路正常工作。
  9. 如权利要求3所述的显示装置，其中，所述数据电压提供单元为设置于所述驱动集成电路中的数据驱动电路，所述判断单元为设置于所述驱动集成电路中的比较器，所述电位控制单元为设置于所述驱动集成电路中的寄存 器，所述数据线控制单元为设置于所述驱动集成电路中的控制器。
  10. 如权利要求3所述的显示装置，其中，所述预定放电电平为地电平。
  11. 一种快速放电方法，应用于如权利要求1或2所述的快速放电电路，其中，所述快速放电方法包括：在显示装置异常掉电时，放电单元控制显示电平端将第一电平写入栅线。
  12. 一种显示控制方法，应用于如权利要求3至10中任一权利要求所述的显示装置，其中，所述显示控制方法包括：
    当判断单元判断到显示装置异常掉电时，判断单元向电位控制单元和数据线控制单元输出异常掉电指示信号；
    当数据线控制单元接收到所述异常掉电指示信号时，所述数据线控制单元控制所述数据开关以使得所述数据电压提供单元将预定放电电平写入数据线；当电位控制单元接收到所述异常掉电指示信号时，所述电位控制单元向放电单元的控制端输出放电控制信号，并控制显示电平端的电位为第一电平；
    当所述放电单元的控制端接收到所述放电控制信号时，所述放电单元控制所述显示电平端将第一电平写入栅线，以控制像素区域内栅极与该栅线连接的薄膜晶体管打开；
    像素电极上的残留电荷通过打开的薄膜晶体管释放至所述数据线。
  13. 如权利要求12所述的显示控制方法，其中，当所述放电单元包括放电晶体管，所述放电晶体管的栅极与所述电位控制单元连接，所述放电晶体管的第一极与相应行栅线连接，所述放电晶体管的第二极与所述显示电平端连接时，所述显示控制方法还包括：
    在所述电位控制单元未接收到所述异常掉电指示信号时，在触控时间段，所述电位控制单元控制所述放电晶体管导通，并控制所述显示电平端将第二电平写入所述栅线。
  14. 如权利要求12所述的显示控制方法，其中，当所述显示装置中的显示电平端为显示用低电平端时，所述显示控制方法还包括：
    控制将显示用低电平端和所述显示装置中的静电防护用低电平端分离，以使得所述显示用低电平端和静电防护用低电平端不连接。
  15. 如权利要求12所述的显示控制方法，其中，所述预定放电电平为地 电平。
PCT/CN2017/104161 2017-03-23 2017-09-29 快速放电电路、显示装置、快速放电方法和显示控制方法 WO2018171160A1 (zh)

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