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WO2018171368A1 - 多晶硅薄膜及其制作方法、薄膜晶体管及其制作方法 - Google Patents

多晶硅薄膜及其制作方法、薄膜晶体管及其制作方法 Download PDF

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Publication number
WO2018171368A1
WO2018171368A1 PCT/CN2018/076760 CN2018076760W WO2018171368A1 WO 2018171368 A1 WO2018171368 A1 WO 2018171368A1 CN 2018076760 W CN2018076760 W CN 2018076760W WO 2018171368 A1 WO2018171368 A1 WO 2018171368A1
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layer
substrate
film layer
polysilicon film
amorphous silicon
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French (fr)
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刘军
苏同上
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BOE Technology Group Co Ltd
Hefei Xinsheng Optoelectronics Technology Co Ltd
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BOE Technology Group Co Ltd
Hefei Xinsheng Optoelectronics Technology Co Ltd
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Definitions

  • the present disclosure relates to the field of display, and in particular to a polysilicon film and a method of fabricating the same, a thin film transistor, and a method
  • Poly-silicon has attracted much attention in the thin film transistor manufacturing industry, especially in the application of thin film transistor-driven displays, because of its superior electrical properties over amorphous silicon and lower cost advantages than single crystal silicon.
  • polycrystalline silicon thin films are generally fabricated by Excimer Laser Anneal (ELA) technology, but this method has disadvantages such as expensive preparation equipment, poor uniformity of the formed polysilicon film layer, complicated manufacturing process, etc., resulting in an increase in production cost, and When a completed polycrystalline silicon film is applied to a thin film transistor, problems such as low performance of the thin film transistor are caused.
  • ELA Excimer Laser Anneal
  • the method for fabricating a polysilicon film provided by the embodiment of the present disclosure, the polysilicon film is applied to a thin film transistor; wherein the manufacturing method comprises:
  • the manufacturing method after the forming the buffer layer, before the forming the amorphous silicon film layer, the manufacturing method further includes:
  • a metal diffusion layer on a side of the buffer layer facing away from the substrate substrate; wherein the metal diffusion layer is diffused from a metal atom of the metal layer to the buffer layer facing away from the liner One side of the base substrate is formed;
  • the catalyzing effect of the metal atom on the amorphous silicon film layer, converting the amorphous silicon film layer into a polysilicon film layer specifically comprising:
  • the amorphous silicon film layer is converted into a polysilicon film layer by catalytic action of the metal diffusion layer by a second annealing process.
  • the forming the amorphous silicon film layer specifically includes:
  • the orthographic projection of the underlying substrate overlaps with the orthographic projection of the pattern of the amorphous silicon film layer on the underlying substrate.
  • the forming the metal layer specifically includes:
  • the catalytic effect of the metal atom on the amorphous silicon film layer converts the amorphous silicon film layer into a polysilicon film layer.
  • the metal atom on the amorphous silicon film layer converts the amorphous silicon film layer into a polysilicon film layer.
  • a third annealing process is performed to diffuse metal atoms of the metal layer to the amorphous silicon film layer, and convert the amorphous silicon film layer into a polysilicon film layer by catalytic action of the metal atoms diffused thereto.
  • the manufacturing method after the converting the amorphous silicon film layer into the polysilicon film layer, the manufacturing method further includes:
  • the surface of the polysilicon film layer facing away from the buffer layer is treated to remove a portion of the film of the polysilicon film layer facing away from the buffer layer.
  • the manufacturing method before the forming the metal layer, the manufacturing method further includes:
  • a barrier layer is formed on the base substrate.
  • an embodiment of the present disclosure further provides a method for fabricating a thin film transistor, including:
  • a patterned polysilicon film is formed on a substrate
  • a source and drain insulating layer having a first via and a second via on a side of the gate facing away from the substrate; wherein an orthographic projection of a pattern of the polysilicon film layer on the substrate Covering an orthographic projection of the first via and the second via in the substrate; an orthographic projection of the first via and the second via in the substrate and the gate The pattern of the poles does not overlap in the orthographic projection of the substrate;
  • embodiments of the present disclosure further provide a polysilicon film, including:
  • a metal layer disposed on one side of the substrate
  • a polysilicon film layer disposed on a side of the buffer layer facing away from the substrate substrate; wherein the polysilicon film layer is fabricated by the method for fabricating the polysilicon film according to any one of claims 1-7.
  • embodiments of the present disclosure further provide a thin film transistor, including:
  • polysilicon film disposed on a side of the substrate; wherein the polysilicon film is a polysilicon film provided by the embodiments of the present disclosure;
  • a source/drain insulating layer disposed on a side of the gate electrode facing away from the substrate substrate and having a first via hole and a second via hole; wherein the pattern of the polysilicon film layer is orthographically projected on the substrate substrate Covering an orthographic projection of the first via and the second via in the substrate; an orthographic projection of the first via and the second via in the substrate and the gate The pattern of the poles does not overlap in the orthographic projection of the substrate;
  • a source and a drain disposed on a side of the source and drain insulating layer facing away from the substrate; wherein the source is connected to the polysilicon film layer through the first via, and the drain passes The second via is connected to the polysilicon film layer.
  • FIG. 1 is a flow chart of a method for fabricating a polysilicon film according to an embodiment of the present disclosure
  • FIG. 2 is a schematic structural view of forming a barrier layer on a substrate according to an embodiment of the present disclosure
  • FIG. 3 is a schematic structural view of forming a metal layer on a barrier layer according to an embodiment of the present disclosure
  • FIG. 4 is a schematic structural view of forming a buffer layer on an amorphous silicon film layer according to an embodiment of the present disclosure
  • FIG. 5 is a schematic structural diagram of forming a metal diffusion layer on a buffer layer according to an embodiment of the present disclosure
  • FIG. 6 is a schematic structural view of forming an amorphous silicon film on a metal diffusion layer according to an embodiment of the present disclosure
  • FIG. 7 is a schematic structural diagram of forming a patterned amorphous silicon film layer according to an embodiment of the present disclosure.
  • FIG. 8 is a schematic structural diagram of converting an amorphous silicon film layer into a polysilicon film layer according to an embodiment of the present disclosure
  • FIG. 9 is a schematic structural diagram of a portion of a film on a side of a polysilicon film layer facing away from a buffer layer according to an embodiment of the present disclosure
  • FIG. 10 is a schematic structural diagram of a thin film transistor according to an embodiment of the present disclosure.
  • the material generally used for the active layer of the thin film transistor is mainly silicon, and includes, for example, amorphous silicon, polycrystalline silicon, microcrystalline silicon, and the like.
  • Polycrystalline silicon has gained much attention in the thin film transistor manufacturing industry because it has superior electrical properties over amorphous silicon and lower cost advantages than single crystal silicon.
  • metal-induced amorphous silicon crystallization (MIC) technology can produce high-performance polysilicon film at low temperature, which has obvious advantages compared with other low-temperature polysilicon technologies.
  • the method of fabricating a polycrystalline silicon film by using MIC technology is generally to first form an amorphous silicon film, and then deposit a metal isolation layer and a metal layer on the amorphous silicon film in order to allow metal atoms of the metal layer to diffuse through the metal isolation layer to The amorphous silicon film is then annealed to form an amorphous silicon film containing metal atoms to convert the amorphous silicon film containing metal atoms into a polysilicon film during the annealing process.
  • the metal atom in the metal layer is generally used as a catalyst to convert the amorphous silicon film layer into a polysilicon film layer under the catalytic action of metal atoms. Since a metal isolation layer is further formed between the metal layer and the amorphous silicon film layer, in order to enable the metal atom of the metal layer to catalyze the amorphous silicon film layer, the metal layer needs to be heated to some extent. The metal atoms in the metal layer can be diffused so that the diffused metal atoms are in contact with the amorphous silicon film layer.
  • the embodiments of the present disclosure provide a method for fabricating a polysilicon film that can be applied to a thin film transistor, which not only does not require additional fabrication of a metal isolation layer, but also eliminates a metal isolation layer and a metal layer removal process, thereby reducing production costs. Simplify the process steps.
  • a method for fabricating a polysilicon film applied in a thin film transistor may include the following steps:
  • a metal layer is formed on one side of the base substrate.
  • a metal layer having a thickness of one nanometer to several hundred nanometers may be formed on a substrate by a process such as sputtering or plasma enhanced chemical vapor deposition (PECVD).
  • the prepared metal layer may have a thickness of 10 nm, 50 nm or 100 nm.
  • the material of the metal may include any one of Ni, Au, Cu, Pd, Co, and Ag.
  • the base substrate in the embodiment of the present disclosure may specifically be a glass substrate.
  • the substrate of the other material may be used as the substrate, which is not limited herein.
  • the manufacturing method may further include: forming a barrier layer on the base substrate.
  • a barrier layer having a thickness of several tens of nanometers to several hundreds of nanometers may be prepared on a base substrate by a process such as PECVD or Low Pressure Chemical Vapor Deposition (LPCVD).
  • the prepared barrier layer may have a thickness of 10 nm, 50 nm or 100 nm.
  • the material of the barrier layer may include a compound of silicon and nitrogen.
  • the material of the barrier layer may specifically include SiNx.
  • a buffer layer having a thickness of several tens of nanometers to several hundreds of nanometers may be prepared on the metal layer by a process such as PECVD or LPCVD.
  • the prepared buffer layer may have a thickness of 10 nm, 50 nm or 100 nm.
  • the buffer layer is generally a buffer layer commonly used in thin film transistors, and in the embodiment of the present disclosure, the buffer layer is not only used as a buffer layer commonly used in thin film transistors, but also can be used when metal atoms in a metal layer are diffused.
  • the amount of metal atoms diffused to the upper amorphous silicon film layer is controlled, that is, a buffer layer is provided between the amorphous silicon film layer and the metal layer, and the metal atoms in the metal layer can be prevented from excessively diffusing to the amorphous silicon. Further, in the film layer, it is possible to prevent the formed thin film transistor from having a large leakage current due to the inclusion of a large number of metal atoms.
  • the material of the specific buffer layer may include a compound of silicon and oxygen, for example, specifically, SiOx.
  • an amorphous silicon film layer having a thickness of 10 nm to 100 nm may be deposited on the buffer layer by a process such as PECVD or LPCVD.
  • the prepared amorphous silicon film layer may be 50 nm.
  • the polysilicon film layer to which the amorphous silicon film layer is converted is generally used as an active layer in a thin film transistor.
  • the method for fabricating a polysilicon film for use in a thin film transistor after sequentially forming a metal layer, a buffer layer, and an amorphous silicon film layer on a substrate, the metal atoms in the metal layer can be diffused by Contact with the amorphous silicon film layer, so that the amorphous silicon film layer can be converted into a polysilicon film layer under the catalytic action of metal atoms. Since the buffer layer existing in the fabricated thin film transistor is used in place of the metal isolation layer in the related art when the amorphous silicon film layer is converted into the polysilicon film layer, it is not necessary to separately form the metal isolation layer. Also, since the buffer layer and the metal layer are prepared before the formation of the amorphous silicon film layer, the process of removing the metal layer and the buffer layer can also be omitted. In turn, the production cost can be reduced and the process steps can be simplified.
  • the metal atom is generally used as a catalyst to convert the amorphous silicon film layer into a polysilicon film layer under the catalytic action of metal atoms.
  • the metal atom In order to form a buffer layer between the metal layer and the amorphous silicon film layer, in order to enable the metal atom of the metal layer to catalyze the amorphous silicon film layer, it is necessary to heat the metal layer to a certain extent.
  • the metal atoms in the metal layer can be diffused and brought into contact with the amorphous silicon film layer.
  • the amorphous silicon film layer can be converted into a polysilicon film layer through different process steps. The following is a specific example.
  • the manufacturing method of the embodiment of the present disclosure forms an amorphous silicon film layer on the buffer layer after forming the buffer layer.
  • the method further includes: forming, by the first annealing process, a metal diffusion layer on a side of the buffer layer facing away from the substrate, wherein the metal diffusion layer is formed by diffusion of metal atoms of the metal layer to a side of the buffer layer facing away from the substrate .
  • the conversion of the amorphous silicon film layer into the polysilicon film layer by the catalytic action of the metal atom on the amorphous silicon film layer may specifically include: using a second annealing process to pass the catalytic effect of the amorphous silicon film layer through the metal diffusion layer Converted to a polysilicon film layer.
  • defects on the surface of the film are relatively large in the interior, and since metal atoms generally diffuse into a region having many defects, metal atoms diffuse toward the surface of the buffer layer to form a metal diffusion layer.
  • the metal diffusion layer is formed on the buffer layer by the first annealing process
  • an amorphous silicon film layer is formed on the side of the metal diffusion layer facing away from the substrate, and the amorphous silicon film layer is formed on the metal by the second annealing process.
  • the metal atoms in the diffusion layer are converted into a polysilicon film layer by the catalytic action.
  • the first annealing process may be an annealing process under a condition that the temperature is lower than 600 ° C and the duration is the first preset duration
  • the second annealing process may be at a temperature lower than 600 ° C and the duration is the second preset duration.
  • the annealing process under the conditions.
  • the first preset duration and the second preset duration need to be determined according to the actual application environment, which is not limited herein.
  • the one-step annealing process can also be realized, that is, after the buffer layer is formed on the metal layer, the amorphous silicon is directly formed on the buffer layer.
  • the film layer can diffuse metal atoms in the metal layer into the amorphous silicon film layer through a long annealing process, that is, using a third annealing process, and diffuse the amorphous silicon film layer into the film layer.
  • the metal atom is converted into a polysilicon film by the catalytic action of the metal atom.
  • the third annealing process may be an annealing process under the condition that the temperature is lower than 600 ° C and the duration is the third predetermined duration. Moreover, the third preset duration is greater than the first preset duration and is also greater than the second preset duration, that is, the duration of the third annealing process is longer than the first annealing process and the second annealing process. In the actual application, the third preset duration needs to be determined according to the actual application environment, which is not limited herein.
  • the polysilicon film layer when the polysilicon film layer is formed, can be directly formed into a patterned polysilicon film layer, that is, the polysilicon film layer is directly provided with a pattern of an active layer.
  • a polysilicon film is formed only in a channel region of a thin film transistor, and an amorphous silicon film layer is converted into a polysilicon film layer by a double annealing process, and a patterned polysilicon film layer may be formed after the first annealing process.
  • amorphous silicon film Forming an amorphous silicon film on a side of the metal diffusion layer facing away from the substrate; afterwards, using a dry etching process, the amorphous silicon film is patterned into an amorphous silicon film layer, that is, the amorphous silicon film layer is directly formed A pattern having an active layer.
  • a suitable over-etch ratio may be selected while removing the metal diffusion layer in other regions than the first region, wherein the first region corresponds to the thin film transistor
  • the channel region, other than the first region corresponds to a non-channel region of the thin film transistor.
  • the metal atoms in the metal layer diffuse above the buffer layer, they may also diffuse to the corresponding regions of the non-channel region, and when the amorphous silicon thin film layer is patterned, the metal diffusion layer is simultaneously removed except the first region.
  • the thin film of other regions can reduce the influence of the metal atoms of the metal layer on the thin film transistor formed by the polysilicon film due to diffusion into the non-channel region. That is, the influence of the metal atoms of the metal layer on the thin film transistor formed by the polysilicon film due to diffusion into the non-channel region can be reduced without increasing the number of fabrication steps.
  • the overetch ratio may be further etched down in the case of removing the amorphous silicon film layer of the non-channel region to remove the metal diffusion layer in the corresponding non-channel region under the amorphous silicon film layer.
  • the etching time may be appropriately extended to 40 min to etch away the metal diffusion layer corresponding to the non-channel region.
  • the above is only exemplified by 30 min and 40 min, and the disclosure is not limited thereto.
  • a mixed gas of a fluorine-based gas and a chlorine-based gas may be used for etching.
  • the metal layer is formed in the embodiment of the present disclosure, and specifically may include: on one side of the substrate Forming a patterned metal layer; wherein the orthographic projection of the pattern of the metal layer on the substrate substrate overlaps with the orthographic projection of the pattern of the amorphous silicon film layer on the substrate substrate. This can leave only the metal layer in the region corresponding to the channel region to diffuse the metal atoms in the metal layer in the region.
  • the metal atoms diffused from the metal layer may be concentrated on the surface of the polysilicon film layer facing away from the buffer layer, so that the surface of the polysilicon film layer facing away from the buffer layer may be processed to remove the polysilicon film layer.
  • a part of the film facing away from the buffer layer can further reduce the problem of high leakage current of the thin film transistor formed of the polysilicon film.
  • the manufacturing method may further include: processing the surface of the polysilicon film layer facing away from the buffer layer, and removing the polysilicon film layer away from the buffer layer. Part of the film on the side.
  • the surface of the polysilicon film layer facing away from the buffer layer may be etched by a dry etching process to remove a portion of the surface film layer enriched in metal atoms in the polysilicon film layer.
  • a dry etching process to remove a portion of the surface film layer enriched in metal atoms in the polysilicon film layer.
  • an ICP (Inductively Coupled Plasma) device can be used, in a CF 4 and O 2 or Cl 2 and O 2 atmosphere, and the source power is the first preset power.
  • the surface of the polysilicon film layer is etched under the condition that the lower electrode bias power (Bias Power) is the second preset power.
  • the first preset power is high power according to the requirements of the actual manufacturing method.
  • the second predetermined power may be made low power or zero power.
  • the method for preparing the polysilicon film in the thin film transistor provided by the embodiment of the present disclosure is specifically described below with reference to FIG. 2 to FIG. It can include the following steps:
  • a 50 nm thick SiNx film layer is deposited as a barrier layer 2 on the base substrate 1 by a plasma chemical vapor deposition process.
  • the base substrate 1 may be a glass substrate, and the SiNx film layer may be used to block alkali metal ions in the glass substrate, for example, Na ions or K ions.
  • a schematic view of the barrier layer 2 formed on the base substrate 1 is shown in FIG.
  • a 50 nm thick patterned Ni metal layer 3 is formed on the barrier layer 2 by a sputtering process and using a mask conforming to the pattern of the polysilicon film layer formed later.
  • the pattern of the polysilicon film layer formed later corresponds to the channel region in the thin film transistor.
  • the orthographic projection of the pattern of the Ni metal layer 3 on the underlying substrate overlaps with the orthographic projection of the pattern of the polysilicon film layer on the underlying substrate.
  • a 50 nm thick SiOx film is deposited on the Ni metal layer 3 as a buffer layer 4 by a plasma chemical vapor deposition process, and the SiOx film is used to control the amount of metal entering the polysilicon film.
  • a schematic view of the buffer layer 4 formed on the Ni metal layer 3 is shown in FIG.
  • Step 4 annealing is performed under the condition that the temperature is 500 ° C and the duration is the first predetermined period of time, and the metal atoms in the Ni metal layer 3 are diffused to the upper surface of the SiOx buffer layer 4, and the surface of the buffer layer 4 is formed by diffusion.
  • a metal diffusion layer 5 composed of metal atoms.
  • a schematic view of the metal diffusion layer 5 formed on the buffer layer 4 is shown in FIG.
  • step five a 50 nm thick amorphous silicon film 60 is deposited on the metal diffusion layer 5 by plasma chemical vapor deposition.
  • a schematic view of the amorphous silicon film 60 formed on the metal diffusion layer 5 is shown in FIG.
  • Step 6 forming a patterned photoresist layer (not shown) on the amorphous silicon film 60, and using a dry etching process, under the shielding of the patterned photoresist layer, in the fluorine gas and
  • the amorphous silicon film 60 is etched in an atmosphere of a mixed gas of chlorine gas to form a patterned amorphous silicon film layer 6, which is converted into a polysilicon film layer after being subjected to crystallization treatment. It can be used as an active layer of a thin film transistor.
  • the overetch ratio can be appropriately increased, and when the patterned amorphous silicon film layer 6 is formed, the metal diffusion layer 5 in the corresponding region of the non-channel region is simultaneously removed.
  • a schematic view after forming the patterned amorphous silicon film layer 6 is shown in FIG.
  • step 7 the annealing is performed under the condition that the temperature is 500 ° C and the duration is the second predetermined period of time, so that the amorphous silicon film layer 6 is converted into the polysilicon film layer 7 under the catalytic action of the metal atoms of the metal diffusion layer.
  • the polysilicon film layer 7 may include a first film layer 7a containing more metal atoms on the side facing away from the buffer layer 4 and a second film containing less or no metal atoms in the error tolerance range.
  • Layer 7b A schematic diagram after converting the amorphous silicon film layer 6 into the polysilicon film 7 is shown in FIG.
  • Step 8 dry etching the surface of the polysilicon film layer 7 by using the ICP device in a mixed gas atmosphere of CF 4 and O 2 with Source Power as the first preset power and Bias Power as the second preset power.
  • the etching treatment is performed to remove a portion of the film of the surface of the polysilicon film layer 7 facing away from the buffer layer 4, that is, the first film layer 7a, while leaving the second film layer 7b.
  • a schematic view after removing the first film layer 7a is shown in FIG.
  • an embodiment of the present disclosure further provides a method for fabricating a thin film transistor, comprising forming a patterned polysilicon film on a substrate by using a method for fabricating a polysilicon film in a thin film transistor provided by an embodiment of the present disclosure.
  • the principle of the method for fabricating the thin film transistor is similar to the method for fabricating the polysilicon film. Therefore, the implementation of the method for fabricating the thin film transistor can be referred to the implementation of the method for fabricating the polysilicon film, and the repeated description is omitted here.
  • the manufacturing method of the thin film transistor further includes a manufacturing step of forming another film layer.
  • the manufacturing step of the thin film transistor may further include the following steps:
  • Step 1 A gate insulating layer 8 and a patterned gate electrode 9 are sequentially formed on the side of the polysilicon film layer 7 facing away from the substrate 1 .
  • the pattern of the polysilicon film layer 7 is orthographically projected on the substrate substrate 1 to cover the orthographic projection of the pattern of the gate electrode 9 on the substrate substrate 1.
  • a gate insulating layer 8 is formed on the polysilicon film layer 7, and a gate electrode 9 is formed on the gate insulating layer 8.
  • the polysilicon film layer 7 herein may refer to a polysilicon film layer after removing a portion of the film from the surface on the side of the buffer layer 4.
  • Step 2 forming a source/drain insulating layer 10 having a first via 13 and a second via 14 on a side of the gate 9 facing away from the substrate 1.
  • the orthographic projection of the pattern of the polysilicon film layer 7 on the substrate substrate 1 covers the front projection of the first via hole 13 and the second via hole 14 in the substrate substrate 1; 1 the first via hole 13 and the second via hole 14
  • the orthographic projection of the substrate 1 and the pattern of the gate 9 do not overlap the orthographic projection of the substrate 1.
  • Step 3 forming a source 11 and a drain 12 on a side of the source/drain insulating layer 10 facing away from the substrate 1; wherein the source 11 is in contact with the polysilicon layer 7 through the first via 13, and the drain 12 The second via hole 14 is in contact with the polysilicon film layer 7.
  • an embodiment of the present disclosure further provides a polysilicon film applied to a thin film transistor, and referring to FIG. 9, may include: a metal layer 3 disposed on one side of the substrate substrate 1; and disposed on the metal layer 3 away from the liner a buffer layer 4 on one side of the base substrate 1; a polysilicon film layer 7 disposed on a side of the buffer layer 4 facing away from the substrate substrate (the polysilicon film layer 7 may be referred to as a second film after removing a surface portion of the film facing away from the buffer layer side) The layer 7b), wherein the polysilicon film layer 7 is fabricated by the method for fabricating the above polysilicon film provided by the embodiments of the present disclosure.
  • the principle of solving the problem of the polysilicon film is similar to the method for fabricating the polysilicon film. Therefore, the implementation of the polysilicon film can be referred to the implementation of the method for fabricating the polysilicon film, and the repeated description is omitted here.
  • the embodiment of the present disclosure further provides a thin film transistor.
  • the principle of solving the problem is similar to the method for fabricating the thin film transistor. Therefore, the implementation of the thin film transistor can be implemented by referring to the implementation of the method for fabricating the thin film transistor. I will not go into details here.
  • the thin film transistor provided by the embodiment of the present disclosure may specifically include: a polysilicon film 7 disposed on one side of the substrate 1; wherein the polysilicon film 7 is a polysilicon film provided by the embodiment of the present disclosure.
  • a gate insulating layer 8 on the side of the polysilicon film layer 7 facing away from the substrate 1 and a patterned gate electrode 9 are sequentially disposed; wherein the pattern of the polysilicon film layer 7 covers the gate electrode 9 in the orthographic projection of the substrate substrate 1 An orthographic projection of the pattern on the base substrate 1.
  • the polysilicon film layer 7 may refer to the second film layer 7b after the partial film (i.e., the first film layer 7a) facing away from the surface of the buffer layer is removed.
  • a source/drain insulating layer 10 disposed on a side of the gate electrode 9 facing away from the substrate substrate 1 and having a first via hole 13 and a second via hole 14; wherein the pattern of the polysilicon film layer 7 is covered by the orthographic projection of the substrate substrate 1
  • the orthographic projections do not overlap.
  • a source 11 and a drain 12 disposed on a side of the source/drain insulating layer 10 facing away from the substrate 1; wherein the source 11 is connected to the polysilicon layer 7 through the first via 13, and the drain 12 passes through the second pass.
  • the hole 14 is connected to the polysilicon film layer 7.
  • the present disclosure allows metal atoms in the metal layer to be contacted with the amorphous silicon film layer by diffusion after sequentially forming a metal layer, a buffer layer, and an amorphous silicon film layer on the substrate.
  • the crystalline silicon film layer can be converted into a polysilicon film layer under the catalytic action of metal atoms. Since the buffer layer existing in the fabricated thin film transistor is used in place of the metal isolation layer in the related art when the amorphous silicon film layer is converted into the polysilicon film layer, it is not necessary to separately form the metal isolation layer. Also, since the buffer layer and the metal layer are prepared before the formation of the amorphous silicon film layer, the process of removing the metal layer and the buffer layer can also be omitted. In turn, the production cost can be reduced and the process steps can be simplified.

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Abstract

多晶硅薄膜及其制作方法、薄膜晶体管及其制作方法，通过在衬底基板（1）上依次形成金属层（3）、缓冲层（4）、非晶硅膜层（6），使金属层（3）中的金属原子可以通过扩散以与非晶硅膜层（6）进行接触，使非晶硅膜层（6）在金属原子的催化作用下可以转化为多晶硅膜层（7）。可以不需要单独制作金属隔离层，且省略去除金属层和缓冲层的工艺。

Description

多晶硅薄膜及其制作方法、薄膜晶体管及其制作方法
本公开要求在2017年3月22日提交中国专利局、公开号为201710172988.3、公开名称为“一种薄膜晶体管中的多晶硅薄膜、薄膜晶体管及制作方法”的中国专利公开的优先权，其全部内容通过引用结合在本公开中。
技术领域
本公开涉及显示领域，尤其涉及多晶硅薄膜及其制作方法、薄膜晶体管及其制作方法。
背景技术
多晶硅(poly-silicon)因其具有优于非晶硅的电气特性，以及低于单晶硅的成本优势，从而在薄膜晶体管制造业中，尤其是在薄膜晶体管驱动显示器的应用上广受重视。目前，一般采用准分子激光回火(Excimer Laser Anneal，ELA)技术制作多晶硅薄膜，但此方法存在制备设备昂贵，形成的多晶硅膜层均一性差，制作过程复杂等缺点，从而导致生产成本增加，以及将制作完成的多晶硅薄膜应用于薄膜晶体管时，导致薄膜晶体管的性能低等问题。
发明内容
本公开实施例提供的多晶硅薄膜的制作方法，所述多晶硅薄膜应用于薄膜晶体管中；其中，所述制作方法包括：
在衬底基板一侧形成金属层；
在所述金属层背离所述衬底基板的一侧形成缓冲层；
在所述缓冲层背离所述衬底基板的一侧形成非晶硅膜层；
通过金属原子对所述非晶硅膜层的催化作用，将所述非晶硅膜层转化为多晶硅膜层；其中，所述金属原子为所述金属层扩散的并与所述非晶硅膜层接触的金属原子。
在一些可能的实施方式中，在本公开实施例提供的制作方法中，在所述形成缓冲层之后，在所述形成非晶硅膜层之前，所述制作方法还包括：
采用第一退火工艺，在所述缓冲层背离所述衬底基板的一侧形成金属扩散层；其中，所述金属扩散层由所述金属层的金属原子扩散到所述缓冲层背离所述衬底基板的一侧形成；
所述通过金属原子对所述非晶硅膜层的催化作用，将所述非晶硅膜层转化为多晶硅膜层，具体包括：
采用第二退火工艺，使所述非晶硅膜层通过所述金属扩散层的催化作用转化为多晶硅膜层。
在一些可能的实施方式中，在本公开实施例提供的制作方法中，所述形成非晶硅膜层，具体包括：
在所述金属扩散层背离所述衬底基板一侧形成非晶硅薄膜；
采用干法刻蚀工艺，使所述非晶硅薄膜形成图案化的非晶硅膜层，并去除除第一区域以外的其余区域中的金属扩散层；其中，所述第一区域在所述衬底基板的正投影与所述非晶硅膜层的图案在所述衬底基板的正投影重叠。
在一些可能的实施方式中，在本公开实施例提供的制作方法中，所述形成金属层，具体包括：
在所述衬底基板的一侧形成图案化的金属层；其中，所述金属层的图案在所述衬底基板的正投影与所述非晶硅膜层的图案在所述衬底基板的正投影重叠。
在一些可能的实施方式中，在本公开实施例提供的制作方法中，所述通过金属原子对所述非晶硅膜层的催化作用，将所述非晶硅膜层转化为多晶硅膜层，具体包括：
采用第三退火工艺，使所述金属层的金属原子扩散到所述非晶硅膜层，并使所述非晶硅膜层通过扩散到的金属原子的催化作用转化为多晶硅膜层。
在一些可能的实施方式中，在本公开实施例提供的制作方法中，在所述将所述非晶硅膜层转化为多晶硅膜层之后，所述制作方法还包括：
对所述多晶硅膜层背离所述缓冲层一侧的表面进行处理，去除所述多晶硅膜层背离所述缓冲层一侧的部分薄膜。
在一些可能的实施方式中，在本公开实施例提供的制作方法中，在所述形成金属层之前，所述制作方法还包括：
在所述衬底基板上形成阻挡层。
相应地，本公开实施例还提供了薄膜晶体管的制作方法，其中，包括：
采用本公开实施例提供的多晶硅薄膜的制作方法，在衬底基板上形成图案化的多晶硅薄膜；
在所述多晶硅膜层背离所述衬底基板的一侧依次形成栅极绝缘层与图案化的栅极；其中，所述多晶硅膜层的图案在所述衬底基板的正投影覆盖所述栅极的图案在所述衬底基板的正投影；
在所述栅极背离所述衬底基板的一侧形成具有第一过孔和第二过孔的源漏极绝缘层；其中，所述多晶硅膜层的图案在所述衬底基板的正投影覆盖所述第一过孔和所述第二过孔在所述衬底基板的正投影；所述第一过孔和所述第二过孔在所述衬底基板的正投影与所述栅极的图案在所述衬底基板的正投影无交叠；
在所述源漏极绝缘层背离所述衬底基板的一侧形成源极和漏极；其中，所述源极通过所述第一过孔与所述多晶硅膜层连接，所述漏极通过所述第二过孔与所述多晶硅膜层连接。
相应地，本公开实施例还提供了多晶硅薄膜，其中，包括：
设置在衬底基板一侧的金属层；
设置在所述金属层背离所述衬底基板一侧的缓冲层；
设置在所述缓冲层背离所述衬底基板一侧的多晶硅膜层；其中，所述多晶硅膜层采用如权利要求1-7任一项所述的多晶硅薄膜的制作方法制作而成。
相应地，本公开实施例还提供了薄膜晶体管，其中，包括：
设置在衬底基板一侧的多晶硅薄膜；其中，所述多晶硅薄膜为本公开实施例提供的多晶硅薄膜；
依次设置在所述多晶硅薄膜背离所述衬底基板一侧的栅极绝缘层和图案化的栅极；其中，所述多晶硅膜层的图案在所述衬底基板的正投影覆盖所述栅极的图案在所述衬底基板的正投影；
设置在所述栅极背离所述衬底基板一侧且具有第一过孔和第二过孔的源漏极绝缘层；其中，所述多晶硅膜层的图案在所述衬底基板的正投影覆盖所述第一过孔和所述第二过孔在所述衬底基板的正投影；所述第一过孔和所述第二过孔在所述衬底基板的正投影与所述栅极的图案在所述衬底基板的正投影无交叠；
设置在所述源漏极绝缘层背离所述衬底基板一侧的源极和漏极；其中，所述源极通过所述第一过孔与所述多晶硅膜层连接，所述漏极通过所述第二过孔与所述多晶硅膜层连接。
附图说明
图1为本公开实施例提供的多晶硅薄膜的制作方法的流程图；
图2为本公开实施例提供的在衬底基板上形成阻挡层的结构示意图；
图3为本公开实施例提供的在阻挡层上形成金属层的结构示意图；
图4为本公开实施例提供的在非晶硅膜层上形成缓冲层的结构示意图；
图5为本公开实施例提供的在缓冲层上形成金属扩散层的结构示意图；
图6为本公开实施例提供的在金属扩散层上形成非晶硅薄膜的结构示意图；
图7为本公开实施例提供的形成图案化的非晶硅膜层的结构示意图；
图8为本公开实施例提供的将非晶硅膜层转换为多晶硅膜层后的结构示意图；
图9为本公开实施例提供的去除多晶硅膜层背离缓冲层一侧的部分薄膜后的结构示意图；
图10为本公开实施例提供的薄膜晶体管的结构示意图。
具体实施方式
一般应用于制作薄膜晶体管的有源层的材料主要为硅，例如包括非晶硅、多晶硅、微晶硅等。由于多晶硅具有优于非晶硅的电气特性，以及低于单晶硅的成本优势，从而在薄膜晶体管制造业中广受重视。目前，采用金属诱导非晶硅晶化(Metal Induced Crystallization，MIC)技术可在低温工艺制备出高性能的多晶硅薄膜，与其它低温多晶硅技术相比有明显的优势。其中，采用MIC技术制作多晶硅薄膜的方法，通常是先制作非晶硅薄膜，再在非晶硅薄膜上依次沉积金属隔离层和金属层，以使金属层的金属原子可以通过金属隔离层扩散到非晶硅薄膜，之后采用退火工艺对含有金属原子的非晶硅薄膜进行退火，以将含有金属原子的非晶硅薄膜在退火工艺过程中转变为多晶硅薄膜。其中，在将非晶硅薄膜转换为多晶硅薄膜时，金属层中的金属原子一般作为催化剂，使非晶硅膜层在金属原子的催化作用下转换为多晶硅膜层。而由于在金属层与非晶硅膜层之间还形成有金属隔离层，为了能够使金属层的金属原子对非晶硅膜层起到催化的作用，通过需要将金属层进行一定程度的加热，使金属层中的金属原子能够进行扩散，以使扩散出的金属原子与非晶硅膜层接触。
但是，在上述MIC技术制作过程中，在将非晶硅薄膜转化为多晶硅薄膜时，由于需要单独制作金属隔离层，并且在将非晶硅薄膜转化为多晶硅薄膜后，还需去除金属隔离层和金属层，从而导致采用现有MIC技术由非晶硅薄膜制作成多晶硅薄膜的成本较高，工艺较为复杂。
因此，本公开实施例提供了可以应用于薄膜晶体管中的多晶硅薄膜的制作方法，不仅可以不需要额外制作金属隔离层，还可以省略金属隔离层和金属层的去除工艺，从而可以降低生产成本，简化工艺制作步骤。
下面结合说明书附图对本公开实施例的实现过程进行详细说明。需要注意的是，自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。下面通过参考附图描述的实施例是示例性的，仅用于解释本 公开，而不能理解为对本公开的限制。并且在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互组合。
参见图1，本公开实施例提供的应用于薄膜晶体管中的多晶硅薄膜的制作方法，可以包括如下步骤：
101，在衬底基板一侧形成金属层。
在具体实施时，可以通过溅射、等离子体化学气相沉积(Plasma Enhanced Chemical Vapor Deposition，PECVD)等工艺在衬底基板上制备一纳米至几百纳米(例如1nm～100nm)厚的金属层。可选地，制备的金属层的厚度可以为10nm、50nm或100nm。具体地，金属的材质可以包括Ni、Au、Cu、Pd、Co、Ag中的任意一种。
本公开实施例中的衬底基板具体可以为玻璃基板。当然，衬底基板也可以采用其它材质的基板，在此不作限定。
为了防止玻璃基板中的杂质离子(例如玻璃中的碱金属，如Na离子或K离子)进入上方膜层，对上方的膜层造成影响，可选的，在衬底基板上形成金属层之前，该制作方法还可以包括：在衬底基板上形成阻挡层。在具体实施时，可以通过PECVD或低压化学气相沉积(Low Pressure Chemical Vapor Deposition，LPCVD)等工艺，在衬底基板上制备几十纳米至几百纳米(例如：10nm～100nm)厚的阻挡层。可选地，制备的阻挡层的厚度可以为10nm、50nm或100nm。在实际应用中，阻挡层的材质可以包括硅和氮的化合物，例如，阻挡层的材质具体可以包括SiNx。
102，在金属层背离衬底基板的一侧形成缓冲层。
在具体实施时，可以通过PECVD或LPCVD等工艺在金属层上制备几十纳米至几百纳米(例如10nm～100nm)厚的缓冲层。可选地，制备的缓冲层的厚度可以为10nm、50nm或100nm。该缓冲层一般为薄膜晶体管中常用的缓冲层，并且在本公开实施例中，该缓冲层不仅作为薄膜晶体管中常用的缓冲层，还可以用于在金属层中的金属原子进行扩散时，对扩散到上方的非晶硅膜层的金属原子的量进行控制，即，在非晶硅膜层和金属层之间设置缓冲层， 可以避免金属层中的金属原子过多地扩散到非晶硅膜层中，进而可以避免形成的薄膜晶体管由于含有较多的金属原子而产生漏电流较大的问题。具体缓冲层的材质可以包括硅和氧的化合物，例如，具体可以为SiOx。
103，在缓冲层背离衬底基板的一侧形成非晶硅膜层。
在具体实施时，可以通过PECVD或LPCVD等工艺在缓冲层上沉积10nm～100nm厚的非晶硅膜层。可选地，制备的非晶硅膜层可以为50nm。应该理解的是，将该非晶硅膜层转换为的多晶硅膜层通常作为薄膜晶体管中的有源层。
104，通过金属原子对非晶硅膜层的催化作用，将非晶硅膜层转化为多晶硅膜层，其中，金属原子为金属层扩散的并与非晶硅膜层接触的金属原子。
本公开实施例提供的应用于薄膜晶体管中的多晶硅薄膜的制作方法，通过在衬底基板上依次形成金属层、缓冲层、非晶硅膜层后，使金属层中的金属原子可以通过扩散以与非晶硅膜层进行接触，使非晶硅膜层在金属原子的催化作用下可以转化为多晶硅膜层。由于在将非晶硅膜层转换为多晶硅膜层时，利用制作成的薄膜晶体管所存在的缓冲层替代上述相关技术中的金属隔离层，从而可以不需要单独制作金属隔离层。并且，由于在形成非晶硅膜层之前制备缓冲层和金属层，还可以省略去除金属层和缓冲层的工艺。进而可以降低生产成本，简化工艺制作步骤。
需要说明的是，在通过金属诱导非晶硅晶化方法将非晶硅薄膜转换为多晶硅薄膜时，金属原子一般作为催化剂，使非晶硅膜层在金属原子的催化作用下转换为多晶硅膜层，而由于在金属层与非晶硅膜层之间还形成有缓冲层，为了能够使金属层的金属原子对非晶硅膜层起到催化的作用，通过需要将金属层进行一定的加热，使金属层中的金属原子能够进行扩散，与非晶硅膜层接触。在具体实施时，可以通过不同的工艺步骤，实现非晶硅膜层转化为多晶硅膜层。以下进行具体举例说明。
为了能够使金属层的金属原子充分扩散到非晶硅膜层，形成结晶性能优异的多晶硅薄膜，本公开实施例的制作方法，在形成缓冲层之后，且在缓冲 层上形成非晶硅膜层之前，还可以包括：通过第一退火工艺，在缓冲层背离衬底基板的一侧形成金属扩散层，其中，金属扩散层由金属层的金属原子扩散到缓冲层背离衬底基板的一侧形成。并且，通过金属原子对非晶硅膜层的催化作用，将非晶硅膜层转化为多晶硅膜层，具体可以包括：采用第二退火工艺，使非晶硅膜层通过金属扩散层的催化作用转化为多晶硅膜层。一般薄膜表面的缺陷相对其内部较多，由于金属原子一般会向缺陷多的区域进行扩散，因此金属原子会向缓冲层的表面上进行扩散，以形成金属扩散层。这样采用第一退火工艺在缓冲层上形成金属扩散层之后，再在金属扩散层背离衬底基板的一侧形成非晶硅膜层，再通过第二退火工艺，使非晶硅膜层在金属扩散层中的金属原子的催化作用下转化为多晶硅膜层。具体的，第一退火工艺可以为在温度低于600℃，时长为第一预设时长的条件下的退火过程，第二退火工艺可以为在温度低于600℃，时长为第二预设时长的条件下的退火过程。在实际应用中，第一预设时长和第二预设时长需要根据实际应用环境来设计确定，在此不作限定。
本公开实施例中，在使非晶硅膜层转化为多晶硅膜层的过程中，还可以通过一步退火工艺实现，即，在金属层上形成缓冲层后，直接在缓冲层上形成非晶硅膜层，可以通过一次较长时间的退火过程，即采用第三退火工艺，使金属层中的金属原子扩散到非晶硅膜层中，并使非晶硅膜层在扩散到其膜层中的金属原子的催化作用下转化为多晶硅膜层。其中，第三退火工艺可以为在温度低于600℃，时长为第三预设时长的条件下的退火过程。并且，第三预设时长大于第一预设时长，同时也大于第二预设时长，即，相比第一退火工艺和第二退火工艺，第三退火工艺的时长更长。在实际应用中，第三预设时长需要根据实际应用环境来设计确定，在此不作限定。
在具体实施时，本公开实施例在制作多晶硅膜层时，可以直接将多晶硅膜层制作为图案化的多晶硅膜层，即，直接使该多晶硅膜层具有有源层的图案。例如，只在薄膜晶体管的沟道区形成多晶硅薄膜，对于通过两次退火工艺将非晶硅膜层转化为多晶硅膜层，若要形成图案化的多晶硅膜层，可以在 经过第一退火工艺后，在金属扩散层背离衬底基板的一侧形成非晶硅薄膜；之后，采用干法刻蚀工艺，使非晶硅薄膜形成图案化的非晶硅膜层，即直接使非晶硅膜层具有有源层的图案。可选地，在形成图案化的非晶硅膜层时，还可以选择合适的过刻比，同时去除除第一区域以外的其它区域中的金属扩散层，其中，第一区域对应薄膜晶体管的沟道区，除第一区域之外的其它区域对应薄膜晶体管的非沟道区。由于金属层中的金属原子在扩散到缓冲层上方时，可能还扩散到非沟道区对应区域，进而在将非晶硅薄膜层进行图案化时，同时去除金属扩散层中除第一区域以外的其它区域的薄膜，可以降低金属层的金属原子由于扩散到非沟道区时对多晶硅薄膜形成的薄膜晶体管的影响。即，可以在不增加制作工艺步骤的情况下，降低金属层的金属原子由于扩散到非沟道区时对多晶硅薄膜形成的薄膜晶体管的影响。其中，过刻比可以为在能够去除非沟道区的非晶硅膜层的情况下，进一步向下刻蚀，以去除非晶硅膜层下方的对应非沟道区中的金属扩散层。例如，若刻蚀去除非沟道区对应的非晶硅膜层的用时为30min，则可以适当延长刻蚀时间为40min，以刻蚀掉对应非沟道区的金属扩散层。当然，上述只是以30min和40min进行举例说明，本公开并不以此为限。具体地，在干法刻蚀工艺中，可以选用氟系气体和氯系气体的混合气体进行刻蚀。
为了进一步降低金属层中金属原子扩散到非沟道区时对多晶硅薄膜形成的薄膜晶体管的影响，在具体实施时，本公开实施例中形成金属层，具体可以包括：在衬底基板的一侧形成图案化的金属层；其中，金属层的图案在衬底基板的正投影与非晶硅膜层的图案在衬底基板的正投影重叠。这样可以仅保留与沟道区对应区域中的金属层，以使该区域中的金属层中的金属原子进行扩散。
在具体实施时，金属层扩散出的金属原子可能会富集在多晶硅膜层背离缓冲层一侧的表面上，从而可以通过对多晶硅膜层背离缓冲层一侧的表面进行处理，去除多晶硅膜层背离缓冲层一侧的部分薄膜，进而可以降低多晶硅薄膜形成的薄膜晶体管的漏电流较高的问题。可选地，本公开实施例在将非 晶硅膜层转化为多晶硅膜层后，制作方法还可以包括：对多晶硅膜层背离缓冲层一侧的表面进行处理，去除多晶硅膜层背离缓冲层一侧的部分薄膜。具体的，可以采用干法刻蚀工艺对多晶硅膜层背离缓冲层一侧的表面进行刻蚀处理，以将多晶硅膜层中富集金属原子的部分表面薄膜层去除。例如，可以利用ICP(Inductively Coupled Plasma，感应耦合等离子体刻蚀)设备，在CF 4与O 2或Cl 2与O 2氛围下，以及在上电极源功率(Source Power)为第一预设功率，下电极偏置功率(Bias Power)为第二预设功率的条件下对多晶硅膜层的表面进行刻蚀处理。其中，可选地，根据实际制作方法的需要，第一预设功率为高功率。并且，为了避免对多晶硅膜层的沟道区截面产生损伤而影响形成的薄膜晶体管的特性，可以使第二预设功率为低功率或为零功率。
为了更详细的对本公开实施例提供的薄膜晶体管中的多晶硅薄膜的制备方法进行说明，结合附图2至附图9举例如下：本公开实施例提供的薄膜晶体管中的多晶硅薄膜的制备方法，具体可以包括如下步骤：
步骤一，采用等离子体化学气相沉积工艺，在衬底基板1上沉积50nm厚的SiNx膜层作为阻挡层2。其中，衬底基板1可以为玻璃基板，该SiNx膜层可用来阻挡玻璃基板中的碱金属离子，例如，Na离子或K离子。在衬底基板1上形成阻挡层2后的示意图如图2所示。
步骤二，通过溅射工艺，并采用与后期形成的多晶硅膜层的图案一致的掩模板，在阻挡层2上形成50nm厚的图案化的Ni金属层3。其中，后期形成的多晶硅膜层的图案与薄膜晶体管中的沟道区对应。为了降低Ni金属层3扩散的金属原子扩散到薄膜晶体管非沟道区的几率，Ni金属层3的图案在衬底基板的正投影与多晶硅膜层的图案在衬底基板的正投影重叠。在阻挡层2上形成Ni金属层3后的结构示意图如图3所示。
步骤三，采用等离子体化学气相沉积工艺，在Ni金属层3上沉积50nm厚的SiOx薄膜作为缓冲层4，此SiOx薄膜用于控制进入多晶硅薄膜的金属量。在Ni金属层3上形成缓冲层4后的示意图如图4所示。
步骤四，在温度为500℃，时长为第一预设时长的条件下进行退火，使 Ni金属层3中的金属原子扩散到SiOx缓冲层4的上表面，在缓冲层4上表面形成由扩散的金属原子构成的金属扩散层5。在缓冲层4上形成金属扩散层5后的示意图如图5所示。
步骤五，采用等离子体化学气相沉积法，在金属扩散层5上沉积50nm厚的非晶硅薄膜60。在金属扩散层5上形成非晶硅薄膜60后的示意图如图6所示。
步骤六，在非晶硅薄膜60上形成图案化的光刻胶层(图中未示出)，并采用干法刻蚀工艺，在图案化的光刻胶层的遮挡下，在氟气和氯气的混合气体的氛围下，对非晶硅薄膜60进行刻蚀，形成图案化的非晶硅膜层6，该图案化的非晶硅膜层6在经过晶化处理转化为多晶硅膜层后可作为薄膜晶体管的有源层。并且，在该步骤中，可适当增加过刻比，在形成图案化的非晶硅膜层6时，同时去除非沟道区对应区域中的金属扩散层5。形成图案化的非晶硅膜层6后的示意图如图7所示。
步骤七，在温度为500℃，时长为第二预设时长的条件下进行退火，使非晶硅膜层6在金属扩散层的金属原子的催化作用下转化为多晶硅膜层7。在实际制备过程中，该多晶硅膜层7可以包括背离缓冲层4一侧的含有较多金属原子的第一膜层7a以及含有较少或在误差允许范围内认为不含金属原子的第二膜层7b。在将非晶硅膜层6转换为多晶硅薄膜7后的示意图如图8所示。
步骤八，通过ICP设备，在CF 4和O 2的混合气体的氛围下，以Source Power为第一预设功率，Bias Power为第二预设功率，对多晶硅膜层7的表面进行干法刻蚀处理，以去除多晶硅膜层7背离缓冲层4一侧的表面的部分薄膜，即第一膜层7a，而保留第二膜层7b。去除第一膜层7a后的示意图如图9所示。
基于同一公开构思，本公开实施例还提供了一种薄膜晶体管的制作方法，包括采用本公开实施例提供的薄膜晶体管中的多晶硅薄膜的制作方法，在衬底基板上形成图案化的多晶硅薄膜。该薄膜晶体管的制作方法解决问题的原理与前述多晶硅薄膜的制作方法相似，因此该薄膜晶体管的制作方法的实施可以参见前述多晶硅薄膜的制作方法的实施，重复之处在此不再赘述。
在具体实施时，对于整体的薄膜晶体管，参见图10，薄膜晶体管的制作方法，还包括形成其它膜层的制作步骤，具体地，薄膜晶体管的制作步骤还可以包括以下步骤：
步骤一、在多晶硅膜层7背离衬底基板1的一侧依次形成栅极绝缘层8与图案化的栅极9。其中，多晶硅膜层7的图案在衬底基板1的正投影覆盖栅极9的图案在衬底基板1的正投影。
具体地，在多晶硅膜层7上形成栅极绝缘层8，并在栅极绝缘层8上形成栅极9。当然，这里的多晶硅膜层7可指去除了背离缓冲层4一侧的表面的部分薄膜后的多晶硅膜层。
步骤二、在栅极9背离衬底基板1的一侧上形成具有第一过孔13和第二过孔14的源漏极绝缘层10。其中，多晶硅膜层7的图案在衬底基板1的正投影覆盖1第一过孔13和第二过孔14在衬底基板1的正投影；1第一过孔13和第二过孔14在衬底基板1的正投影与栅极9的图案在衬底基板1的正投影无交叠.
步骤三、在源漏极绝缘层10背离衬底基板1的一侧上形成源极11和漏极12；其中，源极11通过第一过孔13与多晶硅膜层7连接接触，漏极12通过第二过孔14与多晶硅膜层7连接接触。
基于同一公开构思，本公开实施例还提供一种应用于薄膜晶体管中的多晶硅薄膜，参见图9，可以包括：设置在衬底基板1一侧上的金属层3；设置在金属层3背离衬底基板1一侧的缓冲层4；设置在缓冲层4背离衬底基板一侧的多晶硅膜层7(该多晶硅膜层7可指去除了背离缓冲层一侧的表面部分薄膜后的第二膜层7b)，其中，多晶硅膜层7采用本公开实施例提供的上述多晶硅薄膜的制作方法制作而成。该多晶硅薄膜解决问题的原理与前述多晶硅薄膜的制作方法相似，因此该多晶硅薄膜的实施可以参见前述多晶硅薄膜的制作方法的实施，重复之处在此不再赘述。
基于同一公开构思，本公开实施例还提供了薄膜晶体管，该薄膜晶体管解决问题的原理与前述薄膜晶体管的制作方法相似，因此该薄膜晶体管的实 施可以参见前述薄膜晶体管的制作方法的实施，重复之处在此不再赘述。
具体地，参见图10，本公开实施例提供的薄膜晶体管具体可以包括：设置在衬底基板1一侧的多晶硅薄膜7；其中，多晶硅薄膜7为本公开实施例提供的多晶硅薄膜。依次设置在多晶硅膜层7背离衬底基板1一侧的栅极绝缘层8，和图案化的栅极9；其中，多晶硅膜层7的图案在衬底基板1的正投影覆盖栅极9的图案在衬底基板1上的正投影。并且，该多晶硅膜层7可指去除了背离缓冲层一侧的表面的部分薄膜(即第一膜层7a)后的第二膜层7b。设置在栅极9背离衬底基板1一侧且具有第一过孔13和第二过孔14的源漏极绝缘层10；其中，多晶硅膜层7的图案在衬底基板1的正投影覆盖第一过孔13和第二过孔14在衬底基板1的正投影；第一过孔13和第二过孔14在衬底基板1的正投影与栅极9的图案在衬底基板1的正投影无交叠。以及设置在源漏极绝缘层10背离衬底基板1一侧的源极11和漏极12；其中，源极11通过第一过孔13与多晶硅膜层7连接，漏极12通过第二过孔14与多晶硅膜层7连接。
综上所述，本公开通过在衬底基板上依次形成金属层、缓冲层、非晶硅膜层后，使金属层中的金属原子可以通过扩散以与非晶硅膜层进行接触，使非晶硅膜层在金属原子的催化作用下可以转化为多晶硅膜层。由于在将非晶硅膜层转换为多晶硅膜层时，利用制作成的薄膜晶体管所存在的缓冲层替代上述相关技术中的金属隔离层，从而可以不需要单独制作金属隔离层。并且，由于在形成非晶硅膜层之前制备缓冲层和金属层，还可以省略去除金属层和缓冲层的工艺。进而可以降低生产成本，简化工艺制作步骤。
显然，本领域的技术人员可以对本公开实施例进行各种改动和变型而不脱离本公开实施例的精神和范围。这样，倘若本公开实施例的这些修改和变型属于本公开权利要求及其等同技术的范围之内，则本公开也意图包含这些改动和变型在内。

Claims (10)

  1. 一种多晶硅薄膜的制作方法，所述多晶硅薄膜应用于薄膜晶体管中；其中，所述制作方法包括：
    在衬底基板一侧形成金属层；
    在所述金属层背离所述衬底基板的一侧形成缓冲层；
    在所述缓冲层背离所述衬底基板的一侧形成非晶硅膜层；
    通过金属原子对所述非晶硅膜层的催化作用，将所述非晶硅膜层转化为多晶硅膜层；其中，所述金属原子为所述金属层扩散的并与所述非晶硅膜层接触的金属原子。
  2. 如权利要求1所述的制作方法，其中，在所述形成缓冲层之后，在所述形成非晶硅膜层之前，所述制作方法还包括：
    采用第一退火工艺，在所述缓冲层背离所述衬底基板的一侧形成金属扩散层；其中，所述金属扩散层由所述金属层的金属原子扩散到所述缓冲层背离所述衬底基板的一侧形成；
    所述通过金属原子对所述非晶硅膜层的催化作用，将所述非晶硅膜层转化为多晶硅膜层，具体包括：
    采用第二退火工艺，使所述非晶硅膜层通过所述金属扩散层的催化作用转化为多晶硅膜层。
  3. 如权利要求2所述的制作方法，其中，所述形成非晶硅膜层，具体包括：
    在所述金属扩散层背离所述衬底基板一侧形成非晶硅薄膜；
    采用干法刻蚀工艺，使所述非晶硅薄膜形成图案化的非晶硅膜层，并去除除第一区域以外的其余区域中的金属扩散层；其中，所述第一区域在所述衬底基板的正投影与所述非晶硅膜层的图案在所述衬底基板的正投影重叠。
  4. 如权利要求3所述的制作方法，其中，所述形成金属层，具体包括：
    在所述衬底基板的一侧形成图案化的金属层；其中，所述金属层的图案 在所述衬底基板的正投影与所述非晶硅膜层的图案在所述衬底基板的正投影重叠。
  5. 如权利要求1所述的制作方法，其中，所述通过金属原子对所述非晶硅膜层的催化作用，将所述非晶硅膜层转化为多晶硅膜层，具体包括：
    采用第三退火工艺，使所述金属层的金属原子扩散到所述非晶硅膜层，并使所述非晶硅膜层通过扩散到的金属原子的催化作用转化为多晶硅膜层。
  6. 如权利要求1所述的制作方法，其中，在所述将所述非晶硅膜层转化为多晶硅膜层之后，所述制作方法还包括：
    对所述多晶硅膜层背离所述缓冲层一侧的表面进行处理，去除所述多晶硅膜层背离所述缓冲层一侧的部分薄膜。
  7. 如权利要求1所述的制作方法，其中，在所述形成金属层之前，所述制作方法还包括：
    在所述衬底基板上形成阻挡层。
  8. 一种薄膜晶体管的制作方法，其中，包括：
    采用如权利要求1-7任一项所述的多晶硅薄膜的制作方法，在衬底基板上形成图案化的多晶硅薄膜；
    在所述多晶硅膜层背离所述衬底基板的一侧依次形成栅极绝缘层与图案化的栅极；其中，所述多晶硅膜层的图案在所述衬底基板的正投影覆盖所述栅极的图案在所述衬底基板的正投影；
    在所述栅极背离所述衬底基板的一侧形成具有第一过孔和第二过孔的源漏极绝缘层；其中，所述多晶硅膜层的图案在所述衬底基板的正投影覆盖所述第一过孔和所述第二过孔在所述衬底基板的正投影；所述第一过孔和所述第二过孔在所述衬底基板的正投影与所述栅极的图案在所述衬底基板的正投影无交叠；
    在所述源漏极绝缘层背离所述衬底基板的一侧形成源极和漏极；其中，所述源极通过所述第一过孔与所述多晶硅膜层连接，所述漏极通过所述第二过孔与所述多晶硅膜层连接。
  9. 一种多晶硅薄膜，其中，包括：
    设置在衬底基板一侧的金属层；
    设置在所述金属层背离所述衬底基板一侧的缓冲层；
    设置在所述缓冲层背离所述衬底基板一侧的多晶硅膜层；其中，所述多晶硅膜层采用如权利要求1-7任一项所述的多晶硅薄膜的制作方法制作而成。
  10. 一种薄膜晶体管，其中，包括：
    设置在衬底基板一侧的多晶硅薄膜；其中，所述多晶硅薄膜为如权利要求9所述的多晶硅薄膜；
    依次设置在所述多晶硅薄膜背离所述衬底基板一侧的栅极绝缘层和图案化的栅极；其中，所述多晶硅膜层的图案在所述衬底基板的正投影覆盖所述栅极的图案在所述衬底基板的正投影；
    设置在所述栅极背离所述衬底基板一侧且具有第一过孔和第二过孔的源漏极绝缘层；其中，所述多晶硅膜层的图案在所述衬底基板的正投影覆盖所述第一过孔和所述第二过孔在所述衬底基板的正投影；所述第一过孔和所述第二过孔在所述衬底基板的正投影与所述栅极的图案在所述衬底基板的正投影无交叠；
    设置在所述源漏极绝缘层背离所述衬底基板一侧的源极和漏极；其中，所述源极通过所述第一过孔与所述多晶硅膜层连接，所述漏极通过所述第二过孔与所述多晶硅膜层连接。
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001093853A (ja) * 1999-09-20 2001-04-06 Sanyo Electric Co Ltd 半導体装置および半導体装置の製造方法
CN104299891A (zh) * 2014-10-20 2015-01-21 京东方科技集团股份有限公司 低温多晶硅薄膜的制备方法、tft、阵列基板及显示装置
CN105470312A (zh) * 2016-02-19 2016-04-06 深圳市华星光电技术有限公司 低温多晶硅薄膜晶体管及其制造方法
CN106876478A (zh) * 2017-03-22 2017-06-20 京东方科技集团股份有限公司 一种薄膜晶体管中的多晶硅薄膜、薄膜晶体管及制作方法

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100685855B1 (ko) * 2006-09-20 2007-02-22 삼성에스디아이 주식회사 금속 유도 결정화 방법을 이용한 박막 트랜지스터, 이의제조 방법 및 이를 사용하는 액티브 매트릭스 평판 표시장치
KR100889627B1 (ko) * 2007-08-23 2009-03-20 삼성모바일디스플레이주식회사 박막트랜지스터, 그의 제조방법, 및 이를 구비한유기전계발광표시장치
CN101740359B (zh) 2009-12-08 2011-11-23 四川虹视显示技术有限公司 制作低温多晶硅方法中的镍剥离方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001093853A (ja) * 1999-09-20 2001-04-06 Sanyo Electric Co Ltd 半導体装置および半導体装置の製造方法
CN104299891A (zh) * 2014-10-20 2015-01-21 京东方科技集团股份有限公司 低温多晶硅薄膜的制备方法、tft、阵列基板及显示装置
CN105470312A (zh) * 2016-02-19 2016-04-06 深圳市华星光电技术有限公司 低温多晶硅薄膜晶体管及其制造方法
CN106876478A (zh) * 2017-03-22 2017-06-20 京东方科技集团股份有限公司 一种薄膜晶体管中的多晶硅薄膜、薄膜晶体管及制作方法

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