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WO2018171311A1 - Structure de pixels et son procédé de fabrication - Google Patents

Structure de pixels et son procédé de fabrication Download PDF

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Publication number
WO2018171311A1
WO2018171311A1 PCT/CN2018/072781 CN2018072781W WO2018171311A1 WO 2018171311 A1 WO2018171311 A1 WO 2018171311A1 CN 2018072781 W CN2018072781 W CN 2018072781W WO 2018171311 A1 WO2018171311 A1 WO 2018171311A1
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WO
WIPO (PCT)
Prior art keywords
layer
insulating layer
hole
metal layer
common electrode
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Application number
PCT/CN2018/072781
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English (en)
Chinese (zh)
Inventor
黄威
Original Assignee
南京中电熊猫平板显示科技有限公司
南京中电熊猫液晶显示科技有限公司
南京华东电子信息科技股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from CN201710172821.7A external-priority patent/CN106896603A/zh
Priority claimed from CN201710172813.2A external-priority patent/CN107085334A/zh
Application filed by 南京中电熊猫平板显示科技有限公司, 南京中电熊猫液晶显示科技有限公司, 南京华东电子信息科技股份有限公司 filed Critical 南京中电熊猫平板显示科技有限公司
Publication of WO2018171311A1 publication Critical patent/WO2018171311A1/fr

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  • the present application relates to the field of liquid crystal display technology, and in particular, to a pixel structure and a method of fabricating the same. .
  • the gate source capacitance Cgs is large.
  • the simplest TN mode a-Si 5Mask process is taken as an example, as shown in FIG. 1, the first metal layer 101 and the first layer.
  • the overlapping area of the two-layer metal layer 102 is relatively large, and the distance is small, which causes the feed through voltage ⁇ Vp to be relatively large, ⁇ Vp ⁇ [Cgs / (Cst + Clc)] * (Vgh - Vgl)
  • Cst is the storage capacitor
  • Clc is the liquid crystal capacitor
  • Vgh and Vgl are the gate high voltage and the gate low voltage
  • the vacuum electrode voltage ⁇ Vp is large, which increases the risk of flicker on the liquid crystal screen. Affects the normal display of the LCD screen.
  • ⁇ Vp can be reduced by reducing the gate-source capacitance Cgs, but the storage capacitor Cst is also reduced, and ⁇ Vp cannot be effectively reduced. Therefore, how to reduce the gate-source capacitance Cgs while ensuring the storage capacitor Cst is not Changing or even increasing is an urgent problem to be solved.
  • the invention provides a pixel structure and a manufacturing method thereof, aiming at overcoming the risk of occurrence of flicker in a liquid crystal screen in the prior art.
  • a pixel structure includes a substrate, a first metal layer, a first insulating layer, a semiconductor layer, a second metal layer, a second insulating layer, and a pixel electrode layer, which are sequentially arranged from bottom to top on the substrate, a metal layer is etched to form a gate electrode and a common electrode line, the second metal layer is etched to form a source and a drain, and the first insulating layer is provided with a first hole above the common electrode line.
  • An insulating material layer is disposed between the first hole and the common electrode line; a second hole above the drain is opened on the second insulating layer, and a material forming the pixel electrode layer enters the first hole One hole and two holes.
  • the layer of insulating material is formed by a second insulating layer.
  • a third metal layer is further disposed between the first hole and the insulating material layer.
  • the first insulating layer is a two-layer structure, including a first lower insulating layer on the first metal layer and a first upper insulating layer on the first lower insulating layer, the first upper layer
  • the thickness of the insulating layer is greater than the thickness of the first lower insulating layer
  • the insulating material layer is formed of the first lower insulating layer.
  • the third metal layer is located between the first lower insulating layer and the first upper insulating layer, and the first hole is opened in the first upper insulating layer.
  • the first hole is formed in the first insulating layer, and the insulating material layer is a first insulating layer having a partial thickness.
  • the depth of the first hole is more than 80% of the thickness of the first insulating layer.
  • the first insulating layer is a single layer structure.
  • the material of the pixel electrode layer is an ITO material.
  • the first insulating layer has a thickness of not less than 3000 angstroms.
  • the thickness of the second insulating layer is smaller than the thickness of the first insulating layer.
  • a method of fabricating a pixel structure comprising the steps of:
  • a method of fabricating a pixel structure comprising the steps of:
  • a method of fabricating a pixel structure comprising the steps of:
  • the first insulating layer is provided with a first hole above the common electrode line
  • the second insulating layer is provided with a second hole above the drain, the pixel electrode layer Partially entering the first hole and the second hole
  • the thickness of the first insulating layer is not less than 3000 angstroms, the distance between the first metal layer and the second metal layer may be increased, and the gate source capacitance Cgs may be decreased
  • the storage capacitor Cst can reduce the gate-source capacitance Cgs and increase the storage capacitor Cst, thereby solving the problem of flicker.
  • the structure is simple, the process is easy to implement, and has a good application prospect.
  • FIG. 1 is a schematic diagram of a conventional TN mode a-Si 5Mask process pixel structure
  • FIG. 2 is a cross-sectional structural view showing a first embodiment of a pixel structure of the present invention
  • Figure 3 is a plan view showing the position of the first hole in the first embodiment of the present invention.
  • FIG. 4 is a cross-sectional structural view showing a second embodiment of the pixel structure of the present invention.
  • Figure 5 is a plan view of a third metal layer in a second embodiment of the present invention.
  • FIG. 6 is a cross-sectional structural view showing a third embodiment of a pixel structure of the present invention.
  • Figure 7 is a plan view showing the position of the second hole in the third embodiment of the present invention.
  • 101 first metal layer; 102: second metal layer; 201: substrate; 202: first metal layer; 2021: gate; 2022: common electrode line; 203: first insulating layer; 2031: first Insulating layer; 2032: first upper insulating layer; 204: semiconductor layer; 205: second metal layer; 2051: source; 2052: drain; 206: second insulating layer; 207: pixel electrode layer; 208: third Metal layer; 209: first hole; 210: second hole.
  • the pixel structure of the first embodiment of the present invention includes a substrate 201, a first metal layer 202, a first insulating layer 203, and a semiconductor layer, which are sequentially arranged from bottom to top on the substrate 201.
  • the second metal layer 205, the second insulating layer 206, the pixel electrode layer 207, the first metal layer 202 is etched to form the gate electrode 2021 and the common electrode line 2022, and the second metal layer 205 is etched to form the source electrode 2051 and the drain electrode.
  • the first insulating layer 203 is provided with a first hole 209 above the common electrode line 2022. A portion of the second insulating layer enters the first hole 209.
  • the second insulating layer 206 is disposed above the drain electrode 2052.
  • the second hole 210, the ITO material forming the pixel electrode layer 207 enters the first hole 209 and the second hole 210, and the ITO material enables the pixel electrode layer 207 and the drain electrode 2052 to be electrically connected.
  • the first insulating layer 203 having a thickness of not less than 3000 angstroms can increase the distance between the first metal layer 202 and the second metal layer 205, thereby reducing the gate-source capacitance Cgs, and the first insulating layer 203 is opened on the common electrode
  • a second hole 210 above the drain electrode 2052 is opened on the first hole 209 and the second insulating layer 206 above the line 2022, and the storage capacitor Cst can be increased.
  • the vacuum electrode voltage ⁇ Vp ⁇ Cgs / (Cst + Clc) The vacuum electrode voltage ⁇ Vp is reduced, thereby reducing the risk of flicker on the liquid crystal screen and ensuring the normal display of the liquid crystal screen.
  • the first insulating layer 203 in the first embodiment has a single layer structure.
  • the manufacturing method of the pixel structure of the first embodiment includes the following steps,
  • the pixel structure of the second embodiment of the present invention includes a substrate 201, a first metal layer 202, a first insulating layer 203, and a semiconductor layer, which are sequentially arranged from bottom to top on the substrate 201.
  • the second metal layer 205, the second insulating layer 206, the pixel electrode layer 207, the first metal layer 202 is etched to form the gate electrode 2021 and the common electrode line 2022, and the second metal layer 205 is etched to form the source electrode 2051 and the drain electrode.
  • a first hole 209 is disposed on the first insulating layer 203, and a third metal layer 208 is disposed between the first hole 209 and the common electrode line 2022.
  • the second insulating layer 206 is disposed on the second insulating layer 206.
  • the first insulating layer 203 has a thickness of not less than 3000 angstroms, and the first insulating layer 203 has a two-layer structure, including a first lower insulating layer 2031 on the first metal layer 202 and the first lower insulating layer 2031.
  • the first upper insulating layer 2032, and the thickness of the first upper insulating layer 2032 is greater than the thickness of the first lower insulating layer 2031, because the first hole 209 needs to be opened thereon, and the third metal layer 208 is located at the first lower insulating layer.
  • the first upper insulating layer 2032 is provided with a first hole 209 above the common electrode line 2022, and the second insulating layer 206 is disposed above the drain 2052.
  • the second hole 210 can increase the storage capacitor Cst.
  • the vacuum electrode voltage ⁇ Vp can be reduced, thereby reducing the risk of flicker on the liquid crystal screen, and ensuring the liquid crystal.
  • the normal display of the screen According to the vacuum electrode voltage ⁇ Vp ⁇ Cgs / (Cst + Clc), the vacuum electrode voltage ⁇ Vp can be reduced, thereby reducing the risk of flicker on the liquid crystal screen, and ensuring the liquid crystal. The normal display of the screen.
  • the manufacturing method of the pixel structure of the second embodiment includes the following steps,
  • the pixel structure of the third embodiment of the present invention includes a substrate 201, a first metal layer 202, a first insulating layer 203, and a semiconductor layer, which are sequentially disposed from bottom to top on the substrate 201.
  • the second metal layer 205, the second insulating layer 206, the pixel electrode layer 207, the first metal layer 202 is etched to form the gate electrode 2021 and the common electrode line 2022, and the second metal layer 205 is etched to form the source electrode 2051 and the drain electrode.
  • a first insulating layer 203 is disposed on the first insulating layer 203, and a first insulating layer 203 is disposed between the first hole 209 and the common electrode line 2022.
  • the thickness of the first insulating layer 203 is greater than the thickness of the second insulating layer 206, and the depth of the first hole 209 is more than 80% of the thickness of the first insulating layer 203, so that the first hole 209 is located in the first insulating layer 203, and Not communicating with the upper surface of the common electrode line 2022, leaving a portion of the first insulating layer 203 between the first hole 209 and the common electrode line 2022;
  • the second insulating layer 206 defines a second hole 210 above the drain electrode 2052.
  • the material forming the pixel electrode layer 207 enters the first hole 209 and the second hole 210.
  • the second hole 210 can increase the storage capacitor Cst. According to the vacuum electrode voltage ⁇ Vp ⁇ Cgs / (Cst + Clc), the vacuum electrode voltage ⁇ Vp can be reduced, thereby reducing the risk of flicker on the liquid crystal screen and ensuring the normal display of the liquid crystal screen.
  • the preferred pixel electrode layer 207 is made of an ITO material.
  • the preferred first insulating layer 203 is a single layer structure.
  • the manufacturing method of the pixel structure of the third embodiment described above includes the following steps,
  • the depth is 80% or more of the thickness of the first insulating layer 203, so that the first hole 209 is located on the first insulating layer 203 and is not in communication with the upper surface of the common electrode line 2022;
  • the layers are subjected to processes such as "film formation, photoresist coating, mask exposure, development, etching, photoresist stripping", etc., for the sake of brief description, only The two processes of film formation and etching, and omitting several other conventional processes, are actually necessary.
  • the deep hole is etched, and the first hole or the second hole is etched by a mask (or a halftone mask), wherein the mask is a mask or a mask, and the halftone mask is a multi-level mask or semi-transparent.
  • Membrane mask etching method the specific steps should be after the deep and shallow holes are engraved, coated with photoresist, (there is no film formation and the photoresist is directly coated because the film has been formed before), using mask ( Or halftone mask) exposing the pattern of the first or second holes on the photoresist, then developing, and then etching the unprotected film from which the photoresist is developed, the first or second holes are formed, and then The photoresist is peeled off, and then the next layer (such as the pixel electrode layer) is formed. Since the second insulating layer needs to etch the deep and shallow holes, the second hole cannot be shallow and shallow if no other metal layer is inserted as a barrier.
  • the holes are etched together, and after the deep and shallow holes have been carved, another mask is used to make the second hole.
  • the above process is performed, and only the film formation is omitted.
  • the so-called second hole is a relatively deep and shallow hole. , but the depth of expression is different, not really the hole
  • the figure is a large piece, and the purpose of the second hole is to increase the storage capacitor Cst.
  • the thickness of the first insulating layer is not less than 3000 angstroms, the distance between the first metal layer and the second metal layer is increased, and the gate source capacitance Cgs is reduced.
  • the first insulating layer is provided with a first hole above the common electrode line, and the second insulating layer is provided with a second hole above the drain, which can increase the storage capacitor Cst, thereby reducing the gate-source capacitance.
  • Cgs which can increase the storage capacitor Cst, solves the problem of flicker, has a simple structure, is easy to implement, and has a good application prospect.

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  • Liquid Crystal (AREA)
  • Thin Film Transistor (AREA)

Abstract

Une structure de pixel et son procédé de fabrication. La structure de pixel comprend un substrat (201), et une première couche métallique (202), une première couche d'isolation (203), une couche semi-conductrice (204), une seconde couche métallique (205), une seconde couche d'isolation (206), et une couche d'électrode de pixel (207) disposées séquentiellement de bas en haut sur le substrat (201). La première couche métallique (202) est gravée pour former une grille (2021) et une ligne d'électrode commune (2022). La seconde couche métallique (205) est gravée pour former une source (2051) et un drain (2052). La première couche d'isolation (203) est pourvue d'un premier trou (209) situé au-dessus de la ligne d'électrode commune (2022). Une couche de matériau isolant est disposée entre le premier trou (209) et la ligne d'électrode commune (2022). La seconde couche d'isolation (206) est pourvue d'un second trou (210) situé au-dessus du drain (2052). Un matériau formant la couche d'électrode de pixel (207) pénètre dans le premier trou (209) et le second trou (210). La capacité de source de grille (Cgs) est réduite et la capacité de stockage (Cst) est augmentée, ce qui permet de résoudre le problème de scintillement. La structure est simple, le processus est facilement mis en oeuvre, et des perspectives d'application sont favorables.
PCT/CN2018/072781 2017-03-22 2018-01-16 Structure de pixels et son procédé de fabrication WO2018171311A1 (fr)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
CN201710172821.7A CN106896603A (zh) 2017-03-22 2017-03-22 像素结构及其制造方法
CN201710172813.2 2017-03-22
CN201710172813.2A CN107085334A (zh) 2017-03-22 2017-03-22 一种像素结构及其制造方法
CN201710172821.7 2017-03-22

Publications (1)

Publication Number Publication Date
WO2018171311A1 true WO2018171311A1 (fr) 2018-09-27

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PCT/CN2018/072781 WO2018171311A1 (fr) 2017-03-22 2018-01-16 Structure de pixels et son procédé de fabrication

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WO (1) WO2018171311A1 (fr)

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20060074728A (ko) * 2004-12-28 2006-07-03 비오이 하이디스 테크놀로지 주식회사 박막트랜지스터 액정표시장치
CN101207140A (zh) * 2007-04-24 2008-06-25 友达光电股份有限公司 阵列基板及其制造方法
CN102290413A (zh) * 2010-06-17 2011-12-21 北京京东方光电科技有限公司 阵列基板及其制造方法和液晶显示器
CN202093290U (zh) * 2011-05-27 2011-12-28 北京京东方光电科技有限公司 一种液晶显示器的阵列基板、及液晶显示器
CN103178119A (zh) * 2013-03-25 2013-06-26 京东方科技集团股份有限公司 阵列基板、阵列基板制备方法以及显示装置
CN106896603A (zh) * 2017-03-22 2017-06-27 南京中电熊猫平板显示科技有限公司 像素结构及其制造方法
CN107085334A (zh) * 2017-03-22 2017-08-22 南京中电熊猫平板显示科技有限公司 一种像素结构及其制造方法

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20060074728A (ko) * 2004-12-28 2006-07-03 비오이 하이디스 테크놀로지 주식회사 박막트랜지스터 액정표시장치
CN101207140A (zh) * 2007-04-24 2008-06-25 友达光电股份有限公司 阵列基板及其制造方法
CN102290413A (zh) * 2010-06-17 2011-12-21 北京京东方光电科技有限公司 阵列基板及其制造方法和液晶显示器
CN202093290U (zh) * 2011-05-27 2011-12-28 北京京东方光电科技有限公司 一种液晶显示器的阵列基板、及液晶显示器
CN103178119A (zh) * 2013-03-25 2013-06-26 京东方科技集团股份有限公司 阵列基板、阵列基板制备方法以及显示装置
CN106896603A (zh) * 2017-03-22 2017-06-27 南京中电熊猫平板显示科技有限公司 像素结构及其制造方法
CN107085334A (zh) * 2017-03-22 2017-08-22 南京中电熊猫平板显示科技有限公司 一种像素结构及其制造方法

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