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WO2018171547A1 - Structure d'encapsulation de puce à niveau de tranche et son procédé de fabrication - Google Patents

Structure d'encapsulation de puce à niveau de tranche et son procédé de fabrication Download PDF

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Publication number
WO2018171547A1
WO2018171547A1 PCT/CN2018/079447 CN2018079447W WO2018171547A1 WO 2018171547 A1 WO2018171547 A1 WO 2018171547A1 CN 2018079447 W CN2018079447 W CN 2018079447W WO 2018171547 A1 WO2018171547 A1 WO 2018171547A1
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WO
WIPO (PCT)
Prior art keywords
window
edge
groove
chip
slot
Prior art date
Application number
PCT/CN2018/079447
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English (en)
Chinese (zh)
Other versions
WO2018171547A9 (fr
Inventor
蒋舟
李扬渊
Original Assignee
苏州迈瑞微电子有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 苏州迈瑞微电子有限公司 filed Critical 苏州迈瑞微电子有限公司
Publication of WO2018171547A1 publication Critical patent/WO2018171547A1/fr
Publication of WO2018171547A9 publication Critical patent/WO2018171547A9/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/535—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including internal interconnections, e.g. cross-under constructions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Layout of the interconnection structure
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/011—Manufacture or treatment of image sensors covered by group H10F39/12

Definitions

  • the invention relates to the field of semiconductor technologies, and in particular to a wafer level chip package structure and a packaging method thereof.
  • TSV (Through Silicon Vias) package structure is one of the IC package methods, which can be divided into memory package and wafer level package for chip devices.
  • the wafer level package is applied to an optical image sensor (please refer to FIG. 1).
  • the optical image sensor 2 has a glass substrate 3 supporting the TSV structure 4 to maintain structural strength, the TSV opening 41, the slot 22, the wiring 23, and A Z-axis connection structure such as a solder window 24 is provided at the edge 21 of the image sensor chip to facilitate fabrication.
  • some chips such as capacitive fingerprint sensor chips
  • the optical image sensor TSV package process continues to be used (for example, the TSV package disclosed in the patent CN201510305840.3) Structure) will result in technical defects in the edge strength of the chip, which will bring risks in subsequent processing. For example, when cutting a wafer, the risk of chip fragmentation due to stress is increased, and there is also a risk in the post-laying and assembly stages.
  • the slot of the TSV is disposed inside the chip so that the slot is kept at a certain safe distance from the edge of the chip, for example, greater than 10 um. Since the TSV slot is disposed inside the chip, the thickness of the chip outside the TSV slot is the same as the thickness of the inside of the slot.
  • a wafer level chip package structure comprising: a chip unit having oppositely disposed first surfaces and second surfaces, the first surface arranging at least one solder window for electrical connection; the second surface setting A TSV structure coupled to the solder window, the TSV structure including a through hole extending through the first surface and the second surface and a groove disposed on the second surface, the boundary of the groove being greater than 10 um from the edge of the second surface.
  • the distance L between the boundary of the solder window and the edge of the first surface satisfies the relationship
  • At least one pad is disposed on the second surface of the chip unit, and the soldering window and the pad are electrically connected through the wiring formed on the through hole wall, the slotted bottom wall, the slotted sidewall and the second surface .
  • the present invention also provides a method for fabricating a wafer level chip package structure, including the steps of:
  • the aspect ratio k of the slotted sidewall is approximately equal to 2.75.
  • the trapezoidal groove is a one-stage or multi-stage trapezoidal groove.
  • the height of the chip outside the TSV slot is the same as the height of the chip inside, which improves the strength of the edge of the chip, and avoids the design of the left and right symmetrical solder window structure, thereby avoiding This design has an impact on the circuit design.
  • FIG. 1 is a schematic cross-sectional structural view of a prior art image sensor TSV package structure.
  • FIG. 2a is a perspective view of a TSV package structure of the present invention.
  • FIG. 2b is a perspective view of a TSV package structure of the present invention.
  • FIG 3 is a schematic view of a second surface pad array of the present invention.
  • 4a is a schematic cross-sectional view of the present invention in the TSV manufacturing step S1.
  • Fig. 4b is a schematic cross-sectional view showing the TSV manufacturing step S2 of the present invention.
  • Figure 4c is a schematic cross-sectional view of the TSV manufacturing step S3 of the present invention.
  • Figure 4d is a schematic cross-sectional view of the TSV manufacturing step S4 of the present invention.
  • FIG. 4e is a schematic view of another embodiment of the TSV structure of the present invention.
  • FIG. 5 is a schematic view showing the functional structure of the welding window of the present invention.
  • 6a-6d are schematic views of four kinds of welding window components of the welding window layout of the fifth embodiment of the present invention.
  • the wafer level chip package structure of the present invention comprises a chip unit 1 having a first surface 115 and a second surface 116 disposed opposite each other.
  • a fingerprint sensing chip is taken as an example.
  • the first surface 115 is provided with functional circuits 132 and 131 and a capacitor unit array (not shown) for sensing a fingerprint image, and the functional circuit is electrically connected to the soldering window. .
  • the second surface 116 is provided with a pad 12 and a TSV structure electrically connected to the soldering window, the TSV structure including a through hole 112 penetrating the first surface 115 or the soldering window 13 and the second surface 116, and the through hole 112
  • the connected slot 11 has a grooved boundary distance 110, 111 and the edge 117 of the second surface is greater than 10 um.
  • the grooved boundary 110 is greater than 10 um from the edge 117 of the second surface 116 such that the thickness d1 outside the chip slot 11 is the same as the thickness d2 inside the chip (refer to FIG. 3c), thereby ensuring the chip from the crystal. It can withstand the stress generated during cutting when cutting on a circle to avoid the risk of chip edge cracking.
  • the boundary of the slot 11 includes a longitudinally extending boundary 110 and a laterally extending boundary 111; the boundary of the soldering window of the present invention is greater than 10 um from the edge of the second surface, and refers to any boundary.
  • the edge of the welded window is greater than 10um.
  • the distance from the weld window boundary 110 closest to the second surface edge 117 is at least greater than 10 um
  • the present invention provides the following manufacturing method:
  • a soldering window 13 is disposed on the first surface 115 of the chip in step S1 such that the soldering window 12 is away from the edge 118 of the first surface 115, and the soldering window 13 is away from the first surface edge 118 in order to
  • the boundary 133 of the weld window 13 is maintained at a distance L from the first edge 118 that is set such that the boundary 110 of the slot 11 is greater than 10 um from the edge of the second surface 116.
  • the distance L satisfies the relationship
  • the first surface edge 118 should understand the outermost side of the first surface 115, and the boundary of the solder window 113 should be understood as the boundary line between the solder window and the chip; the distance L should be understood as the boundary 113. The minimum distance that can be achieved with the first surface edge 118.
  • the central axis x of the soldering window 13 coincides with the central axis of the slot 11 and the corresponding slot 11 is changed when the position of the soldering window 13 on the chip unit changes. The same position change also occurs in the position.
  • the function circuits 131, 132 and the fingerprint sensing array are arranged simultaneously with the solder window 13.
  • the shape and number of the weld windows 13 are designed differently as needed.
  • a plurality of soldering windows 13 may be disposed, and the soldering windows 13 are spaced apart from each other such that the through holes 112 corresponding to the different pads 13 do not interfere with each other when the through holes 112 are prepared.
  • a slot 11 is formed on the second surface 116 of the chip unit 1 by air/chemical etching or the like in step S2.
  • the slot 11 is disposed under the solder window 13, and the thickness of the chip 11 can be thinned. The preparation of the subsequent vias 112 is facilitated.
  • the etching method determines the aspect ratio of the sidewall of the groove, and the angle between the side wall of the groove formed by the air etching and the vertical direction is approximately 20°, and the width h of the grooved sidewall is greater than k.
  • the bottomed wall 1122 of the groove covers the soldering window 13 on the projection area S on the first surface (see also FIG. 1) to facilitate the preparation of the subsequent via 112.
  • the slot 11 is a trapezoidal structure whose central axis x coincides with the central axis of the slot, and the left boundary 110 of the slot is maintained larger than the left edge of the second surface 116 of the chip by more than 10 um while preparing the slot 11 while maintaining The upper and lower boundaries 110 at both ends of the slot 11 are larger than 10 ⁇ m from the upper and lower edges of the second surface of the chip (refer to FIG. 1 or FIG. 5b).
  • the second surface edge 117 should understand the outermost side of the second surface 116, and the grooved boundary 110 should be understood as the boundary line between the slot 11 and the second surface; the boundary 110 and the second surface The distance of the edge 117 should be understood as the minimum distance that the boundary 110 can reach between the second surface edge 118.
  • etching is performed between the slot 11 and the soldering window 13 in step S3 to form a through hole 112 penetrating the first surface 115 or the soldering window 13 and the second surface 116.
  • the through hole 112 The shape is a hollow truncated cone shape, and may be a columnar shape or the like in other embodiments.
  • a circular pad 12 is formed on the second surface 116 of the chip unit and on the periphery of the slot 11, and then electrically connected by the wiring 121 between the pad 12 and the solder window 13, so that The functional circuit is electrically coupled to the pad 12.
  • the wiring is formed in the through hole 1121 wall, the grooved bottom wall 1122, the grooved side wall 1123, and the second surface 116.
  • a plurality of stages of slots 11 may be provided, that is, the overlapping trapezoidal slots 113 extend along the trapezoidal shape of the trapezoidal slots 11, 113, and the boundary 110 of the multi-stage trapezoidal slots 11
  • the distance from the second surface edge 117 is greater than 10 um, that is, at least the boundary distance 117 of the first-stage trapezoidal groove of the multi-stage trapezoidal groove is greater than 10 um when the trapezoidal groove is prepared.
  • the soldering window and the functional circuit arranged in the above step S1 are logical operation circuit 132, ESD protection circuit 131, solder window 13, solder window 13 and logic in order from top to bottom in the figure.
  • the arithmetic circuit 131 and the ESD protection circuit 132 form a circuit arrangement unit 14 in which a plurality of the circuit arrangement units 14 are juxtaposed on the first surface 115 of the chip 1, the solder window 13 being disposed on the side close to the first surface edge 118
  • the logical operation circuit 132 and the ESD protection circuit 131 are disposed on a side away from the first surface edge 118.
  • the relative positional relationship between the soldering window 13 and the logic operation circuit 132 and the ESD protection circuit 131 is the same as that of the prior art, and the slot of the slot 11 is slotted from the second surface edge 117 in order to satisfy the slotting in step S2. More than 10um, the position of the arrangement unit is moved away from the edge of the first surface as a whole, that is, moving upwards and to the right (referred to as a paper surface).
  • the arrangement of the weld window in Figure 6a differs in that a plurality of arrangement units 14 are added to the left side of the first surface 115.
  • the increased placement unit 14 position moves generally away from the first surface edge 118 relative to the prior art, i.e., downwards and to the left (referenced to the paper surface).
  • the arrangement of the welding window 13 in FIG. 6a is different in that the position of the arrangement unit 14 is reversed, that is, the logic operation circuit 132, and the ESD protection circuit 131 is arranged close to The position of the first surface edge 118, the weld window 13 is disposed in a direction away from the first surface edge 118.
  • An advantage over the weld window arrangement of Figure 6a is that the circuit is disposed in the lower weld window 13 and the circuit arrangement requires a certain distance.
  • the weld window 13 is naturally remote from the edge 118 of the first surface and can be slotted in step S2. A sufficient distance is reserved so that the boundary 110 of the slot 11 is larger than 10 um from the second surface, and the circuit fully utilizes the area of the chip, and the partial chip area waste in FIG. 5a does not occur.

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Geometry (AREA)
  • Manufacturing & Machinery (AREA)
  • Solid State Image Pick-Up Elements (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

La présente invention concerne une structure d'encapsulation de puce à niveau de tranche et son procédé de fabrication, comprenant une unité de puce ayant une première surface et une seconde surface disposées à l'opposé l'une de l'autre, et au moins une fenêtre de soudure destinée à un couplage électrique qui est disposée sur la première surface ; la seconde surface étant pourvue d'une structure TSV connectée à la fenêtre de soudure, la structure TSV comprenant un trou traversant pénétrant à travers la première surface et la seconde surface, et une fente disposée sur la seconde surface, la distance entre les bords de la fente et les bords de la seconde surface étant supérieure à 10 µm. Le progrès obtenu par rapport à l'état de la technique améliore la résistance structurelle de la puce.
PCT/CN2018/079447 2017-03-21 2018-03-19 Structure d'encapsulation de puce à niveau de tranche et son procédé de fabrication WO2018171547A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201710171067.5A CN107068652A (zh) 2017-03-21 2017-03-21 晶圆级芯片封装结构及封装方法
CN201710171067.5 2017-03-21

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Publication Number Publication Date
WO2018171547A1 true WO2018171547A1 (fr) 2018-09-27
WO2018171547A9 WO2018171547A9 (fr) 2019-01-10

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CN (1) CN107068652A (fr)
TW (1) TWI669798B (fr)
WO (1) WO2018171547A1 (fr)

Cited By (1)

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CN119560392A (zh) * 2025-01-21 2025-03-04 中科华艺(天津)科技有限公司 一种在芯片同一焊窗上打多根线的方法及封装结构

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CN107068652A (zh) * 2017-03-21 2017-08-18 苏州迈瑞微电子有限公司 晶圆级芯片封装结构及封装方法

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CN103474365A (zh) * 2013-09-04 2013-12-25 惠州硕贝德无线科技股份有限公司 一种半导体封装方法
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US20150255499A1 (en) * 2014-03-07 2015-09-10 Xintec Inc. Chip package and method of fabricating the same
CN105047628B (zh) * 2015-06-05 2017-08-22 苏州迈瑞微电子有限公司 晶圆级芯片tsv封装结构及其封装方法
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US20100007030A1 (en) * 2008-07-10 2010-01-14 Oki Semiconductor Co., Ltd. Semiconductor device, method for manufacturing semiconductor device, method for manufacturing semiconductor package
CN103400808A (zh) * 2013-08-23 2013-11-20 苏州晶方半导体科技股份有限公司 影像传感器的晶圆级封装结构及封装方法
CN103474365A (zh) * 2013-09-04 2013-12-25 惠州硕贝德无线科技股份有限公司 一种半导体封装方法
CN107068652A (zh) * 2017-03-21 2017-08-18 苏州迈瑞微电子有限公司 晶圆级芯片封装结构及封装方法
CN206650071U (zh) * 2017-03-21 2017-11-17 苏州迈瑞微电子有限公司 晶圆级芯片封装结构

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN119560392A (zh) * 2025-01-21 2025-03-04 中科华艺(天津)科技有限公司 一种在芯片同一焊窗上打多根线的方法及封装结构

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TWI669798B (zh) 2019-08-21
TW201901910A (zh) 2019-01-01
CN107068652A (zh) 2017-08-18
WO2018171547A9 (fr) 2019-01-10

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