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WO2018177041A1 - Procédé et appareil pour sauvergarder et recombiner un fragment de message, et support de stockage informatique - Google Patents

Procédé et appareil pour sauvergarder et recombiner un fragment de message, et support de stockage informatique Download PDF

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Publication number
WO2018177041A1
WO2018177041A1 PCT/CN2018/076322 CN2018076322W WO2018177041A1 WO 2018177041 A1 WO2018177041 A1 WO 2018177041A1 CN 2018076322 W CN2018076322 W CN 2018076322W WO 2018177041 A1 WO2018177041 A1 WO 2018177041A1
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WIPO (PCT)
Prior art keywords
packet
fragment
ram
bundle group
sequence number
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PCT/CN2018/076322
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English (en)
Chinese (zh)
Inventor
李向文
何波
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中兴通讯股份有限公司
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Publication of WO2018177041A1 publication Critical patent/WO2018177041A1/fr

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04W—WIRELESS COMMUNICATION NETWORKS
    • H04W4/00—Services specially adapted for wireless communication networks; Facilities therefor
    • H04W4/02—Services making use of location information
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/90—Buffering arrangements
    • H04L49/9057—Arrangements for supporting packet reassembly or resequencing
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/90—Buffering arrangements
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/90—Buffering arrangements
    • H04L49/9063—Intermediate storage in different physical parts of a node or terminal
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04W—WIRELESS COMMUNICATION NETWORKS
    • H04W4/00—Services specially adapted for wireless communication networks; Facilities therefor

Definitions

  • Embodiments of the present invention relate to, but are not limited to, the field of data communications, and in particular, to a method, an apparatus, and a computer storage medium for packet fragment storage and reassembly.
  • multi-link bundling is a logical channel, and techniques for increasing bandwidth and improving stability are often used in internal and underlying transmissions of devices.
  • link aggregation technology MLPPP (Multilink PPP) uses link aggregation technology to bundle multiple PPP (Point-to-Point Protocol) services to provide greater bandwidth while one of the links appears. When the problem occurs, it does not affect other links, ensuring its stability.
  • each link In the traditional design, when multiple bundles and multiple links are to be reorganized, it is common practice for each link to require a RAM (Random-Access Memory) to store the corresponding data.
  • the serial number related information is compared with the serial number of all links in the same bundle group to find the minimum value, and the minimum value is sorted to the sorted queue, and the ordered fragments are finally sorted. According to the package start position and end position, the complete message is assembled.
  • Embodiments of the present invention provide a method, a device, and a computer storage medium for packet fragment storage and reorganization, so as to reduce dependence on system RAM resources.
  • the embodiment of the invention provides a method for packet fragment storage, including:
  • the information of the message fragment is stored in an address corresponding to the bundle group number of the packet fragment in the four RAMs.
  • An embodiment of the present invention further provides an apparatus for packet fragment storage, including: a specified storage unit and four RAMs, wherein
  • the designated storage unit is configured to store data of the received packet fragmentation
  • the four RAMs are configured to store the information of the message fragmentation in an address corresponding to the bundle group number of the packet fragment.
  • the embodiment of the invention further provides a method for reassembling a message fragment, comprising:
  • the data of the packet fragment is stored in a designated storage unit, and the packet is stored in an address corresponding to the bundle group number of the packet fragment in the four RAMs.
  • the information of the packet fragment is read from the four RAMs from the first serial number of the packet to be grouped for packet processing.
  • the embodiment of the invention further provides an apparatus for packet fragmentation and reorganization, comprising:
  • the storage module is configured to: after receiving the packet fragmentation, store the data of the packet fragment in a specified storage unit, and store the data in an address corresponding to the bundle group number of the packet fragment in four RAMs respectively. Information about the fragmentation of the message;
  • the processing module when configured as a group package, starts from the first serial number of the to-be-grouped packet, and reads information of the packet fragment from the four RAMs to perform packet processing.
  • the embodiment of the present invention further provides a computer storage medium, where the computer storage medium stores computer executable instructions, and the computer executable instructions are used to execute the method for storing message fragments according to the embodiment of the present invention; or,
  • the computer executable instructions are used to perform the method for packet fragmentation and reassembly according to the embodiment of the present invention.
  • An embodiment of the present invention further provides an apparatus for packet fragment storage, comprising a memory, a processor, and a computer program stored on the memory and operable on the processor, the processor implementing the program to implement the present invention The method for packet fragment storage described in the embodiment.
  • An embodiment of the present invention further provides an apparatus for reassembling a message fragment, including a memory, a processor, and a computer program stored on the memory and operable on the processor, where the processor implements the present invention when executing the program
  • the method for packet fragmentation and reorganization described in the embodiment including a memory, a processor, and a computer program stored on the memory and operable on the processor, where the processor implements the present invention when executing the program The method for packet fragmentation and reorganization described in the embodiment.
  • the method, device and computer storage medium for packet fragment storage and reorganization provided by the embodiments of the present invention can reduce the dependency on the system RAM resources, thereby ensuring the system achievability.
  • FIG. 1 is a schematic diagram of a conventional multi-Bundle multi-Link packet fragmentation reorganization manner
  • FIG. 2 is a flowchart of a method for packet fragment storage according to an embodiment of the present invention
  • FIG. 3 is a schematic diagram of a multi-Bundle multi-Link packet fragmentation recombination state according to an embodiment of the present invention
  • FIG. 4 is a flowchart of a method for packet fragmentation and recombination according to Embodiment 2 of the present invention.
  • FIG. 5 is a flowchart of a method for packet fragmentation and recombination according to Embodiment 2 of the present invention.
  • FIG. 6 is a schematic diagram of an apparatus for packet fragment storage according to an embodiment of the present invention.
  • FIG. 7 is a schematic diagram of an apparatus for packet fragmentation and reassembly according to an embodiment of the present invention.
  • FIG. 2 is a flowchart of a method for packet fragment storage according to an embodiment of the present invention. As shown in FIG. 2, the method in this embodiment includes the following steps:
  • step S12 the method may include:
  • m represents the number of links
  • n represents the number of bundled groups
  • t represents the number of serial numbers that can be supported
  • s represents the serial number value.
  • bit width, t and s are related.
  • the sequence number normally received does not exceed the value of the last sequence number plus t. Therefore, the embodiment does not need to support a large number of serial numbers.
  • the depth of the four sets of RAM is n, and the corresponding addresses represent the current bundle group number.
  • the multi-bundle group shares one RAM, so that the RAM resources are not greatly increased by the number of bundle groups.
  • RAM0 indicates whether there is a slice in the corresponding serial number, and the bit width is t.
  • the RAM1 indicates the B/E (slice start/end) flag of each slice and the first sequence number value of the bundle group to be the packet, and the bit width is 2t+s;
  • RAM2 stores the length corresponding to each serial number, and sets the RAM bit width according to the maximum fragment length in the system divided by the DDR (Double Data Rate) read/write Burst (burst) length, such as the maximum score in the system.
  • the chip length is 1024B, and the Burst length is 32B, then the RAM bit width is 5, and the bit width is 5*t;
  • the RAM 3 stores the current expected value sequence number of each bundle (ie, the next arriving sequence number), and the bit width is s.
  • FIG. 3 A method for packet fragment storage provided in this embodiment is shown in FIG. 3.
  • the embodiment of the present invention has a RAM resource.
  • Significant changes by replacing the 2048 FIFOs (First In First Out) in Figure 1 with 4 RAMs, greatly saving RAM resources.
  • FIG. 4 is a flowchart of a method for reassembling a packet according to an embodiment of the present invention. As shown in FIG. 4, the method in this embodiment includes the following steps:
  • the information about the packet fragmentation is stored in an address corresponding to the bundle group number of the packet fragment in the four RAMs, including: In the address corresponding to the bundle group number of the packet fragment, storing information indicating whether each sequence number has a fragment; and storing an indication in the address corresponding to the bundle group number of the packet fragment in the second RAM Decoding the start or end tag of the message fragment and the first sequence number value of the bundled group to be grouped; storing the newspaper in an address corresponding to the bundle group number of the packet fragment in the third RAM
  • the length of the fragment of the packet is stored in the address corresponding to the bundle group number of the packet fragment in the fourth RAM, and the sequence number of the next arrival of the bundle group to which the packet fragment belongs belongs.
  • the method further includes: if the serial number of the received packet fragment is the same as the sequence number that has been read and has not been successfully packaged, or detected If the next packet fragment is not received within the specified time, the packet fragmentation of all the received bundles is forcibly grouped.
  • the method further includes: if the sequence number of the packet fragment is greater than a sequence number of the next arrival read from the fourth RAM plus a first designated value, corresponding to the sequence number of the second specified value from all the RAMs starting from the first address of the message to the next arriving sequence number read from the fourth RAM Data elimination, the second specified value being less than or equal to the first specified value.
  • the four-letter RAM starts from a first address of the message, and the next arriving sequence number read from the fourth RAM is added with a second specified value.
  • Data elimination corresponding to the serial number including: if it is determined that the fragment corresponding to the serial number to be eliminated is a trailer fragment, then reading the corresponding packet first sequence number from the second RAM until the end of the packet Framing the serial number of the packet, and then clearing the information of the corresponding serial number in the first RAM, the second RAM and the third RAM, and writing the packet first serial number of the next packet into the In the second RAM, the next arriving sequence number value in the fourth RAM is incremented by one, and then the next sequence number to be eliminated is continued to be read.
  • the method further includes: if the received packet fragment is the header fragment of the next packet, the packet before the packet header fragment is received. Fragmentation performs mandatory grouping.
  • the group packet starts from the first serial number of the packet to be grouped, and the information of the packet fragment is read from the four RAMs according to the bundle group number of the packet fragment.
  • the packet processing includes: starting from the first serial number of the to-be-grouped packet to the end-of-packet serial number, and sequentially reading the length of the packet fragment from the four RAMs, according to the sequence number of the packet fragment and the packet score.
  • the length of the slice is read from the specified storage unit to read the data of the corresponding packet fragment.
  • FIG. 5 is a flowchart of a method for reassembling a packet according to an embodiment of the present invention. As shown in FIG. 5, the embodiment includes the following steps:
  • Step S101 Being in an idle state.
  • Step S102 It is determined whether the next packet fragment is received after the specified time is exceeded. If the next packet fragment is not received within the specified time, the process proceeds to step S116, otherwise, the process proceeds to step 103.
  • the timeout mechanism is controlled by a timer, and the specific size can be set according to the respective system.
  • the working principle of the timer is that the new serial number satisfies the expected value, or the timer is cleared during the clearing process in step S105. Cleared, only when the serial number is no longer coming or does not satisfy the clear watermark, and the serial number in the RAM has not been read, the timeout will be triggered, avoiding the prior art, when the expected value serial number has not come. When waiting, increase the cache resources.
  • the clear water line is set according to the system requirements. It is assumed that one Bundle is bundled with 32 links. Therefore, according to the normal situation, the maximum value of the two serial numbers before and after the same link is 63, and the water line can be cleared.
  • Setting 128, of course, can also be other values, such as 256, etc., to prevent the bandwidth from being uneven in some cases, resulting in an excessive difference between the two serial numbers before and after the same Link.
  • Step S103 determining whether a new packet fragment is received, and if so, storing the packet fragment data in the DDR, writing the packet fragmentation information into the four RAMs, and detecting the reception
  • the received message fragment is a packet tail fragment, and the sequence number is equal to the expected sequence number stored in the RAM 3. Then, all the information of the to-be-packaged packets in the four RAMs is read out, and the process proceeds to step S104. Otherwise, the process proceeds to step S101. .
  • Step S104 It is judged whether the serial number of the currently received message fragment is the same as the sequence number of the unpacked packet read out by the RAM0. If yes, the process proceeds to step S116, otherwise, the process proceeds to step S105.
  • Step S105 It is judged whether the serial number of the currently received message fragment is larger than the expected value serial number read out in the RAM 3 plus the clear watermark value. If yes, the process proceeds to step S111, otherwise, the process proceeds to step S106.
  • Step S106 It is judged whether the serial number of the currently received message fragment is equal to the expected value read out in the RAM 3, and if yes, the process proceeds to step S107, otherwise, the process proceeds to step S117.
  • Step S107 It is judged whether the packet position flag of the currently received message fragment is E (message end flag), and if yes, the process proceeds to step S108, otherwise, the process proceeds to step S109.
  • Step S108 Start the group package, start from the packet first serial number read out from the RAM1, continue until the serial number of the current E, and group the related serial number information read out in the RAM1, RAM2, and RAM3, and assemble the packet. After the completion, write all the serial number indication marks of the packet in RAM0 to 0, write B in the RAM1, write 0 in the RAM2, and update the first serial number value of the next packet to the RAM1, and proceed to step S109.
  • Step S109 The expected value serial number value is incremented by one, written in the RAM 3, and proceeds to step S110.
  • Step S110 Whether the next serial number in RAM0 is also present, and if yes, the process proceeds to step S107, and if no, the process proceeds to step S117.
  • Step S111 Start clearing the lost serial number.
  • serial number in the RAM is cleared from the first address of the message to the desired value plus 32. If yes, the process proceeds to step S110. Otherwise, the process proceeds to step S112.
  • the 32 in this is based on the assumption that a Bundle bundles 32 links in the current system, so it can be set to 32.
  • Step S112 Whether the packet position flag of the currently cleared serial number is E (message end tag) or the packet position of the next serial number is marked as B (message start tag), and if so, the expected value in RAM3 is incremented by 1, entering In step S113, if no, the process proceeds to step S111.
  • Step S113 Start the group package, start from the packet first serial number read out from the RAM1, continue until the serial number of the current E or continue to the position of the previous serial number whose serial number is the B mark, and simultaneously set the RAM0 and the RAM1.
  • the serial number indication mark, B/E attribute, and message length are all read out and given to the respective serial numbers.
  • all the serial number indication marks of the package in RAM0 are written to 0, and B/E is written in RAM1.
  • the length of the message in RAM2 is written as 0, and the value of the first serial number of the next packet is updated to the RAM1, and the flow proceeds to step S115.
  • Step S114 The expected value serial number value is incremented by 1, written in the RAM 3, and proceeds to step S115.
  • Step S115 Is the next serial number in RAM0 also present, and if yes, the process proceeds to step S112, otherwise, the process proceeds to step S117.
  • Step S116 Forcibly grouping the packets, and clearing all the existing serial numbers, that is, the RAM0 indicates the serial number mark, the B/E of the RAM1, and the length of the RAM2 are all written with 0; and the last serial number in the process of the timeout group is added.
  • 1 is the first serial number value of the next group packet in the RAM 1, and the expected value in the RAM 3 is also equal to the next packet first sequence number value.
  • Step S117 The end of the package or the new serial number has been stored.
  • FIG. 6 is a schematic diagram of an apparatus for packet fragment storage according to an embodiment of the present invention.
  • the apparatus of this embodiment includes: a storage unit and four RAMs (including: RAM0, RAM1, RAM2, and RAM3). ,among them,
  • the storage unit is configured to store data of the received packet fragmentation
  • the four RAMs are configured to store the information of the message fragmentation in an address corresponding to the bundle group number of the packet fragment.
  • the RAM0 is configured to store, in an address corresponding to the bundle group number of the packet fragment, information indicating whether each sequence number has a fragment;
  • the RAM1 is configured to store, in an address corresponding to the bundle group number of the packet fragment, information indicating a start or end mark of the packet fragmentation and a first sequence number value of the bundled group to be grouped packet;
  • the RAM2 is configured to store the length of the packet fragment in an address corresponding to the bundle group number of the packet fragmentation
  • the RAM3 is configured to store, in an address corresponding to the bundle group number of the packet fragment, a sequence number of the next arrival of the bundle group to which the packet fragment belongs.
  • the apparatus for packet fragment storage in this embodiment can save RAM resources and reduce dependence on system RAM resources, thereby ensuring system achievability.
  • the apparatus for storing the packet fragmentation in the foregoing embodiment is only illustrated by the division of each of the foregoing program modules. In actual applications, the foregoing processing may be allocated according to requirements. It is completed by different program modules, that is, the internal structure of the device is divided into different program modules to complete all or part of the processing described above.
  • the apparatus for packet fragment storage provided by the foregoing embodiment is the same as the method embodiment of the packet fragment storage, and the specific implementation process is described in detail in the method embodiment, and details are not described herein again.
  • FIG. 7 is a schematic diagram of an apparatus for packet fragmentation and reorganization according to an embodiment of the present invention. As shown in FIG. 7, the apparatus of this embodiment includes:
  • the storage module is configured to: after receiving the packet fragmentation, store the data of the packet fragment in a specified storage unit, and store the data in an address corresponding to the bundle group number of the packet fragment in four RAMs respectively. Information about the fragmentation of the message;
  • the processing module when configured as a group package, starts from the first serial number of the to-be-grouped packet, and reads information of the packet fragment from the four RAMs to perform packet processing.
  • the storage module includes the designated storage unit and four RAMs, where
  • the designated storage unit is configured to store data of the received packet fragmentation
  • the four RAMs are configured to store the information of the message fragment in an address corresponding to the bundle group number of the packet fragment, wherein the four RAMs include: RAM0, RAM1, RAM2, and RAM3;
  • the RAM0 is configured to store, in an address corresponding to the bundle group number of the packet fragment, information indicating whether each sequence number has a fragment;
  • the RAM1 is configured to store, in an address corresponding to the bundle group number of the packet fragment, information indicating a start or end mark of the packet fragmentation and a first sequence number value of the bundled group to be grouped packet;
  • the RAM2 is configured to store, in an address corresponding to the bundle group number of the packet fragment, a length of the packet fragment.
  • the RAM3 is configured to store, in an address corresponding to the bundle group number of the packet fragment, a sequence number of the next arrival of the bundle group to which the packet fragment belongs.
  • the processing module is configured to receive the same serial number of the packet fragment as the serial number that has been read out and has not been successfully packaged, or that the specified time is not received. If the next packet is fragmented, the packet fragmentation of all the received bundles is forcibly grouped.
  • the processing module is configured to receive, as the received message fragment, a sequence number greater than a next arriving sequence number read from the fourth RAM, plus a first specified value, And erasing data corresponding to the sequence number of the next arriving sequence plus the sequence number of the second specified value from the first address of the message in the all the RAM to the fourth RAM, The second specified value is less than or equal to the first specified value.
  • the processing module is configured to: if it is determined that the fragment corresponding to the sequence number to be eliminated is a trailer fragment, start reading the corresponding packet first sequence number from the second RAM. Until the sequence number of the end-of-packet fragment is grouped, and then the information of the corresponding serial number in the first RAM, the second RAM, and the third RAM is cleared, and the packet sequence of the next packet is The number is written into the second RAM, the next arriving sequence number value in the fourth RAM is incremented by 1, and then the next sequence number to be eliminated is continued to be read.
  • the processing module is configured to receive the packet header after receiving the packet fragmentation, and if the received packet fragment is the header fragment of the next packet, The previous packet fragmentation is forcibly grouping.
  • the processing module is configured to: when the packet is configured as a group packet, start from the first serial number of the packet to be grouped, and read information of the packet fragment from the four RAMs to perform packet processing, including: The length of the message fragment is read from the four RAMs in sequence from the first sequence number of the packet to be packaged until the end sequence number, according to the sequence number of the packet fragment and the length of the packet fragment. The data of the corresponding packet fragment is read in the specified storage unit for grouping.
  • the apparatus for reassembling the message fragment in the foregoing embodiment is only illustrated by the division of each of the foregoing program modules. In actual application, the foregoing processing may be allocated according to requirements. It is completed by different program modules, that is, the internal structure of the device is divided into different program modules to complete all or part of the processing described above. In addition, the apparatus for reassembling the packet fragmentation and the method for reassembling the packet fragment are provided in the same concept. The specific implementation process is described in the method embodiment, and details are not described herein again.
  • An embodiment of the present invention further provides an apparatus for packet fragment storage, including a memory, a processor, and a computer program stored on the memory and operable on the processor, where the processor implements: receiving After the packet is fragmented, the data of the packet fragment is stored in the specified storage unit; and the packet fragment is stored in an address corresponding to the bundle group number of the packet fragment in the four RAMs. Information.
  • the processor executes the program, the information corresponding to the bundle group number of the packet fragment in the first RAM is stored, and information indicating whether each sequence number has a fragment is stored; And storing, in an address corresponding to the bundle group number of the packet fragment in the second RAM, information indicating a start or end mark of the packet fragment and a first sequence number value of the bundled group to be grouped packet; And storing, in an address corresponding to the bundle group number of the packet fragment in the third RAM, a length of the packet fragment; and an address corresponding to the bundle group number of the packet fragment in the fourth RAM And storing a sequence number of the next arrival of the bundle group to which the packet fragment belongs.
  • the memory can be either volatile memory or non-volatile memory, and can include both volatile and nonvolatile memory.
  • the non-volatile memory may be a Read Only Memory (ROM), a Programmable Read-Only Memory (PROM), or an Erasable Programmable Read (EPROM). Only Memory), Electrically Erasable Programmable Read-Only Memory (EEPROM), Ferromagnetic Random Access Memory (FRAM), Flash Memory, Magnetic Surface Memory , CD-ROM, or Compact Disc Read-Only Memory (CD-ROM); the magnetic surface memory can be a disk storage or a tape storage.
  • the volatile memory can be a random access memory (RAM) that acts as an external cache.
  • RAM Random Access Memory
  • SRAM Static Random Access Memory
  • SSRAM Synchronous Static Random Access Memory
  • SSRAM Dynamic Random Access
  • DRAM Dynamic Random Access Memory
  • SDRAM Synchronous Dynamic Random Access Memory
  • DDRSDRAM Double Data Rate Synchronous Dynamic Random Access Memory
  • ESDRAM enhancement Enhanced Synchronous Dynamic Random Access Memory
  • SLDRAM Synchronous Dynamic Random Access Memory
  • DRRAM Direct Memory Bus Random Access Memory
  • the method disclosed in the foregoing embodiments of the present invention may be applied to a processor or implemented by a processor.
  • the processor may be an integrated circuit chip with signal processing capabilities.
  • each step of the above method may be completed by an integrated logic circuit of hardware in a processor or an instruction in a form of software.
  • the above processor may be a general purpose processor, a digital signal processor (DSP), or other programmable logic device, discrete gate or transistor logic device, discrete hardware component, or the like.
  • DSP digital signal processor
  • the processor may implement or perform the methods, steps, and logic blocks disclosed in the embodiments of the present invention.
  • a general purpose processor can be a microprocessor or any conventional processor or the like.
  • the steps of the method disclosed in the embodiment of the present invention may be directly implemented as a hardware decoding processor, or may be performed by a combination of hardware and software modules in the decoding processor.
  • the software module can be located in a storage medium, the storage medium being located in the memory, the processor reading the information in the memory, and completing the steps of the foregoing methods in combination with the hardware thereof.
  • an embodiment of the present invention further provides a computer storage medium, such as a memory including a computer program, which may be executed by a processor of a device for message slice storage to perform the steps of the foregoing method.
  • the computer storage medium may be a memory such as FRAM, ROM, PROM, EPROM, EEPROM, Flash Memory, magnetic surface memory, optical disk, or CD-ROM; or may be various devices including one or any combination of the above memories.
  • the embodiment of the present invention provides a computer storage medium, where the computer storage medium stores computer executable instructions, and the computer executable instructions are used to perform: after receiving the message fragment, the message is fragmented.
  • the data is stored in the designated storage unit; the information of the message fragment is stored in an address corresponding to the bundle group number of the packet fragment in the four RAMs.
  • the computer executable instructions are configured to: store, in an address corresponding to the bundle group number of the packet fragment in the first RAM, information indicating whether each sequence number has a fragment; And storing, in the address corresponding to the bundle group number of the packet fragment, the information indicating the start or end mark of the packet fragment and the first sequence number value of the bundle group to be grouped; The length of the packet fragment is stored in the address corresponding to the bundle group number of the packet fragment in the third RAM; and the address corresponding to the bundle group number of the packet fragment in the fourth RAM And storing the sequence number of the next arrival of the bundle group to which the message fragment belongs.
  • An embodiment of the present invention further provides an apparatus for reassembling a message fragment, including a memory, a processor, and a computer program stored on the memory and operable on the processor, where the processor implements the program: receiving After the packet is fragmented, the data of the packet fragment is stored in a specified storage unit, and the packet fragment is stored in an address corresponding to the bundle group number of the packet fragment in the four RAMs. The information of the packet fragment is read from the four RAMs for group packet processing starting from the first serial number of the packet to be grouped.
  • the processor executes the program, the information corresponding to the bundle group number of the packet fragment in the first RAM is stored, and information indicating whether each sequence number has a fragment is stored; And storing, in an address corresponding to the bundle group number of the packet fragment in the second RAM, information indicating a start or end mark of the packet fragment and a first sequence number value of the bundled group to be grouped packet; And storing, in the third RAM, an address of the packet fragment corresponding to the bundle group number of the packet fragment; in the address corresponding to the bundle group number of the packet fragment in the fourth RAM And storing a sequence number of the next arrival of the bundle group to which the packet fragment belongs.
  • the serial number of the received message fragment is the same as the sequence number that has been read out and has not been successfully packaged, or is detected to exceed the specified time. If the next packet fragment is not received, the packet fragmentation of all the received bundles is forcibly grouped.
  • the processor executes the program, after receiving the message fragment, if the sequence number of the message fragment is greater than the next arrival from the fourth RAM. Adding the first specified value to the serial number, starting from the first address of the message in all the RAMs, and adding the second specified value to the next arriving sequence number read from the fourth RAM. The data corresponding to the serial number is eliminated, and the second specified value is less than or equal to the first specified value.
  • the processor executes the program, if it is determined that the fragment corresponding to the sequence number to be eliminated is a trailer fragment, the corresponding packet header sequence is read from the second RAM. The number starts until the serial number of the end-of-packet fragment is grouped, and then the information of the corresponding serial number in the first RAM, the second RAM and the third RAM is cleared, and the packet of the next packet is The first serial number is written into the second RAM, the next arriving sequence number value in the fourth RAM is incremented by 1, and then the next serial number to be eliminated is continued to be read.
  • the processor executes the program, after receiving the packet fragmentation, if the received packet fragment is the header fragment of the next packet, the packet header is received. The packet fragmentation before the fragmentation is forced to be packaged.
  • the length of the message fragment is read from the four RAMs in sequence, starting from the first serial number of the packet to be grouped until the end sequence number, according to The sequence number of the packet fragment and the length of the packet fragment are read from the specified storage unit to read the data of the corresponding packet fragment.
  • an embodiment of the present invention further provides a computer storage medium, such as a memory including a computer program, which may be executed by a processor of a device for packet fragmentation to complete the steps of the foregoing method.
  • the computer storage medium may be a memory such as FRAM, ROM, PROM, EPROM, EEPROM, Flash Memory, magnetic surface memory, optical disk, or CD-ROM; or may be various devices including one or any combination of the above memories.
  • the embodiment of the present invention provides a computer storage medium, where the computer storage medium stores computer executable instructions, and the computer executable instructions are used to perform: after receiving the message fragment, the message is fragmented.
  • the data is stored in the designated storage unit, and the information of the packet fragmentation is stored in an address corresponding to the bundle group number of the packet fragment in the four RAMs; the first serial number of the packet to be grouped when the packet is grouped Initially, the information of the message fragment is read from the four RAMs for packet processing.
  • the computer executable instructions are configured to: store, in an address corresponding to the bundle group number of the packet fragment in the first RAM, information indicating whether each sequence number has a fragment; And storing, in the address corresponding to the bundle group number of the packet fragment, the information indicating the start or end mark of the packet fragment and the first sequence number value of the bundle group to be grouped;
  • the length of the packet fragment is stored in an address corresponding to the bundle group number of the packet fragment in the third RAM, and is stored in an address corresponding to the bundle group number of the packet fragment in the fourth RAM.
  • the sequence number of the next arrival of the bundle group to which the packet fragment belongs are configured to: store, in an address corresponding to the bundle group number of the packet fragment in the first RAM, information indicating whether each sequence number has a fragment; And storing, in the address corresponding to the bundle group number of the packet fragment, the information indicating the start or end mark of the packet fragment and the first sequence number value of the bundle group to be grouped;
  • the length of the packet fragment is stored in
  • the computer executable instructions are configured to: if the serial number of the received message fragment is the same as the serial number that has been read and has not been successfully packaged, or is detected to be more than the specified time. After receiving the next packet fragmentation, the packet fragmentation of all the received bundles is forcibly grouped.
  • the computer executable instructions are configured to: after receiving the message fragment, if the sequence number of the message fragment is greater than the next arrival sequence read from the fourth RAM Adding a first specified value to the sequence of all the RAMs from the first address of the message to the next arriving sequence number read from the fourth RAM plus a second specified value The data corresponding to the number is eliminated, and the second specified value is less than or equal to the first specified value.
  • the computer executable instructions are configured to: if it is determined that the slice corresponding to the serial number to be eliminated is a trailer fragment, the corresponding packet first sequence number is read from the second RAM. Starting to assemble the serial number of the end-of-packet fragment, and then clearing the information of the corresponding serial number in the first RAM, the second RAM, and the third RAM, and the packet header of the next packet The serial number is written into the second RAM, the next arriving sequence number value in the fourth RAM is incremented by 1, and then the next sequence number to be eliminated is continued to be read.
  • the computer executable instructions are configured to: after receiving the message fragmentation, if the received message fragment is the header fragment of the next message, the packet header is received. The packet fragment before the slice is forced to be packaged.
  • the computer executable instructions are configured to: read the length of the message fragment from the four RAMs in sequence, starting from the first serial number of the packet to be grouped until the end sequence number, according to the report The sequence number of the fragment and the length of the packet fragment are read from the specified storage unit to read the data of the corresponding packet fragment.
  • the method and the device provided by the embodiments of the present invention can greatly reduce the occupation rate of the RAM resources under the premise of multi-bundle multi-link, and only need to pass 4 RAMs, and the address of each RAM is the bundle group number.
  • the main function of packet splicing and reassembly of multi-bundle group greatly saves RAM resources, brings more abundant resource space to the system, and enhances achievability.
  • the embodiment of the present invention can also quickly clear the discarded fragments by clearing the waterline when the serial number is lost, so that the expected value is gradually approached to the latest serial number, so that the service is quickly restored; the timeout mechanism of the embodiment of the present invention can also save the RAM. Resources: The timeout mechanism will only be triggered if the fragmentation in the RAM has not been grouped out and the new serial number does not satisfy the clear watermark. It does not need to wait for the expected value sequence number to arrive, and all the non-conformities are expected. The serial number is specially cached, which wastes the cache resources. The timeout mechanism also ensures that the data does not stay in the RAM, ensuring the smooth flow of the business.
  • the disclosed apparatus and method may be implemented in other manners.
  • the device embodiments described above are merely illustrative.
  • the division of the unit is only a logical function division.
  • there may be another division manner such as: multiple units or components may be combined, or Can be integrated into another system, or some features can be ignored or not executed.
  • the coupling, or direct coupling, or communication connection of the components shown or discussed may be indirect coupling or communication connection through some interfaces, devices or units, and may be electrical, mechanical or other forms. of.
  • the units described above as separate components may or may not be physically separated, and the components displayed as the unit may or may not be physical units, that is, may be located in one place or distributed to multiple network units; Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of the embodiment.
  • each functional unit in each embodiment of the present invention may be integrated into one processing unit, or each unit may be separately used as one unit, or two or more units may be integrated into one unit;
  • the unit can be implemented in the form of hardware or in the form of hardware plus software functional units.
  • the foregoing program may be stored in a computer readable storage medium, and the program is executed when executed.
  • the foregoing steps include the steps of the foregoing method embodiments; and the foregoing storage medium includes: a removable storage device, a ROM, a RAM, a magnetic disk, or an optical disk, and the like, which can store program codes.
  • the above-described integrated unit of the present invention may be stored in a computer readable storage medium if it is implemented in the form of a software function module and sold or used as a standalone product.
  • the technical solution of the embodiments of the present invention may be embodied in the form of a software product in essence or in the form of a software product stored in a storage medium, including a plurality of instructions.
  • a computer device (which may be a personal computer, server, or network device, etc.) is caused to perform all or part of the methods described in various embodiments of the present invention.
  • the foregoing storage medium includes various media that can store program codes, such as a mobile storage device, a ROM, a RAM, a magnetic disk, or an optical disk.
  • the technical solution of the embodiment of the present invention can greatly reduce the occupation rate of the RAM resources under the premise of multi-bundle multi-link, and only needs to pass 4 RAMs, and the address of each RAM is the bundle group number, so that the multi-bundle group can be realized.
  • the main function of message fragmentation reorganization which greatly saves RAM resources, brings more resource space to the system, and enhances the achievability.

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)

Abstract

L'invention concerne un procédé et un appareil pour sauvegarder un fragment de message. Le procédé consiste à : recevoir un fragment de message et sauvegarder des données dans le fragment de message dans une unité de stockage spécifiée ; et stocker respectivement des informations concernant le fragment de message à des adresses dans quatre mémoires à accès aléatoire (RAM) correspondant à un numéro de groupe lié du fragment de message. L'invention concerne un procédé et un appareil pour recombiner un fragment de message, ainsi qu'un support de stockage informatique.
PCT/CN2018/076322 2017-03-27 2018-02-11 Procédé et appareil pour sauvergarder et recombiner un fragment de message, et support de stockage informatique WO2018177041A1 (fr)

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