WO2018181265A1

WO2018181265A1 - Liquid crystal display device

Info

Publication number: WO2018181265A1
Application number: PCT/JP2018/012335
Authority: WO
Inventors: 諒米林; 隆之西山; 示寛横野; 耕平田中; 吉田　圭介
Original assignee: シャープ株式会社
Priority date: 2017-03-30
Filing date: 2018-03-27
Publication date: 2018-10-04

Abstract

Provided is a technique by which decrease of the display quality is able to be suppressed even in cases where a wiring line is arranged within a pixel. A liquid crystal display device according to the present invention is provided with: an active matrix substrate 10; a counter substrate that is arranged so as to face the active matrix substrate 10; and a liquid crystal layer that is held between the active matrix substrate and the counter substrate. The active matrix substrate 10 is provided with: a plurality of pixels PIX, each of which has a light-blocking region Pb and a non-light-blocking region Pa, while being provided with pixel electrodes 210a, 210b that have a slit 214 in the non-light-blocking region Pa; and a wiring line 13 which is arranged in a pixel region. The liquid crystal molecules in the liquid crystal layer are driven in a horizontal alignment mode. Each one of some pixels PIXb among the plurality of pixels has a low transmission region 2141b in which the transmittance within a slit 214b in the pixel is lower than the transmittance within a slit 214a in each of the other pixels PIXa. The wiring line 13 is arranged in the low transmission regions 2141b of the some pixels PIXb.

Description

Liquid crystal display

The present invention relates to a liquid crystal display device.

Japanese Patent Application Laid-Open No. 2002-107730 discloses a technique for arranging a wiring at a position that becomes a boundary between domains in a liquid crystal display device having pixels composed of a plurality of domains having different alignment directions of liquid crystal molecules when a voltage is applied to the liquid crystal molecules. Is disclosed. Since a dark line is generated at the domain boundary, a decrease in transmittance when the wiring is arranged in the pixel is reduced by arranging the wiring at the domain boundary.

By the way, the wiring arranged in the non-light-shielding region (opening) of the pixel may vary in wiring width and wiring position in the process of forming the wiring. As the width and position of the wiring vary, the transmittance varies between pixels in which such a wiring is arranged. For example, when the wiring is arranged in a pixel of a specific color, the transmittance of the pixel in which the wiring is arranged varies, resulting in a color different from the original color and a phenomenon such as color shift may occur. Even when the wiring is arranged in pixels of different colors, the transmittance of the pixels in which the wiring is arranged varies, so that the balance of the transmittance of the entire pixel is lost and the display quality is deteriorated.

An object of the present invention is to provide a technique capable of suppressing a reduction in display quality even when wiring is arranged in a non-light-shielding region of a pixel.

A liquid crystal display device according to the present invention includes an active matrix substrate, a counter substrate disposed opposite to the active matrix substrate and including a light shielding member, and a liquid crystal layer sandwiched between the active matrix substrate and the counter substrate. A pixel electrode having a light shielding region shielded by the light shielding member and a non-light shielding region excluding the light shielding region, and having a slit in the non-light shielding region. A plurality of pixels each provided with a wiring disposed in a pixel region, the liquid crystal molecules in the liquid crystal layer are driven in a horizontal alignment mode, and each of some of the plurality of pixels is The transmittance in the slit of the pixel is lower than the transmittance in the slit of other pixels, Line is placed in the low transmission region at the part of the pixels.

According to the configuration of the present invention, it is possible to suppress deterioration in display quality even when wiring is arranged in a pixel.

FIG. 1 is a schematic diagram illustrating a schematic configuration of the liquid crystal display device according to the first embodiment. FIG. 2 is a schematic diagram showing a schematic configuration of the active matrix substrate shown in FIG. FIG. 3 is an enlarged schematic view of a part of the active matrix substrate 10 shown in FIG. FIG. 4A is an enlarged view of the pixel electrode shown in FIG. 4B is a schematic diagram illustrating the alignment direction of the liquid crystal molecules of the pixel illustrated in FIG. 3. FIG. 5 is a schematic diagram of pixel electrodes of installed pixels and non-installed pixels in the first embodiment. FIG. 6 is a schematic diagram illustrating a pixel according to a modified example of the first embodiment. FIG. 7A is a schematic diagram illustrating a schematic configuration of a part of pixels according to the second embodiment. FIG. 7B is a schematic diagram showing a low transmission region in the pixel shown in FIG. 7A. FIG. 8A is a schematic diagram of pixel electrodes of installed pixels and non-installed pixels in the second embodiment. FIG. 8B is a schematic diagram illustrating a non-installed pixel and a low transmission region of the installed pixel illustrated in FIG. 8A. FIG. 9A is an enlarged schematic view of a part of pixels of an active matrix substrate in a modification of the second embodiment. FIG. 9B is a schematic diagram showing an example of wiring arrangement different from FIG. 9A. FIG. 10 is an enlarged schematic view of a part of the pixels of the active matrix substrate in the third embodiment. FIG. 11 is a schematic diagram illustrating a schematic arrangement example of gate drivers provided on the active matrix substrate according to the fourth embodiment. FIG. 12 is a diagram illustrating an equivalent circuit of the gate driver shown in FIG. FIG. 13 is a timing chart when the gate driver shown in FIG. 12 drives the gate line. FIG. 14 is a schematic diagram showing an arrangement example of circuit elements of the gate driver shown in FIG. FIG. 15 is a schematic diagram illustrating a configuration example of a pixel provided with the circuit element, internal wiring, and control wiring of the gate driver illustrated in FIG. FIG. 16 is a schematic diagram of a part of pixels in the first modification, and illustrates the case where the wiring is a source line. FIG. 17 is a schematic diagram of some pixels in the second modification.

A liquid crystal display device according to an embodiment of the present invention includes an active matrix substrate, a counter substrate disposed opposite to the active matrix substrate and including a light shielding member, and sandwiched between the active matrix substrate and the counter substrate. The active matrix substrate includes a light shielding region shielded by the light shielding member and a non-light shielding region excluding the light shielding region, and a slit is formed in the non-light shielding region. A plurality of pixels each provided with a pixel electrode and a wiring arranged in the pixel region, wherein liquid crystal molecules in the liquid crystal layer are driven in a horizontal alignment mode, and a part of the plurality of pixels is Each pixel has a low transmission region in which the transmittance in the slit in the pixel is lower than the transmittance in the slit in other pixels A, the wiring, the in the part of the pixels are arranged in the low transmission region (first configuration).

According to the first configuration, the pixel electrode includes a pixel electrode having a slit in the non-light-shielding region, and the liquid crystal molecules are driven in the horizontal alignment mode. Some pixels have a low transmission region in which the transmittance in the slit of the pixel electrode of the pixel is lower than the transmittance in the slit of the pixel electrode of another pixel. The wiring is arranged in a low transmission region in some pixels. Therefore, even if there are variations in the width and position of the wiring, the transmittance between the pixels where the wiring is arranged is less likely to vary than in the case where the transmittance in the slits of the pixel electrodes of all the pixels is uniform. It is possible to reduce the deterioration of the overall display quality.

In the first configuration, the pixel electrode includes a first electrode and a second electrode, the slit is provided between the first electrode and the second electrode, and the wiring is It is substantially parallel to the extending direction, and the width of the slit in the some pixels is wider than the width of the slit in the other pixels, and the low transmission region in the some pixels is the first of the pixels. It is good also as including the area | region where the distance from 1 electrode and said 2nd electrode becomes a substantially intermediate | middle (2nd structure).

According to the first configuration, the low transmission region includes a region in which the distance from the first electrode and the second electrode is substantially in the middle. In the region that is approximately between the first electrode and the second electrode, the alignment regulating force due to the voltage applied to the liquid crystal molecules is weaker than the vicinity of the first electrode and the second electrode, and the first electrode and the second electrode The transmittance tends to be lower than in the vicinity of the second electrode. By making the slit width of some pixels wider than the slit width of other pixels, it is possible to widen the low transmission region where the alignment regulating force due to the voltage applied to the liquid crystal molecules is weakened in some pixels. . As a result, even if there is a variation in the width, position, etc. of the wiring, the transmittance between the pixels in which the wiring is arranged is difficult to vary, and a reduction in display quality such as a color shift can be reduced.

In the first configuration, an active matrix substrate, a counter substrate disposed opposite to the active matrix substrate and including a light shielding member, and a liquid crystal layer sandwiched between the active matrix substrate and the counter substrate are provided. In the liquid crystal display device, the active matrix substrate includes a plurality of pixels each provided with a pixel electrode and having a light shielding region shielded by the light shielding member and a non-light shielding region excluding the light shielding region, and a pixel region. A liquid crystal molecule in the liquid crystal layer is driven in a vertical alignment mode, and each of the plurality of pixels is aligned when the liquid crystal molecules are driven in the non-light-shielding region of the pixel. A plurality of alignment division regions having different directions, and a boundary between the plurality of alignment division regions is substantially parallel to a direction in which the wiring extends. The width of the boundary portion in some of the plurality of pixels is wider than the width of the boundary portion in other pixels, and the wiring is the non-light-shielding region of the some pixels. It is good also as arrange | positioning in the said boundary part in (3rd structure).

According to the third configuration, each pixel includes a boundary portion that is a boundary between a plurality of alignment division regions in the pixel and substantially parallel to the extending direction of the wiring. A dark line is generated at the boundary portion of the alignment division region, and the transmittance tends to decrease. By making the width of the boundary portion of some pixels substantially parallel to the extending direction of the wiring wider than that of the other pixels, the region where the dark line is generated becomes wider than the other pixels. The wiring is arranged in a region where dark lines of some pixels are generated. Therefore, compared to the case where the area where the dark line is generated in all pixels is uniform, even if the width and position of the wiring are varied, the transmittance between the pixels in which the wiring is arranged is less likely to vary, and display such as a color shift is displayed. Degradation can be reduced.

In any one of the first to third configurations, the active matrix substrate or the counter substrate further includes a common electrode disposed to face the pixel electrode in the plurality of pixels, and in the partial pixel The common electrode may have an opening substantially parallel to a direction in which the wiring extends in a position overlapping the wiring (fourth configuration).

According to the fourth configuration, the common electrode in some pixels is provided with an opening at a position overlapping the wiring. In some pixels, no voltage is applied to the portion where the opening is provided, and the alignment regulating force on the liquid crystal molecules is weakened. Therefore, the transmittance is likely to be lower in the portion where the opening is provided than in the other portions. As a result, even if there is a variation in the width, position, etc. of the wiring, the transmittance between the pixels in which the wiring is arranged is difficult to vary, and a reduction in display quality such as a color shift can be reduced.

In any one of the first to fourth configurations, the active matrix substrate further includes a plurality of gate lines, a plurality of source lines intersecting with the plurality of gate lines, and each of the plurality of gate lines. And a drive circuit that switches a corresponding one gate line to a selected state or a non-selected state according to a supplied control signal, and the drive circuit includes a drive circuit element including a plurality of switching elements. The drive circuit element may be disposed in the part of the pixels and connected to the wiring, and the wiring may supply the control signal to the drive circuit element connected to the wiring. Good (fifth configuration).

According to the fifth configuration, the drive circuit element of the drive circuit that drives the gate line and the wiring that supplies the control signal to the drive circuit element can be arranged in some pixels. And reduction in display quality can be reduced.

In any one of the first to fourth configurations, the active matrix substrate further includes a plurality of gate lines and a plurality of source lines intersecting the plurality of gate lines, and the pixel electrode of each pixel is , Connected to one gate line and one source line, and the wiring may be the one source line connected to a pixel electrode of a pixel in which the wiring is arranged (sixth configuration). .

According to the sixth configuration, since the source line connected to the pixel electrode of the pixel in which the wiring is arranged can be arranged in the pixel, the degree of freedom of arrangement of the elements provided in the pixel is increased, and the display Degradation can be reduced.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals and description thereof will not be repeated.

<First Embodiment>
FIG. 1 is a schematic diagram showing a schematic configuration of the liquid crystal display device according to the present embodiment. The liquid crystal display device 1 includes an active matrix substrate 10, a counter substrate 20, and a liquid crystal layer 30 sandwiched between these substrates. Although not shown, the liquid crystal display device 1 includes a pair of polarizing plates that sandwich the active matrix substrate 10 and the counter substrate 20, and includes a backlight on the active matrix substrate 10 side.

In the present embodiment, the liquid crystal molecules in the liquid crystal layer 30 are driven in a VA mode or a TN mode that is vertically aligned according to a voltage applied between the active matrix substrate 10 and the counter substrate 20.

The counter substrate 20 includes a common electrode, a black matrix (BM), and three color filters of red (R), green (G), and blue (B) (all not shown).

FIG. 2 is a schematic diagram showing a schematic configuration of the active matrix substrate 10. In the active matrix substrate 10, M (M: natural number) gate lines G (1) to G (M) are formed substantially in parallel at regular intervals from one end to the other end in the X-axis direction. Hereinafter, when the gate lines are not distinguished, they are referred to as gate lines G. In the active matrix substrate 10, a plurality of source lines S are formed so as to intersect with the gate lines G.

FIG. 3 is an enlarged schematic view of a part of the active matrix substrate 10. As shown in FIG. 3, a plurality of pixels PIX each having a pixel electrode 11 are formed on the active matrix substrate 10. The pixel PIX corresponds to one of the colors R, G, and B of the color filter in the counter substrate 20 and is arranged in the order of R, G, and B along the extending direction of the gate line G, for example.

Each pixel PIX has a light shielding region Pb covered with a black matrix provided on the counter substrate 20 and a non-light shielding region Pa (also referred to as an opening). The pixel electrode 11 is connected to the gate line G and the source line S through a thin film transistor 12 (TFT: Thin Film Transistor) (hereinafter referred to as a pixel TFT). The gate line G, the source line S, and the pixel TFT 12 are provided in the light shielding region Pb.

When the pixel TFT 12 is turned on, the data signal voltage supplied to the source line S is input to the pixel electrode 11 via the pixel TFT 12. A predetermined voltage is applied to the common electrode (not shown) in the counter substrate 20. The potential of the pixel PIX corresponds to the potential of the source line S, the capacitance between the pixel electrode 11 and the gate line G, and the pixel electrode 11 and the common electrode (not shown) according to the potential change of the gate line G. Controlled by the capacity of

Here, the structure of the pixel electrode 11 in this embodiment will be described. Hereinafter, the pixel electrode 11a of the left pixel PIXa shown in FIG. 3 will be described as an example, but the pixel electrodes 11 of other pixels also have the same structure. 4A is an enlarged view of the pixel electrode 11a shown in FIG. As shown in FIG. 4A, the pixel electrode 11a has a so-called fishbone shape including a trunk portion 111, a plurality of branch portions 112, a plurality of slits 113, and a contact portion 114.

The trunk portion 111 has a cross shape including a first trunk portion 111y parallel to the Y axis and a second trunk portion 111x parallel to the X axis.

The plurality of branch portions 112 are non-parallel to the trunk portion 111 and are arranged so as to be substantially line symmetric with respect to the trunk portion 111. Specifically, the branch portions 112 provided in the four regions (A to D) divided by the first trunk portion 111y and the second trunk portion 111x are branched portions 112 provided in the same region in the direction extending from the trunk portion 111. Is different from the branch portion 122 provided in another region.

The slit 113 is formed between the branch part 112 and the branch part 112 for each region. In this case, the orientation of the liquid crystal molecules in the pixel PIX is four directions (Da, Db, Dc, Dd) toward the trunk 111 along each slit 113, as shown in FIG. 4B. It has four domains with different directions.

Referring back to FIG. 3, a wiring 13 passing through the non-light-shielding region Pa is arranged in the pixel PIXb. The wiring 13 is disposed so as to be substantially parallel to the source line S in the non-light-shielding region Pa. In the present embodiment, the wiring 13 is, for example, a wiring used for a drive circuit that drives the gate line G, an auxiliary wiring connected to the common electrode, or the like. A specific example of the wiring 13 will be described later.

When the wiring 13 is arranged in the non-light-shielding area Pa of the pixel, the transmittance of the portion where the wiring 13 is arranged is lowered. If the wirings 13 are arranged in all the R, G, and B pixels, the change in the transmittance of the entire pixel becomes large. Therefore, in this embodiment, the wirings 13 are connected to pixels of a specific color (for example, B (blue)). Deploy. Further, the transmittance of a pixel in which the wiring 13 is disposed (hereinafter referred to as an installed pixel) and a pixel in which the wiring 13 is not disposed (hereinafter referred to as a non-installed pixel) excluding the contribution due to the difference in color of the color filter is equal. Thus, the width of the installed pixel and the width of the non-light-shielding area Pa are adjusted to be larger than those of the non-installed pixel. Specifically, as illustrated in FIG. 3, the pixel width L2 and the non-light-shielding region Pa width L12 in the installation pixel PIXb are larger than the pixel width L1 and the non-light-shielding region Pa width L11 in the non-installation pixel PIXa. It has become.

In each pixel PIX, the trunk portion 111 is a boundary between four domains, and the boundary portion is such that the orientation direction of liquid crystal molecules to which a voltage is applied is parallel or perpendicular to the transmission axis of a polarizing plate (not shown). Therefore, the transmittance is lowered and dark lines are generated. In the present embodiment, the wiring 13 is arranged in a region where a dark line is generated in the pixel (hereinafter referred to as a dark line region). Since the dark line region in the pixel has lower transmittance than the other regions of the pixel, the transmittance of the pixel hardly changes even if the wiring 13 is arranged in the dark line region. Furthermore, in the present embodiment, the installed pixel is configured so that the dark line region in the installed pixel is wider than the dark line region in the non-installed pixel. This will be specifically described below.

FIG. 5 is a schematic diagram showing the

pixel electrodes

11a and 11b of the non-installed pixel PIXa and the installed pixel PIXb. As shown in FIG. 5, the pixel electrode 11b of the installed pixel PIXb has a width W2 of the first trunk 111y substantially parallel to the extending direction of the wiring 13, and a width W1 of the first trunk 111y of the pixel electrode 11a of the non-installed pixel PIXa. Wider than. As described above, a dark line is generated in the area where the trunk 111 is provided in both the installed pixel PIXb and the non-installed pixel PIXa. By increasing the width of the first trunk 111y of the installation pixel PIXb, the dark line region is expanded in the first trunk 111y of the installation pixel PIXb. Therefore, even if there is some variation in the width of the wiring 13 and the position of the wiring 13, it is easy to arrange the wiring 13 in the dark line region of the installation pixel PIXb, and variation in transmittance between the installation pixels PIXb is reduced. As a result, even if the wirings 13 having different widths, positions, and the like are arranged in the pixels of a specific color, the display quality such as a color shift is unlikely to deteriorate.

It is preferable that the wiring 13 described above is disposed at the approximate center in the X-axis direction of the first trunk portion 111y of the installed pixel. With this configuration, the parasitic capacitance between the wiring 13 and another signal line provided in the same layer can be reduced. In addition, it is possible to minimize the variation in the transmittance of the installed pixels due to the variation in the width and position of the wiring 13.

(Modification)
In the above example, an example in which one wiring 13 substantially parallel to the source line S is provided in the non-light-shielding region Pa of the pixel has been described. However, as illustrated in FIG. In addition, a wiring 130 substantially parallel to the gate line G may be further provided.

In this case, since the wiring 130 is disposed in the pixels PIXa and PIXb, the width of the second trunk 111x that is substantially parallel to the extending direction of the wiring 130 is set to be the second of the non-installed pixel in which the wiring 130 is not provided. It is wider than the trunk 111x. The area where the second trunk 111x is provided is a dark line area where a dark line is generated. Therefore, by making the width of the second trunk portion 111x in the installed pixel in which the wiring 130 is arranged wider than that in the non-installed pixel, in the installed pixel in which the wiring 130 is arranged, a dark line region substantially parallel to the extending direction of the wiring 130 is formed. Can be spread. As a result, even when the width, position, and the like of the wiring 130 vary, it is easy to arrange the wiring 130 in the dark line region, and variation in transmittance between installed pixels where the wiring 130 is arranged can be reduced.

<Second Embodiment>
In the first embodiment, the example in which the liquid crystal layer 30 (see FIG. 1) is driven in the vertical alignment mode has been described. However, the liquid crystal layer 30 may be driven in the horizontal alignment mode. In the present embodiment, for example, the configuration of the display panel 2 in the FFS mode will be described.

FIG. 7A is an enlarged schematic view of a part of the pixels of the active matrix substrate 10 in the present embodiment.

As shown in FIG. 7A, the source line S is bent and the pixel PIX has a non-rectangular shape. The pixel PIX has two domains having different alignment directions (arrows P1 and P2) of liquid crystal molecules.

The pixel electrode 210 includes two electrode portions 211 (hereinafter referred to as a long side electrode portion), two electrode portions 212 (hereinafter referred to as short side electrode portions) connected to the long side electrode portion 211, a contact portion 213, and a slit. 214. The two long side electrode portions 211 are bent and spaced apart so as to be substantially parallel to the source line S, and have a slit 214 between the two long side electrode portions 211. The two short side electrode portions 212 are substantially parallel to the X axis, and one short side electrode portion 212 is connected to one long side electrode portion 211 and the contact portion 213.

Although not shown in FIG. 7A, the active matrix substrate 10 is provided with a common electrode through an insulating film so as to face the pixel electrode 210.

The liquid crystal molecules in the liquid crystal layer 30 rotate in the horizontal direction with respect to the direction of the electric field in accordance with a lateral electric field (fringe electric field) generated between the common electrode and the pixel electrode 210.

In the region where the slit 214 is provided, an electric field in a direction substantially perpendicular to the extending direction of the long side electrode portion 211 is formed along the edge of the slit 214, but in the slit 214, the long side electrode portion 211 is formed. The further away from the field, the weaker the electric field and the weaker the alignment regulating force on the liquid crystal molecules. Therefore, as shown in FIG. 7B, the transmittance is likely to decrease in a region immediately above the center of the slit 214, that is, a region 2141 including a position where the distance from the long-side electrode portion 211 is substantially intermediate.

Here, in the present embodiment, the configuration of the pixel when the wiring 13 is arranged will be described.

FIG. 8A is a schematic diagram illustrating a configuration example of a pixel of an installed pixel PIXb in which the wiring 13 is installed and a non-installed pixel PIXa in which the wiring 13 is not arranged. In the present embodiment as well, as in the first embodiment, the width of the installed pixel PIXb in the X-axis direction is wider than the width of the non-installed pixel PIXa in the X-axis direction.

FIG. 8B is a diagram showing only the pixel electrode 210a of the non-installed pixel PIXa and the pixel electrode 210b of the installed pixel PIXb shown in FIG. 8A.

In this embodiment, in the non-installed pixel PIXa, the width W3 of the slit 214a is set so that the transmittance in the slit 214a of the pixel electrode 210a is substantially the same as the transmittance in the vicinity of the long side electrode portion 211. Yes. On the other hand, in the installed pixel PIXb, the width W4 of the slit 214b is set so that the transmittance of the region overlapping the wiring 13 in the slit 214b of the pixel electrode 210b is lower than that of the non-installed pixel PIXa. That is, as shown in FIG. 8B, the width W4 of the slit 214b in the pixel electrode 210b of the installed pixel PIXb is wider than the width W3 of the slit 214a in the pixel electrode 210a of the non-installed pixel PIXa.

As described above, in the slit 214 of the pixel electrode 210, the longer the distance from the long-side electrode portion 211, the weaker the alignment regulating force on the liquid crystal molecules and the lower the transmittance. Therefore, by increasing the width of the slit 214b of the pixel electrode 210b in the installation pixel PIXb, the region 2141b where the alignment regulation force is weakened is also widened. That is, in the installed pixel PIXb, the width W41 of the region 2141b in the slit 214b is wider than the width W31 of the region 2141a in the slit 214a in the non-installed pixel PIXa. Therefore, the installed pixel PIXb has a region 2141b (hereinafter referred to as a low transmission region) having a lower transmittance than that in the slit 214a in the non-installed pixel PIXa in the slit 214b.

In the present embodiment, the wiring 13 is arranged along the region 2141b in the slit 214 of the pixel electrode 210b in the installation pixel PIXb.

Thus, since the installed pixel has the low transmission region 2141b in the slit 214b of the pixel electrode 210b, the width of the wiring 13 is compared with the case where the transmittance in the slit 214 of the pixel electrode 210 of all the pixels is uniform. Even when the positions and the positions are different, it is possible to reduce the variation in transmittance between the installed pixels. As a result, even if the wiring 13 having a different shape or the like is arranged in a pixel of a specific color, it is possible to make it difficult for display quality deterioration such as color shift to occur.

(Modification)
In the above-described second embodiment, the example in which the source line S and a part of the pixel electrode 210 are bent has been described, but the gate line G and a part of the pixel electrode 210 may be bent. Good.

FIG. 9A is an enlarged schematic view of a part of the pixels of the active matrix substrate 10a in the present modification. As shown in FIG. 9A, the gate lines G in the active matrix substrate 10a are bent in the Y-axis direction. Two electrode portions 221 (hereinafter referred to as long side electrode portions) of the pixel electrode 220 are bent in the same manner as the gate line G in the non-light-shielding region Pa. The pixel electrode 220 has a slit 224 between the long side electrode portions 221.

In this modification, for example, the pixels are arranged in the order of R, G, and B along the extending direction of the source line S.

In the lower pixel PIX shown in FIG. 9A, a wiring 131 passing through the non-light-shielding region Pa is arranged. The wiring 131 is a wiring used for a drive circuit for driving the gate line G, an auxiliary wiring connected to the common electrode, or the like, similar to the wiring 13 described above. The wiring 131 is bent in the same manner as the gate line G, and is disposed substantially parallel to the extending direction of the gate line G.

Also in this example, in order to make the transmittance of the installed pixel PIXb and the non-installed pixel PIXa uniform, the width of the installed pixel PIXb in the Y-axis direction is wider than that of the non-installed pixel PIXa and The axial width is also wider than that of the non-installed pixel PIXa.

9A, in the non-installed pixel PIXa, the width W5 of the slit 224 is set so that the transmittance in the slit 224 of the pixel electrode 220 is substantially the same as the transmittance in the vicinity of the long side electrode portion 221. Is set. The width W6 of the slit 224 of the pixel electrode 220 in the installed pixel PIXb is larger than the width W5 of the slit 224 of the pixel electrode 220 in the non-installed pixel PIXa. With this configuration, the width 61 of the region 2241b in the vicinity of the center of the slit 224b in which the orientation regulating force is weakened in the installed pixel PIXb is wider than the width 51 of the region 2241a of the non-installed pixel PIXa. That is, the installation pixel PIXb has the low transmission region 2241b in the slit 224b. The wiring 13 is arranged in the low transmission region 2241b in the installation pixel PIXb. Therefore, even if the width, position, and the like of the wiring 131 vary, it is possible to reduce variation in transmittance between the installed pixels PIXb as compared with the case where the transmittance in the slits 224 of all the pixels is uniform.

In the example of FIG. 9A, the wiring 131 that is substantially parallel to the extending direction of the gate line G is disposed in the pixel. However, as shown in FIG. 9B, the wiring 132 that is substantially parallel to the source line S is further provided. May be arranged in the pixel. In this case, since the

regions

2241a and 2241b intersect the extending direction of the wiring 132, the wiring 132 cannot be completely overlapped with the

regions

2241a and 2241b even if the width of the slit 224 of each pixel is increased. Therefore, when the width, position, and the like of the wiring 132 are varied, variation in transmittance between installed pixels provided with the wiring 132 is not suppressed. However, since at least the variation in the transmittance between the installed pixels in which the wiring 131 is disposed can be suppressed, it is possible to reduce deterioration in display quality.

<Third Embodiment>
In the first and second embodiments described above, the shape of the pixel electrode of the installed pixel that overlaps the wiring is different from the pixel electrode of the non-installed pixel, so that the dark line region or the low transmission region in the installed pixel is more than the non-installed pixel. Increased to suppress variation in transmittance between installed pixels. In this embodiment, an example in which variation in transmittance between installed pixels is further suppressed by using a common electrode will be described.

FIG. 10 is an enlarged schematic view of a part of the pixels of the active matrix substrate 10b in the present embodiment. In FIG. 10, the same components as those of the second embodiment are denoted by the same reference numerals as those of the second embodiment. Further, in FIG. 10, for the sake of convenience, the illustration of the light shielding region Pb covered with the black matrix is omitted.

The common electrode 15 shown in FIG. 10 is arranged to face the pixel electrode 210 with an insulating film interposed therebetween. The common electrode 15 has a slit (opening) 151 at a position overlapping the wiring 13 in the non-light-shielding region Pa of the installation pixel PIXb. The width 151 of the slit 151 in the X-axis direction is wider than that of the wiring 13.

In the installed pixel PIXb, since the voltage is not applied to the liquid crystal molecules in the region where the slit 151 is provided, the transmittance is lower than that of the portion where the slit 151 is not provided. Therefore, even if the width, position, and the like of the wiring 13 arranged in the installation pixel PIXb vary, the variation in transmittance between the installation pixels PIXb can be further reduced as compared with the second embodiment.

It is preferable that the wiring 13 is disposed at substantially the center of the width of the slit 151. With this configuration, the parasitic capacitance between the wiring 13 and other signal lines can be reduced. In addition, it is possible to reduce variations in the transmittance of installed pixels due to variations in the width and position of the wiring 13.

In this example, the slit width of the pixel electrode 210 in the installed pixel PIXb is wider than the slit of the pixel electrode 210 in the non-installed pixel PIXa, but the slit of the pixel electrode 210 of the installed pixel PIXb and the non-installed pixel PIXa. May be equal in width. Even when the slit 151 is provided only at the position where the common electrode 15 overlaps the wiring 13 in the installation pixel PIXb, when a voltage is applied to the liquid crystal molecules, the alignment regulating force on the liquid crystal molecules at the position of the slits 151 is weakened. The transmittance decreases. That is, the installed pixel has a low transmission region having a lower transmittance than the non-installed pixel in the region where the slit 151 is provided. Therefore, by arranging the wiring 13 in the low transmission region provided in the common electrode 15, it is possible to reduce variation in transmittance between installed pixels due to variation in the width and position of the wiring 13.

In this example, the pixel electrode 210 similar to that of the second embodiment has been described as an example, but the shape of the pixel electrode is not limited thereto. As the pixel electrode, a pixel electrode having the same fishbone shape as in the first embodiment may be used, or a pixel electrode in which no slit is formed may be used.

<Fourth Embodiment>
Next, specific examples of the wiring in the first to third embodiments described above will be described.

FIG. 11 is a schematic diagram showing a schematic arrangement example of gate drivers provided on the active matrix substrate 10c in the present embodiment. In FIG. 11, the source line S is not shown for convenience.

As illustrated in FIG. 11, for each gate line G, one gate driver 40 that switches the gate line G to a selected state or a non-selected state is provided. The gate driver 40 is disposed between adjacent gate lines G. That is, in this example, the gate driver 40 is disposed in the pixel.

Except for the gate driver 40 provided for the gate line G (1) in the first row, each gate driver 40 is arranged between the corresponding gate line G and the gate line G adjacent to the gate line G. The

In this example, the gate drivers 40 provided for the odd-numbered gate lines G (G (1), (3), (5)...) Are connected to each other via the control wiring 411. The gate drivers 40 provided for the even-numbered gate lines G (G (2), (4), (6)...) Are connected to each other via the control wiring 411.

In the active matrix substrate 10c,

terminal portions

71 and 72 are provided in the frame region on the side where the source driver 42 is provided. The terminal unit 71 is connected to the display control circuit 50 and the power supply 60. The terminal portion 72 is connected to the display control circuit 50, the source driver 42, and the source line S (see FIG. 2).

The display control circuit 50 has, as a control signal, a signal that repeats an H level (VDD) potential and an L level (VSS) potential alternately (hereinafter referred to as a clock signal) at a constant cycle, and the same potential as the H level of the clock signal. A signal (hereinafter, reset signal) is supplied to the terminal unit 71.

The power supply 60 supplies a power supply voltage signal to the source driver 42 and the terminal unit 71.

The terminal unit 71 receives signals such as a supplied control signal and a power supply voltage signal, and supplies each signal to each gate driver 40 via the control wiring 411. The gate driver 40 outputs a voltage signal indicating one of the selected state and the non-selected state to the corresponding gate line G in accordance with the supplied signal. The source driver 42 outputs a data signal to each source line S (see FIG. 2) via the terminal unit 72 in accordance with a signal input from the display control circuit 50.

Next, the configuration of the gate driver 40 will be described. FIG. 12 is a diagram illustrating an equivalent circuit of the gate driver 40 (n) that drives the gate line G (n).

As shown in FIG. 12, the gate driver 40 (n) includes thin film transistors (TFT: Thin Film Transistor) (hereinafter referred to as TFT-A to TFT-E) denoted by alphabets A to E as switching elements, a capacitor Cbst, , NetA which is an internal wiring of the gate driver 40.

The drain terminal of the TFT-B is connected to the previous gate line G (n−1), the gate terminal is connected to the control wiring 411 that supplies the clock signal CKB, and the source terminal is connected to netA. The TFT-B controls the raising and lowering of the potential of the netA according to the clock signal CKB and the potential of the gate line G (n−1).

The drain terminal of TFT-A is connected to netA, the gate terminal is connected to a control wiring 411 that supplies a reset signal CLR, and the source terminal is connected to a control wiring 411 that supplies a power supply voltage signal VSS. The TFT-A sets the potential of netA to the level of the power supply voltage signal VSS at the timing specified by the reset signal CLR.

The gate terminal of the TFT-E is connected to netA, the drain terminal is connected to the control wiring 411 that supplies the clock signal CKA, and the source terminal is connected to the gate line G (n).

The drain terminal of the TFT-D is connected to the gate line G (n), the gate terminal is connected to the control wiring 411 that supplies the reset signal CLR, and the source terminal is connected to the control wiring 411 that supplies the power supply voltage signal VSS. Connected.

The drain terminal of the TFT-C is connected to the gate line G (n), the gate terminal is connected to the control wiring 411 that supplies the clock signal CKB, and the source terminal is connected to the control wiring 411 that supplies the power supply voltage signal VSS. Connected.

The capacitor Cbst has one electrode connected to netA (n) and the other electrode connected to the gate line G (n). The capacitor Cbst boosts the potential of netA (n) in accordance with the potential of the clock signal CKA output from the TFT-E.

Note that the connection of the clock signals CKA and CKB is switched in the gate lines G (n + 1) and G (n−1) of the next stage and the previous stage. For example, in the next stage and the previous stage, the drain terminal of the TFT-E is connected to the control wiring 411 that supplies the clock signal CKB, and the gate terminals of the TFT-B and TFT-C are the control wiring 411 that supplies the clock signal CKA. Connected.

The reset signal CLR is, for example, a signal that becomes H level for a certain period before the scanning of the gate line G is started. In this case, the reset signal CLR becomes H level for each vertical scanning period. When the reset signal CLR becomes H level, the netA and the gate line G are reset to L level (the level of the power supply voltage signal VSS). In addition, GSP (gate start pulse gate start pulse) is input from the display control circuit 50 as the set signal St to the first stage gate line G (1) at the beginning of one vertical scanning period.

Here, the operation when the gate driver 40 (n) drives the gate line G (n) will be described. FIG. 13 is a timing chart when the gate driver 40 (n) drives the gate line G (n). As shown in FIG. 13, the clock signals CKA and CKB alternately repeat the potentials at the H level and the L level every horizontal scanning period (1H) so as to have opposite phases to each other.

At time t1, the previous gate line G (n−1) is in a selected state, and the clock signal CKA becomes L level and the clock signal CKB becomes H level. As a result, the TFT-B is turned on, the H-level potential of the gate line G (n−1) is input to the drain terminal of the TFT-B, and netA is charged to the H level. Further, since TFT-E is turned off, the potential of netA is maintained without being lowered. During this time, since the TFT-C is in the on state, the potential of the gate line G (n) is at the L level.

At time t2, when the clock signal CKA becomes H level and the clock signal CKB becomes L level, the TFT-E is turned on and the TFT-C is turned off. Since the capacitor Cbst is provided between the netA and the gate line G (n), the netA is charged to a potential higher than the H level of the clock signal CKA as the potential of the drain of the TFT-F increases. . During this period, the H level potential of the clock signal CKA is output to the gate line G (n). As a result, the gate line G (n) is selected, and the gate driver 40 (n + 1) that drives the next-stage gate line G (n + 1) receives the H of the gate line G (n) as the set signal St. A level potential is output.

At time t3, when the clock signal CKA becomes L level and the clock signal CKB becomes H level, the TFT-B is turned on, and netA is charged to L level. Further, since the TFT-E is turned off and the TFT-C is turned on, the gate line G (n) is charged to the L level and switched to the non-selected state. Thereafter, the gate line G (n) is maintained at the L level potential by the clock signal CKB and the TFT-C.

Next, an arrangement example of circuit elements of the gate driver 40 will be described. FIG. 14 is an equivalent circuit diagram illustrating an arrangement example of circuit elements of the gate driver 40.

FIG. 14 shows an arrangement example of circuit elements of the gate drivers 40 (n−2) to 40 (n + 1) for driving the gate lines G (n−2) to G (n + 1), respectively. .

As shown in FIG. 14, each gate driver 40 is arranged in a row between the gate line G driven by the gate driver 40 and the previous gate line G. In addition, the gate driver 40 (n−2) and the gate driver 40 (n), and the gate driver 40 (n−1) and the gate driver 40 (n + 1) are connected to each other through a common control wiring 411.

The circuit elements such as TFT-A to TFT-E indicated by alphabets A to E and the capacitor Cbst and the internal wiring such as netA for connecting the circuit elements are distributed in different pixels in the same row. Here, the configuration of the pixel in which the circuit element, the internal wiring, and the control wiring 411 of the gate driver 40 are arranged will be specifically described.

FIG. 15 is an enlarged schematic view of a part of pixels including a pixel in which circuit elements, internal wirings, and control wirings 411 of the gate driver 40 are arranged. In FIG. 15, the same reference numerals as those in the first embodiment are given to the same configurations as those in the first embodiment.

As shown in FIG. 15, the circuit element 410 of the gate driver 40 is arranged in the light shielding region of the pixel PIXb. The internal wiring 412 is connected to the circuit element 410 and is arranged substantially in parallel with the gate line G in a light shielding region of a plurality of pixels adjacent in the extending direction of the gate line G. The control wiring 411 is connected to the circuit element 410, and a part of the control wiring 411 is disposed so as to be substantially parallel to the source line S in the non-light-shielding region Pa of the pixel PIXb. That is, in this example, the control wiring 411 corresponds to the wiring 13 in the first embodiment described above, and the pixel PIXb is an installed pixel in which the wiring 13 is arranged.

The pixel electrode 11 has the same fishbone shape as in the first embodiment. The control wiring 411 is disposed so as to overlap the first trunk portion 111y of the pixel electrode 11 in the installation pixel PIXb. The width of the first trunk portion 111y of the pixel electrode 11 of the installed pixel PIXb is wider than the pixel electrode 11 of the non-installed pixel PIXa, as in the first embodiment. Therefore, it is easy to arrange the control wiring 411 in the dark line region in the installation pixel PIXb, and even if the width, position, etc. of the control wiring 411 vary, the transmittance between the installation pixels PIXb hardly varies.

In this example, a fishbone-shaped pixel electrode is used, but a pixel electrode similar to the pixel electrode 210 of the second embodiment may be used. Further, as in the third embodiment, in the common electrode 15 (see FIG. 10) arranged to face the pixel electrode 11, a slit may be formed at a position overlapping the control wiring 411. Moreover, the internal wiring 412 of the gate driver 40 may be arranged as the

wirings

130 and 131 in the (modification) of the first embodiment and the second embodiment described above.

<Modification>
(1) In the embodiment described above, the use and type of the wiring arranged in the non-light-shielding region of the pixel are not limited. For example, as shown in FIG. 16, in the above-described fourth embodiment, the control wiring 411 is arranged in the light shielding region between the adjacent pixels PIXa and PIXb, and is connected to the pixel electrode 11 of one pixel PIXb. The source line S (Sb) may be arranged in the non-light-shielding region Pa of the pixel PIXb. That is, in this case, the wiring arranged in the non-light-shielding region Pa of the pixel is the source line S. With this configuration, the region between the source lines Sa and Sb is widened, and the circuit element 410 of the gate driver 40 can be easily arranged.

(2) In this modification, a configuration example of a pixel different from the above-described second embodiment will be described. FIG. 17 is an enlarged schematic diagram of a part of pixels of the active matrix substrate in the present modification. In FIG. 17, the same reference numerals as those in the second embodiment are assigned to the same configurations as those in the second embodiment.

As shown in FIG. 17, two electrode portions 2301 (hereinafter, long-side electrode portions) of each pixel electrode 2301 are substantially parallel to each other and have a linear shape. Each pixel electrode 230 has a slit 2340 between two long-side electrode portions 2301 of the pixel electrode 230.

The long side electrode portion 2301 constituting the

pixel electrodes

231a and 231b connected to the gate line G (n) via the pixel TFT 12 is inclined to the X axis positive direction side, whereas the gate line G (n−1) ) And the

pixel electrodes

232a and 232b connected via the pixel TFT 12 are inclined to the X-axis negative direction side.

In this modification, the liquid crystal molecules of the pixel PIX provided with each pixel electrode 230 connected to the same gate line G are aligned along the extending direction of the slit 2340 of the pixel electrode 230 of the pixel when a voltage is applied. Although aligned in the same direction, the alignment direction of the liquid crystal molecules in the pixel adjacent to the extending direction of the source line S is different. That is, for example, the alignment direction of the liquid crystal molecules of the upper pixels PIX1a and PIX1b in FIG. 17 is the arrow P11 direction toward the gate line G (n) along the extending direction of the slits 2340 of the pixels. On the other hand, the alignment direction of the liquid crystal molecules of the lower pixels PIX2a and PIX2b in FIG. 17 is an arrow P12 direction toward the gate line G (n) along the extending direction of the slits 2340 of the pixels.

In the region portion 2341 that is approximately in the middle of the width of the slit 2340 in each pixel electrode 230, when a voltage is applied, the alignment of the liquid crystal molecules is weakened, and the transmittance tends to decrease. Therefore, also in this example, the non-installed pixels PIX1a and PIX2a in which the wiring 13 is not provided have slits so that the transmittance in the region in which the slit 2340 is provided is equal to the transmittance in the vicinity of the long side electrode portion 2301. A width of 2340 in the X-axis direction is set.

On the other hand, the width in the X-axis direction of the slits 2340 of the installed pixels PIX1b and PIX2b provided with the wiring 13 is wider than the slits 2340 of the non-installed pixels PIX1a and PIX2a. With this configuration, in the installed pixels PIX1b and PIX2b, the region 2341 in which the orientation of liquid crystal molecules is weakened when a voltage is applied becomes wider than the region 2341 of the pixels PIX1a and PIX2a. That is, the installation pixels PIX1b and PIX2b have the low transmission region 2341 in the slit 2340. Therefore, even if there is a variation in the width, position, etc. of the wiring 13, the variation in the transmittance between the installed pixels is suppressed as compared with the case where the transmittance in the slits 2340 of all the pixels is uniform. Can be reduced.

In the second embodiment described above, the viewing angle of the entire pixel is improved by forming two domains having different orientation directions in one pixel. However, in each pixel, a dark line is generated at the domain boundary. In this modification, since there is one domain in one pixel, no dark line is generated. Moreover, in this modification, since the orientation directions of the pixels in adjacent rows are different from each other, the viewing angle of the entire pixels can be improved.

As in the second embodiment, the configuration in which a plurality of domains are formed in one pixel is difficult to apply to a high-definition pixel, but the configuration of this modification is easy to apply to a high-definition pixel. In this case, the pixel TFT 12 is preferably formed using an oxide semiconductor containing indium (In), gallium (Ga), zinc (Zn), and oxygen (O). By using such an oxide semiconductor, pixels can be easily made high-definition as compared with the case where amorphous silicon (a-Si) or LTPS (Low Temperature Poly-silicon) is used. Also in this modification, similarly to the third embodiment, the slit 151 may be provided at a position overlapping the wiring 13 in the common electrode 15 (see FIG. 10) in the pixel where the wiring 13 is installed.

(3) In the above-described embodiment, the example in which the wiring is arranged in the pixel of the specific color (B (blue)) has been described, but the pixel in which the wiring is arranged may not be a pixel of the specific color. Even when the wiring is arranged in pixels of different colors, the transmittance varies between the installed pixels where the wiring is arranged due to variations in the width and position of the wiring. Since the transmittance between the installed pixels varies, the balance between the transmittance of the non-installed pixels and the installed pixels is lost, so that the display quality is deteriorated. As in the above-described embodiment, by setting the dark line region or the low transmission region extending substantially parallel to the wiring extension direction in the installation pixel more than the non-installation pixel, variation in transmittance of the installation pixel is suppressed, It is possible to reduce the deterioration of display quality as a whole pixel.

(4) In the above-described embodiment, the width of the installed pixel and the width of the non-light-shielding area in the installed pixel are configured wider than the non-installed pixel in order to make the transmittance of the installed pixel and the non-installed pixel uniform. The width of the pixel and the width of the opening in the non-installed pixel may be the same. Even in such a configuration, the configuration of the above-described embodiment suppresses the variation in transmittance between the installed pixels, and the balance between the transmittance of the non-installed pixels and the installed pixels is not easily lost. The reduction can be reduced.

(5) The shape of the pixel electrode provided in each pixel of the above-described embodiment is an example, and the shape of the pixel electrode is not limited to this. In short, it is sufficient that at least some of the pixels are configured so that a dark line region or a low transmission region extending substantially parallel to the wiring extending direction is formed.

(6) The configuration of the gate driver 40 used in the above-described embodiment is an example, and is not limited to this as long as the configuration includes a plurality of switching elements.

(7) As the semiconductor material of the TFTs constituting the pixel TFT 12 and the gate driver 40 in the above-described embodiment, amorphous silicon (a-Si) or LTPS (Low Temperature Poly-silicon) may be used, but indium (In ), An oxide semiconductor containing gallium (Ga), zinc (Zn), and oxygen (O) is more preferable. By applying an oxide semiconductor containing indium (In), gallium (Ga), zinc (Zn), and oxygen (O), higher definition and higher aperture ratio can be achieved than when amorphous silicon and LTPS are used. Cheap.

Claims

A liquid crystal display device comprising: an active matrix substrate; a counter substrate disposed opposite to the active matrix substrate and including a light shielding member; and a liquid crystal layer sandwiched between the active matrix substrate and the counter substrate. ,
The active matrix substrate is
A plurality of pixels each having a light shielding region shielded by the light shielding member and a non-light shielding region excluding the light shielding region, each provided with a pixel electrode having a slit in the non-light shielding region;
Wiring disposed in the pixel region,
Liquid crystal molecules in the liquid crystal layer are driven in a horizontal alignment mode,
Each of some of the plurality of pixels has a low transmission region in which the transmittance in the slit in the pixel is lower than the transmittance in the slit in the other pixels,
The liquid crystal display device, wherein the wiring is arranged in the low transmission region in the partial pixel.
The pixel electrode has a first electrode and a second electrode,
The slit is provided between the first electrode and the second electrode, and is substantially parallel to a direction in which the wiring extends.
The width of the slit in the some pixels is wider than the width of the slit in the other pixels,
2. The liquid crystal display device according to claim 1, wherein the low transmission region in the partial pixel includes a region in which a distance from the first electrode and the second electrode of the pixel is substantially intermediate.
A liquid crystal display device comprising: an active matrix substrate; a counter substrate disposed opposite to the active matrix substrate and including a light shielding member; and a liquid crystal layer sandwiched between the active matrix substrate and the counter substrate. ,
The active matrix substrate is
A plurality of pixels each provided with a pixel electrode and having a light shielding region shielded by the light shielding member and a non-light shielding region excluding the light shielding region;
Wiring disposed in the pixel region,
Liquid crystal molecules in the liquid crystal layer are driven in a vertical alignment mode,
Each of the plurality of pixels has a plurality of alignment division regions having different alignment directions when the liquid crystal molecules are driven in the non-light-shielding region of the pixels,
The boundary between the plurality of alignment division regions has a boundary portion substantially parallel to the direction in which the wiring extends,
The width of the boundary portion in some of the plurality of pixels is wider than the width of the boundary portion in other pixels,
The liquid crystal display device, wherein the wiring is disposed at the boundary portion in the non-light-shielding region of the some pixels.
The active matrix substrate or the counter substrate further includes a common electrode disposed to face the pixel electrode in the plurality of pixels,
4. The liquid crystal display device according to claim 1, wherein the common electrode in the partial pixel has an opening substantially parallel to a direction in which the wiring extends at a position overlapping the wiring. 5.
The active matrix substrate further includes:
Multiple gate lines,
A plurality of source lines intersecting the plurality of gate lines;
A driving circuit that is provided for each of the plurality of gate lines and switches a corresponding one gate line to a selected state or a non-selected state in accordance with a supplied control signal;
The drive circuit has a drive circuit element including a plurality of switching elements,
The drive circuit element is disposed in the part of the pixels and connected to the wiring,
5. The liquid crystal display device according to claim 1, wherein the wiring supplies the control signal to the drive circuit element connected to the wiring. 6.
The active matrix substrate further includes:
Multiple gate lines,
A plurality of source lines intersecting with the plurality of gate lines,
The pixel electrode of each pixel is connected to one gate line and one source line,
The liquid crystal display device according to claim 1, wherein the wiring is the one source line connected to a pixel electrode of a pixel in which the wiring is arranged.