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WO2018181296A1 - Procédé de fabrication d'un transistor à couches minces de type à gravure de canal - Google Patents

Procédé de fabrication d'un transistor à couches minces de type à gravure de canal Download PDF

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Publication number
WO2018181296A1
WO2018181296A1 PCT/JP2018/012407 JP2018012407W WO2018181296A1 WO 2018181296 A1 WO2018181296 A1 WO 2018181296A1 JP 2018012407 W JP2018012407 W JP 2018012407W WO 2018181296 A1 WO2018181296 A1 WO 2018181296A1
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layer
electrode
channel
film
thin film
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PCT/JP2018/012407
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Japanese (ja)
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中村　好伸
宮本　忠芳
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シャープ株式会社
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/18, H10D48/04 and H10D48/07, with or without impurities, e.g. doping materials
    • H01L21/46—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428
    • H01L21/477—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/23—Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes

Definitions

  • One embodiment of the present invention relates to a method for manufacturing a channel-etched thin film transistor.
  • the active matrix substrate includes a switching element such as a thin film transistor (hereinafter, “TFT”) for each pixel.
  • TFT thin film transistor
  • An active matrix substrate including TFTs as switching elements is called a TFT substrate.
  • a TFT substrate used in a liquid crystal display device has, for example, a glass substrate, a plurality of TFTs supported by the glass substrate, gate wirings and source wirings, and pixel electrodes arranged in a matrix.
  • the gate electrode of each TFT is electrically connected to the gate wiring
  • the source electrode is electrically connected to the source wiring
  • the drain electrode is electrically connected to the pixel electrode.
  • the TFT, source wiring and gate wiring are usually covered with an interlayer insulating layer
  • the pixel electrode is provided on the interlayer insulating layer, and is connected to the drain electrode of the TFT in a contact hole formed in the interlayer insulating layer. Has been.
  • amorphous silicon TFT As TFTs, TFTs using an amorphous silicon film as an active layer (hereinafter referred to as “amorphous silicon TFT”) and TFTs using a polycrystalline silicon film as an active layer (hereinafter referred to as “polycrystalline silicon TFT”) have been widely used. Yes. Recently, an oxide semiconductor has attracted attention as a material for an active layer of a TFT. An oxide semiconductor TFT can operate at a higher speed than an amorphous silicon TFT. In addition, since the oxide semiconductor film is formed by a simpler process than the polycrystalline silicon film, the oxide semiconductor film can be applied to a device that requires a large area. In this specification, a TFT having an oxide semiconductor film as an active layer may be referred to as an “oxide semiconductor TFT”.
  • the source electrode and the source electrode of the TFT are generally formed from the same conductive film together with the source wiring.
  • a material of the conductive film aluminum (Al) or Al alloy having high conductivity is widely used. Recently, it has also been proposed to use copper (Cu) which is more excellent in conductivity.
  • a layer including the source wiring and formed of the same conductive film may be referred to as a “source wiring layer”.
  • a source wiring having a low wiring resistance can be formed.
  • Al film (or Al alloy film) and the semiconductor layer of the TFT are brought into contact with each other, there is a possibility that Al diffuses inside the semiconductor layer and desired TFT characteristics cannot be obtained. Even when the source wiring layer is formed using Cu, Cu may diffuse into the semiconductor layer, and desired TFT characteristics may not be obtained.
  • a heat treatment for example, about 200 to 600 ° C.
  • the surface of the Al layer may be deformed to generate a projection called hillock. Hillocks on the surface of the Al layer reduce the insulating properties of the interlayer insulating layer.
  • Patent Documents 1 and 2 disclose a source electrode and a drain electrode having a structure in which a molybdenum (Mo) layer, an Al layer, and a Mo layer are sequentially stacked.
  • Patent Document 3 discloses that a titanium (Ti) layer is formed between an Al layer or a Cu layer and an oxide semiconductor layer.
  • Patent Document 4 discloses a source electrode and a drain electrode having a structure in which a Ti layer, an Al layer, and a Ti layer are sequentially stacked.
  • the metal wiring material of the TFT may be formed in a laminated structure in which an Al layer is sandwiched between a Ti layer or a Mo layer in consideration of adhesion to upper and lower layers, reactivity, productivity, and the like. It is common.
  • the resistance and load capacity of the wiring have increased, and the problem of wiring delay has become apparent.
  • the only way to prevent the aperture ratio from decreasing is to increase the thickness of the wiring.
  • FIG. 1A and 1B are diagrams schematically showing main components of a TFT
  • FIG. 1A is a plan view
  • FIG. 1B is a cross-sectional view taken along line XX in FIG. 1A.
  • reference numeral 101 denotes a gate electrode
  • reference numeral 102 denotes a channel layer
  • reference numerals 103 and 104 denote source / drain electrodes (hereinafter referred to as “S / D electrodes”). Since reference numerals 103 and 104 are connected from the S / D electrode to the wiring, they are referred to as S / D electrode wirings here.
  • the film thicknesses of the S / D electrode wirings 103 and 104 are indicated by h.
  • FIG. 2A and 2B are enlarged views of the vicinity of the S / D electrode wiring 103 and the channel layer 102 on the left side of FIG. 1B, and FIG. 2A shows the case where the film thickness of the S / D electrode wiring 103 is h1. Is a case where the thickness of the S / D electrode wiring 103 is thicker than that in the case of FIG. 2A.
  • FIG. 2A and FIG. 2B what is indicated by reference numeral 105 using a dotted line is an upper insulating film (Pas film, protective film).
  • the upper insulating film 105 covers the tapered portion (including the end surface 103 a) of the S / D electrode wiring 103 between the S / D electrode wiring 103 and the channel layer 102.
  • the covering portions of the tapered portion (including the end surface 103a) of the upper insulating film 105 in FIGS. 2A and 2B are denoted by A1 and A2, respectively.
  • the coating of the end surface 103a extending in the direction perpendicular to the substrate is thinner than the coating of the surface 103b extending in the direction parallel to the substrate. Therefore, the covering portion A2 in the case of FIG. 2B in which the height of the end surface 103b, that is, the S / D electrode wiring 103 is thick, is deteriorated as compared with the covering portion A1 in the case of FIG. 2A.
  • oxide semiconductor TFTs that have recently been attracting attention, particularly channel etch type structures, moisture or the like is generated from the portions with poor coverage of the tapered portion of the S / D electrode (covered portions A1 and A2 in FIGS. 2A and 2B). Intrusion will result in abnormal characteristics and lead to serious defects leading to poor reliability.
  • the oxide semiconductor TFT is annealed at 300 ° C. or higher (eg, 350 ° C. for 1 hour) after forming the upper insulating film (passivation (Pas) film (eg, SiO 2 film), protective film) to diffuse oxygen from the Pas film.
  • passivation (Pas) film eg, SiO 2 film
  • protective film to diffuse oxygen from the Pas film. It is necessary to reduce the oxygen defects in the oxide semiconductor, but the deterioration of the coverage of the taper portion of the S / D electrode is caused by the volume change (shrink) of Al during the annealing and the volume change of Ti and Mo. This is because Al voids are generated in the tapered portion of the S / D electrode.
  • the “channel etch TFT” will be described in comparison with the “etch stop TFT”.
  • the etch stop layer is not formed on the channel region (layer), and the lower surface of the end of the source and drain electrodes on the channel side
  • the oxide semiconductor layer having a region (layer) is disposed in contact with the upper surface.
  • the “channel etch TFT” is formed, for example, by forming a conductive film for a source / drain electrode on an oxide semiconductor layer forming a channel region (layer) and performing source / drain separation. In the source / drain separation step, the surface portion of the channel region may be etched.
  • etch stop type TFT that is, a TFT in which an etch stop layer is formed on the channel region
  • the lower surface of the end of the source and drain electrodes on the channel side is located on the etch stop layer
  • Etch-stop type TFT forms an etch stop layer that covers the channel region of the oxide semiconductor layer, and then forms a conductive film for the source and drain electrodes on the oxide semiconductor layer and the etch stop layer. However, it is formed by performing source / drain separation.
  • One aspect of the present invention has been made in view of such circumstances, and an object of the present invention is to provide a method for manufacturing a channel-etched thin film transistor that can reduce deterioration in the coverage of the S / D electrode taper portion of the passivation film.
  • At least one of the source electrode and the drain electrode has a laminated structure of a metal layer other than Al / an Al layer / a metal layer other than Al
  • energy is applied so as to reduce a volume of an Al layer in the conductive film and a step of forming a conductive film for a source electrode and a drain electrode.
  • the step of applying energy may be a metal ion implantation step.
  • the metal ion implantation step may be performed by heating the substrate temperature to 100 to 250 ° C.
  • the metal layer may be made of either Ti or Mo.
  • a method for manufacturing a channel-etched thin film transistor that can reduce deterioration in the coverage of the S / D electrode taper portion of the passivation film can be provided.
  • FIG. 1B is a diagram schematically showing main components of a TFT, and is a cross-sectional view taken along line XX in FIG. 1A.
  • FIG. 1B is an enlarged view of the vicinity of the S / D electrode wiring 103 and the channel layer 102 on the left side of FIG. 1B, and shows a case where the film thickness of the S / D electrode wiring 103 is h1.
  • 1B is an enlarged view of the vicinity of the S / D electrode wiring 103 and the channel layer 102 on the left side of FIG. 1B, and is a case where the thickness of the S / D electrode wiring 103 is thicker than that in the case of FIG. 2A.
  • FIG. 3 is a first process cross-sectional view illustrating an example of a method for manufacturing a channel-etched thin film transistor according to one embodiment of the present invention and illustrating a method for manufacturing a channel-etched thin film transistor.
  • FIG. 7 is a second process cross-sectional view illustrating an example of a method for manufacturing a channel-etched thin film transistor according to one embodiment of the present invention and illustrating a method for manufacturing a channel-etched thin film transistor.
  • FIG. 7 is a third process cross-sectional view illustrating an example of a method for manufacturing a channel-etched thin film transistor according to one embodiment of the present invention and illustrating a method for manufacturing a channel-etched thin film transistor.
  • FIG. 9 is a fourth process cross-sectional view illustrating an example of a method for manufacturing a channel-etched thin film transistor according to one embodiment of the present invention and illustrating a method for manufacturing a channel-etched thin film transistor.
  • FIG. 9 is a fifth process cross-sectional view illustrating an example of a method for manufacturing a channel-etched thin film transistor according to one embodiment of the present invention and illustrating a method for manufacturing a channel-etched thin film transistor.
  • FIG. 10 is a sixth process cross-sectional view illustrating an example of a method for manufacturing a channel-etched thin film transistor according to one embodiment of the present invention and illustrating a method for manufacturing a channel-etched thin film transistor.
  • FIG. 9 is a fourth process cross-sectional view illustrating an example of a method for manufacturing a channel-etched thin film transistor according to one embodiment of the present invention and illustrating a method for manufacturing a channel-etched thin film transistor.
  • FIG. 9 is a fifth process cross-sectional view illustrating an example of a method for
  • FIG. 11 is a seventh process cross-sectional view illustrating an example of a method for manufacturing a channel-etched thin film transistor according to one embodiment of the present invention and illustrating a method for manufacturing a channel-etched thin film transistor. It is a graph which shows the result of the TFT characteristic before and behind performing the high temperature, high humidity reliability test which was placed for 150 hours in the environment of temperature 60 degreeC and humidity 95% about an Example and a comparative example. The result of the TFT characteristic before a property test is shown. It is a graph which shows the result of the TFT characteristic before and after performing the high temperature, high humidity reliability test which was placed in the environment of temperature 60 ° C. and humidity 95% for 150 hours for the example and the comparative example.
  • the result of the TFT characteristic after a property test is shown. It is a graph which shows the result of the TFT characteristic before and behind performing the high temperature, high humidity reliability test which was placed for 150 hours in the environment of temperature 60 degreeC and humidity 95% about an Example and a comparative example. The result of the TFT characteristic after a property test is shown.
  • At least one of the source electrode and the drain electrode has a laminated structure of a metal layer other than Al / an Al layer / a metal layer other than Al
  • a channel etch type thin film transistor having a channel layer made of an oxide semiconductor a conductive film forming process for an electrode for forming a conductive film for a source electrode and a drain electrode, and a volume of an Al layer in the conductive film
  • An energy applying step for applying energy so as to reduce the thickness an electrode forming step for patterning the conductive film to form a source electrode and a drain electrode, and a passivation film forming step for forming a passivation film.
  • 4A to 4G an example of a method for manufacturing a channel-etched thin film transistor according to one embodiment of the present invention will be described.
  • 4A to 4G are process cross-sectional views for explaining a method for manufacturing the channel-etched thin film transistor 10.
  • the substrate 11 is prepared.
  • a glass substrate, a silicon substrate, a heat-resistant plastic substrate, a resin substrate, or the like can be used.
  • plastic substrate or the resin substrate polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyethersulfone (PES), acrylic, polyimide, or the like can be used.
  • silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy) (x> y), silicon nitride oxide (SiNxOy) (x> y), or the like may be appropriately used as a base coat for each substrate. it can.
  • the gate electrode 12 is formed on the substrate 11.
  • the gate electrode 12 can be formed by depositing a conductive film on the substrate 11 by a sputtering method or the like and then patterning the conductive film using a photolithography process.
  • a metal such as aluminum (Al), tungsten (W), molybdenum (Mo), tantalum (Ta), chromium (Cr), titanium (Ti), copper (Cu), or an alloy thereof, or metal nitriding thereof A thing can be used suitably. Further, a plurality of these layers may be stacked.
  • W / TaN 370 nm / 50 nm as a conductive film with a sputtering apparatus
  • it can be patterned into a desired pattern by a photolithography method and a dry etching method.
  • a gate insulating film 14 is formed on the gate electrode 12.
  • the gate insulating film 14 can be formed using, for example, a CVD method.
  • the gate insulating film may be a single layer film or a multilayer film.
  • silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy) (x> y), silicon nitride oxide (SiNxOy) (x> y), or the like can be used as appropriate.
  • the lower-layer side gate insulating film is formed using silicon nitride (SiNx), silicon nitride oxide (SiNxOy) (x> y) or the like, and the upper-layer side gate insulating film Is preferably formed using silicon oxide (SiOx), silicon oxynitride (SiOxNy) (x> y), or the like.
  • a rare gas element such as argon is preferably contained in the reaction gas and mixed into the insulating film.
  • a SiN layer (325 nm) and a SiO 2 layer (50 nm) can be successively deposited on the gate electrode 12 using a CVD apparatus.
  • the oxide semiconductor film 15 is formed over the gate insulating film 14.
  • the oxide semiconductor film 15 is formed by forming a thin film for an oxide semiconductor film on the gate insulating film 14 by sputtering or CVD, and then patterning the thin film for an oxide semiconductor film using a photolithography process. Can be formed.
  • etching can be performed using a resist mask in a photolithography process, and the oxide semiconductor film can be patterned into a desired shape. .
  • the oxide semiconductor included in the oxide semiconductor layer 15 may be an amorphous oxide semiconductor or a crystalline oxide semiconductor having a crystalline portion.
  • the crystalline oxide semiconductor include a polycrystalline oxide semiconductor, a microcrystalline oxide semiconductor, and a crystalline oxide semiconductor in which the c-axis is oriented substantially perpendicular to the layer surface.
  • the oxide semiconductor layer 15 may have a stacked structure of two or more layers. In the case where the oxide semiconductor layer 15 has a stacked structure, the oxide semiconductor layer 15 may include an amorphous oxide semiconductor layer and a crystalline oxide semiconductor layer. Alternatively, a plurality of crystalline oxide semiconductor layers having different crystal structures may be included. In addition, a plurality of amorphous oxide semiconductor layers may be included.
  • the energy gap of the oxide semiconductor included in the upper layer is preferably larger than the energy gap of the oxide semiconductor included in the lower layer.
  • the energy gap of the lower oxide semiconductor may be larger than the energy gap of the upper oxide semiconductor.
  • the oxide semiconductor layer 15 may include at least one metal element of In, Ga, and Zn, for example.
  • the oxide semiconductor layer 15 is, for example, an In—Ga—Zn—O-based semiconductor (hereinafter, abbreviated as “In—Ga—Zn—O-based semiconductor”, and sometimes abbreviated as “IGZO”).
  • a TFT having an In—Ga—Zn—O-based semiconductor layer has high mobility (more than 20 times that of an a-Si TFT) and low leakage current (less than one hundredth of that of an a-Si TFT). It is suitably used as a drive TFT and a pixel TFT.
  • a TFT having an In—Ga—Zn—O-based semiconductor layer is used, power consumption of the display device can be significantly reduced.
  • the In—Ga—Zn—O based semiconductor may be amorphous or may have a crystalline part.
  • a crystalline In—Ga—Zn—O-based semiconductor in which the c-axis is oriented substantially perpendicular to the layer surface is preferable.
  • Such a crystal structure of an In—Ga—Zn—O-based semiconductor is disclosed in, for example, Japanese Patent Laid-Open No. 2012-134475.
  • the oxide semiconductor layer may include another oxide semiconductor instead of the In—Ga—Zn—O-based semiconductor.
  • an In—Sn—Zn—O based semiconductor eg, In 2 O 3 —SnO 2 —ZnO
  • an In—Al—Zn—O based semiconductor e.g. In 2 O 3 —SnO 2 —ZnO
  • ZnO Zn—O based semiconductor
  • IZO In—Zn—O based semiconductor
  • ZTO Zn—Ti—O based semiconductor
  • Cd—Ge—O based semiconductor Cd—Pb—O based semiconductor
  • InGaO 3 (ZnO) 5 magnesium zinc oxide (Mg x Zn 1 ⁇ x O), cadmium zinc oxide (Cd x Zn 1-x O), cadmium oxide (CdO), Mg—Zn—O-based semiconductor, In—Ga—Sn—O-based semiconductor, and the like may be included.
  • ZnO is amorphous in which one or more impurity elements of Group 1 element, Group 13 element, Group 14 element, Group 15 element or Group 17 element are added.
  • a state, a polycrystalline state, a microcrystalline state in which an amorphous state and a polycrystalline state are mixed, or a state in which no impurity element is added can be used.
  • a conductive film 16 for forming a source electrode and a drain electrode is formed on the entire surface of the oxide semiconductor layer 15 and the gate insulating film 14.
  • the conductive layer 16 has a laminated structure in which an aluminum (Al) layer is sandwiched between metal layers other than Al.
  • a metal such as titanium (Ti) or molybdenum (Mo), an alloy thereof, or a metal nitride thereof can be used as appropriate.
  • a Ti layer (50 nm) / Al layer (300 nm) / Ti layer (30 nm) can be formed by sputtering.
  • ion implantation is performed with acceleration energy that passes through the metal layer disposed on the Al layer and does not reach the metal layer disposed below the Al layer (for example, 150 keV, 10 16 / cm 2 ), and by applying the energy, the volume of the Al layer is changed (shrinked) in advance.
  • the acceleration energy for ion implantation can be, for example, 80 to 200 keV, and the density can be, for example, 10 15 to 10 17 ions / cm 2 .
  • various ion-implanted metal elements for imparting energy can be used, but aluminum (Al) is preferable because aluminum (Al) generally includes an impurity element and thus the electrical conductivity is lowered.
  • the laminated structure of the conductive film for S / D electrodes is Ti layer / Al layer / Ti layer
  • the Ti layer under the Al layer and the oxide semiconductor layer for example, IGZO layer
  • the Ti layer under the Al layer and the oxide semiconductor layer react to form a deteriorated layer.
  • the electrode conductive film 16 is processed into a desired shape using a resist mask in a photolithography process, thereby forming the source electrode 16A or the drain electrode 16B.
  • a passivation film (Pas film) 17 that is an insulating film is formed so as to cover the entire structure that has been formed.
  • the thickness of the passivation film is, for example, about 300 to 500 nm.
  • This insulating film can be formed using an insulating material such as silicon nitride, silicon oxide, silicon nitride oxide, or silicon oxynitride using a thin film formation method such as a plasma CVD method or a sputtering method.
  • annealing is performed at a temperature of about 200 to 400 ° C.
  • the passivation film Pas film
  • it can be set to 350 ° C. for 1 hour.
  • the same conditions as the annealing for reducing oxygen defects in the oxide semiconductor film for example, When annealing is performed at 350 ° C. for 1 hour, the lowermost Ti layer or Mo layer of the S / D electrode conductive film reacts with the oxide semiconductor layer, and the oxide semiconductor layer in the channel region changes in quality. Therefore, a TFT having good characteristics cannot be obtained.
  • the layer to which energy is applied can be only the Al layer in the conductive film for the S / D electrode.
  • Such a reaction between the lowermost Ti layer or Mo layer of the S / D electrode conductive film and the oxide semiconductor layer does not occur.
  • a resist mask is formed on the passivation film (Pas film) by a photolithography process, etching for contact holes is performed, and heat treatment is performed on the entire surface of the substrate.
  • the passivation film (Pas film) is not limited to a single layer, and may be two layers or three or more layers. However, the film in contact with the oxide semiconductor layer (for example, the IGZO film) contains oxygen. It is preferably included. Further, a planarizing film made of an organic insulating material may be further formed on the passivation film (Pas film).
  • a transparent conductive film such as ITO or IZO film is formed on the entire surface of the substrate on which the passivation film (Pas film) is formed, for example, by sputtering, and then photolithography, wet etching, and A transparent electrode is formed by removing and cleaning the resist.
  • a display device is obtained in which a liquid crystal layer is sandwiched and held between a counter substrate.
  • Example 10 Glass (AN100 manufactured by Asahi Glass Co., Ltd.) is used as the substrate, and a laminated film of W (370 nm) / TaN (50 nm) is deposited as a conductive film on this substrate using a sputtering apparatus, and then a photolithography method and a dry etching method. To form a gate electrode by processing into a desired pattern. Next, SiN (325 nm) and SiO 2 (50 nm) were successively deposited on the gate electrode by a CVD apparatus to form a gate insulating film. Next, a channel layer made of IGZO was formed on the gate electrode.
  • a three-layer laminated structure of Ti layer (50 nm) / Al layer (300 nm) / Ti layer (30 nm) was formed as a conductive film for S / D electrodes by a sputtering apparatus.
  • the substrate was set to 200 ° C., and Al ion implantation (150 keV, 10 16 ions / cm 2 ) was performed for 1 hour.
  • the S / D electrode conductive film was processed into a desired pattern by a photolithography method and a dry etching method to form an S / D electrode.
  • SiO 2 (300 nm) / SiN (300 nm) was deposited as a passivation film, and annealing (350 ° C., 1 hour) was performed to reduce oxygen defects in the channel layer made of IGZO. Thereafter, an organic flattening film was formed, and an ITO transparent electrode was further formed as a common electrode to produce a channel etch type TFT.
  • the comparative example produced a channel etch type TFT in the same manner as the example except that the Al ion implantation step was not performed.
  • FIG. 5A to 5C show the results of TFT characteristics before and after conducting a high-temperature and high-humidity reliability test for 150 hours in an environment of a temperature of 60 ° C. and a humidity of 95% for the examples and comparative examples.
  • FIG. 5A shows the result of TFT characteristics before the high-temperature and high-humidity reliability test for the example
  • FIG. 5B shows the result of TFT characteristics after the high-temperature and high-humidity reliability test for the comparative example
  • FIG. 5C shows the results of TFT characteristics after the high-temperature and high-humidity reliability test for the example.
  • the TFT characteristics before the high-temperature and high-humidity reliability test were the same as in FIG. 5A.
  • the TFT size (channel size) has a length (L) and a width (W) of 10 ⁇ m and 480 ⁇ m, respectively.
  • the TFT manufactured by the manufacturing method according to one embodiment of the present invention was good with no change in TFT characteristics even after the high temperature and high humidity reliability test.
  • the TFT characteristics of the TFT manufactured by the conventional process deteriorated after the high temperature and high humidity reliability test. This is presumably because moisture entered from cracks generated in the Pas film due to Al voids in the tapered portion of the S / D electrode.
  • One embodiment of the present invention can be applied to a method for manufacturing a channel-etched thin film transistor in which it is necessary to reduce deterioration of the coverage of the S / D electrode taper portion of the passivation film.
  • TFT Thin film transistor
  • SYMBOLS Substrate 12
  • Gate electrode 14 Gate insulating film 15
  • Channel layer 16 Electrode conductive film 16A
  • Source electrode 16B Drain electrode 17 Passivation film (protective film)

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  • Thin Film Transistor (AREA)

Abstract

La présente invention concerne, selon un mode de réalisation, un procédé de fabrication d'un transistor à couches minces de type à gravure de canal qui est un procédé de fabrication d'un transistor à couches minces de type à gravure de canal dans lequel au moins une électrode parmi une électrode source et une électrode déversoir comprend une structure stratifiée de couche de métal autre que Al/couche d'Al/couche de métal autre que Al, et qui a une couche de canal comprenant un semi-conducteur d'oxyde. Le procédé comprend une étape consistant à former un film électroconducteur pour une électrode dans laquelle un film électroconducteur destiné à être utilisé comme électrode source et électrode déversoir est formé, une étape de transmission d'énergie consistant à conférer de l'énergie de façon à réduire le volume de la couche d'Al dans le film électroconducteur, une étape de formation d'électrode consistant à former l'électrode source et l'électrode déversoir par la formation de motifs sur le film électroconducteur, et une étape de formation de film de passivation consistant à former un film de passivation.
PCT/JP2018/012407 2017-03-29 2018-03-27 Procédé de fabrication d'un transistor à couches minces de type à gravure de canal WO2018181296A1 (fr)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007242848A (ja) * 2006-03-08 2007-09-20 Mitsubishi Electric Corp 基板の製造方法及び基板処理装置
JP2015046613A (ja) * 2009-12-04 2015-03-12 株式会社半導体エネルギー研究所 半導体装置
JP2015097272A (ja) * 2009-12-04 2015-05-21 株式会社半導体エネルギー研究所 半導体装置
JP2015149489A (ja) * 2008-09-01 2015-08-20 株式会社半導体エネルギー研究所 酸化物半導体膜及び半導体装置

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007242848A (ja) * 2006-03-08 2007-09-20 Mitsubishi Electric Corp 基板の製造方法及び基板処理装置
JP2015149489A (ja) * 2008-09-01 2015-08-20 株式会社半導体エネルギー研究所 酸化物半導体膜及び半導体装置
JP2015046613A (ja) * 2009-12-04 2015-03-12 株式会社半導体エネルギー研究所 半導体装置
JP2015097272A (ja) * 2009-12-04 2015-05-21 株式会社半導体エネルギー研究所 半導体装置

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