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WO2018182570A1 - Agencements de transistors asymétriques avec régions de drain à espacement intelligent - Google Patents

Agencements de transistors asymétriques avec régions de drain à espacement intelligent Download PDF

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Publication number
WO2018182570A1
WO2018182570A1 PCT/US2017/024391 US2017024391W WO2018182570A1 WO 2018182570 A1 WO2018182570 A1 WO 2018182570A1 US 2017024391 W US2017024391 W US 2017024391W WO 2018182570 A1 WO2018182570 A1 WO 2018182570A1
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Prior art keywords
drain region
transistor
gate
region
drain
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PCT/US2017/024391
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English (en)
Inventor
Luis Felipe GILES
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Intel IP Corporation
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Priority to PCT/US2017/024391 priority Critical patent/WO2018182570A1/fr
Publication of WO2018182570A1 publication Critical patent/WO2018182570A1/fr

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/117—Shapes of semiconductor bodies
    • H10D62/118—Nanostructure semiconductor bodies
    • H10D62/119—Nanowire, nanosheet or nanotube semiconductor bodies
    • H10D62/121—Nanowire, nanosheet or nanotube semiconductor bodies oriented parallel to substrates
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/024—Manufacture or treatment of FETs having insulated gates [IGFET] of fin field-effect transistors [FinFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/40—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels
    • H10D30/43—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having 1D charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/601—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs 
    • H10D30/603—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs  having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended drain IGFETs [EDMOS]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/62—Fin field-effect transistors [FinFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
    • H10D30/6713—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes
    • H10D30/6715—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes characterised by the doping profiles, e.g. having lightly-doped source or drain extensions
    • H10D30/6717—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes characterised by the doping profiles, e.g. having lightly-doped source or drain extensions the source and the drain regions being asymmetrical
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/6735—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes having gates fully surrounding the channels, e.g. gate-all-around
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6757—Thin-film transistors [TFT] characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/23—Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
    • H10D64/251—Source or drain electrodes for field-effect devices

Definitions

  • This disclosure relates generally to the field of semiconductor devices, and more specifically, to asymmetric transistor devices/arrangements with smartly spaced drain regions.
  • Source and drain terminals of the transistor are connected to individual highly doped regions separated by a body region made of a channel material.
  • the source and drain regions can be either P-type or N-type, as long as they are of the same type and of opposite type to the body region. Performance (i.e. on-resistance) of source and drain regions affects performance of a transistor.
  • FIGS. 1A and IB are different cross-sectional views of an exemplary conventional tri-gate MOS transistor.
  • FIG. 2 is a cross-sectional side view of an exemplary conventional extended drain (ED) MOS transistor (EDMOS).
  • EDMOS extended drain MOS transistor
  • FIG. 3 is a cross-sectional side view of an example FinFET having a highly doped (HD) drain region laterally shifted away from a gate stack, in accordance with various embodiments.
  • HD highly doped
  • FIG. 4 is a cross-sectional side view of an example FinFET having an HD drain region vertically shifted away from a gate stack, in accordance with various embodiments.
  • FIG. 5 is a perspective view of an example FinFET, in accordance with various embodiments.
  • FIG. 6 is a perspective view of an example all-around gate transistor, in accordance with various embodiments.
  • FIG. 7 is a flow diagram of an example method of manufacturing a transistor having an HD drain region laterally or/and vertically shifted away from a gate stack, in accordance with various embodiments.
  • FIGS. 8A and 8B are top views of a wafer and dies that include one or more transistors having HD drain regions laterally or/and vertically shifted away from gate stacks in accordance with any of the embodiments disclosed herein.
  • FIG. 9 is a cross-sectional side view of an integrated circuit (IC) device that may include one or more transistors having HD drain regions laterally or/and vertically shifted away from gate stacks in accordance with any of the embodiments disclosed herein.
  • IC integrated circuit
  • FIG. 10 is a cross-sectional side view of an IC device assembly that may include one or more transistors having HD drain regions laterally or/and vertically shifted away from gate stacks in accordance with any of the embodiments disclosed herein.
  • FIG. 11 is a block diagram of an example computing device that may include one or more transistors having HD drain regions laterally or/and vertically shifted away from gate stacks in accordance with any of the embodiments disclosed herein.
  • a transistor arrangement may include one or more semiconductor materials in which a channel of a transistor will be formed during operation (these one or more semiconductor materials referred to in the following as a "channel material"), a gate stack that includes a gate electrode and a gate dielectric and is provided over a portion of the channel material, a source region adjacent to the gate stack, and an HD drain region that is provided at a distance to the gate stack (i.e. is removed, laterally or/and vertically, from the gate stack).
  • the term "HD drain region” refers to a portion of the drain region (i.e.
  • the distance between the HD drain region and the gate stack (e.g. between the closest two points of the HD drain region and the gate stack) may be between about 2 and 100 nanometers (nm), including all values and ranges therein, e.g. between about 2 and 50 nm, or between about 5 and 50 nm.
  • the device is asymmetric because the source region, which can also be (but does not have to be) an HD drain region, is provided adjacent to the gate stack (i.e. is aligned with the gate stack or is overlapping with the gate stack), while the HD drain region is shifted away from the gate stack.
  • providing the HD drain region at a controlled distance between about 2 and 100 nm away from the gate stack advantageously allows controlling the onset GIDL without having to occupy large die area.
  • Transistor arrangements having an HD drain region laterally or/and vertically shifted away from a gate stack as described herein may be implemented in one or more components associated with an integrated circuit (IC) or/and between various such components.
  • components associated with an IC include, for example, transistors, diodes, power sources, resistors, capacitors, inductors, sensors, transceivers, receivers, antennas, etc.
  • Components associated with an IC may include those that are mounted on an IC, provided as an integral part of an IC, or those connected to an IC.
  • the IC may be either analog or digital and may be used in a number of applications, such as microprocessors, optoelectronics, logic blocks, audio amplifiers, etc., depending on the components associated with the IC.
  • the IC may be employed as part of a chipset for executing one or more related functions in a computer.
  • the phrase “A and/or B” means (A), (B), or (A and B).
  • the phrase “A, B, and/or C” means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C).
  • the term "between,” when used with reference to measurement ranges, is inclusive of the ends of the measurement ranges.
  • a "high-k dielectric” refers to a material having a higher dielectric constant than silicon oxide.
  • the terms “substantially,” “close,” “approximately,” “near,” and “about,” generally refer to being within +/- 20% of a target value based on the context of a particular value as described herein or as known in the art.
  • the terms “oxide,” “carbide,” “nitride,” etc. refer to compounds containing, respectively, oxygen, carbon, nitrogen, etc.
  • the performance of a transistor may depend on a number of factors.
  • One factor is how a transistor of a given type and architecture behaves in terms of an early junction breakdown (also known as the "Zener * s breakdown") caused by Gate Induced Drain Leakage (GIDL).
  • GIDL Gate Induced Drain Leakage
  • Transistors can have planar or non-planar architecture. Recently, MOSFETs with non-planar architecture, such as e.g. tri-gate/FinFET and all-around gate transistors, have been extensively explored as alternatives to transistors with planar architecture.
  • FinFETs refer to transistors having a non-planar architecture where a fin, formed of one or more semiconductor materials, extends away from a base. FinFETs are sometimes referred to as "tri-gate transistors," where the name “tri-gate” originates from the fact that, in use, such a transistor may form conducting channels on three "sides" of the fin. FinFETs potentially improve performance relative to single-gate transistors and double-gate transistors.
  • FIGs. 1A and IB An example of a FinFET is shown in FIGs. 1A and IB, illustrating two different cross-sectional views of an exemplary conventional FinFET 100.
  • FIG. 1A illustrates a side view of the FinFET 100, with a cross-section taken along the length of the fin
  • FIG. IB illustrates a front view of the FINFET 100 with a cross-section taken across the gate of the FinFET - i.e.
  • FIG. IB illustrates a cross-sectional view with a cross-section taken along a plane AA shown in FIG. 1A
  • FIG. 1A illustrates a cross-sectional view with a cross-section taken along a plane BB shown in FIG. IB
  • FIG. 1A is also a cross-sectional view with a cross-section taken along a plane CC shown in FIG. 5 that illustrates an exemplary perspective view of a FinFET
  • FIG. IB is a cross-sectional view with a cross-section taken along a plane DD shown in FIG. 5).
  • the FinFET 100 typically includes a substrate 102 over which a channel material 104 is provided.
  • the channel material 104 is formed as a fin 120 extending away from the substrate (the fin 120 is not specifically shown in FIG. 1A because FIG. 1 illustrates a cross- sectional view with a cross-section taken along the length of the fin 120, but can be better seen in FIG. IB).
  • the high-k dielectric 108 may wrap around the upper portion of the fin 120 and the gate electrode material 106 may wrap around the high-k dielectric 108.
  • a dielectric material 112 typically an oxide, commonly referred to as a "shallow trench isolation" (STI).
  • STI shallow trench isolation
  • a gate stack includes a stack of one or more gate electrode metals and a stack of one or more gate dielectrics and is provided over the top and sides of the upper portion of the fin (i.e. the portion above the STI), thus wrapping around the upper portion of the fin and forming a three-sided gate of a tri-gate transistor.
  • FIG. 1A further illustrates source and drain electrodes 124 and 126 formed of one or more electrically conductive materials 110, electrically connected to, respectively, a source region 134 and an HD drain region 136.
  • source/drain (S/D) regions of a transistor also sometimes interchangeably referred to as “diffusion regions" are regions of doped semiconductors, e.g. regions of doped channel material, so as to supply charge carriers for the transistor channel.
  • the S/D regions are highly doped, e.g. with dopant concentrations of at least above 1-10 21 dopants per cubic centimeter (cm '3 ), in order to advantageously form Ohmic contacts with the respective S/D electrodes, although these regions may also have lower dopant concentrations in some
  • the S/D regions 134 and 136 are the regions having dopant concentration higher than in other regions, e.g. in between the source region 134 and the drain region 136, and, therefore, are referred to as HD drain regions.
  • Reference numeral 128 shown in FIG. 1A illustrates a channel region of the FinFET 100.
  • Band-to-band tunneling is the most widely acknowledged mechanism responsible for GIDL GIDL occurs predominantly in the region where the HD drain region is adjacent to or overlaps the gate (i.e. is adjacent to or overlaps the channel material under the gate stack) where the gate work- function and high drain doping concentration enhance the electric field, triggering the band-to-band tunneling of carriers. Therefore, a conventional FinFET device such as the one shown in FIGS. 1A and IB, with its HD drain region being adjacent to the gate stack, is not the first choice to build a high- voltage device. Instead, the most used approach conventionally used to improve on GIDL is a so- called extended drain (ED) MOS (EDMOS), an example of which is illustrated in FIG. 2.
  • ED MOS extended drain MOS
  • FIG. 2 is a cross-sectional side view of an EDMOS FinFET transistor 200, similar to the view of FIG. 1A, where the same reference numerals as those shown in FIGS. 1A-1B illustrate the same or analogous elements, description of which is not, therefore, repeated in detail.
  • the acronym implies, the EDMOS concept requires an extended drain field region with the HD drain region 136 being physically separated from the gate stack 122 by a dummy drain electrode 226 and a dummy gate electrode 222, as shown in FIG. 2.
  • FIG. 2 further illustrates a region 242 which is a region of moderate doping concentration extending from the HD drain region 136 towards, but not reaching, the source region 134.
  • the term "moderate doping region” refers to a region having a doping concentration, of the same type of dopants as the drain region, that is lower than the doping concentration of the HD drain region but higher than that of the channel material.
  • the moderate doping region 242 may have a doping concentration between about 5-10 16 and 2-10 18 cm '3
  • the HD drain region 136 may have a doping concentration higher than about 2 10 18 cm '3 , e.g. above 1-10 19 cm '3 , or 1-10 21 cm '3 .
  • the moderate doping region 242 and the HD drain region 136 both have the same type of dopants - e.g. for an NMOS transistor, both are doped with N-type dopants (thus, the moderate doping region 242 is part of an N-well), while the channel material is a semiconductor material of an opposite type - e.g. for an NMOS transistor the channel material is a P-type semiconductor.
  • the moderate doping region 242 extends, from the edge of the gate stack 122 closest to the HD drain region 136, towards the source region 134, under the gate stack 122, by a length shown in FIG. 2 as a length "CD2." In this manner, contrary to a conventional MOSFET as e.g. shown in FIGS.
  • the gate stack 122 is provided over a P-N junction formed where the channel material 104 interfaces the moderate doping region 242, which reduces the electric field near the gate edge directly impacting band to band tunneling and therefore reducing GIDL.
  • a dimension shown in FIG. 1 as "CD1” then refers to the actual channel length, i.e. a distance between the source region 134 and the moderate doping region 242, while a dimension shown in FIG. 1 as “CD3" refers to the distance by which the HD drain region 136 is laterally/horizontally shifted away from the edge of the gate stack 122 that is closest to the HD drain region.
  • the gate length Lg also indicated in FIG. 2, is equal to the sum of CD1 and CD2.
  • CD1 may be equal to CD2 and equal to e.g. 100 nm
  • CD3 is typically between about 500 and 1000 nm (one to two poly pitches).
  • the distance CD3 shown in FIG. 2 is typically between 500 and 1000 nm.
  • Embodiments of the present disclosure are based on a recognition that the onset of the GIDL can be controlled by creating an asymmetric MOS device placing the HD drain region not adjacent to the gate but at a scalable distance from it that is anywhere between about 2 and 100 nm, in absence of a dummy gate electrode and a dummy drain electrode as is done in conventional EDMOS transistors, advantageously allows controlling the onset of GIDL without having to occupy large die area to implement such control.
  • Embodiments of the present disclosure are further based on a recognition that the control of GIDL may be provided by placing the HD drain region further away from the gate stack by shifting the HD drain region laterally (as shown in the example of FIG.
  • the HD source region is kept at its conventional location, while the HD drain region is separated from the gate by a specific distance, enabling an accurate control of the rise in leakage current.
  • the distance between the HD drain region and the gate stack it is possible to control the onset of GIDL and, if required, delay the P-N junction breakdown event.
  • FIG. 3 is a cross-sectional side view of an example FinFET 300 having an HD drain region laterally shifted away from a gate stack, in accordance with various embodiments.
  • FIG. 3 illustrates a side view, i.e. a cross-section taken along the length of the fin, similar to that shown in FIG. 1A and FIG. 2.
  • the FinFET 300 includes a substrate 302 over which a channel material 304 is provided.
  • the substrate 302 may be any structure on which one or more transistors having HD drain regions spaced from the gate stacks as described herein can be disposed.
  • the substrate 302 may include a semiconductor, such as silicon.
  • the substrate 302 may include an insulating layer, such as an oxide isolation layer, e.g. to electrically isolate the semiconductor material of the substrate 302 from the S/D regions and the channel material 304, and thereby mitigate the likelihood that a conductive pathway will form between the HD source region 334 and the HD drain region 336 through the substrate 302.
  • ILDs that may be included in/on a substrate 302 in some embodiments may include silicon oxide, silicon nitride, aluminum oxide, and/or silicon oxynitride. Any suitable ones of the embodiments of the substrate 302 described with reference to FIG. 3 may be used for the substrate of others of the transistors having HD drain regions laterally or/and vertically shifted away from gate stacks in accordance with any of the embodiments disclosed herein.
  • the channel material 304 may be composed of semiconductor material systems including, for example, N-type or P-type materials systems.
  • the channel material 304 may be formed of a monocrystalline semiconductor.
  • the channel material 304 may be formed of a compound semiconductor with a first sub-lattice of at least one element from group III of the periodic table (e.g., Al, Ga, In), and a second sub-lattice of at least one element of group V of the periodic table (e.g., P, As, Sb).
  • the channel material 304 may be a binary, ternary, or quaternary lll-V compound semiconductor that is an alloy of two, three, or even four elements from groups III and V of the periodic table, including boron, aluminum, indium, gallium, nitrogen, arsenic, phosphorus, antimony, and bismuth.
  • the channel material 304 may
  • the channel material 304 may have a Ge content between 0.6 and 0.9, and advantageously is at least 0.7.
  • the channel material 304 may
  • the channel material 304 may be a ternary lll-V alloy, such as InGaAs or GaAsSb.
  • In content in the channel material 304 may be between 0.6 and 0.9, and advantageously at least 0.7 (e.g., lno.7Gao.3As).
  • the channel material 304 may include a high mobility oxide semiconductor material, such as tin oxide, antimony oxide, indium oxide, indium tin oxide, titanium oxide, zinc oxide, indium zinc oxide, gallium oxide, titanium oxynitride, ruthenium oxide, or tungsten oxide.
  • a high mobility oxide semiconductor material such as tin oxide, antimony oxide, indium oxide, indium tin oxide, titanium oxide, zinc oxide, indium zinc oxide, gallium oxide, titanium oxynitride, ruthenium oxide, or tungsten oxide.
  • the channel material 304 may have a thickness e.g. between about 5 and 100 nanometers, including all values and ranges therein.
  • the channel material 304 is an intrinsic lll-V or IV semiconductor material or alloy, not intentionally doped with any electrically active impurity.
  • nominal impurity dopant levels may be present within the channel material 304, for example to set a threshold voltage Vt, or to provide HALO pocket implants, etc.
  • impurity dopant level within the channel material 304 may be relatively low, for example below about 10 15 cm '3 , and advantageously below 10 13 cm '3 .
  • the channel material 304 is formed as a fin 320 extending away from the substrate (a view of the FinFET 300 with the fin 320 in a cross-section across the fin would be similar to that shown in FIG. IB). Some further considerations with respect to the fin are described below, with reference to FIG. 5.
  • the upper portion of the fin is wrapped by a gate stack 322 including a gate electrode material 306 and a gate dielectric 308, with the active region of the channel material 304 corresponding to the portion of the fin wrapped by the gate stack.
  • the gate dielectric 308 may wrap around the upper portion of the fin and the gate electrode material 306 may wrap around the gate dielectric 308.
  • the gate electrode material 306 may include at least one P-type work function metal or N- type work function metal, depending on whether the transistor 300 is a P-type metal oxide semiconductor (PMOS) transistor or an N-type metal oxide semiconductor (NMOS) transistor (P-type work function metal used as the gate electrode material 306 when the transistors 300 is a PMOS transistor and N-type work function metal used as the gate electrode material 306 when the transistor 300 is an NMOS transistor).
  • PMOS P-type metal oxide semiconductor
  • NMOS N-type metal oxide semiconductor
  • metals that may be used for the gate electrode material 306 may include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, and conductive metal oxides (e.g., ruthenium oxide).
  • metals that may be used for the gate electrode material 306 include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide).
  • the gate electrode material 306 may include a stack of two or more metal layers, where one or more metal layers are work function metal layers and at least one metal layer is a fill metal layer. Further layers may be included next to the gate electrode material 306 for other purposes, such as to act as a diffusion barrier layer or/and an adhesion layer, not specifically shown in FIG. 3.
  • the gate dielectric 308 may be a high-k dielectric (i.e. a dielectric material that has a higher dielectric constant (k) than silicon dioxide) including elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc.
  • k dielectric constant
  • Examples of high-k materials that may be used in the gate dielectric 308 may include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, tantalum oxide, tantalum silicon oxide, lead scandium tantalum oxide, and lead zinc niobate.
  • an annealing process may be carried out on the gate dielectric 308 during manufacture of the transistor 300 to improve the quality of the gate dielectric 308.
  • the gate dielectric 308 may have a thickness, a dimension measured in the vertical direction in the view of FIG. 3, that may, in some embodiments, be between about 0.4 nanometers and 5 nanometers, including all values and ranges therein (e.g., between about 0.5 and 3 nanometers, or between 1 and 2 nanometers).
  • the gate stack 322 of the gate dielectric material 308 and the gate electrode material 306 may be surrounded by a gate spacer, not shown in FIG. 3, configured to provide separation between the gates of different transistors.
  • a gate spacer is typically made of a low-k dielectric material (i.e. a dielectric material that has a lower dielectric constant (k) than silicon dioxide).
  • low-k materials that may be used in such a dielectric spacer may include, but are not limited to, fluorine-doped silicon dioxide, carbon-doped silicon dioxide, spin-on organic polymeric dielectrics such as e.g. polyimide, polynorbornenes, benzocyclobutene, and polytetrafluoroethylene (PTFE), or spin-on silicon based polymeric dielectric such as e.g.
  • low-k materials such as for example porous silicon dioxide or porous carbon-doped silicon dioxide, where large voids or pores are created in a dielectric in order to reduce the overall dielectric constant of the layer, since voids can have a dielectric constant of nearly 1.
  • the lower portion of the fin in the transistor 300 i.e. sub-fin, is surrounded by a dielectric material, typically an oxide, referred to as STI (not specifically shown in the cross-sectional side view of FIG. 3).
  • the dielectric material of the STI layer may e.g. include any of the high-k dielectric materials described herein.
  • the fin of the transistor 300 may further include an HD source region 334 and an HD drain region 336 on either side of the gate stack 322.
  • the source region 334 may be provided adjacent to the gate stack 322 (or could be overlapping with the gate stack, i.e. a portion of the source region 334 could be below the gate stack 322)
  • the HD drain region 336 is
  • lateral/horizontal shift by the distance dv means that the edge of the HD drain region 336 closest to the edge of the gate stack 322 is separated from the gate stack 322 by that distance, as illustrated with showing the distance d L in FIG. 3, or, equally, the distance d L represents the distance between the closest two points of the HD drain region and the gate stack (these two points shown in FIG. 3 as a point 350 of the HD drain region 336 and a point 352 of the gate stack 322).
  • the distance di may be between about 2 and 100 nm, including all values and ranges therein, e.g. a distance between 2 and 50 nm or a distance between 5 and 50 nm.
  • Manufacturing the HD drain region 336 provided at a distance d L from the gate stack may be achieved by e.g. using an appropriate mask or/and an appropriate spacer.
  • the HD source and HD drain regions 334 and 336 are formed within the channel material 304 and, in some embodiments, may include one or more highly doped crystalline semiconductor materials, compared to the channel material 304.
  • dopant levels within the HD source and HD drain regions may be at least 1-10 19 cm '3 , e.g. between about 1-10 19 and 10 ⁇ 10 21 cm '3 .
  • embodiments of the present disclosure may also be implemented for source or/and drain regions having lower doping concentrations, i.e. when the source region or/and HD drain region form Schottky contacts with their respective electrode(s), e.g. doping concentrations between about 5-10 16 and 1-10 19 cm '3 .
  • the HD source and HD drain regions 334 and 336 may be formed within the channel material 304 using either an implantation/diffusion process or a deposition process.
  • dopants such as boron, aluminum, antimony, phosphorous, or arsenic may be ion- implanted into the channel material 304 to form the highly doped regions.
  • An annealing process that activates the dopants and causes them to diffuse farther into the channel material 304 may follow the ion implantation process.
  • an epitaxial deposition process may provide material that is used to fabricate the highly doped regions.
  • the highly doped regions may be fabricated using a silicon alloy such as silicon germanium or silicon carbide.
  • the epitaxially deposited silicon alloy may be doped in situ with dopants such as boron, arsenic, or phosphorous.
  • the highly doped regions may be formed using one or more alternate semiconductor materials such as germanium or a group lll-V material or alloy.
  • one or more layers of metal and/or metal alloys may be used to form the highly doped regions.
  • an etch process may be performed before the epitaxial deposition to create recesses in the channel material 304 in which the material for the highly doped regions is deposited.
  • FIG. 3 further illustrates source and drain electrodes 324 and 326 formed of one or more electrically conductive materials 310, electrically connected to, respectively, the HD source region 334 and the HD drain region 336.
  • the S/D electrode material 310 may include any suitable electrically conductive material, alloy, or a stack of multiple electrically conductive materials.
  • the S/D electrode material 310 may include one or more metals or metal alloys, with metals such as e.g. ruthenium, palladium, platinum, cobalt, nickel, hafnium, zirconium, titanium, tantalum, and aluminum.
  • the S/D electrode material 310 may include one or more electrically conductive alloys oxides or carbides of one or more metals.
  • the S/D conductive material 310 could be the same or different materials for the source electrode 324 and the drain electrode 326, and could be the same or different materials as the gate electrode material 306.
  • the S/D electrode material 310 may have a thickness between about 5 and 500 nm, including all values and ranges therein, e.g. between 5 and 100 nm.
  • FIG. 3 illustrates an embodiment where the HD drain region 336 is shifted away from the gate stack 322 by a lateral shift
  • the onset of GIDL may be analogously controlled by shifting the HD drain region 336 vertically away from the gate stack 322 (i.e. placing the HD drain region 336 at a distance from the drain electrode 326).
  • An exemplary embodiment of such a vertical shift is shown in FIG. 4 providing a cross-sectional side view of an example FinFET400 which is similar to the FinFET 300 except that the HD drain region 336 is now moved down from the position where it would be in a conventional FinFET (e.g. the one illustrated in FIG. 1A-1B) by a vertical distance d v , as shown in FIG. 4.
  • the HD drain region 336 Due to the vertical shift by the distance dv, the HD drain region 336 is provided below the surface of the channel material 304, inside the active region of the transistor, in contrast to the HD drain region being placed substantially at the surface of the channel material in conventional FinFET and EDMOS implementations.
  • vertical shift by the distance dv means that the HD drain region 336 is separated from its drain electrode 326 by that distance, as illustrated with showing the distance dv in FIG. 4, or, equally, the distance dv represents the distance between the closest two points of the HD drain region and the gate stack (these two points shown in FIG.4 as a point 450 of the HD drain region 336 and a point 452 of the gate stack 322).
  • the HD drain region 336 of the FinFET 400 may be embedded in the channel material 304 of the FinFET 400, i.e. it may be surrounded, at least partially or completely (i.e. on all sides) by the channel material 304 or/and the material of the moderate doping region 342.
  • the HD drain region 336 may be positioned so far down within the channel material 304 that may be adjacent to some other material below it, e.g. the material of the substrate 302 or any of the materials which may be provided between the substrate 302 and the channel material 304, such as e.g. a dielectric as described above.
  • Controlling the onset of GIDL by vertically shifting the HD drain region away from the gate stack may be particularly suitable for implementations when it is desirable to e.g. stay with the existing distances between gates of adjacent devices, to stay with the existing poly-pitches used for device manufacturing, etc.
  • the gate, source, and drain electrodes may remain in the same place as in conventional devices, while the HD drain region is provided under the surface of, i.e. embedded in, the channel material, with a via filled with a conductive material providing electrical connectivity between the sub-surface HD drain region and the drain electrode on the surface of the channel material, as e.g. shown in FIG. 4 with a via 440.
  • shifting the HD drain region down as shown in FIG. 4, as opposed to laterally as shown in FIG. 3, may have an additional advantage of saving the device area.
  • Forming an HD drain region embedded in the channel material 306 may be done e.g. by using higher energies to provide a deeper dopant implantation range.
  • the distance dv may be between about 2 and 100 nm, including all values and ranges therein, e.g. a distance between about 2 and 50 nm or a distance between about 5 and 50 nm.
  • the voltages that would trigger the onset of GIDL may be different for the same distance values, depending on whether that distance is a lateral distance or a vertical distance.
  • the triggering voltage may be about 4 Volts (V) for the lateral distance d L of 40 nm, but it would be only about 2 V for the same vertical distance (i.e. for the vertical distance d v of 40 nm). While FIGS.
  • an HD drain region may be shifted away from the gate stack both horizontally and vertically (i.e. diagonally), by a distance comparable to the distances dL and dv described herein.
  • the triggering voltage increases as the distance increases.
  • the triggering voltage may be 2 V for the lateral shift (i.e. the distance d L ) of 10 nm, 3 V - for the lateral shift of 20 nm, 4 V - for the lateral shift of 40 nm, and 5 V - for the lateral shift of 50 nm, and so on (for comparison, the triggering voltage may be 1 V when the HD drain region 336 is positioned adjacent to the gate stack, as e.g. shown in FIG. 1A, i.e. the horizontal distance dL is 0 nm).
  • the triggering voltage may be 2 V for the vertical shift (i.e. the distance dv) of 40 nm, 3 V - for the vertical shift of 65 nm, 4 V - for the vertical shift of 75 nm, 5 V - for the vertical shift of 90 nm, and 6 V - for the vertical shift of 100 nm, and so on (again, for comparison, the triggering voltage may be 1 V when the HD drain region 336 is positioned adjacent to the gate stack, as e.g. shown in FIG. 1A, i.e. the vertical distance dv is 0 nm).
  • Electrostatic discharge refers to a phenomenon of a sudden flow of electricity between two electrically charged objects.
  • ESD presents a challenge in integrated circuits because solid state electronics components used in such circuits, e.g. transistors, can suffer permanent damage when subjected to high voltages.
  • ESD can affect transistors during manufacturing/testing, transit (e.g. shipping, handling, and storage), as well as during normal operation.
  • ESD can be responsible for providing the voltage high enough to trigger GIDL and cause Zener breakdown of a device.
  • One approach to addressing ESD is to create a set of transistor devices, e.g.
  • ESD protection devices serve as fuses or sacrificial devices which may be rendered dysfunctional due to taking on the ESD themselves but thereby protecting from the ESD other circuit components.
  • ESD protection devices serve as fuses or sacrificial devices which may be rendered dysfunctional due to taking on the ESD themselves but thereby protecting from the ESD other circuit components.
  • Conventionally, such a set of devices has been manufactured by varying dopant implantation conditions to achieve various doping concentrations in the HD drain region, hence varying the triggering voltages.
  • Such a conventional approach can be cumbersome and complicated due to the learning and optimization loops required to accurately modify implantation conditions (e.g. implant doses, energies used to implant, etc.) in a given setting.
  • a first transistor may be provided having its HD drain region positioned at a first location with respect to its gate stack, the first location corresponding to a first triggering voltage for that transistor
  • a second transistor may be provided having its HD drain region positioned at a second location with respect to its gate stack, the second location corresponding to a second triggering voltage (different from the first triggering voltage), and so on.
  • such transistors with different triggering voltages may be placed at various location in an IC - e.g.
  • Forming a set of ESD protection devices by varying the location of the HD drain region as described herein to vary the triggering voltage that controls the onset of GIDL is a compromise between valuable die area being used and the level of ESD protection achieved.
  • Strategically arranging devices with various triggering voltages allows achieving sufficient ESD protection even though some of these devices may have lower triggering voltages than others.
  • well regions of moderate doping concentration similar to the moderate doping region 242 shown in FIG. 2 and described above, may, optionally, be implemented as well.
  • An optional moderate doping region is shown in the embodiments of FIGS. 3 and 4 as a region 342.
  • the region 342 extends from the HD drain region 336 towards, but not reaching, the source region 334.
  • the moderate doping region 342 is a region having a doping concentration of the same type of dopants as the HD drain region 336 but lower than the doping concentration of the HD drain region 336 and higher than that of the channel material 304.
  • the moderate doping region 342 may have a doping concentration between about 5-10 16 and 2-10 18 cm ' 3
  • the HD drain region 336 may have a doping concentration higher than about 2-10 18 cm '3 , e.g.
  • the doping concentration of the moderate doping region 342 would also be correspondingly lower, e.g. between about 1-10 15 and 2-10 16 cm '3 .
  • the moderate doping region 242 and the HD drain region 136 both have the same type of dopants - e.g.
  • the moderate doping region 342 forms an N- well
  • the channel material 304 is a semiconductor material of an opposite type - e.g. for an NMOS transistor the channel material is a P-type semiconductor.
  • the moderate doping region 342 may be provided also above the HD drain region 336, as shown in FIG. 4.
  • the moderate doping region 342 extends, from the edge of the gate stack 322 closest to the HD drain region 336, towards the source region 334, under the gate stack 322, by a length shown in FIGS.
  • CD1 may be about 40 nm while CD2 may be about 120 nm if low leakage is an important goal, or, if high performance is an important goal, then CD2 may be about 40 nm while CD1 may be about 120 nm.
  • CD1 may be about 40 nm while CD1 may be about 120 nm.
  • different division of the gate length into CD1 and CD2 is also possible, for various design requirements, all of which are within the scope of the present disclosure.
  • distances d L and dv being between about 2 and 100 nm, these distances may be in different ranges depending e.g. on whether a device in which such transistors are implemented is intended for high-voltage applications such as e.g. input/output (I/O) devices/drivers or low-voltage applications such as e.g. logic gates.
  • I/O input/output
  • low-voltage applications such as e.g. logic gates.
  • gate lengths and, correspondingly, poly pitch distances used in the low- voltage applications are smaller than those used in high-voltage applications.
  • a gate length Lg may be between about 5 and 50 nm, including all values and ranges therein, e.g. between 5 and 20 nm, or between 7 and 10 nm. In other embodiments, e.g. those suitable for low-voltage applications, a gate length Lg may be above 50 nm, e.g. between about 50 and 1000 nm (or even higher), including all values and ranges therein, e.g. between 75 and 200 nm, or between 50 and 100 nm. Thus, in some
  • ranges for the distance dL may be expressed in terms of a poly-pitch distance (i.e. a dimension indicative of the distance between the outer edges of two adjacent poly gates) - e.g. the distance dL may be between about 0.01 x pp and 0.35 x pp, including all values and ranges therein, where pp is a poly pitch distance used in a particular design.
  • a poly-pitch distance pp could be a distance between the outer edges of a gate of the gate stack 322 and a gate that would be provided next along the fin (that gate not specifically shown in FIG. 3 in order to not clutter the drawing).
  • a range for the distance d v may be expressed in terms of a fin-height (i.e. a height of the fin above the STI) - e.g. the distance dv may be between 0.01 x fh and 2.5 x fh including all values and ranges therein, where fh is a fin-height distance used in a particular technology.
  • a fin-height distance fh could be a height of the fin above the STI as e.g. shown with fh in FIG. IB, applied to various embodiments of the present disclosure. Inspection of layout and mask data and reverse engineering of parts of a device to reconstruct the circuit using e.g.
  • transistors having HD drain regions laterally or/and vertically shifted away from gate stacks have been described above with reference to FinFETs, in various embodiments such transistors may be implemented using any suitable transistor structure, two examples of which are shown in FIGS. 5 and 6, both illustrating different non-planar architectures. In other embodiments, teachings of the present disclosure may also be implemented with transistors having planar architectures.
  • FIG. 5 is a perspective view of an example FinFET 500, in accordance with various embodiments.
  • the FinFET 500 may be seen as illustrating a perspective drawing for the FinFET 300 shown in FIGS. 3 or 4, or any other FinFET with an HD drain region laterally or vertically shifted from a gate stack.
  • FIG. 5 illustrates the substrate 302, the channel material 304, the gate electrode 306, the gate dielectric 308, the fin 320, the gate stack 322, the source region 334, and the HD drain region 336.
  • FIG. 5 illustrates STI 512, similar to the STI 112 described above.
  • the fin 320 illustrated in FIG. 5 is shown as having a rectangular cross section, the fin 320 may instead have a cross section that is rounded or sloped at the "top" of the fin 320, and the gate stack 322 may conform to this rounded or sloped fin 320.
  • the FinFET 500 may form conducting channels on three "sides" of the fin 320 wrapped around by the gate stack 322, potentially improving performance relative to single-gate transistors (which may form conducting channels on one "side” of a channel material or substrate) and double-gate transistors (which may form conducting channels on two "sides" of a channel material or substrate).
  • multiple FinFETs similar to that shown in FIG. 5 may be provided along a single fin such as the fin 320, with considerations relevant to providing multiple devices on a single fin being known in the art and, therefore, in the interests of brevity, not specifically described here.
  • FIG. 6 is a perspective view of an example all-around gate transistor 600, in accordance with various embodiments.
  • the transistor 600 of FIG. 6 may include one or more semiconductor materials, including a channel material 304, as described above, the one or more semiconductor materials formed as a wire 620 provided over a substrate, e.g. the substrate 302 as described above.
  • the wire 620 may take the form of a nanowire or nanoribbon, for example.
  • a gate stack including a gate electrode material 306 and a high-k dielectric 308 may wrap entirely or almost entirely around the wire 620 as shown in FIG. 6, with the active region of the channel material 304 corresponding to the portion of the wire 620 wrapped by the gate stack.
  • the high-k dielectric 308 may wrap around the wire 620 and the gate electrode material 306 may wrap around the high-k dielectric 308.
  • the gate stack may fully encircle the wire 620.
  • a layer of oxide material (not specifically shown in FIG. 6) may be provided between the substrate 302 and the gate electrode 306.
  • the wire 620 may include a source region 634 and an HD drain region 636 on either side of the gate stack, as shown.
  • the composition of the channel material 304, the HD source region 634, and the HD drain region 636 may take the form of any of the embodiments disclosed herein, or known in the art.
  • the HD source region 634 and the HD drain region 636 may be implemented as the source region HD 334 and the HD drain region 336 as described above, where the HD drain region 636 is shifted, horizontally or/and vertically from the gate dielectric 308 to be at a non-zero distance from the gate stack of the transistor 600.
  • a dielectric spacer may be provided between the source electrode and the gate stack as well as between the transistor drain electrode and the gate stack of the all-around-gate transistor 600 in order to provide electrical isolation between the source, gate, drain electrodes, similar to a dielectric spacer described above for the FinFET 300.
  • the wire 620 illustrated in FIG. 6 is shown as having a rectangular cross section, the wire 620 may instead have a cross section that is rounded or otherwise irregularly shaped, and the gate stack may conform to the shape of the wire 620.
  • the all-around-gate transistor 600 may form conducting channels on more than three "sides" of the wire 620, potentially improving performance relative to FinFETs.
  • FIG. 6 depicts an embodiment in which the longitudinal axis of the wire 620 runs substantially parallel to a plane of the substrate 302, this need not be the case; in other embodiments, for example, the wire 620 may be oriented "vertically" so as to be perpendicular to a plane of the substrate 302.
  • multiple all-around-gate transistors similar to that shown in FIG. 6 may be provided along a single wire such as the wire 620, with considerations relevant to providing multiple devices on a single wire being known in the art and, therefore, in the interests of brevity, not specifically described here.
  • FIGS. 3-6 do not represent an exhaustive set of transistor structures in which HD drain regions laterally or/and vertically shifted away from gate stacks may be included, but merely provide examples of such structures. Although particular arrangements of materials are discussed with reference to FIGS. 3-6, intermediate materials may be included in the transistor devices of these FIGS. Note that FIGS. 3-6 are intended to show relative arrangements of the components therein, and that transistor devices of these FIGS may include other components that are not illustrated (e.g., gate spacers or various interfacial layers). Additionally, although various components of the transistor devices are illustrated in FIGS.
  • transistor 3-6 as being planar rectangles or formed of rectangular solids, this is simply for ease of illustration, and embodiments of these transistors may be curved, rounded, or otherwise irregularly shaped as dictated by, and sometimes inevitable due to, the manufacturing processes used to fabricate the transistors.
  • FIG. 7 is a flow diagram of an example method 700 of manufacturing a transistor having an HD drain region laterally or/and vertically shifted away from a gate stack, in accordance with various embodiments.
  • the operations of the method 700 are illustrated once each and in a particular order, the operations may be performed in any suitable order and repeated as desired.
  • one or more operations may be performed in parallel to manufacture multiple transistors HD drain regions laterally or/and vertically shifted away from gate stacks substantially simultaneously.
  • the operations may be performed in a different order to reflect the structure of a transistor in which the HD drain region laterally or/and vertically shifted away from gate stack will be included.
  • one or more semiconductor materials for forming a channel may be provided.
  • the one or more semiconductor materials provided at 702 may take the form of any of the embodiments of the channel material 304 disclosed herein, for example (e.g., any of the embodiments discussed herein with reference to the transistors 300, 400, 500, and 600).
  • the one or more semiconductor materials may be provided at 702 using any suitable deposition and patterning techniques known in the art.
  • future S/D regions may be provided within the one or more semiconductor materials 304.
  • the S/D regions defined at 704 may take the form of any of the embodiments of the HD source regions 334 and the HD drain regions 336 disclosed herein, for example (e.g., any of the
  • the S/D regions provided at 704 may be manufactured using any suitable techniques known in the art, such as e.g. using an implantation/diffusion process or a deposition process, possibly using a suitable mask for implementing the HD drain region 336 at a desired location at a distance from the gate stack of a transistor, as described above.
  • the gate dielectric material may be provided.
  • the gate dielectric material provided at 706 may take the form of any of the embodiments of the gate dielectric material 308 disclosed herein, for example (e.g., any of the embodiments discussed herein with reference to the transistors 300, 400, 500, and 600).
  • the gate dielectric material may be provided at 706 using any suitable deposition and patterning techniques known in the art.
  • the gate, source, and drain electrodes may be provided.
  • the S/D electrode material provided at 708 may take the form of any of the embodiments of the S/D electrode material 310 disclosed herein while the gate electrode material provided at 708 may take the form of any of the embodiments of the gate electrode material 306 disclosed herein, for example (e.g., any of the embodiments discussed herein with reference to the transistors 300, 400, 500, and 600).
  • the gate, source, and drain electrodes may be provided at 708 using any suitable deposition and patterning techniques known in the art.
  • Transistors having HD drain regions laterally or/and vertically shifted from gate stacks disclosed herein may be included in any suitable electronic device.
  • FIGS. 8-11 illustrate various examples of apparatuses that may include one or more of the transistor devices with HD drain regions positioned at lateral or/and vertical offsets with respect to gate stacks, as disclosed herein.
  • FIGS. 8A-B are top views of a wafer 2000 and dies 2002 that may include one or more transistors having HD drain regions laterally or/and vertically shifted away from gate stacks in accordance with any of the embodiments disclosed herein.
  • the wafer 2000 may be composed of semiconductor material and may include one or more dies 2002 having IC structures formed on a surface of the wafer 2000.
  • Each of the dies 2002 may be a repeating unit of a semiconductor product that includes any suitable IC (e.g., ICs including one or more transistors 300, 400, 500, 600, or any other transistors having HD drain regions laterally or/and vertically shifted away from gate stacks as described herein).
  • the wafer 2000 may undergo a singulation process in which each of the dies 2002 is separated from one another to provide discrete "chips" of the semiconductor product.
  • devices that include one or more transistors having HD drain regions laterally or/and vertically shifted away from gate stacks as disclosed herein may take the form of the wafer 2000 (e.g., not singulated) or the form of the die 2002 (e.g., singulated).
  • the die 2002 may include one or more transistors (e.g., one or more of the transistors 2140 of FIG. 9, discussed below, which may take the form of any of the transistors having HD drain regions laterally or/and vertically shifted away from gate stacks as described herein) and/or supporting circuitry to route electrical signals to the transistors, as well as any other IC components.
  • the wafer 2000 or the die 2002 may include a memory device (e.g., a static random access memory (SRAM) device), a logic device (e.g., an AND, OR, NAND, or NOR gate), or any other suitable circuit element. Multiple ones of these devices may be combined on a single die 2002.
  • a memory device e.g., a static random access memory (SRAM) device
  • a logic device e.g., an AND, OR, NAND, or NOR gate
  • a memory array formed by multiple memory devices may be formed on a same die 2002 as a processing device (e.g., the processing device 2302 of FIG. 11) or other logic that is configured to store information in the memory devices or execute instructions stored in the memory array.
  • a processing device e.g., the processing device 2302 of FIG. 11
  • other logic that is configured to store information in the memory devices or execute instructions stored in the memory array.
  • FIG. 9 is a cross-sectional side view of an IC device 2100 that may include one or more transistors having HD drain regions laterally or/and vertically shifted away from gate stacks in accordance with any of the embodiments disclosed herein.
  • the IC device 2100 may be formed on a substrate 2102 (e.g., the wafer 2000 of FIG. 8A) and may be included in a die (e.g., the die 2002 of FIG. 8B).
  • the substrate 2102 may be a semiconductor substrate composed of semiconductor material systems including, for example, N-type or P-type materials systems.
  • the substrate 2102 may include, for example, a crystalline substrate formed using a bulk silicon or a silicon-on-insulator substructure.
  • the semiconductor substrate 2102 may be formed using alternative materials, which may or may not be combined with silicon, that include, but are not limited to, germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. Further materials classified as group ll-VI, lll-V, or IV may also be used to form the substrate 2102. Although a few examples of materials from which the substrate 2102 may be formed are described here, any material that may serve as a foundation for an IC device 2100 may be used.
  • the substrate 2102 may be part of a singulated die (e.g., the dies 2002 of FIG. 8B) or a wafer (e.g., the wafer 2000 of FIG. 8A).
  • the IC device 2100 may include one or more device layers 2104 disposed on the substrate 2102.
  • the device layer 2104 may include features of one or more transistors 2140 (e.g., metal oxide semiconductor field-effect transistors (MOSFETs)) formed on the substrate 2102.
  • the device layer 2104 may include, for example, one or more source and/or drain (S/D) regions 2120, a gate 2122 to control current flow in the transistors 2140 between the S/D regions 2120, and one or more S/D contacts 2124 to route electrical signals to/from the S/D regions 2120.
  • S/D source and/or drain
  • the S/D regions 2120 may include the HD source region 334 and the HD drain region 336 as described herein, or any other asymmetric source and drain regions where an HD drain region is positioned as a horizontal or/and vertical shift with respect to the gate and is not adjacent to the gate.
  • the transistors 2140 may include additional features not depicted for the sake of clarity, such as device isolation regions, gate contacts, and the like.
  • the transistors 2140 are not limited to the type and configuration depicted in FIG. 9 and may include a wide variety of other types and configurations such as, for example, planar transistors, non-planar transistors, or a combination of both.
  • Non-planar transistors may include FinFET transistors, such as double-gate transistors or FinFETs, and wrap-around or all-around gate transistors, such as nanoribbon and nanowire transistors.
  • FinFET transistors such as double-gate transistors or FinFETs
  • wrap-around or all-around gate transistors such as nanoribbon and nanowire transistors.
  • at least some of the one or more of the transistors 2140 may have an HD drain region laterally or/and vertically shifted away from a gate stack in accordance with any of the embodiments disclosed herein.
  • a transistor 2140 may take the form of any of the transistors 300, 400, 500, or 600 disclosed herein.
  • Each transistor 2140 may include a gate 2122 formed of at least two layers, a gate dielectric layer and a gate electrode layer.
  • the gate dielectric layer of a transistor 2140 may include one layer or a stack of layers, and the one or more layers may include silicon oxide, silicon dioxide, and/or a high-k dielectric material.
  • the high-k dielectric material included in the gate dielectric layer of the transistor 2140 may take the form of any of the embodiments of the high-k dielectric 308 disclosed herein, for example.
  • the gate electrode when viewed as a cross section of the transistor 2140 along the source-channel-drain direction, may include a U-shaped structure that includes a bottom portion substantially parallel to the surface of the substrate and two sidewall portions that are substantially perpendicular to the top surface of the substrate (e.g., as illustrated for a FinFET of FIGS. 1A and IB).
  • at least one of the metal layers that form the gate electrode may simply be a planar layer that is substantially parallel to the top surface of the substrate and does not include sidewall portions substantially perpendicular to the top surface of the substrate.
  • the gate electrode may include a combination of U-shaped structures and planar, non-U-shaped structures.
  • the gate electrode may include one or more U-shaped metal layers formed atop one or more planar, non-U-shaped layers.
  • the gate electrode may include a V-shaped structure (e.g., when the fin of a FinFET does not have a "flat" upper surface, but instead has a rounded peak).
  • a pair of sidewall spacers may be formed on opposing sides of the gate stack to bracket the gate stack.
  • the sidewall spacers may be formed from a material such as silicon nitride, silicon oxide, silicon carbide, silicon nitride doped with carbon, and silicon oxynitride.
  • Processes for forming sidewall spacers are well known in the art and generally include deposition and etching process steps.
  • a plurality of spacer pairs may be used; for instance, two pairs, three pairs, or four pairs of sidewall spacers may be formed on opposing sides of the gate stack.
  • the S/D regions 2120 may be formed within the substrate 2102 and asymmetric with respect to the gate 2122 of each transistor 2140, as described herein.
  • the S/D regions 2120 formed within the substrate 2102 may take the form of any of the embodiments of the HD source region 334 and the HD drain region 336 discussed above with reference to the having HD drain regions laterally or/and vertically shifted away from gate stacks.
  • the S/D regions 2120 may be formed within the substrate 2102 using any suitable processes known in the art, some of which are described above.
  • Electrical signals such as power and/or input/output (I/O) signals, may be routed to and/or from the transistors 2140 of the device layer 2104 through one or more interconnect layers disposed on the device layer 2104 (illustrated in FIG. 9 as interconnect layers 2106-2110).
  • interconnect layers 2106-2110 electrically conductive features of the device layer 2104 (e.g., the gate 2122 and the S/D contacts 2124) may be electrically coupled with the interconnect structures 2128 of the interconnect layers 2106-2110.
  • the one or more interconnect layers 2106-2110 may form an interlayer dielectric (ILD) stack 2119 of the IC device 2100.
  • ILD interlayer dielectric
  • the interconnect structures 2128 may be arranged within the interconnect layers 2106-1210 to route electrical signals according to a wide variety of designs (in particular, the arrangement is not limited to the particular configuration of interconnect structures 2128 depicted in FIG. 9). Although a particular number of interconnect layers 2106-1210 is depicted in FIG. 9, embodiments of the present disclosure include IC devices having more or fewer interconnect layers than depicted.
  • the interconnect structures 2128 may include trench structures 2128a (sometimes referred to as "lines") and/or via structures 2128b (sometimes referred to as "holes") filled with an electrically conductive material such as a metal.
  • the trench structures 2128a may be arranged to route electrical signals in a direction of a plane that is substantially parallel with a surface of the substrate 2102 upon which the device layer 2104 is formed.
  • the trench structures 2128a may route electrical signals in a direction in and out of the page from the perspective of FIG. 9.
  • the via structures 2128b may be arranged to route electrical signals in a direction of a plane that is substantially perpendicular to the surface of the substrate 2102 upon which the device layer 2104 is formed.
  • the via structures 2128b may electrically couple trench structures 2128a of different interconnect layers 2106-2110 together.
  • the interconnect layers 2106-2110 may include a dielectric material 2126 disposed between the interconnect structures 2128, as shown in FIG. 9.
  • the dielectric material 2126 disposed between the interconnect structures 2128 in different ones of the interconnect layers 2106-2110 may have different compositions; in other embodiments, the composition of the dielectric material 2126 between different interconnect layers 2106-2110 may be the same.
  • a first interconnect layer 2106 (referred to as Metal 1 or "Ml”) may be formed directly on the device layer 2104.
  • the first interconnect layer 2106 may include trench structures 2128a and/or via structures 2128b, as shown.
  • the trench structures 2128a of the first interconnect layer 2106 may be coupled with contacts (e.g., the S/D contacts 2124) of the device layer 2104.
  • a second interconnect layer 2108 (referred to as Metal 2 or "M2") may be formed directly on the first interconnect layer 2106.
  • the second interconnect layer 2108 may include via structures 2128b to couple the trench structures 2128a of the second interconnect layer 2108 with the trench structures 2128a of the first interconnect layer 2106.
  • the trench structures 2128a and the via structures 2128b are structurally delineated with a line within each interconnect layer (e.g., within the second interconnect layer 2108) for the sake of clarity, the trench structures 2128a and the via structures 2128b may be structurally and/or materially contiguous (e.g., simultaneously filled during a dual-damascene process) in some embodiments.
  • a third interconnect layer 2110 (referred to as Metal 3 or "M3") (and additional interconnect layers, as desired) may be formed in succession on the second interconnect layer 2108 according to similar techniques and configurations described in connection with the second interconnect layer 2108 or the first interconnect layer 2106.
  • M3 Metal 3
  • the IC device 2100 may include a solder resist material 2134 (e.g., polyimide or similar material) and one or more bond pads 2136 formed on the interconnect layers 2106-2110.
  • the bond pads 2136 may be electrically coupled with the interconnect structures 2128 and configured to route the electrical signals of the transistor(s) 2140 to other external devices.
  • solder bonds may be formed on the one or more bond pads 2136 to mechanically and/or electrically couple a chip including the IC device 2100 with another component (e.g., a circuit board).
  • the IC device 2100 may have other alternative configurations to route the electrical signals from the interconnect layers 2106-2110 than depicted in other embodiments.
  • FIG. 10 is a cross-sectional side view of an IC device assembly 2200 that may include components having one or more transistors with HD drain regions laterally or/and vertically shifted away from gate stacks in accordance with any of the embodiments disclosed herein.
  • the IC device assembly 2200 includes a number of components disposed on a circuit board 2202 (which may be, e.g., a motherboard).
  • the IC device assembly 2200 includes components disposed on a first face 2240 of the circuit board 2202 and an opposing second face 2242 of the circuit board 2202;
  • components may be disposed on one or both faces 2240 and 2242.
  • any suitable ones of the components of the IC device assembly 2200 may include any of the transistors having HD drain regions laterally or/and vertically shifted away from gate stacks in accordance with any of the embodiments disclosed herein.
  • the circuit board 2202 may be a printed circuit board (PCB) including multiple metal layers separated from one another by layers of dielectric material and interconnected by electrically conductive vias. Any one or more of the metal layers may be formed in a desired circuit pattern to route electrical signals (optionally in conjunction with other metal layers) between the components coupled to the circuit board 2202.
  • the circuit board 2202 may be a non-PCB substrate.
  • the IC device assembly 2200 illustrated in FIG. 10 includes a package-on-interposer structure 2236 coupled to the first face 2240 of the circuit board 2202 by coupling components 2216.
  • the coupling components 2216 may electrically and mechanically couple the package-on-interposer structure 2236 to the circuit board 2202, and may include solder balls (as shown in FIG. 10), male and female portions of a socket, an adhesive, an underfill material, and/or any other suitable electrical and/or mechanical coupling structure.
  • the package-on-interposer structure 2236 may include an IC package 2220 coupled to an interposer 2204 by coupling components 2218.
  • the coupling components 2218 may take any suitable form for the application, such as the forms discussed above with reference to the coupling components 2216. Although a single IC package 2220 is shown in FIG. 10, multiple IC packages may be coupled to the interposer 2204; indeed, additional interposers may be coupled to the interposer 2204.
  • the interposer 2204 may provide an intervening substrate used to bridge the circuit board 2202 and the IC package 2220.
  • the IC package 2220 may be or include, for example, a die (the die 2002 of FIG. 8B), an IC device (e.g., the IC device 2100 of FIG.
  • the interposer 2204 may spread a connection to a wider pitch or reroute a connection to a different connection.
  • the interposer 2204 may couple the IC package 2220 (e.g., a die) to a ball grid array (BGA) of the coupling components 2216 for coupling to the circuit board 2202.
  • BGA ball grid array
  • the IC package 2220 and the circuit board 2202 are attached to opposing sides of the interposer 2204; in other embodiments, the IC package 2220 and the circuit board 2202 may be attached to a same side of the interposer 2204.
  • BGA ball grid array
  • three or more components may be interconnected by way of the interposer 2204.
  • the interposer 2204 may be formed of an epoxy resin, a fiberglass-reinforced epoxy resin, a ceramic material, or a polymer material such as polyimide. In some implementations, the interposer 2204 may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other group lll-V and group IV materials.
  • the interposer 2204 may include metal interconnects 2208 and vias 2210, including but not limited to through-silicon vias (TSVs) 2206.
  • TSVs through-silicon vias
  • the interposer 2204 may further include embedded devices 2214, including both passive and active devices.
  • Such devices may include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices. More complex devices such as radio-frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and microelectromechanical systems (MEMS) devices may also be formed on the interposer 2204.
  • RF radio-frequency
  • MEMS microelectromechanical systems
  • the package-on-interposer structure 2236 may take the form of any of the package-on-interposer structures known in the art.
  • the IC device assembly 2200 may include an IC package 2224 coupled to the first face 2240 of the circuit board 2202 by coupling components 2222.
  • the coupling components 2222 may take the form of any of the embodiments discussed above with reference to the coupling components 2216
  • the IC package 2224 may take the form of any of the embodiments discussed above with reference to the IC package 2220.
  • the IC device assembly 2200 illustrated in FIG. 10 includes a package-on-package structure 2234 coupled to the second face 2242 of the circuit board 2202 by coupling components 2228.
  • the package-on-package structure 2234 may include an IC package 2226 and an IC package 2232 coupled together by coupling components 2230 such that the IC package 2226 is disposed between the circuit board 2202 and the IC package 2232.
  • the coupling components 2228 and 2230 may take the form of any of the embodiments of the coupling components 2216 discussed above, and the IC packages 2226 and 2232 may take the form of any of the embodiments of the IC package 2220 discussed above.
  • the package-on-package structure 2234 may be configured in accordance with any of the package-on-package structures known in the art.
  • FIG. 11 is a block diagram of an example computing device 2300 that may include one or more components including one or more transistor having HD drain regions laterally or/and vertically shifted away from gate stacks in accordance with any of the embodiments disclosed herein.
  • any suitable ones of the components of the computing device 2300 may include a die (e.g., the die 2002 (FIG. 8B)) having one or more transistors having HD drain regions laterally or/and vertically shifted away from gate stacks in accordance with any of the embodiments disclosed herein.
  • Any one or more of the components of the computing device 2300 may include, or be included in, an IC device 2100 (FIG. 9).
  • Any one or more of the components of the computing device 2300 may include, or be included in, an IC device assembly 2200 (FIG. 10).
  • FIG. 11 A number of components are illustrated in FIG. 11 as included in the computing device 2300, but any one or more of these components may be omitted or duplicated, as suitable for the application. In some embodiments, some or all of the components included in the computing device 2300 may be attached to one or more motherboards. In some embodiments, some or all of these components are fabricated onto a single system-on-a-chip (SoC) die.
  • SoC system-on-a-chip
  • the computing device 2300 may not include one or more of the components illustrated in FIG. 11, but the computing device 2300 may include interface circuitry for coupling to the one or more components.
  • the computing device 2300 may not include a display device 2306, but may include display device interface circuitry (e.g., a connector and driver circuitry) to which a display device 2306 may be coupled.
  • the computing device 2300 may not include an audio input device 2324 or an audio output device 2308, but may include audio input or output device interface circuitry (e.g., connectors and supporting circuitry) to which an audio input device 2324 or audio output device 2308 may be coupled.
  • the computing device 2300 may include a processing device 2302 (e.g., one or more processing devices).
  • processing device e.g., one or more processing devices.
  • the term "processing device” or “processor” may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.
  • the processing device 2302 may include one or more digital signal processors (DSPs), application-specific integrated circuits (ASICs), central processing units (CPUs), graphics processing units (GPUs), cryptoprocessors (specialized processors that execute cryptographic algorithms within hardware), server processors, or any other suitable processing devices.
  • DSPs digital signal processors
  • ASICs application-specific integrated circuits
  • CPUs central processing units
  • GPUs graphics processing units
  • cryptoprocessors specialized processors that execute cryptographic algorithms within hardware
  • server processors or any other suitable processing devices.
  • the computing device 2300 may include a memory 2304, which may itself include one or more memory devices such as volatile memory (e.g., dynamic random access memory (DRAM)), nonvolatile memory (e.g., read-only memory (ROM)), flash memory, solid state memory, and/or a hard drive.
  • volatile memory e.g., dynamic random access memory (DRAM)
  • nonvolatile memory e.g., read-only memory (ROM)
  • flash memory solid state memory
  • solid state memory solid state memory
  • a hard drive e.g., solid state memory, and/or a hard drive.
  • the memory 2304 may include memory that shares a die with the processing device 2302. This memory may be used as cache memory and may include embedded dynamic random access memory (eDRAM) or spin transfer torque magnetic random-access memory (STT-MRAM).
  • eDRAM embedded dynamic random access memory
  • STT-MRAM spin transfer torque magnetic random-access memory
  • the computing device 2300 may include a communication chip 2312 (e.g
  • the communication chip 2312 may be configured for managing wireless communications for the transfer of data to and from the computing device 2300.
  • wireless and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a nonsolid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not.
  • the communication chip 2312 may implement any of a number of wireless standards or protocols, including but not limited to Institute for Electrical and Electronic Engineers (IEEE) standards including Wi-Fi (IEEE 802.11 family), IEEE 802.16 standards (e.g., IEEE 802.16-2005 Amendment), Long-Term Evolution (LTE) project along with any amendments, updates, and/or revisions (e.g., advanced LTE project, ultramobile broadband (UMB) project (also referred to as "3GPP2”), etc.).
  • IEEE 802.16 compatible Broadband Wireless Access (BWA) networks are generally referred to as WiMAX networks, an acronym that stands for Worldwide Interoperability for
  • Microwave Access which is a certification mark for products that pass conformity
  • the communication chip 2312 may operate in accordance with a Global System for Mobile Communication (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE network.
  • GSM Global System for Mobile Communication
  • GPRS General Packet Radio Service
  • UMTS Universal Mobile Telecommunications System
  • High Speed Packet Access HSPA
  • E-HSPA Evolved HSPA
  • LTE LTE network.
  • the communication chip 2312 may operate in accordance with Enhanced Data for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN).
  • EDGE Enhanced Data for GSM Evolution
  • GERAN GSM EDGE Radio Access Network
  • UTRAN Universal Terrestrial Radio Access Network
  • E-UTRAN Evolved UTRAN
  • the communication chip 2312 may operate in accordance with Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution-Data Optimized (EV-DO), and derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond.
  • CDMA Code Division Multiple Access
  • TDMA Time Division Multiple Access
  • DECT Digital Enhanced Cordless Telecommunications
  • EV-DO Evolution-Data Optimized
  • the communication chip 2312 may operate in accordance with other wireless protocols in other embodiments.
  • the computing device 2300 may include an antenna 2322 to facilitate wireless communications and/or to receive other wireless communications (such as AM or FM radio transmissions).
  • the communication chip 2312 may manage wired communications, such as electrical, optical, or any other suitable communication protocols (e.g., the Ethernet). As noted above, the communication chip 2312 may include multiple communication chips. For instance, a first communication chip 2312 may be dedicated to shorter-range wireless
  • a second communication chip 2312 may be dedicated to longer-range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, or others.
  • a first communication chip 2312 may be dedicated to wireless communications, and a second communication chip 2312 may be dedicated to wired communications.
  • the computing device 2300 may include battery/power circuitry 2314.
  • the battery/power circuitry 2314 may include one or more energy storage devices (e.g., batteries or capacitors) and/or circuitry for coupling components of the computing device 2300 to an energy source separate from the computing device 2300 (e.g., AC line power).
  • the computing device 2300 may include a display device 2306 (or corresponding interface circuitry, as discussed above).
  • the display device 2306 may include any visual indicators, such as a heads-up display, a computer monitor, a projector, a touchscreen display, a liquid crystal display (LCD), a light-emitting diode display, or a flat panel display, for example.
  • LCD liquid crystal display
  • the computing device 2300 may include an audio output device 2308 (or corresponding interface circuitry, as discussed above).
  • the audio output device 2308 may include any device that generates an audible indicator, such as speakers, headsets, or earbuds, for example.
  • the computing device 2300 may include an audio input device 2324 (or corresponding interface circuitry, as discussed above).
  • the audio input device 2324 may include any device that generates a signal representative of a sound, such as microphones, microphone arrays, or digital instruments (e.g., instruments having a musical instrument digital interface (MIDI) output).
  • MIDI musical instrument digital interface
  • the computing device 2300 may include a global positioning system (GPS) device 2318 (or corresponding interface circuitry, as discussed above).
  • GPS global positioning system
  • the GPS device 2318 may be in
  • the computing device 2300 may include an other output device 2310 (or corresponding interface circuitry, as discussed above).
  • Examples of the other output device 2310 may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or an additional storage device.
  • the computing device 2300 may include an other input device 2320 (or corresponding interface circuitry, as discussed above).
  • Examples of the other input device 2320 may include an accelerometer, a gyroscope, a compass, an image capture device, a keyboard, a cursor control device such as a mouse, a stylus, a touchpad, a bar code reader, a Quick Response (QR) code reader, any sensor, or a radio frequency identification (RFID) reader.
  • RFID radio frequency identification
  • the computing device 2300 may have any desired form factor, such as a hand-held or mobile computing device (e.g., a cell phone, a smart phone, a mobile internet device, a music player, a tablet computer, a laptop computer, a netbook computer, an ultrabook computer, a personal digital assistant (PDA), an ultramobile personal computer, etc.), a desktop computing device, a server or other networked computing component, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a vehicle control unit, a digital camera, a digital video recorder, or a wearable computing device.
  • the computing device 2300 may be any other electronic device that processes data.
  • Example 1 provides a transistor, including a channel material; a gate electrode material provided over the channel material as a part of a gate stack; a source region coupled to the channel material (i.e. electrically coupled in order to be able to provide carriers for the channel materials); and an HD drain region laterally separated from the gate electrode, by the channel material, by a distance between 2 and 100 nm, e.g. a distance between 2 and 50 nm or a distance between 5 and 50 nm, where the HD drain region is a region having a dopant concentration higher than a dopant concentration between the HD drain region and the source region.
  • each of the source and drain regions are regions of doped semiconductor materials, while the channel material may include one or more semiconductor materials with doping concentrations significantly smaller than those of the source and drain regions.
  • the channel material may be an intrinsic (i.e. undoped) lll-V or IV semiconductor material or alloy, not intentionally doped with any electrically active impurity.
  • one or more a nominal impurity dopant level may be present within the channel material, for example to set a threshold voltage Vt, or to provide HALO pocket implants, etc.
  • impurity dopant level within the channel material are still significantly lower than in the source and drain regions, for example below 10 15 dopant elements per cubic centimeter (cm '3 ), and advantageously below 10 13 cm '3 .
  • the gate electrode material, as well as each of the source electrode material and the drain electrode material may include one or more of conductor materials, e.g. one or more metals.
  • Example 2 provides the transistor according to Example 1, where the HD drain region has a dopant concentration of at least 1-5-10 16 dopant elements (dopants) per cubic centimeter, e.g. between 1-10 19 and 10 ⁇ 10 21 dopants per cubic centimeter.
  • dopants dopant elements
  • Example 3 provides the transistor according to Examples 1 or 2, further including a gate dielectric between the gate electrode material and the channel material.
  • Example 4 provides the transistor according to Example 3, where the channel material is shaped as a fin, and the gate dielectric wraps around the fin. Thus, the transistor may be a FinFET.
  • Example 5 provides the transistor according to Example 3, where the channel material is shaped as a wire, and the gate dielectric wraps around the wire. Thus, the transistor may be a wraparound transistor.
  • Example 6 provides the transistor according to Example 5, where the gate dielectric wraps entirely around the wire.
  • the transistor may be an all-around gate transistor.
  • Example 7 provides the transistor according to any one of the preceding Examples, where the transistor has a gate length between 10 and 1000 nm, e.g. between 5 and 20 nm, or between 30 and 300 nm.
  • Example 8 provides the transistor according to any one of the preceding Examples, further including a source electrode electrically connected to the source region and a drain electrode electrically connected to the HD drain region.
  • Example 9 provides a transistor, including a channel material; a gate electrode material; an HD source region; and an HD drain region embedded within the channel material.
  • an HD drain region being "embedded" within the channel material refers to the HD drain region being surrounded by the channel material at least on the top and bottom sides and the side facing the source region, possibly surrounded on all sides.
  • the channel material may include a plurality of semiconductor materials and the channel materials on different sides of the embedded HD drain region may be different materials (e.g. a portion of the channel material below the HD drain region may be made of a semiconductor material that is different from a portion of the channel material above the embedded HD drain region).
  • Example 10 provides the transistor according to Example 9, further including a drain electrode electrically connected to the HD drain region.
  • Example 11 provides the transistor according to Example 10, where a distance between the HD drain region and the drain electrode is between about 2 and 100 nanometers, e.g. between about 2 and 75 nm or between about 5 and 50 nm.
  • Example 12 provides the transistor according to any one of Examples 9-11, further including a gate dielectric between the gate electrode material and the channel material.
  • Example 13 provides the transistor according to Example 12, where the channel material is shaped as a fin, and the gate dielectric wraps around the fin.
  • the transistor may be a FinFET.
  • Example 14 provides the transistor according to Example 12, where the channel material is shaped as a wire, and the gate dielectric wraps around the wire.
  • the transistor may be a wraparound transistor.
  • Example 15 provides the transistor according to Example 14, where the gate dielectric wraps entirely around the wire. Thus, the transistor may be an all-around gate transistor.
  • Example 16 provides the transistor according to any one of Examples 9-15, where the HD drain region has a doping concentration of at least 5-10 16 dopant elements, e.g. between 1-10 19 dopant elements per cubic centimeter and 10 ⁇ 10 21 dopant elements per cubic centimeter.
  • Example 17 provides the transistor according to any one of Examples 9-16, where the transistor has a gate length between 10 and 1000 nm, e.g. between 5 and 20 nm, or between 30 and 300 nm.
  • Example 18 provides a method of manufacturing a transistor.
  • the method includes providing one or more semiconductor materials for forming a channel of the transistor; providing an HD source region and an HD drain region including one or more doped semiconductor materials; providing a gate dielectric material over the channel; and providing a gate electrode material over the gate dielectric material, where the HD drain region is separated from the gate dielectric material, either laterally or vertically, by a distance between 2 and 100 nm, e.g. a distance between 2 and 50 nm or a distance between 5 and 50 nm.
  • Example 19 provides the method according to Example 18, where providing the HD drain region includes doping the one or more semiconductor materials of the channel to form the HD drain region.
  • Example 20 provides the method according to Example 19, further including performing an anneal of the transistor to activate dopants of the HD drain region.
  • Example 21 provides the method according to Example 18, where providing the HD drain region includes forming an opening for the HD drain region in the one or more semiconductor materials of the channel, and depositing the one or more doped semiconductor materials into the opening, e.g. using chemical vapor deposition (CVD), atomic layer deposition (ALD), or physical vapor deposition (PVD).
  • CVD chemical vapor deposition
  • ALD atomic layer deposition
  • PVD physical vapor deposition
  • the method also includes providing a source electrode material to be in electrical contact with the source region and providing a drain electrode material to be in electrical contact with the HD drain region.
  • providing transistor electrode materials includes depositing titanium, aluminum, titanium nitride, erbium, gadolinium, or ytterbium, using any suitable deposition and patterning techniques.
  • Example 22 provides a computing device that includes a substrate and an integrated circuit (IC) die coupled to the substrate.
  • the IC die includes a transistor having a channel material, a gate electrode material, a gate dielectric material between the gate electrode material and the channel material, an HD drain region separated from the gate dielectric material, either laterally or vertically, by a distance between 2 and 100 nm, e.g. a distance between 2 and 50 nm or a distance between 5 and 50 nm.
  • Example 23 provides the computing device according to Example 22, where the computing device is a wearable or handheld computing device.
  • Example 24 provides the computing device according to Examples 22 or 23, where the computing device further includes one or more communication chips and an antenna.
  • Example 25 provides the computing device according to any one of Examples 22-24, where the substrate is a motherboard.

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Abstract

La présente invention concerne des agencements de transistors ayant des régions de source et de drain asymétriques, et des procédés et des dispositifs associés. Un agencement de transistor donné à titre d'exemple comprend un matériau de canal, un empilement de grille qui comprend une électrode de grille et un diélectrique de grille et est disposé sur une partie du matériau de canal, une région de source adjacente à l'empilement de grille, et une région de drain hautement dopée (HD) qui est décalée par rapport à l'empilement de grille, latéralement et/ou verticalement, d'une distance comprise entre environ 2 et 100 nanomètres, la région de drain HD étant une région d'un matériau semi-conducteur ayant une concentration de dopant supérieure à une concentration de dopant entre la région de drain HD et la région de source. La disposition de la région de drain HD à une distance régulée entre environ 2 et 100 nanomètres à l'opposé de l'empilement de grille permet avantageusement de commander l'apparition de GIDL sans devoir occuper une grande zone de puce pour mettre en œuvre une telle commande.
PCT/US2017/024391 2017-03-28 2017-03-28 Agencements de transistors asymétriques avec régions de drain à espacement intelligent WO2018182570A1 (fr)

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EP4350774A4 (fr) * 2022-08-03 2024-08-21 Changxin Memory Technologies, Inc. Structure semi-conductrice et son procédé de fabrication

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