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WO2018182636A1 - Fusible intégré dans une interconnexion locale et techniques de formation - Google Patents

Fusible intégré dans une interconnexion locale et techniques de formation Download PDF

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Publication number
WO2018182636A1
WO2018182636A1 PCT/US2017/025124 US2017025124W WO2018182636A1 WO 2018182636 A1 WO2018182636 A1 WO 2018182636A1 US 2017025124 W US2017025124 W US 2017025124W WO 2018182636 A1 WO2018182636 A1 WO 2018182636A1
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WO
WIPO (PCT)
Prior art keywords
fuse
contact
semiconductor
trench
layer
Prior art date
Application number
PCT/US2017/025124
Other languages
English (en)
Inventor
Chen-Guan LEE
Roman OLAC-VAW
Walid Hafez
Joodong Park
Rahul RAMASWAMY
Original Assignee
Intel Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corporation filed Critical Intel Corporation
Priority to PCT/US2017/025124 priority Critical patent/WO2018182636A1/fr
Publication of WO2018182636A1 publication Critical patent/WO2018182636A1/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
    • H01L23/5256—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising fuses, i.e. connections having their state changed from conductive to non-conductive
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/40—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00 with at least one component covered by groups H10D10/00 or H10D18/00, e.g. integration of IGFETs with BJTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H10D84/834—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET] comprising FinFETs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822—Multilayer substrates

Definitions

  • Fuses are used in integrated circuit devices to provide overcurrent protection. When an excessive current is applied to a fuse such as a thin metal line, the fuse changes from electrically conductive to electrically open. The amount of current needed to form an open circuit depends at least in part on the cross-sectional area of the fuse structure. In general, it is difficult to form an integrated fuse having a desired breaking current, particularly as the size of integrated circuits shrinks with each advance in manufacturing nodes.
  • FIG. 1. depicts a top plan view of a semiconductor structure, arranged according to embodiments of the disclosure.
  • FIG. 2 depicts a side cross-sectional view of the semiconductor structure of FIG. 1.
  • FIG. 3 depicts a close-up side cross-section view of an integrated fuse according to embodiments of the disclosure.
  • FIG. 4. depicts a top plan view of another semiconductor structure, arranged according to other embodiments of the disclosure.
  • FIG. 5 depicts a side cross-sectional view of the semiconductor structure of FIG. 4.
  • FIGs. 6-13 depict a side cross-section view of a substrate at different stages of a process flow, in accordance with various embodiments of the disclosure.
  • FIG. 14 depicts an exemplary first process flow.
  • FIG. 15 depicts an exemplary second process flow.
  • FIG. 16 depicts an exemplary third process flow.
  • FIG. 17 illustrates an exemplary system.
  • the embodiments of the present disclosure present integrated fuse structures and techniques for forming integrated fuse structures in integrated circuit (IC) devices.
  • the integrated circuit devices may be formed in a semiconductor die that includes a substrate and various other components for performing functions such as logical operations, memory storage or retrieval, communications, or other functions.
  • the embodiments are not limited in this context.
  • integrated fuses are described that are integrated into the front end of an integrated circuit, and in particular, form part of a local interconnect structure directly connecting semiconductor devices, such as transistors. It is noted, to produce a fuse having a low program current (break current), in a simple fuse structure the cross-section of the fuse may be designed to be small compared to other circuit conductors connected to the fuse. The ability to accurately and reproducibly produce fuses having a designed program current in this manner may be limited by lithographic patterning capabilities, which capabilities determine linewidth, and thus cross-section area for a given fuse.
  • Another approach for fuse design harnesses the property of electromigration observed between two different metallic materials.
  • two different metal lines may be stacked together in an integrated circuit device, and may be connected to one another through a metallic contact, such as a via.
  • a metallic contact such as a via.
  • momentum transfer between the conduction electrons in an electrical current and the metal ions is vigorous. Above a certain current level, atoms move and create voids close to the interface, between different metal materials, thus creating an open a circuit.
  • Accurate design of program current for an electromigration fuse accordingly depends on a number of factors including control of interfaces between different metals. Additionally, with efforts to reduce electromigration in integrated circuit wiring, the value of program current generated by such fuses may increase substantially and beyond an acceptable level.
  • FIG. 1 depicts a top plan view of a semiconductor structure 10, arranged according to embodiments of the disclosure.
  • FIG. 2 depicts a side cross-sectional view of the semiconductor structure 10, shown along the section A- A of FIG. 1.
  • the semiconductor structure 10 may be formed in a substrate 12, such as a monocrystalline semiconductor.
  • the substrate 12 may represent a bulk semiconductor, a layer of semiconductor-on-insulator, or other structure.
  • the semiconductor structure 10 may include components such as transistors.
  • the transistors may include a number of configurations such as, for example, planar and non-planar transistors such as dual- or double-gate transistors, tri-gate transistors, and all-around gate (AAG) or wrap- around gate transistors.
  • AAG all-around gate
  • the semiconductor structure 10 may include a pair of semiconductor fins, shown as a first semiconductor fin 14A and a second semiconductor fin 14B, disposed adjacent to the first semiconductor fin 14 A.
  • the first semiconductor fin 14A and the second semiconductor fin 14B may be a monocrystalline semiconductor, integrally formed from the substrate 12, where the substrate 12 is also a monocrystalline semiconductor. Examples of a monocrystalline semiconductor include silicon, silicon germanium alloy, and strained silicon. The embodiments are not limited in this context.
  • the term "substrate” as used herein may refer to a substrate base supporting other elements, layers or features, including features that are formed integrally from the substrate base.
  • the semiconductor structure 10 may further include a first contact structure 18 A, disposed around the first semiconductor fin 14A.
  • the semiconductor structure 10 may also include a second contact structure 18B, disposed around the second semiconductor fin 14B, as shown.
  • the first contact structure 14A and the second contact structure 14B may be formed as trench contacts.
  • a first trench contact may be used to contact to a first source/drain region associated with the first fin structure 14A, and where the second trench contact is used to contact to a second source/drain region associated with the second fin structure 14B.
  • the semiconductor structure 10 may include gate structures 30, where the gate structures 30 are used to form transistor device(s) using the first semiconductor fin 14A and second semiconductor fin 14B.
  • the gate structures 30 may in particular regulate current flow along the first semiconductor fin 14A and/or second semiconductor fin 14B along the X-axis of the Cartesian coordinate system shown.
  • an integrated fuse 20 is provided. As shown, the integrated fuse 20 is disposed between the first contact structure 18A and the second contact structure 18B, where the integrated fuse 20 forms a fusible link between the first contact structure 18A and the second contact structure 18B.
  • the semiconductor structure 10 includes an insulator material 16, where the insulator material 16 is disposed subjacent the integrated fuse 20 and is disposed between the first contact structure 18A and the second contact structure 18B.
  • the insulator material may be, for example, an oxide or other suitable electrical insulator.
  • the integrated fuse 20 includes a fuse element 22 arranged in a fuse layer, where the fuse element 20 is disposed in contact with the insulator layer 16.
  • the integrated fuse 20 also includes a plug 24, disposed at least partially over the fuse element 22.
  • the integrated fuse 20 Under normal operation where current in the semiconductor structure 10 does not exceed a program current, the integrated fuse 20 provides a local electrical interconnection between the first contact structure 18A and the second contact structure 18B. When program current is exceeded in the semiconductor structure 10, the integrated fuse 20 may open, limiting current in semiconductor structure 10 due to breaking of the local interconnect between first contact structure 18A and second contact structure 18B.
  • the plug 24 of the integrated fuse 20 may be formed from an electrical insulator. Accordingly, electrical current may be conducted just through the fuse element 22 under normal operation.
  • the program current of integrated fuse 20 may be controlled accurately by the selection of material for fuse element 22, as well as the thickness of the fuse element 22.
  • FIG. 3 there is shown a close-up side cross-section view of the integrated fuse 20, wherein the fuse element 22 is arranged as a fuse layer having a layer thickness IF along a direction parallel to the Z-axis as shown.
  • the fuse element 22 may be formed by blanket deposition of a metal layer of a material to be used for the fuse element 22. Because suitable deposition processes such as physical vapor deposition or chemical vapor deposition, or atomic layer deposition are highly controllable, the thickness of the fuse element 22 may be very accurately and reproducibly (precisely) controlled. Accordingly, the architecture of the semiconductor structure 10 provides an accurately controlled break current for limiting current at the local interconnect level between devices.
  • the metal material or materials to be used as the fuse element 22 may be selected to adjust the program current. For example, for a given layer thickness, a tungsten layer may generate a lower program current than a cobalt layer. Metals or combination of metals to be used for fuse element 22 may include any combination of one or more suitable metal. In various non-limiting embodiments, the layer thickness for fuse element may be between 1 nm to 50 nm.
  • a notable feature of the semiconductor structure 10 is that the integrated fuse 20 may be formed in electrical contact with the first contact structure 18 A and the second contact structure 18B is a reliable structure.
  • a semiconductor structure provides an integrated fuse where two separate contact structures for front-end devices are self- aligned to the integrated fuse that electrically connects the separate contact structures.
  • this self-alignment is facilitated by the plug 24, as well as the additional plugs, shown as plugs 32, which plugs may act as an etch mask during formation of the semiconductor structure 10.
  • This feature provides a simple and more robust architecture, facilitating the incorporation of a reliable fuse of accurately controllable properties within a local interconnect environment.
  • FIG. 4 there is shown a top plan view of a semiconductor structure 100, arranged according to additional embodiments of the disclosure.
  • FIG. 5 depicts a side cross- sectional view of the semiconductor structure 100, shown along the section A- A of FIG. 4.
  • the semiconductor structure 100 may be formed in a substrate 102, such as a monocrystalline semiconductor.
  • the semiconductor structure 100 may include components such as transistors, as described above with respect to semiconductor structure 10.
  • the semiconductor structure 100 may include a multiplicity of semiconductor fins, shown as four semiconductor fins 104.
  • a pair of the semiconductor fins 104 is covered by a first contact structure 108 A, arranged as a trench contact.
  • An additional pair of semiconductor fins 104 is covered by a second contact structure 108B.
  • the semiconductor structure 100 may be formed in a substrate 102, such as a monocrystalline semiconductor.
  • the semiconductor structure 100 may include components such as transistors, as described above with respect to semiconductor structure 10.
  • the semiconductor structure 100 may include a multiplicity of semiconductor fins, shown as four semiconductor fins 104.
  • a pair of the semiconductor fins 104 is covered by a first contact structure 108 A, arranged as a trench contact.
  • An additional pair of semiconductor fins 104 is covered by a second contact structure 108B.
  • semiconductor structure 100 includes an integrated fuse 114, disposed between the first contact structure 108 A and the second contact structure 108B.
  • the semiconductor structure 100 may further include gate structures 124, where the gate structures 124 are used to form transistor device(s) using one or more of the semiconductor fins 104.
  • the semiconductor structure 100 includes an insulator material 106, where the insulator material 106 is disposed subjacent the integrated fuse 114 and is disposed between the first contact structure 108 A and the second contact structure 108B.
  • additional contact structures, contact structure 108C and contact structure 108D are additional contact structures, contact structure 108C and contact structure 108D, where these other contact structures may not necessarily be linked to additional components through a fuse.
  • the integrated fuse 114 includes a fuse element 116 arranged in a fuse layer, where the fuse element 116 is disposed in contact with the insulator layer 106.
  • the integrated fuse 114 also includes a plug 112, disposed at least partially over the fuse element 114.
  • the integrated fuse 114 may operate similarly to integrated fuse 20, described above.
  • the semiconductor structure 100 also may include wiring to back-end levels of an integrated circuit, as depicted particularly in FIG. 5.
  • a layer 118 is shown therein, not visible in the top plan view of FIG. 4.
  • the layer 118 includes a matrix of interlevel dielectric (ILD), formed from any suitable material for ILD, as well as contact vias 122, which vias extend to electrically couple the contact structure 108A, contact structure 108B, as well as contact structure 108C to wiring at higher levels, or back-end levels.
  • ILD interlevel dielectric
  • An advantage of providing an integrated fuse 114 between the contact structure 108A and contact structure 108B is the better control of fuse properties as compared to a known electromigration-based fuses operating between different wiring levels, by intentionally using fuse materials having desired fuse properties, such as a desired electromigration or conductivity.
  • FIGS. 6-13 there are shown a side cross-section view of a substrate at different stages of a process flow, in accordance with various embodiments of the disclosure.
  • a semiconductor structure 150 is formed, similar to the semiconductor structure 100 discussed previously.
  • the cross-section shown in FIGS. 6-13 may correspond to the cross-section A-A shown in FIG. 4.
  • FIG. 6 schematically illustrates a cross-section side view of an example substrate at one stage of a process flow, in accordance with embodiments of the disclosure.
  • a substrate 102 is provided, while semiconductor fins 104 are formed above the substrate 102.
  • the semiconductor fins 104 may be monocrystalline and may be formed integrally from the same structure of substrate 102.
  • An insulator layer 106 has been deposited on the substrate 102.
  • the semiconductor fins may be doped to form device structures, such as transistors.
  • An insulator layer 106 has been deposited on the substrate 102, which deposition may be followed by a planarization operation.
  • a mask is formed on the insulator layer 106, which mask includes mask features 130.
  • the mask features 130 may be formed using any suitable process, such as a blanket deposition of a photoresist layer or hardmask layer, followed by lithographic patterning.
  • FIG. 7 a subsequent stage is shown.
  • an etch operation removes portions of the insulator layer 106 that are not protected by the mask feature 130.
  • the removal of the mask features 130 leaves a multiplicity of recesses, shown as recesses 132, in the surface of the insulator layer 106.
  • the etching of the insulator layer 106 may be performed to generate a depth D of the recesses 132, according to a designed thickness of plugs to be formed in the recesses 132, or equivalently to a designed height H of an integrated device to be formed (see FIG. 3).
  • the width may be designed to equal a fuse width WF.
  • FIG. 8 shows a subsequent stage after the depositing of a fuse layer 114A on the insulator layer 106.
  • the fuse layer 114A may be deposited to a thickness along the Z-axis according to a designed layer thickness of the fuse element 114, discussed previously.
  • the fuse layer 114A may be deposited by any suitable deposition process, such as blanket deposition processes, including, but not limited to, physical vapor deposition, chemical vapor deposition, and atomic layer deposition. As shown, the fuse layer 114A coats the recesses 132.
  • patterning of the fuse layer 114A is performed.
  • the patterning may be performed using any suitable technique.
  • a blanket patterning layer, such as photoresist is deposited, followed by lithographic definition to form a mask feature on the fuse layer 114A, and etching of the fuse layer 114A in regions not covered by the mask.
  • FIG. 9 shows a subsequent stage after the patterning of fuse layer 114A.
  • a precursor fuse element 114B is formed within a select recess, shown as the recess 132B.
  • the precursor fuse element 114B represents the fuse layer 114A after patterning to remove portions of the fuse layer 114A that are not disposed over recess 114B. In other recesses where an integrated fuse is not to be formed, the fuse layer 114A may be removed.
  • the mask opening to form the precursor fuse element 114B may be designed to generate a width WFP of the precursor fuse element 114B that is greater than WF, ensuring that with proper alignment the precursor fuse element 114B extends from one sidewall to the opposite sidewall of the recess 132B.
  • FIG. 10 shows a subsequent stage after the formation of plugs 112 within the recesses 132.
  • the plugs 112 may be formed by depositing a plug layer in a blanket deposition over the fuse layer, precursor fuse layer 114B, and the insulator layer 106.
  • the plug layer may be, for example, an electrical insulator. After the depositing of the plug layer, the plug layer may be polished to remove plug material that is not disposed within the recesses 132, forming a planar surface. As shown, an integrated fuse 114 has now been formed in the recess 132B, while plugs 112 also are formed in other of the recesses 132.
  • the plugs 112 may subsequently be employed to define a multiplicity of trench contacts, such as a pair of trench contacts, as well as an integrated fuse that is self-aligned to the pair of trench contacts.
  • FIG. 11 shows a subsequent stage after etching of the insulator layer 106 to form first trench 140 and second trench 142. While the first trench 140 and second trench 142 may be formed using an additional mask operation to deposit and define a mask pattern corresponding to the trench openings, in one embodiment, the plugs 112 are used as mask features. A directional etch is then performed, where the directional etch may selectively remove the insulator layer 106 with respect to the plugs 112. As shown, a portion of the insulator layer 106 separating first trench 140 from second trench 142 remains directly below the integrated fuse 114. In this manner, opposite ends of the integrated fuse 114 define part of the sidewall 144 of the first trench 140 and sidewall 146 of second trench 142.
  • the contact material may be any appropriate material such as tungsten (W) or titanium nitride (TiN). The embodiments are not limited in this context.
  • the contact material layer 108 may be deposited in a blanket fashion, filling the first trench 140 and the second trench 142, as well as covering the upper surfaces of the plugs 112.
  • a planarization operation such as chemical mechanical polishing (CMP) may be performed to generate the semiconductor structure 140, shown in FIG. 13.
  • CMP chemical mechanical polishing
  • the first contact structure 108A, the second contact structure 108B, and the integrated fuse 114 have been formed.
  • the first contact structure 108 A, the second contact structure 108B, and the integrated fuse 114 define a common surface, shown as surface 148.
  • additional wiring levels may be added to the semiconductor structure 140, such as layer 118, discussed above.
  • a hallmark of the semiconductor structure 140 is that the integrated fuse 114 inherently abuts against the first contact structure 108 A and the second contact structure 108B, thus ensuring formation of a local fusible link between the first contact structure 108 A and the second contact structure 108B. Said differently, by virtue of filling the first trench 140 and the second trench 142, the contact material layer 108 contacts opposite ends of the integrated fuse 114 along sidewall 144 and sidewall 146.
  • FIG. 14 illustrates an exemplary flow diagram of a method 1400 in accordance with embodiments of the disclosure.
  • a fuse layer is deposited on an insulator layer, where the insulator layer covers first and second semiconductor fins.
  • the first and second semiconductor fins may form portions of respective first and second devices on a semiconductor substrate.
  • the insulator layer may be made from any suitable dielectric material.
  • the fuse layer may be a metal, metal alloy, metal compound, or other metallic material suitable for use as a fuse element.
  • patterning of the fuse layer is conducted, to form a fuse element over a portion of the insulator layer. Notably, in some portions of the surface of the insulator layer, the fuse layer may be removed.
  • a first contact structure is formed to contact the first semiconductor fin.
  • the first contact structure is formed adjacent a first end of the fuse element.
  • the first contact structure may be formed within in a first trench that contains the first semiconductor fin, where a sidewall of the first trench coincides with the first end of the fuse element.
  • the first contact structure may be formed by filling the first trench with a suitable contact material, such as tungsten or titanium nitride. The filling of the first trench be accomplished using a blanket deposition process in some embodiments.
  • a second contact structure is formed to contact the second semiconductor fin. At the same time, the second contact structure is formed adjacent a second end of the fuse element.
  • the second contact structure may be formed within in a second trench that contains the second semiconductor fin, where a sidewall of the second trench coincides with the second end of the fuse element.
  • the second contact structure may be formed by filling the second trench with a suitable contact material during the same operation used to fill the first trench.
  • a semiconductor structure may be formed, providing an integrated fuse in a local interconnect level between two different semiconductor device contacts.
  • FIG. 15 illustrates another exemplary flow diagram of a method 1500 in accordance with embodiments of the disclosure.
  • an insulator layer is etched to form a multiplicity of recesses in the surface of the insulator layer.
  • the insulator layer may be made from any suitable dielectric material and may be disposed over a semiconductor substrate.
  • the insulator layer may cover a multiplicity of semiconductor fins, including semiconductor fins forming semiconductor devices.
  • the etching may be performed using any suitable mask features to mask portions of an upper surface of the insulator not to be etched.
  • the etching may generate recesses that extend to a depth within the insulator layer according to the height H of an integrated fuse to be formed.
  • an integrated fuse is formed in at least one recess of the multiplicity of recesses, where the integrated fuse includes a plug element.
  • the integrated fuse may be formed by depositing a blanket layer over the surface of the insulator layer, where the blanket layer is made of fuse material to form a fuse.
  • the blanket layer of fuse material may be patterned to form a fuse element by etching fuse material from the surface of the insulator layer, except in a designed recess.
  • plugs are formed in a plurality of additional recesses of the multiplicity of recesses in the insulator layer.
  • a pair of plugs may be formed in a respective pair of recesses that are disposed on opposite sides of the designed recess that contains the fuse element.
  • a plug layer may be deposited over the insulator layer and the fuse element in a blanket deposition.
  • the plug material for the plug layer may be a dielectric, for example.
  • the deposition of the plug layer may be followed by a planarization operation to expose the surface of the insulator layer, except in the multiplicity of recesses where plug material remains.
  • an integrated fuse may be formed in a designated recess, including a fuse element and a plug disposed over the fuse element.
  • a first insulating plug may be formed in a first recess adjacent a first side of the fuse element, while a second insulating plug is formed in a second recess adjacent a second side of the fuse element, opposite the first side.
  • the insulator layer may be selectively etched using the plugs as etch masks elements, including using the integrated fuse.
  • the selective etching may form a pair of trenches adjacent the integrated fuse.
  • a known etch process such as reactive ion etching, sputtering, or other process may be employed, where the etch process etches the material of the insulator layer more rapidly than etching of the plug material. Accordingly, a first trench may be formed in a first region of the insulator layer between the first plug and the integrated fuse, while a second trench is formed in a second region of the insulator layer between the second plug and integrated fuse.
  • the pair of trenches are filled with trench contact metal to from a local interconnect structure having an integrated fuse.
  • the pair of trenches may be filled using a blanket deposition of a suitable metal, followed by CMP processing where metal is removed from surfaces of the plugs. In this manner, a pair of trench contacts may be formed that are electrically coupled to one another via the integrated fuse, while being electrically isolated from other structures by the first plug and second plug.
  • FIG. 16 illustrates a further exemplary flow diagram of a method 1600 in accordance with other embodiments of the disclosure.
  • an insulator layer is provided over a first semiconductor fin and over a second semiconductor fin.
  • the insulator layer may be provided as a blanket layer covering the first semiconductor fin and the second semiconductor fin, as well as portions of an underlying substrate.
  • a multiplicity of recesses are formed in the surface of the insulator layer, including at least three recesses.
  • a central recess may be designated as fuse recess while a first recess is formed on a first side of the central recess and a second recess is formed on a second side of the central recess, opposite to the first side.
  • an integrated fuse is formed in the first recess.
  • the integrated fuse may include a fuse element and a fuse plug.
  • a first plug is formed in the first recess and a second plug is formed in the second recess.
  • the first plug and the second plug may be formed of a same material as used to form the fuse plug.
  • a first trench contact is formed in a first region of the insulator layer, between the first recess and the fuse recess.
  • the first trench contact may be formed by selective etching of the insulator layer in portions not covered by the first plug, second plug, and integrated fuse, followed by deposition of a trench contact metal.
  • a second trench contact is formed in a second region of the insulator layer, between the second recess and the fuse recess. The second trench contact may be formed at the same time as the first trench contact according to the same operations.
  • FIG. 17 schematically illustrates an example system (e.g., computing device 1700) that may include an integrated fuse as described herein, in accordance with some embodiments.
  • the computing device 1700 may house a board such as motherboard 1702.
  • the motherboard 1702 may include a number of components, including but not limited to a processor 1704 and at least one communication chip 1706.
  • the processor 1704 may be physically and electrically coupled to the motherboard 1702.
  • the at least one communication chip 1706 may also be physically and electrically coupled to the motherboard 1702.
  • the communication chip 1706 may be part of the processor 1704.
  • computing device 1700 may include other components that may or may not be physically and electrically coupled to the motherboard 1702.
  • volatile memory e.g., DRAM
  • non-volatile memory e.g., ROM
  • flash memory e.g., a graphics processor, a digital signal processor, a crypto processor, a chipset, an antenna, a display, a touchscreen display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, a Geiger counter, an accelerometer, a gyroscope, a speaker, a camera, and a mass storage device (such as hard disk drive, compact disk (CD), digital versatile disk (DVD), and so forth).
  • volatile memory e.g., DRAM
  • non-volatile memory e.g., ROM
  • flash memory e.g., a graphics processor, a digital signal processor, a crypto processor, a chipset, an antenna, a display, a touchscreen display, a touchscreen controller, a battery, an audio codec,
  • the communication chip 1706 may enable wireless communications for the transfer of data to and from the computing device 1700.
  • wireless and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not.
  • the communication chip 1706 may implement any of a number of wireless standards or protocols, including but not limited to Institute for Electrical and Electronic Engineers (IEEE) standards including Wi-Fi (IEEE 802.11 family), IEEE 802.16 standards (e.g., IEEE 802.16-2005 Amendment), Long-Term Evolution (LTE) project along with any amendments, updates, and/or revisions (e.g., advanced LTE project, ultra mobile broadband (UMB) project (also referred to as "3GPP2”), etc.).
  • IEEE 802.16 compatible BWA networks are generally referred to as WiMAX networks, an acronym that stands for Worldwide
  • the communication chip 1706 may operate in accordance with a Global System for Mobile Communication (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE network.
  • GSM Global System for Mobile Communication
  • GPRS General Packet Radio Service
  • UMTS Universal Mobile Telecommunications System
  • HSPA High Speed Packet Access
  • E-HSPA Evolved HSPA
  • LTE LTE network.
  • the communication chip 1706 may operate in accordance with Enhanced Data for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN).
  • EDGE Enhanced Data for GSM Evolution
  • GERAN GSM EDGE Radio Access Network
  • UTRAN Universal Terrestrial Radio Access Network
  • E-UTRAN Evolved UTRAN
  • the communication chip 1706 may operate in accordance with Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution-Data Optimized (EV-DO), derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond.
  • CDMA Code Division Multiple Access
  • TDMA Time Division Multiple Access
  • DECT Digital Enhanced Cordless Telecommunications
  • EV-DO Evolution-Data Optimized
  • derivatives thereof as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond.
  • the communication chip 1706 may operate in accordance with other wireless protocols in other embodiments.
  • the computing device 1700 may include a plurality of communication chips 1706.
  • a first communication chip 1706 may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth and a second communication chip 1706 may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.
  • the processor 1704 of the computing device 1700 may include a die (e.g., substrate 102 of FIGS. 1-2) having a fuse structure as described herein.
  • the substrate 102 of FIGS. 1-2 may be mounted in a package assembly that is mounted on the motherboard 1702.
  • the term "processor” may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.
  • Processor 1004 may be a central processing unit comprising one or more processor cores and may include any number of processors having any number of processor cores.
  • the processor 1004 may include any type of processing unit, such as, for example, CPU, multi-processing unit, a reduced instruction set computer (RISC), a processor that have a pipeline, a complex instruction set computer (CISC), digital signal processor (DSP), and so forth.
  • processor 1704 may be multiple separate processors located on separate integrated circuit chips.
  • processor 1004 may be a processor having integrated graphics, while in other embodiments processor 1004 may be a graphics core or cores.
  • the communication chip 1706 may also include a die (e.g., substrate 102 of FIGS. 1-2) having a fuse structure as described herein.
  • another component e.g., memory device or other integrated circuit device housed within the computing device 1700 may contain a die (e.g., substrate 102 of FIGS. 1-2) having a fuse structure as described herein.
  • the computing device 1700 may be a mobile computing device, laptop, a netbook, a notebook, an ultrabook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder.
  • the computing device 1700 may be any other electronic device that processes data.
  • Example 1 pertains to a semiconductor structure that may include a first contact structure on a first semiconductor fin and a second contact structure on a second semiconductor fin.
  • the first semiconductor fin may be adjacent to the second semiconductor fin.
  • the semiconductor structure may further include an integrated fuse between the first contact structure and the second contact structure, where the integrated fuse is electrically connected to the first contact structure and to the second contact structure.
  • the semiconductor structure of example 1 may include an insulator material that is subjacent to the integrated fuse and between the first contact structure and the second contact structure.
  • the integrated fuse of the semiconductor structure of any of examples 1-2 may include a fuse element arranged in a fuse layer, where the fuse element is in contact with the insulator layer.
  • the integrated fuse may include a fuse plug, where the fuse plug is at least partially over the fuse element.
  • the integrated fuse may be between the first contract structure and the second contact structure.
  • the fuse layer of the semiconductor structure of any of examples 1-3 may have a layer thickness, wherein a program current of the integrated fuse is proportional to the layer thickness.
  • the first contact structure, the second contact structure, and the integrated fuse of the semiconductor structure of any of examples 1-4 may define a common surface.
  • the first contact structure of the semiconductor structure of any of examples 1-5 comprises a first trench contact and the second contact structure comprises a second trench contact.
  • the first trench contact may form a first contact to a first source/drain region associated with the first fin structure
  • the second trench contact may form a second contact to a second source/drain region associated with the second fin structure.
  • first contact structure and the second contact structure of the semiconductor structure of any of examples 1-7 are separated by a first distance along a first direction, where the integrated fuse has a fuse width along the first direction, equal to the first distance.
  • the fuse element of the semiconductor structure of any of examples 1-7 may comprise a metallic fuse element arranged in a fuse layer.
  • the fuse layer may have a layer thickness extending along a second direction that extends perpendicularly to the first direction.
  • the layer thickness may be between 1 nm to 50 nm.
  • At least one of the first semiconductor fin or second semiconductor fin of the semiconductor structure of any of examples 1-8 may form part of a tri-gate transistor.
  • Example 10 pertains to a method, where the method includes depositing a fuse layer on an insulator layer on a substrate.
  • the insulator layer may cover a first semiconductor fin and a second semiconductor fin.
  • the method may include patterning the fuse layer to form a fuse element, where the fuse element is over a portion of the insulator layer.
  • the method may also include forming a first contact structure adjacent a first end of the fuse element and a second contact structure adjacent a second end of the fuse element.
  • the first contact structure may be over the first semiconductor fin and the second contact structure over the second semiconductor fin.
  • the fuse element may be electrically connected to the first contact structure and to the second contact structure.
  • the method of example 10 may include patterning the insulator layer to form a recess in a surface of the insulator layer before the depositing the fuse layer, where the recess is between the first contact structure and the second contact structure. After the patterning the fuse layer, the fuse element may be in the recess.
  • the method of any of examples 10-11 may include depositing a plug layer over the fuse element and over the insulator layer, and polishing the plug layer to form an integrated fuse, where the first contact structure, the second contact structure, and the integrated fuse define a common surface.
  • the patterning of the insulator layer in any of examples 10-12 may include forming a multiplicity of recesses in the surface of the insulator layer, where after the polishing the plug layer, a multiplicity of plugs are formed at a surface of the insulator layer.
  • the method may also include, the method further selectively etching the insulator layer using the multiplicity of plugs as a mask, where a first trench and a second trench are formed within the insulator layer.
  • the method may also include depositing a trench contact metal on the substrate, wherein the first trench and the second trench are filled with the trench contact metal and polishing the contact material layer. Accordingly, a local interconnect structure may be formed, comprising the first contact structure, the second contract structure, and the integrated fuse.
  • the method of any of examples 10-13 may include depositing an interlevel dielectric layer over the first contact structure, over the second contact structure, and over the integrated fuse.
  • the method may include patterning the interlevel dielectric layer to form a first via, and a second via, the first via communicating with the first contact structure, and the second via communicating with the second contact structure.
  • the method may also include filling the first via and the second via with a conductive material.
  • At least one of the first semiconductor fin and the second semiconductor fin may form a tri-gate transistor.
  • Example 16 pertains to an apparatus, including a semiconductor substrate, a first semiconductor fin and a second semiconductor fin, where the first semiconductor fin and the second semiconductor fin are on the semiconductor substrate.
  • the apparatus may include a first trench contact around the first semiconductor fin, and a second trench contact around the second semiconductor fin.
  • the apparatus may also include an integrated fuse between the first trench contact and the second trench contact, where the integrated fuse forms a fusible link between the first trench contact and the second trench contact.
  • the apparatus of example 16 may also include an insulator material, where the insulator material being over the semiconductor substrate and subjacent the integrated fuse.
  • the integrated fuse of any of examples 16-17 may include a fuse layer, where the fuse layer is in contact with the insulator layer, and may include a fuse plug, where the fuse plug is at least partially over the fuse layer.
  • the integrated fuse may be between the first trench contract and the second trench contact.
  • first trench contact, the second trench contact, and the integrated fuse of the apparatus of any of examples 16-18 may define a common surface.
  • the first trench contact of the apparatus of any of examples 16-19 may form a first contact to a first source/drain region associated with the first fin structure and the second trench contact may form a second contact to a second source/drain region associated with the second fin structure.
  • the first trench contact and the second trench contact of the apparatus of any of examples 16-20 are separated by a first distance along a first direction, where the integrated fuse has a fuse width along the first direction, equal to the first distance.
  • the first semiconductor fin and the second semiconductor fin of the apparatus of any of examples 16-21 may comprise a monocrystalline semiconductor, integrally formed from the substrate. At least one of the first semiconductor fin or the second
  • semiconductor fin may form a tri-gate transistor.
  • Example 23 pertains to a system, including a circuit board; and a processor coupled to the circuit board, the processor including a semiconductor die.
  • the semiconductor die may include a semiconductor substrate and a first semiconductor fin and second semiconductor fin on the semiconductor substrate.
  • the semiconductor die may also include a first trench contact on the first semiconductor fin, a second trench contact on a second semiconductor fin and an integrated fuse between the first trench contact and the second trench contact.
  • the integrated fuse may form a fusible link between the first trench contact and the second trench contact.
  • the first trench contact and the second trench contact of the system of example 23 may be separated by a first distance along a first direction, where the integrated fuse has a first width along the first direction, equal to the first distance.
  • the first trench contact, the second trench contact, and the integrated fuse of the system of examples 23-24 may define a common surface.
  • Example 26 pertains to a method for forming a local interconnect structure.
  • the method may include forming a multiplicity of recesses on a surface of an insulator layer, where the insulator layer is over a substrate, a first semiconductor fin, and a second semiconductor fin.
  • the method may include forming an integrated fuse within a fuse recess of the multiplicity of recesses.
  • the method may further include forming a first plug in a first recess of the multiplicity of recesses and a second plug in a second recess of the multiplicity of recesses.
  • the method may also include forming a first trench contact in a first region of the insulator layer between the first recess and the fuse recess, and forming a second trench contact in a second region of the insulator layer between the second recess and the fuse recess.
  • the first region in the method of example 26 may include the first semiconductor fin and the second region may include the second semiconductor fin.
  • the method of any examples 26-27 may include depositing a fuse layer on the insulator layer, and patterning the fuse layer to form a fuse element in the fuse recess.
  • the method may also include depositing a plug layer comprising plug material over a top surface of the insulator layer and the fuse element, and polishing the plug layer to remove the plug material from regions of the top surface outside of the fuse recess.
  • the depositing the plug layer and the polishing the plug layer may form the first plug and the second plug.
  • the forming the first trench contact and the second trench contact in the method of any of examples 26-29 may include etching the insulator layer using the integrated fuse, the first plug and the second plug as a mask, where a first trench and a second trench are formed.
  • the forming the first trench contact and the second contact of the method of any of examples 26-30 may include depositing a trench contact metal layer in the first trench and the second trench.
  • the forming the first trench contact and the second contact of the method of any of examples 26-30 may include polishing the trench contact metal layer, so the first trench contact, the second trench contact, and the integrated fuse define a common surface.
  • At least one of the first semiconductor fin and the second semiconductor fin may form a tri-gate transistor.
  • the first trench contact and the second trench contact may be self-aligned to the integrated fuse, where a first end of the integrated fuse contacts the first trench, and where a second end of the integrated fuse contacts the second trench contact.
  • the method of any of examples 26-24 may include depositing an interlevel dielectric layer over the first trench contact, over the second trench contact, and over the integrated fuse.
  • the method may also include patterning the interlevel dielectric layer to form a first via communicating with the first trench contact, and a second via communicating with the second trench contact.
  • the method may further include filling the first via and the second via with a conductive material.
  • an element is defined as a specific structure performing one or more operations. It may be appreciated, however, that any element defined as a specific structure performing a specific function may be expressed as a means or step for performing the specified function without the recital of structure, material, or acts in support thereof, and such means or step is meant to cover the corresponding structure, material, or acts described in the detailed description and equivalents thereof. The embodiments are not limited in this context.
  • Some embodiments may be described using the expression “one embodiment” or “an embodiment” along with their derivatives. These terms mean that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. The appearances of the phrase “in one embodiment” in various places in the specification are not necessarily all referring to the same embodiment. Further, some embodiments may be described using the expression “coupled” and “connected” along with their derivatives. These terms are not necessarily intended as synonyms for each other. For example, some embodiments may be described using the terms “connected” and/or “coupled” to indicate that two or more elements are in direct physical or electrical contact with each other. The term “coupled,” however, may also mean that two or more elements are not in direct contact with each other, but yet still co-operate or interact with each other.

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

La présente invention concerne une structure semi-conductrice qui peut comprendre une première structure de contact sur une première ailette semi-conductrice et une deuxième structure de contact sur une deuxième ailette semi-conductrice, la première ailette semi-conductrice étant adjacente à la deuxième ailette semi-conductrice. La structure semi-conductrice peut comprendre en outre un fusible intégré entre la première structure de contact et la deuxième structure de contact, le fusible intégré étant électriquement connecté à la première structure de contact et à la deuxième structure de contact.
PCT/US2017/025124 2017-03-30 2017-03-30 Fusible intégré dans une interconnexion locale et techniques de formation WO2018182636A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
PCT/US2017/025124 WO2018182636A1 (fr) 2017-03-30 2017-03-30 Fusible intégré dans une interconnexion locale et techniques de formation

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Application Number Priority Date Filing Date Title
PCT/US2017/025124 WO2018182636A1 (fr) 2017-03-30 2017-03-30 Fusible intégré dans une interconnexion locale et techniques de formation

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120187528A1 (en) * 2011-01-21 2012-07-26 International Business Machines Corporation Finfet fuse with enhanced current crowding
US20130105895A1 (en) * 2011-10-27 2013-05-02 Taiwan Semiconductor Manufacturing Company, Ltd. Fin-like field effect transistor (finfet) based, metal-semiconductor alloy fuse device and method of manufacturing same
US20150014785A1 (en) * 2011-02-14 2015-01-15 Shine C. Chung Circuit and System of Using Finfet for building Programmable Resistive Devices
US20150097266A1 (en) * 2013-10-07 2015-04-09 International Business Machines Corporation High performance e-fuse fabricated with sub-lithographic dimension
US20150255469A1 (en) * 2014-03-04 2015-09-10 Hyun-Min CHOI Fuse structure and semiconductor device including the same

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120187528A1 (en) * 2011-01-21 2012-07-26 International Business Machines Corporation Finfet fuse with enhanced current crowding
US20150014785A1 (en) * 2011-02-14 2015-01-15 Shine C. Chung Circuit and System of Using Finfet for building Programmable Resistive Devices
US20130105895A1 (en) * 2011-10-27 2013-05-02 Taiwan Semiconductor Manufacturing Company, Ltd. Fin-like field effect transistor (finfet) based, metal-semiconductor alloy fuse device and method of manufacturing same
US20150097266A1 (en) * 2013-10-07 2015-04-09 International Business Machines Corporation High performance e-fuse fabricated with sub-lithographic dimension
US20150255469A1 (en) * 2014-03-04 2015-09-10 Hyun-Min CHOI Fuse structure and semiconductor device including the same

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