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WO2018182740A1 - Dispositif à effet hall de spin avec couche d'absorption de spin - Google Patents

Dispositif à effet hall de spin avec couche d'absorption de spin Download PDF

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Publication number
WO2018182740A1
WO2018182740A1 PCT/US2017/025604 US2017025604W WO2018182740A1 WO 2018182740 A1 WO2018182740 A1 WO 2018182740A1 US 2017025604 W US2017025604 W US 2017025604W WO 2018182740 A1 WO2018182740 A1 WO 2018182740A1
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WIPO (PCT)
Prior art keywords
layer
spin
thick
hall effect
memory cell
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Application number
PCT/US2017/025604
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English (en)
Inventor
Sasikanth Manipatruni
Dmitri E. Nikonov
Ian A. Young
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Intel Corporation
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Priority to PCT/US2017/025604 priority Critical patent/WO2018182740A1/fr
Publication of WO2018182740A1 publication Critical patent/WO2018182740A1/fr

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/161—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/165—Auxiliary circuits
    • G11C11/1675—Writing or programming circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/18—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using Hall-effect devices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/18—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using galvano-magnetic devices, e.g. Hall-effect devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B61/00—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N50/00—Galvanomagnetic devices
    • H10N50/10—Magnetoresistive devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N50/00—Galvanomagnetic devices
    • H10N50/80—Constructional details
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N59/00—Integrated devices, or assemblies of multiple devices, comprising at least one galvanomagnetic or Hall-effect element covered by groups H10N50/00 - H10N52/00

Definitions

  • embedded non-volatile memory Integration of non-volatile memory cells on a same substrate as logic transistors is often referred to as “embedded non-volatile memory” or “eNVM.”
  • Embedding non-volatile memory on a same substrate as logic transistors improves computational speed and efficiency compared to memory devices and semiconductor devices that are disposed on separate substrates and that therefore communicate through an inter-substrate bus.
  • common types of integrated memory devices include eDRAM and SRAM, various types of resistive and magneto-resistive random access memory (RRAM and MRAM, respectively) devices are of increasing interest, particularly for embedded non-volatile memory devices.
  • RRAM and MRAM resistive and magneto-resistive random access memory
  • MRAM devices store a bit of data by magnetizing or de-magnetizing a "free" layer of a magneto-resistive device. The electrical resistance of the free layer relative to an associated magnetized “fixed” or “reference” layer is then used to determine a binary value of "1" or "0" in the MRAM device. Because resistive data storage does not require periodic electrical refreshment, as do memory storage devices that use an electrical charge such as eDRAM and SRAM, the data stored in the MRAM device persists even after power is removed from the circuit. Examples of MRAM memory devices include, but are not limited to, spin Hall effect magnetic random access memory (SHE-MRAM), and spin transfer torque MRAM (STT- MRAM).
  • SHE-MRAM spin Hall effect magnetic random access memory
  • STT- MRAM spin transfer torque MRAM
  • FIG. 1 is a schematic circuit diagram of a spin torque transfer (STT) magnetic tunnel junction (MTJ) controlled by one transistor (IT).
  • STT spin torque transfer
  • MTJ magnetic tunnel junction
  • FIG. 2 is a perspective view schematic diagram of a magnetic tunnel junction that includes a spin Hall effect (SHE) material layer, in accordance with an embodiment of the present disclosure.
  • SHE spin Hall effect
  • FIG. 3 is a schematic illustration of reduction in spin polarization at an interface between a SHE material layer and a spin absorption layer, in accordance with an embodiment of the present disclosure.
  • FIG. 4 is a perspective view schematic diagram of a magnetic tunnel junction that includes a spin Hall effect material layer in contact with a continuous layer of a spin absorption material, in accordance with an embodiment of the present disclosure.
  • FIG. 5 is a perspective view schematic diagram of a magnetic tunnel junction that includes a spin Hall effect material layer in contact with a discontinuous layer of a spin absorption material, in accordance with an embodiment of the present disclosure.
  • FIG. 6 is a perspective view schematic diagram of a magnetic tunnel junction that includes a spin Hall effect material layer in contact with a spin absorption material fabricated from a ferromagnetic material, in accordance with an embodiment of the present disclosure.
  • FIG. 7 is a perspective view schematic diagram of a magnetic tunnel junction that includes a spin Hall effect material layer in contact with a spin absorption material, in which a free layer of the magnetic tunnel junction is fabricated from alternating layers of cobalt and palladium, in accordance with an embodiment of the present disclosure.
  • FIG. 8 is a flow chart illustrating an example method for fabricating a SHE magnetic tunnel junction that includes a spin absorption layer, in accordance with an embodiment of the present disclosure.
  • FIG. 9 is a cross-sectional view through a logic circuit implementing a spin orbit logic circuit devices cascaded in series, in accordance with an embodiment of the present disclosure.
  • FIG. 10 is a graph comparing example data of switching efficiency between two MTJs, one of which is switched via a SHE material layer and another of which is switched via a SHE material layer in contact with a spin absorption layer, in accordance with an embodiment of the present disclosure.
  • FIG. 11 is a graph illustrating a comparison of write times for a spin Hall effect switched MRAM and a spin torque switched MRAM, configured in accordance with an embodiment of the present disclosure.
  • FIG. 12 is a depiction of a computing system configured in accordance with an embodiment of the present disclosure.
  • MRAM magnetic random access memory
  • MTJ magnetic tunnel junction
  • SHE spin Hall effect
  • SHE material spin Hall effect material
  • the switching efficiency is improved because the spin absorption material prevents diffusion of oppositely spin polarized electrons within the SHE material, thus decreasing current and voltage needed to switch a device with the SHE material, as compared to a traditional MTJ. This has the effect of reducing a current internal to the SHE material that otherwise suppresses the switching current applied to the device.
  • an MTJ can store a bit of data using a relative resistance between a magnetized free layer and a magnetized reference layer.
  • the magnetization of the free layer which can be "switched” to have a low resistance or a high resistance relative to the reference layer, is often configured to use one of two magnetic phenomena: spin torque transfer (“STT”) or spin orbit coupling ("SOC”).
  • STT spin torque transfer
  • SOC spin orbit coupling
  • SHE spin Hall effect
  • the STT effect can be used to switch devices (e.g., between low resistance and high resistance states) by providing an electrical current to a first magnetic domain in a device. The electrons in the provided electrical current become spin polarized according to the magnetization in the first magnetic domain.
  • the spin polarized electrons When flowing into a different magnetic domain, the spin polarized electrons transfer momentum corresponding to the spin polarization of the first domain to the electrons within the different magnetic domain. As more momentum is transferred, the magnetic polarization of the different domain eventually switches to match that of the incoming polarized electrons (and the first domain).
  • the SHE can be used to switch magnetization of a magnetic domain (e.g., a free layer in an MTJ) through spin orbit coupling. Rather than transferring moment between electrons as in the STT effect, the SHE polarizes electron spin in a current that is applied to a material that exhibits the spin Hall effect.
  • the polarized electrons of one spin migrate to one lateral surface of the SHE material and electrons of the opposite spin migrate to an opposing lateral surface of the SHE material.
  • This polarization, with spin orbit coupling, can be used to switch a device (e.g., change a
  • FIG. 1 is a schematic circuit diagram of an STT magnetic tunnel junction controlled by one transistor.
  • the relative resistance can be read from or written to an MTJ using the one transistor.
  • the electrical paths used for both writing and reading are the same.
  • An MTJ memory device that is switched using STT has some drawbacks, however.
  • the current used to write data to the MTJ via the one transistor is limited by the electrical resistance of a tunneling layer disposed between the reference layer and free layer of the MTJ.
  • the voltage and current needed to write data to an STT MTJ memory cell are relatively high.
  • Write currents can be has high as ⁇ or higher.
  • Write voltages can be as high as 0.7 V or higher.
  • Write (or magnetization "switching") times are often over 20 nanoseconds (ns) and can have high error rates.
  • presence of a tunneling path in STT devices can cause long term device reliability degradation.
  • SHE MTJ memory devices e.g., devices having a MTJ and a SHE material layer
  • SHE MTJ memory devices are of interest.
  • An example perspective view of a SHE MTJ device 200 is illustrated in FIG. 2.
  • the SHE MTJ device 200 includes electrodes 21 1 and 212, a SHE material layer 210, a magnetic tunnel junction (MTJ) 226, a synthetic anti-ferromagnet 250, and an anti- ferromagnet 234.
  • MTJ magnetic tunnel junction
  • the electrodes 211, 212 are used to apply a voltage to the SHE material layer 210, thus providing spin polarized electrons (in the direction of arrow IWRITE) that can be used for writing a bit to the MTJ 226.
  • the electrodes, in electrical contact with the SHE material layer 210 can be fabricated from any good electrical conductor, including copper, aluminum, gold, alloys thereof, among others.
  • the electrodes 211, 212 can be formed by any convenient technique, such as sputtering, chemical vapor deposition (CVD), and atomic layer deposition (ALD), among others.
  • a voltage is applied between the electrode 211 and a top electrode (not shown in FIG.
  • the current (IREAD) is sent to a sense amplifier to determine the voltage.
  • the sense amplifier (not shown) is a peripheral circuit that uses the current and the applied voltage value to determine the resistance of the MTJ 226.
  • a high resistance can be associated with a bit value of " 1" and a low resistance is associated with a bit value of "0.”
  • the SHE material layer 210 causes electrons of opposite spins to polarize toward opposing lateral surface of the layer 210.
  • the polarized electrons adjacent to the free layer 220 of the magnetic tunnel junction 226 (described below) can then switch magnetic polarization of the free layer 220 via spin orbit coupling.
  • Examples of materials exhibiting the SHE include platinum, beta-phase tungsten (“ ⁇ -W”), and beta-phase tantalum (“ ⁇ -Ta”), or alloys of various combinations of copper, platinum, iridium, and/or bismuth.
  • the magnetic tunnel junction 226 of the device 200 includes a free layer 220, a tunneling layer 222, and a reference layer 224. As described above, the free layer 220 can switch a direction of its magnetization with respect to the reference layer 224. This affects the resistance between these layers within the MTJ 226, which can be interpreted as a bit of data (e.g., either a "1" or a "0").
  • the free layer 220 is fabricated from a material having a lower magnetic coercivity than the reference layer 224 described below, and thus can more easily switch between electron spin states than the reference layer 224.
  • the free layer 220 can be fabricated from ferromagnetic materials including, but not limited to, cobalt iron (CoFe) or cobalt iron boron (CoFeB).
  • the ferromagnetic material of the free layer 220 can be deposited using any of a variety of techniques including, but not limited to, epitaxial deposition, atomic layer deposition.
  • the tunneling layer 222 (sometimes referred to as a "barrier layer”) is generally a dielectric material that permits electron tunneling between the reference layer 224 and the free layer 220.
  • the barrier layer 222 can facilitate selective tunneling so that electrons having a preferred spin polarity can tunnel from the reference layer 224 through the barrier layer 222 into the free layer 220, and/or vice versa. This selective tunneling can be used to control the magnetization polarity of electrons in the free layer 220, and thus control the resistance of the device 200.
  • the barrier layer 222 is fabricated from magnesium oxide (MgO) or aluminum oxide (A1 2 0 3 ) although other dielectric materials may also be used.
  • the barrier layer 222 can be deposited using any of a variety of techniques including, but not limited to chemical vapor deposition, organometallic chemical vapor deposition, atomic layer deposition, sputtering, among other deposition techniques.
  • the reference layer 224 can, in some examples, be fabricated from a material or a stack of materials that maintains a magnetic polarity (i.e., a spin of electrons) and is a "hard" magnetic material having a magnetic coercivity higher than that of the free layer 220.
  • Types of materials used to fabricate the reference layer 224 include permanent magnetic materials, such as ferromagnetic materials.
  • the reference layer 224 is fabricated from a single layer of cobalt iron boron (CoFeB).
  • the reference layer 224 is composed of a stack of materials that includes a cobalt iron boron (CoFeB) layer, a ruthenium (Ru) layer, and another cobalt iron boron (CoFeB) layer.
  • the reference layer 224 can be deposited using any of a variety of techniques including, but not limited to, chemical vapor deposition, atomic layer deposition, sputtering, among other deposition techniques.
  • the synthetic anti-ferromagnet (“SAF") 250 which is disposed between the MTJ 226 and the anti-ferromagnet 234 deposited on the SAF 250, in this example includes a layer of cobalt iron boron 224, a layer of ruthenium 230 and a layer of cobalt iron alloy 232.
  • the anti-ferromagnet 234 can be a layer of iron manganese.
  • the SAF layer allows for cancelling dipole fields around the free layer 220 of the MTJ 226 to ensure the magnetic layer 232 has an opposite magnetization to the magnetic layer 224.
  • additional layers may be included on the anti-ferromagnet 234, including a second layer of ruthenium on the anti-ferromagnet 234, a layer of tantalum on the second layer of ruthenium, and a third layer of ruthenium on the layer of tantalum.
  • embodiments that increase the efficiency of spin orbit coupling memory devices and spin orbit coupling logic devices by disposing a spin absorption material layer in contact with a SHE material layer.
  • the spin absorption material layer reduces spin polarization of electrons at the adjacent interface of the SHE material layer. Reducing the spin polarizations of electrons at this interface improves various features of the MTJ device and its operation. These improvements include improving a spin Hall angle (spin current injection) by a factor of at least 2.5, reducing a voltage needed to switch a SHE MTJ memory device and to switch a SHE logic device. Improvements exhibited by some embodiments also include reducing write error ratio that can result in increasing MRAM write speed to 10 ns or lower.
  • devices that include embodiments of the present disclosure can be configured so that write and read current paths are decoupled, which allows read path resistance to be optimized for operation of a read sense amplifier circuit.
  • the effect of one or more of these is to improve read speeds, and reduce read current by a factor of 10 or more to less than 10 ⁇ .
  • the reliability of the tunneling layer is also improved for MRAM devices, thus improving reliability of the MRAM devices as a whole.
  • the tunneling layer can be eliminated.
  • using the spin absorption layer improves the spin injection efficiency, as will be appreciated in light of the present disclosure.
  • a select transistor can be placed in saturation, which overcomes some challenges when configuring MRAM arrays to megabyte or gigabyte scales.
  • FIG. 3 schematically illustrates a reduction in spin polarization at an interface between a SHE material layer and a spin absorption layer, in accordance with an embodiment of the present disclosure.
  • the illustration in FIG. 3 includes a SHE material layer 310 and a spin absorption material layer 314 in contact with the SHE material layer 310 at an interface 318. It will be appreciated that the layers 310, 314 and the corresponding interface 318 are present in various embodiments of the present disclosure, whether memory devices or logic devices.
  • FIG. 3 Various embodiments of the configuration depicted in the FIG. 3 are described below in more detail in the context of example memory devices of FIGS. 4-7, and an example logic device in FIG. 9.
  • a voltage is applied to the SHE material layer 310 which generates current (IWRITE).
  • IWRITE current
  • examples of materials exhibiting the SHE include platinum, beta-phase tungsten, and beta-phase tantalum, or alloys of various combinations of copper, platinum, iridium, and/or bismuth.
  • the electrons in the current are spin polarized to opposing lateral surfaces 312a and 312b in the SHE material layer 310. These opposite spin polarizations are indicated by opposing arrows corresponding to the opposing lateral surfaces 312a and 312b.
  • the spin absorption material layer 314 is placed in contact with the lateral surface 312b of the SHE material layer 310, in this example.
  • the spin absorption material layer 314 reduces the magnitude of the spin polarization of the electrons at the lateral surface 312b. This reduction of spin polarization at the lateral surface 312b is indicated in FIG. 3 with dashed lines on arrows (representing a decreased magnitude of spin polarization) proximate to the interface 318.
  • Materials that can comprise the spin absorption material layer 314 generally have a spin resistivity less than the spin resistivity of the SHE material layer 310. More specifically, examples of materials for the spin absorption material layer 314 include, but are not limited to, ruthenium, chromium, titanium, titanium nitride, zirconium, platinum, and manganese. Example combinations of materials follow in Table 1 and are provided for illustration purposes only.
  • the spin absorption material layer 314 can comprise materials that include a ferromagnet or anti-ferromagnet generally having a resistivity less than the spin resistivity of the SHE material layer 310.
  • examples include cobalt, cobalt iron alloys, iron, nickel, cobalt nickel allows, manganese, and Heusler alloys.
  • the architecture depicted in FIG. 3 in cooperation with electrodes (e.g., electrodes 211, 212) can write a bit (i.e., an electron spin corresponding to a " 1" or a "0") to an MTI (e.g., MTI 226) by applying a charge current via the SHE material layer 310.
  • the spin polarization of the electrons is based on a direction of the applied charge current.
  • Positive currents (indicated by the direction of the arrow corresponding to I wr i te in FIG. 2) produce a spin injection current with a transport direction along +z and spins pointing in the +x direction in the coordinate system shown in FIG. 3.
  • the injected spin current in turn produces spin torque to align the magnet in the +x or -x direction.
  • Device properties that include embodiments of the present disclosure, including various relevant material properties, are summarized below in Table 2. The improvements in efficiency afforded by the SHE material as compared to a traditional 1T-MTJ are apparent, as shown in Table 2. Efficiency greater than 100% is achieved using a SHE material for performing the writing. As the electrons flow horizontally, they are bouncing on the top surface of the SHE material, and thus an efficiency greater than 100% can be achieved.
  • the term SHA refers to the spin Hall angle, which is a measure of conversion efficiency between charge currents and pure spin currents, and is a material- dependent parameter.
  • the effective polarization factor, P is an effective coefficient of transduction from charge current to spin current. As shown, the effective polarization factor P for the Ta-SHE layer is approximately 135. Also the effective polarization factor for a W-SHE layer is approximately 270%, having a significantly improved effective polarization factor as compared to a traditional MTJ, which is less than 100% efficient. In an MTJ, only a portion of an applied current (approximately 90%) is spin polarized.
  • an electron flowing horizontally through the SHE material bounces off the top surface of the SHE layer, and can bounce many times. This can result in efficiency greater than 100%, such as approximately 135% with the Ta-SHE layer for the SHE material, and approximately 270% with the W-SHE layer for the SHE material, as will be appreciated in light of the present disclosure.
  • FIGS. 4, 5, 6 and 7 illustrate various example configurations of MTJs, in accordance with embodiments of the present disclosure. Many of the elements of the MTJs shown in FIGS. 4, 5, 6, and 7 are described above in the context of FIGS. 2 and 3, and need no further explanation.
  • FIG. 4 illustrates an MTJ 400 that includes a spin absorption layer 404 in accordance with an embodiment of the present disclosure.
  • the MTJ 400 includes a "continuous" spin absorption material layer 404 in contact with the SHE material layer 210 that extends fully from electrode 211 to electrode 212.
  • the continuous spin absorption material layer 414 can only extend partially under the electrodes 212, 212.
  • the continuous spin absorption material layer 404 extends in a continuous layer under at least a portion of the electrodes 21 1, 212 and under the entire width of the SHE material layer 210.
  • FIG. 5 illustrates an MTJ 500 similar to the MTJ 400, except that the MTJ 500 includes a "discontinuous" or “partial” spin absorption material layer 504 that is not coextensive with the electrodes 211, 212.
  • the discontinuous spin absorption material layer 504 extends partially under a portion of the SHE material layer 210.
  • the discontinuous spin absorption material layer 504 is coextensive with the SHE material layer 210, but does not extend so far as to overlap with one or both of the electrodes 21 1, 212.
  • the embodiment of the partial spin absorption material layer 504 shown (as well as the others described), has the effect of reducing a current (I W rite) needed to switch the bit of the MTJ 500.
  • FIG. 6 illustrates an MTJ 600 similar to the MTJ 400, except that the MTJ 600 includes a ferromagnetic spin absorption material layer 604 fabricated from a ferromagnetic material.
  • ferromagnetic materials used to fabricate a ferromagnetic spin absorption material layer 604 include cobalt, iron, and cobalt iron alloys.
  • the free layer 620 can include a layer of perpendicular magnetic anisotropy (PMA) material.
  • a PMA material has an orientation of c-axis that is perpendicular to the film plane, and results in a tendency for the material to point out of plane.
  • the PMA free layer 620 can be formed by interface anisotropy, where the CoFeB layer 620 is processed such that the way it interfaces with the MgO layer will lead to PMA, which makes polarization out of the direction of the plane.
  • FIG. 7 illustrates an MTJ 700 similar to the MTJ 600, except that the MTJ 700 includes a free layer 708 comprised of alternating layers of cobalt and palladium.
  • the free layer 708 can comprise a multilayer PMA that includes alternating layers of cobalt and palladium, for example.
  • the alternating layers of cobalt and palladium function as a PMA to point the polarization out of plane, so that it requires less energy to place the free layer into and out of plane.
  • FIG. 8 illustrates an example method 800 for fabricating an interface for improving efficiency of device switching using a spin absorption layer in contact with a SHE material layer. While the method 800 can be applied to any of a variety of integrated circuit device types (e.g., memory, logic), the method 800 is presented specially in the context of MTJ fabrication for convenience of explanation.
  • integrated circuit device types e.g., memory, logic
  • the method 800 includes forming 810 a spin absorption layer and then forming 820 a spin Hall effect layer directly on the spin absorption layer.
  • the spin absorption layer is formed 820 so as to absorb accumulated spin polarization at an interface between the spin Hall effect layer and the spin absorption layer.
  • a magnetic tunnel junction is formed 830 on the spin Hall effect layer.
  • the various layers can be formed by non-epitaxial processes including sputtering, CVD, among others.
  • FIG. 9 illustrates a spin orbit logic circuit 910 that includes a spin Hall effect (SHE) layer and a spin absorption layer to enhance the SH, in accordance with an embodiment of the present disclosure.
  • the spin orbit logic circuit 910 includes a first spin orbit logic device 915 and a second spin orbit logic device 939.
  • the first spin orbit logic device 915 includes a ferromagnetic layer 924, a spacer layer 925, a spin Hall effect (SHE) layer 920, a spin absorption layer 922, an inverse spin Hall effect (ISHE) layer 926, and a via 941.
  • the second spin orbit logic device 939 includes elements analogous to the first spin orbit logic device, including a ferromagnetic layer 934, a spacer layer 935, a SHE layer 936, a spin absorption layer 937, an ISHE layer 932, and a via 940.
  • the first spin orbit logic device 915 and the second spin orbit logic device 939 are connected in series with each other by a channel 930. Although only two spin orbit logic devices are shown, any number may be cascaded in series to achieve switching as described.
  • the first spin orbit logic device 915 includes the SHE layer 920 and associated spin absorption layer 922, in accordance with an embodiment of the present disclosure.
  • the SHE layer 920 and an ISHE layer 926 are both positioned on a spacer material 925 that in turn is disposed on the ferromagnetic layer 924.
  • the ISHE layer 926 is connected to the ground interconnect 945 through the via 941.
  • a supply 942 is coupled to the ferromagnetic layer 934, and a supply 943 is coupled to the ferromagnetic layer 924.
  • a ground interconnect 945 is coupled to the via 940 and to the via 941 to provide ground for the logic circuit 910.
  • the SHE layer 920 writes to the spin orbit logic device 915, and the ISHE layer 926 reads from the spin orbit logic device 915.
  • the ferromagnetic layer 924 is coupled to a supply 942 that supplies voltage to the spin orbit logic device 915.
  • the second spin orbit logic device 939 is configured analogously to the first spin orbit logic device 915 described above.
  • the second spin orbit logic device 939 includes the SHE layer 936 and associated spin absorption layer 937, in accordance with an embodiment of the present disclosure.
  • the SHE layer 936 and an ISHE layer 932 are both positioned on a spacer material 935 that in turn is positioned on the ferromagnetic layer 934.
  • the ISHE layer 932 is connected to ground interconnect 945 through the via 940.
  • the SHE layer 936 is responsible for performing the writing, and the ISHE layer 932 is responsible for performing the reading of the spin orbit logic device 939.
  • the ferromagnetic layer 934 is coupled to a supply 943 that supplies voltage to the spin orbit logic device 939.
  • the ferromagnetic layer 934 and ferromagnetic layer 924 are fabricated from low magnetic coercivity materials so that the magnetic polarization can be switched from one direction to another through the SHE layers 920, 936 respectively. For example, if the spin current polarization within one of SHE layers 920, 936 is in a same direction as a direction of magnetization within an FM layer 924, 934 (respectively), then the direction of magnetization in the corresponding FM layer 924, 934 will not change (i.e., not switch).
  • the magnetization of the corresponding FM layer 924, 934 will change to match that of the SHE layer.
  • current can be applied to the ferromagnetic layer 934 (for example, via the supply 942) which then flows into the ISHE material 932 and through via contact 940 to ground 945.
  • the charge current hits layer 932 and the ISHE layer 932 causes current to be spin polarized by the ferromagnetic layer 934.
  • the spin polarized current flows out of the ferromagnetic layer 934 and into the ISHE layer 932.
  • the ISHE material 932 generates a charge current from the spin polarized current received from the ferromagnetic layer 934.
  • the direction of magnetization of the ferromagnetic layer 934 determines the direction of spin current injected into the channel 930.
  • the current travels from the ISHE layer 932 through the channel 930 and then to the SHE material 920 with associated spin absorption layer 922.
  • the SHE layer 920 receives the current and spin polarizes the current.
  • the spin polarization generated in the current from the SHE material 920 determines whether the ferromagnetic layer 924 is switched, as described above.
  • the ferromagnetic layer 924 and ferromagnetic layer 934 are not directly switched by the current from the supplies 942,943, respectively, but are switched instead by the spin polarized current induced by the spin Hall (SH) effect layer 920, 936, respectively.
  • the ferromagnetic layer 924 is switched by the spin polarized current that is induced by the SHE layer 920, and not by a voltage applied by the supply 943.
  • the ferromagnetic layer 934 is switched by spin polarized current that is induced by SHE layer 936, and not by the voltage applied by supply 942.
  • the logic circuit 910 of FIG. 9 does not require a MTJ or a ferromagnetic having fixed direction of magnetization (e.g., a high magnetic coercivity layer analogous to a reference layer in an MTJ). Nor does the logic circuit 910 require a sense amplifier to read the circuit. It will also be appreciated in light of the present disclosure that the logic circuit of FIG. 9 does not require an insulating or dielectric material (such as magnesium oxide) between layers to operate, as is generally used in an MTJ. Thus, manufacturing is simplified, and device failure mechanisms related to dielectric breakdown are avoided, thus improving device reliability. There is also a lower read voltage required by the logic circuit as compared to a traditional MTJ, as will be appreciated in light of the present disclosure.
  • FIG. 10 is a graph comparing example data of switching efficiency between two MTJs, one of which is switched via a SHE material layer and another of which is switched via a SHE material layer in contact with a spin absorption layer, in accordance with an embodiment of the present disclosure.
  • FIG. 10 illustrates switching efficiency which is a ratio of the energy barrier (Eb, related to bit stability) and the threshold switching current (Ic).
  • the line 1010 illustrates the switching efficiency of an MTJ having a SHE layer and a spin absorption layer to enhance the spin Hall effect, in accordance with an embodiment of the present disclosure.
  • the line 1012 which illustrates the switching efficiency of an MTJ having a SHE layer without the spin absorption layer. As shown, the switching efficiency of the SHE layer with adjacent spin absorption layer is significantly improved as compared to a SHE layer that does not include the spin absorption layer.
  • injected spin current (indicated as IWRITE in various figures) produces spin torque that aligns a magnet in a + x or - x direction (see e.g., FIG. 3).
  • PSHE ( — 11 )/( + ) is the spin Hall injection efficiency, which is a ratio of a magnitude of transverse spin current to lateral charge current, w is a width of a magnet, t is a thickness of the SHE layer, is a spin flip length in the SHE material layer, and ⁇ SHE is a spin Hall angle for the SHE material layer to a spin absorption layer material.
  • FIG. 11 is a graph showing a comparison of write times for a SHE switched MRAM and a spin torque switched MRAM, configured in accordance with an embodiment of the present disclosure.
  • the graph shows the write time at a write error ratio (WER) of 1 x 10 '10 as a function of the thermal energy (kT) of the magnet thermal barrier.
  • the thermal energy, kT is measured as a product of the Boltzmann constant, k, and the temperature, T. This product is a characteristic value of energy of thermal fluctuations and indicates the amount of heat required to increase the thermodynamic entropy of a system by one nat. As shown, as the thermal energy increases, this can impact the write error ratios of the MRAM, depending upon the material used.
  • the graph compares write time for in plane and PMA MTJs as compared to a spin Hall MRAM having a spin absorption layer in accordance with an embodiment of the present disclosure.
  • the line 1110 shows an in plane MTJ and the write time as a function of the magnet thermal barrier.
  • the line 1112 shows a PMA MTJ and the write time of the PMA MTJ as a function of the magnet thermal barrier. Note that with both the in-plane MTJ and the PMA MTJ, the write time increases as the thermal energy (i.e., heat) increases. This can
  • the line 1114 shows a spin Hall MRAM having a spin absorption layer.
  • the write time for the in-plan MTJ 1110 and PMA MTJ 1112 increases.
  • the write time for the spin Hall MRAM having spin absorption layer remains substantially constant and does not increase as the thermal energy increases. This improves the overall performance of the device and also helps prolong the usable period of the components, by allowing them to operate under a variety of thermal energy conditions.
  • Use of the techniques and structures provided herein may be detectable using tools such as: electron microscopy including scanning/transmission electron microscopy (SEM/TEM), scanning transmission electron microscopy (STEM), and reflection electron microscopy (REM); composition mapping; x-ray crystallography or diffraction (XRD); energy-dispersive x-ray spectroscopy (EDS); secondary ion mass spectrometry (SIMS); time-of-flight SIMS (ToF- SEV1S); atom probe imaging or tomography; local electrode atom probe (LEAP) techniques; 3D tomography; or high resolution physical or chemical analysis, to name a few suitable example analytical tools.
  • tools such as: electron microscopy including scanning/transmission electron microscopy (SEM/TEM), scanning transmission electron microscopy (STEM), and reflection electron microscopy (REM); composition mapping; x-ray crystallography or diffraction (XRD); energy-dispersive x-ray spectroscopy (EDS); secondary ion mass spect
  • such tools may indicate the presence of a SHE material layer in contact with a spin absorption layer, as described above.
  • these two materials can be shown using some or all of the these techniques as being a component within a memory cell (e.g., an MTJ) or a logic circuit.
  • FIG. 12 is an example computing system implemented with one or more of the integrated circuit structures as disclosed herein, in accordance with some embodiments of the present disclosure.
  • the computing system 1200 houses a motherboard 1202.
  • the motherboard 1202 may include a number of components, including, but not limited to, a processor 1204 and at least one communication chip 1206, each of which can be physically and electrically coupled to the motherboard 1202, or otherwise integrated therein.
  • the motherboard 1202 may be, for example, any printed circuit board, whether a main board, a daughterboard mounted on a main board, or the only board of system 1200, etc.
  • computing system 1200 may include one or more other components that may or may not be physically and electrically coupled to the motherboard 1202. These other components may include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), a graphics processor, a digital signal processor, a crypto processor, a chipset, an antenna, a display, a touchscreen display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, an accelerometer, a gyroscope, a speaker, a camera, and a mass storage device (such as hard disk drive, compact disk (CD), digital versatile disk (DVD), and so forth).
  • volatile memory e.g., DRAM
  • non-volatile memory e.g., ROM
  • graphics processor e.g., a digital signal processor
  • crypto processor e.g., a graphics processor
  • any of the components included in computing system 1200 may include one or more integrated circuit structures or devices configured in accordance with an example embodiment (e.g., including a device switched using SHE spin polarization made more efficient by including a spin absorption layer that is in contact with a SHE material layer).
  • multiple functions can be integrated into one or more chips (e.g., for instance, note that the
  • communication chip 1206 can be part of or otherwise integrated into the processor 1204).
  • the communication chip 1206 enables wireless communications for the transfer of data to and from the computing system 1200.
  • wireless and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non- solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not.
  • the communication chip 1206 may implement any of a number of wireless standards or protocols, including, but not limited to, Wi-Fi (IEEE 802.1 1 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev- DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond.
  • the computing system 1200 may include a plurality of communication chips 1206.
  • a first communication chip 1206 may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth and a second communication chip 1206 may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.
  • communication chip 1206 may include one or more transistor structures having a gate stack an access region polarization layer as variously described herein.
  • the processor 1204 of the computing system 1200 includes an integrated circuit die packaged within the processor 1204.
  • the integrated circuit die of the processor includes onboard circuitry that is implemented with one or more integrated circuit structures or devices as variously described herein.
  • the term "processor" may refer to any device or portion of a device that processes, for instance, electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.
  • the communication chip 1206 also may include an integrated circuit die packaged within the communication chip 1206.
  • the integrated circuit die of the communication chip includes one or more integrated circuit structures or devices as variously described herein.
  • multi-standard wireless capability may be integrated directly into the processor 1204 (e.g., where functionality of any chips 1206 is integrated into processor 1204, rather than having separate communication chips).
  • processor 1204 may be a chip set having such wireless capability.
  • any number of processor 1204 and/or communication chips 1206 can be used.
  • any one chip or chip set can have multiple functions integrated therein.
  • the computing system 1200 may be a laptop, a netbook, a notebook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra-mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, a digital video recorder, or any other electronic device that processes data or employs one or more integrated circuit structures or devices formed using the disclosed techniques, as variously described herein.
  • PDA personal digital assistant
  • Example 1 is a memory cell including a first layer comprising a transition metal; a second layer directly on the first layer, the second layer comprising a spin Hall effect material, wherein the first layer absorbs spin accumulation at a bottom surface of the second layer; and a magnetic tunnel junction directly on the second layer.
  • Example 2 includes the subject matter of Example 1, wherein the memory cell defines a first path for writing to the memory cell and a second path distinct from the first path for reading from the memory cell .
  • Example 3 includes the subject matter of Example 1 or 2, wherein the first path for writing occurs via the second layer.
  • Example 4 includes the subject matter of any of Examples 1-3, wherein the second path for reading occurs via the magnetic tunnel junction by measuring a resistance between a free layer of the magnetic tunnel junction and a fixed layer of the magnetic tunnel junction.
  • Example 5 includes the subject matter of any of Examples 1-3, wherein the first layer is discontinuous.
  • Example 6 includes the subject matter of any of Examples 1-5, wherein the first layer comprises at least one of: ruthenium, chromium, titanium, titanium nitride, and zirconium.
  • Example 7 includes the subject matter of any of Examples 1-6, wherein the first layer comprises a ferromagnet or an anti-ferro magnet.
  • Example 8 includes the subject matter of any of Examples 1-7, wherein the first layer comprises at least one of: cobalt, cobalt iron, iron, nickel, cobalt nickel, manganese, and a Heusler alloy.
  • Example 9 includes the subject matter of any of Examples 1-8, wherein the second layer comprises at least one of: beta-tantalum, beta-tungsten, platinum, iridium, copper doped with platinum, copper doped with iridium, and copper doped with bismuth.
  • Example 10 includes the subject matter of any of Examples 1-9, wherein the first layer and the second layer comprise at least one of the following combinations of materials: a beta-tantalum layer from 1 nm to 5 nm thick for the second layer and a platinum layer from 1 nm to 2 nm thick for the first layer, a beta-tungsten layer from 1 nm to 5 nm thick for the second layer and a platinum layer from 1 nm to 2 nm thick for the first layer, a beta-tantalum layer from 1 nm to 5 nm thick for the second layer and a ruthenium layer from 1 nm to 2 nm thick for the first layer, a beta-tungsten layer from 1 nm to 5 nm thick for the second layer and a ruthenium layer from 1 nm to 2 nm thick for the first layer, a beta-tantalum layer from 1 nm to 5 nm thick for the second layer and a titanium layer from 1 nm to 2 nm thick for the
  • Example 11 includes the subject matter of any of Examples 1-10, wherein a fixed layer of the magnetic tunnel junction is directly on the second layer and comprises cobalt iron boron as a perpendicular magnetic anisotropy magnet.
  • Example 12 includes the subject matter of any of Examples 1-1 1, wherein a fixed layer of the magnetic tunnel junction is directly on the second layer and comprises alternating layers of cobalt and lead.
  • Example 13 includes the subject matter of any of Examples 1-12, wherein the magnetic tunnel junction further comprises a fixed layer of cobalt iron boron directly on the second layer, a tunneling layer of magnesium oxide directly on the fixed layer, and a free layer of cobalt iron boron directly on the tunneling layer.
  • Example 14 includes the subject matter of any Example 13, and further includes a first ruthenium layer directly on the free layer of the magnetic tunnel junction, and a cobalt iron layer directly on the first ruthenium layer.
  • Example 15 includes the subject matter of Example 14, and further includes an iron manganese layer directly on the cobalt iron layer, a second ruthenium layer directly on the iron manganese layer, a tantalum layer directly on the second ruthenium layer, and a third ruthenium directly on the tantalum layer.
  • Example 16 includes the subject matter of any of Examples 1-15, wherein the second layer has a first electrode on a first end and a second electrode on an opposing second end.
  • Example 17 includes the subject matter of Example 16, wherein the first layer that absorbs spin accumulation at a bottom surface of the second layer extends fully between the first electrode and the second electrode, and the second layer is in contact with the first electrode and the second electrode.
  • Example 18 includes the subject matter of Example 16, wherein the first layer that absorbs spin accumulation at a bottom surface of the second layer extends partially between the first electrode and the second electrode, and the second layer does not contact the first electrode, and the second layer does not contact the second electrode.
  • Example 19 is a memory cell including a fixed layer of a magnetic tunnel junction; a spin absorption layer comprising a transition metal; and a spin Hall effect layer between the spin absorption layer and the fixed layer of the magnetic tunnel junction.
  • Example 20 includes the subject matter of Example 19, wherein the memory cell defines a first path for writing to the memory cell and a second path distinct from the first path for reading from the memory cell.
  • Example 21 includes the subject matter of Example 20, wherein the first path for writing occurs via the spin absorption layer.
  • Example 22 includes the subject matter of Example 20, wherein the second path for reading occurs via the magnetic tunnel junction by measuring a resistance between a free layer of the magnetic tunnel junction and a fixed layer of the magnetic tunnel junction.
  • Example 23 includes the subject matter of any of Examples 19-22, wherein the spin absorption layer is discontinuous.
  • Example 24 includes the subject matter of any of Examples 19-23, wherein the spin absorption layer comprises at least one of: ruthenium, chromium, titanium, titanium nitride, and zirconium.
  • Example 25 includes the subject matter of any of Examples 19-24, wherein the spin absorption layer comprises a ferro magnet or an anti-ferro magnet.
  • Example 26 includes the subject matter of any of Examples 19-25, wherein the spin absorption layer comprises at least one of: cobalt, cobalt iron, iron, nickel, cobalt nickel, manganese, and a Heusler alloy.
  • Example 27 includes the subject matter of any of Examples 19-26, wherein the spin Hall effect layer comprises at least one of: beta-tantalum, beta-tungsten, platinum, iridium, copper doped with platinum, copper doped with iridium, and copper doped with bismuth.
  • the spin Hall effect layer comprises at least one of: beta-tantalum, beta-tungsten, platinum, iridium, copper doped with platinum, copper doped with iridium, and copper doped with bismuth.
  • Example 28 includes the subject matter of any of Examples 19-27, wherein the spin absorption layer and the spin Hall effect layer comprise at least one of the following combinations of materials: a beta-tantalum layer from 1 nm to 5 nm thick for the spin Hall effect layer and a platinum layer from 1 nm to 2 nm thick for the spin absorption layer, a beta-tungsten layer from 1 nm to 5 nm thick for the spin Hall effect layer and a platinum layer from 1 nm to 2 nm thick for the spin absorption layer, a beta-tantalum layer from 1 nm to 5 nm thick for the spin Hall effect layer and a ruthenium layer from 1 nm to 2 nm thick for the spin absorption layer, a beta- tungsten layer from 1 nm to 5 nm thick for the spin Hall effect layer and a ruthenium layer from 1 nm to 2 nm thick for the spin absorption layer, a beta-tantalum layer from 1 nm to 5 nm thick
  • Example 29 includes the subject matter of any of Examples 19-28, wherein the fixed layer of the magnetic tunnel junction comprises cobalt iron boron as a perpendicular magnetic anisotropy magnet.
  • Example 30 includes the subject matter of any of Examples 19-29, wherein the fixed layer of the magnetic tunnel junction comprises alternating thin layers of cobalt and lead.
  • Example 31 includes the subject matter of any of Examples 19-30, wherein the fixed layer of the magnetic tunnel junction comprises cobalt iron boron, a tunneling layer of the magnetic tunnel junction comprises magnesium oxide, and a free layer of the magnetic tunnel junction comprises cobalt iron boron.
  • Example 32 includes the subject matter of Example 31, and further includes a first ruthenium layer directly on the free layer of the magnetic tunnel junction, and a cobalt iron boron layer on the first ruthenium layer.
  • Example 33 includes the subject matter of Example 32, and further includes an iron manganese layer on the cobalt iron layer, a second ruthenium layer on the iron manganese layer, a tantalum layer on the second ruthenium layer, and a third ruthenium on the tantalum layer.
  • Example 34 is a method of forming a memory cell, the method including forming a spin absorption layer that comprises at least one transition metal; forming a spin Hall effect layer directly on the spin absorption layer, the spin Hall effect layer comprising a spin orbit material; and forming a fixed layer of a magnetic tunnel junction directly on the spin Hall effect layer.
  • Example 35 includes the subject matter of Example 34, wherein the spin absorption layer absorbs spin accumulation at an interface between the spin Hall effect layer and the spin absorption layer.
  • Example 36 includes the subject matter of Example 34 or 35, and further includes forming a tunneling barrier on the fixed layer, and forming a free layer directly on the tunneling barrier.
  • Example 37 includes the subject matter of any of Examples 34-36, and further includes writing to the memory cell via the spin Hall effect layer; and reading from the memory cell by measuring a resistance of the magnetic tunnel junction based on an electron spin in the spin Hall effect layer.
  • Example 38 includes a logic circuit comprising a first spin orbit logic device including a first spin Hall effect layer deposited between a first ferromagnetic layer and a first spin absorber layer, the first spin orbit logic device including a first inverse spin Hall effect layer deposited on the first ferromagnetic layer; a second spin orbit logic device including a second spin Hall effect layer deposited between a second ferromagnetic layer and a second spin absorber layer, the second spin orbit logic device including a second inverse spin Hall effect layer deposited on the second ferromagnetic layer; and a channel coupled between the second inverse spin Hall effect layer of the second spin orbit logic device and the first spin Hall effect layer of the first spin orbit logic device.
  • Example 39 includes the subject matter of Example 38, wherein the second inverse spin Hall effect layer converts spin current generated by the second ferromagnetic layer into charge current, and wherein the channel carries the charge current generated by the second inverse spin Hall effect to the first spin Hall effect layer, so that a value read from the second ferromagnetic layer is written to the first ferromagnetic layer.
  • Example 40 includes the subject matter of Example 38 or 39, and further includes a first via coupled between the first inverse spin Hall effect layer and a ground interconnect, and a second via coupled between the second inverse spin Hall effect layer and the ground interconnect.

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Mram Or Spin Memory Techniques (AREA)
  • Hall/Mr Elements (AREA)

Abstract

L'invention concerne des techniques permettant de former des dispositifs de mémoire vive magnétique (MRAM) et des dispositifs logiques qui comprennent une couche de matériau pour induire un effet Hall de spin (SHE) qui est en contact avec une couche d'un matériau d'absorption de spin. La disposition d'une couche de matériau d'absorption de spin en contact avec un matériau SHE améliore l'efficacité de commutation des dispositifs qui comprennent cette interface.
PCT/US2017/025604 2017-03-31 2017-03-31 Dispositif à effet hall de spin avec couche d'absorption de spin WO2018182740A1 (fr)

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CN112466359A (zh) * 2020-12-04 2021-03-09 首都师范大学 基于自旋轨道耦合效应的全电压调控逻辑器件
CN114184833A (zh) * 2021-10-27 2022-03-15 中国科学院微电子研究所 自旋霍尔器件、霍尔电压的获取方法及最大池化的方法
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Publication number Priority date Publication date Assignee Title
WO2020095360A1 (fr) * 2018-11-06 2020-05-14 Tdk株式会社 Élément de mouvement de paroi de domaine, élément d'enregistrement magnétique de type à mouvement de paroi de domaine et réseau d'enregistrement magnétique
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CN112466359A (zh) * 2020-12-04 2021-03-09 首都师范大学 基于自旋轨道耦合效应的全电压调控逻辑器件
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CN114184833A (zh) * 2021-10-27 2022-03-15 中国科学院微电子研究所 自旋霍尔器件、霍尔电压的获取方法及最大池化的方法
WO2023164827A1 (fr) * 2022-03-02 2023-09-07 中国科学院微电子研究所 Cellule de mémoire sot-mram, matrice de mémoire, mémoire et procédé de fonctionnement

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