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WO2018182714A1 - Transistors à couches minces à grille supérieure dotés de multiples couches de canal - Google Patents

Transistors à couches minces à grille supérieure dotés de multiples couches de canal Download PDF

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Publication number
WO2018182714A1
WO2018182714A1 PCT/US2017/025503 US2017025503W WO2018182714A1 WO 2018182714 A1 WO2018182714 A1 WO 2018182714A1 US 2017025503 W US2017025503 W US 2017025503W WO 2018182714 A1 WO2018182714 A1 WO 2018182714A1
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WIPO (PCT)
Prior art keywords
channel layer
tft
layer
oxygen
electrode
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PCT/US2017/025503
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English (en)
Inventor
Abhishek A. SHARMA
Van H. Le
Gilbert Dewey
Tahir Ghani
Jack T. Kavalieros
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Intel Corp
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Intel Corp
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Priority to PCT/US2017/025503 priority Critical patent/WO2018182714A1/fr
Publication of WO2018182714A1 publication Critical patent/WO2018182714A1/fr
Anticipated expiration legal-status Critical
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
    • H10D30/6706—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device for preventing leakage current 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D88/00—Three-dimensional [3D] integrated devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/08—Manufacture or treatment characterised by using material-based technologies using combinations of technologies, e.g. using both Si and SiC technologies or using both Si and Group III-V technologies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]

Definitions

  • Embodiments of the present disclosure generally relate to the field of integrated circuits, and more particularly, to transistors.
  • a memory device e.g., a dynamic random access memory (DRAM) array, may include a plurality of memory cells, where a memory cell may include a selector, e.g., a transistor, to control the access to a storage cell.
  • a selector e.g., a transistor
  • the silicon transistor may be very leak ⁇ 7 , which may bring adverse impact to the performance of the storage cell.
  • the storage cell is a capacitor
  • a relatively large capacitor may be used to store enough charge for the storage cell due to the leakage of the transistor as a selector, which may take up a significant substrate area.
  • a large capacitor may be implemented by creating a deep trench in a silicon substrate, making the process non-CMOS compatible.
  • a thin-film transistor is a kind of field-effect transistor including a channel layer, a gate electrode, and source and drain electrodes, over a supporting but nonconducting substrate.
  • a TFT differs from a conventional transistor, where a channel of the conventional transistor is typically within a substrate, such as a silicon substrate.
  • TFTs have emerged as an attractive option to fuel Moore's law by integrating TFTs vertically in the back-end, while leaving the silicon substrate areas for high-speed transistors.
  • a TFT may be used as a selector for a memory cell in a memory device. However, a TFT may often have low mobility. When a TFT is used as a selector for a memory cell, high mobility may be desired for the TFT.
  • a high mobility TFT may have higher leakage.
  • a TFT may be configured into different structures based on positions of the electrodes: top gate top electrode, top gate bottom electrode, bottom gate bottom electrode, and bottom gate top electrode.
  • different TFT structures may have dissimilar device characteristics while using the same materials.
  • FIG. 1 schematically illustrates a memory- array with multiple memory cells wherein a thin-film transistor (TFT) may be a selector of a memory cell, in accordance with various embodiments.
  • TFT thin-film transistor
  • Figure 2 schematically illustrates a diagram of a top-gated TFT having multiple channel layers including a low ieakage layer and a high mobility layer, in accordance with some embodiments.
  • FIG. 3 schematically illustrates a diagram of another top-gated TFT having multiple channel layers including a low leakage layer and a high mobility layer, in accordance with some embodiments.
  • Figure 4 schematically illustrates a diagram of a memory ceil including a top- gated TFT coupled to a storage cell, wherein the top-gated TFT has multiple channel layers including a low leakage layer and a high mobility layer, in accordance with some embodiments.
  • Figure 5 illustrates a process for forming a top-gated TFT having multiple channel layers including a low leakage layer and a high mobility layer, in accordance with some embodiments.
  • Figure 6 schematically illustrates an mterposer implementing one or more embodiments of the disclosure, in accordance with some embodiments.
  • Figure 7 schematically illustrates a computing device built in accordance with an embodiment of the disclosure, in accordance with some embodiments.
  • Figure 8 schematically illustrates a diagram of a top-gated TFT having multiple channel layers including a high mobility layer and a low ieakage layer formed in back- end-of-line (BEOL) on a substrate, in accordance with some embodiments.
  • a memory cell in a memory device may include a selector, e.g., a transistor, to control the access to a storage cell.
  • the storage cell may be a capacitor to store charge, resulting in a 1T1 C (one transistor, one capacitor) architecture for the memory cell, or a resistive random access memory (RRAM) storage cell, resulting in a 1T1 R (one transistor, one resistive ceil) architecture for the memory cell.
  • RRAM resistive random access memory
  • a thin-film transistor may be used as a selector of a memory cell.
  • a TFT may have low leakage or high mobility, but not both.
  • a TFT with low mobility may be useful for low power applications, e.g., displays.
  • a TFT may be configured into different structures based on positions of the electrodes, for example, a top gate top electrode, a top gate bottom electrode, a bottom gate bottom electrode, a bottom gate top electrode, and the like. Sometimes different TFT structures may have dissimilar device characteristics while using the same materials.
  • a top-gated TFT may have better control over the gate length, since the gate electrode may be between a source electrode and a drain electrode, which make the gate length more variation tolerant.
  • Embodiments herein may present techniques to form a top-gated TFT having multiple channel layers including a high mobility layer and a low leakage layer, so that the top-gated TFT may have high mobility while keeping the leakage low.
  • Embodiments herein may present top-gated TFTs having multiple channel layers including a high mobility layer and a low leakage layer.
  • the top-gated TFTs may be used as selectors for memory cells with improved performance.
  • a top-gated TFT presented herein may have belter contacts between the multiple channel layers and the source electrode or the drain electrode due to a top high mobility channel layer.
  • the top- gated TFT presented herein may also have better channel passivation through a buried channel layer.
  • a top-gated TFT presented herein may improve gate length scaling without increasing off current for the top-gated TFT.
  • Other advantages for the top-gated TFT presented herein may include: low off current and high drive current which may be useful for memory devices, tuning and controlling of work function and threshold voltage of the top-gated TFT based on different channel layers, doping-friendly layers either exposed or buried as a buffer layer, and/or formation of backside surface charge to mitigate short channel effects.
  • Embodiments herein may present a semiconductor device, which may include a dielectric layer above a substrate. Multiple channel layers may be above the dielectric layer.
  • the semiconductor device may include a first channel layer including a first material above the dielectric layer and a second channel layer including a second material above the first channel layer.
  • the first material may be a low leakage material and the second material may be a high mobility material.
  • the first material may have lower leakage than the second material, and the second material may have higher mobility than the first material.
  • the semiconductor device may further include a source electrode and a drain electrode above the second channel layer.
  • the semiconductor device may include a gate electrode above the second channel layer and between the source electrode and the drain electrode.
  • the semiconductor device may be a top-gated TFT having high mobility, while keeping the leakage low.
  • Embodiments herein may present a computing device, which may include a circuit board, and a memory- device coupled to the circuit board and including a memory- array.
  • the memory array may include a plurality of memory cells, wherein a memory cell of the plurality of memory cells may include a transistor and a storage cell.
  • the transistor may include a first channel layer including a first material above a substrate, and a second channel layer including a second material above the first channel layer.
  • the first material may be a low leakage material and the second material may be a high mobility material.
  • the first material may have lower leakage than the second material, and the second material may have higher mobility than the first material.
  • the transistor may further include a source electrode above the second channel layer and coupled to a source line of the memory array, a drain electrode above the second channel layer and coupled to a first electrode of the storage cell, and a gate electrode above the second channel layer, between the source electrode and the drain electrode, and coupled to a word line of the memory array.
  • the storage cell may further include a second electrode coupled to a bit line of the memory array.
  • a method for forming a semiconductor device may include: forming a dielectric layer above a substrate, forming a first channel layer including a first material above the dielectric layer, and forming a second channel layer including a second material above the first channel layer.
  • the first material may be a low leakage material and the second material may be a high mobility material.
  • the first material may have lower leakage than the second material, and the second material may have higher mobility than the first material.
  • the method may- further include forming a source electrode and a drain electrode above the second channel layer.
  • the method may include forming a gate electrode above the second channel layer and between the source electrode and the drain electrode.
  • the semiconductor device formed by the method may be a top-gated TFT having high mobility, while keeping the leakage low.
  • phrase “A and/or B” means (A), (B), or (A and B).
  • phrase “A, B, and/or C” means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B and C).
  • over,” “under,” “between,” “above,” and “on” as used herein may refer to a relative position of one material layer or component with respect to other layers or components.
  • one layer disposed over or under another layer may be directly in contact with the other layer or may have one or more intervening layers.
  • one layer disposed between two layers may be directly in contact with the two layers or may have one or more intervening layers.
  • a first layer “on” a second layer is in direct contact with that second layer.
  • one feature disposed between two features may be in direct contact with the adjacent features or may have one or more intervening features.
  • Coupled may mean one or more of the following. “Coupled” may mean that two or more elements are in direct physical or electrical contact. However, “coupled” may also mean that two or more elements indirectly contact each other, but yet still cooperate or interact with each other, and may mean that one or more other elements are coupled or connected between the elements that are said to be coupled with each other.
  • directly coupled may mean that two or more elements are in direct contact.
  • the phrase "a first feature formed, deposited, or otherwise disposed on a second feature” may mean that the first feature is formed, deposited, or disposed over the second feature, and at least a part of the first feature may ⁇ be in direct contact (e.g., direct physical and/or electrical contact) or indirect contact (e.g. , having one or more other features between the first feature and the second feature) with at least a part of the second feature.
  • circuitry may refer to, be part of, or include an Application Specific Integrated Circuit (ASIC), an electronic circuit, a processor (shared, dedicated, or group), and/or memory (shared, dedicated, or group) that execute one or more software or firmware programs, a combinational logic circuit, and/or other suitable hardware components that provide the described functionality.
  • ASIC Application Specific Integrated Circuit
  • computer-implemented method may refer to any method executed by one or more processors, a compuier system having one or more processors, a mobile device such as a smartphone (which may include one or more processors), a tablet, a laptop computer, a set-top box, a gaming console, and so forth.
  • Implementations of the disclosure may be formed or carried out on a substrate, such as a semiconductor substrate.
  • the semiconductor substrate may be a crystalline substrate formed using a bulk silicon or a silicon-on-insulator substructure.
  • the semiconductor substrate may be formed using alternate materials, which may or may not be combined with silicon, that include but are not limited to germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, indium gallium arsenide, gallium antimonide, or other combinations of group III-V or group IV materials.
  • any material that may serve as a foundation upon which a semiconductor device may be built falls within the spirit and scope of the present disclosure.
  • a plurality of transistors such as metal-oxide-semiconductor field-effect transistors (MOSFET or simply MOS transistors), may be fabricated on the substrate.
  • the MOS transistors may be planar transistors, nonplanar transistors, or a combination of both.
  • Nonplanar transistors include FinFET transistors such as double-gate transistors and tri-gate transistors, and wrap-around or all- around gate transistors such as nanorihhon and nanowire transistors.
  • the implementations described herein may illustrate only planar transistors, it should be noted that the disclosure may also be carried out using nonplanar transistors.
  • Each MOS transistor includes a gate stack formed of at least two layers, a gate dielectric layer and a gate electrode layer.
  • the gate dielectric layer may include one layer or a stack of layers.
  • the one or more layers may include silicon oxide, silicon dioxide (Si0 2 ) and/or a high-k dielectric material.
  • the high-k dielectric material may include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc.
  • high-k materials that may be used in the gate dielectric layer include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate.
  • an annealing process may be earned out on the gate dielectric layer to improve its quality when a high-k material is used.
  • the gate electrode layer is formed on the gate dielectric layer and may consist of at least one P-type work function metal or N-type work function metal, depending on whether the transistor is to be a PMOS or an NMOS transistor.
  • the gate electrode layer may consist of a stack of two or more metal layers, where one or more metal layers are work function metal layers and at least one metal layer is a fill metal layer. Further metal layers may be included for other purposes, such as a barrier layer.
  • metals that may be used for the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, and conductive metal oxides, e.g. , ruthenium oxide.
  • a P-type metal layer will enable the formation of a PMOS gate electrode with a work function that is between about 4.9 eV and about 5.2 eV.
  • metals that may be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals such as hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide.
  • An N-type metal layer will enable the formation of an NMOS gate electrode with a work function that is between about 3,9 eV and about 4.2 eV.
  • the gate electrode when viewed as a cross-section of the transistor along the source-channel-drain direction, may consist of a "U"-shaped structure that includes a bottom portion substantially parallel to the surface of the substrate and two sidewall portions that are substantiaily perpendicular to the top surface of the substrate.
  • at least one of the metal layers that form the gate electrode may simply be a planar layer that is substantially parallel to the top surface of the substrate and does not include sidewall portions substantially perpendicular to the top surface of the substrate.
  • the gate electrode may consist of a combination of U-shaped structures and planar, non-U-shaped structures.
  • the gate electrode may consist of one or more U-shaped metal layers formed atop one or more planar, non-U-shaped layers.
  • a pair of sidewall spacers may be formed on opposing sides of the gate stack that bracket the gate stack.
  • the sidewall spacers may be formed from a material such as silicon nitride, silicon oxide, silicon carbide, silicon nitride doped with carbon, and silicon oxynitride. Processes for forming sidewall spacers are well known in the art and generally include deposition and etching process operations. In an alternate implementation, a plurality of spacer pairs may be used, for instance, two pairs, three pairs, or four pairs of sidewall spacers may be formed on opposing sides of the gate stack.
  • source and drain regions are formed within the substrate adjacent to the gate stack of each MOS transistor.
  • the source and drain regions are generally formed using either an implantation/diffusion process or an etching/deposition process.
  • dopants such as boron, aluminum, antimony, phosphorous, or arsenic may be ion-implanted into the substrate to form the source and drain regions.
  • An annealing process that activates the dopants and causes them to diffuse further into the substrate typically follows the ion implantation process.
  • the substrate may first be etched to form recesses at the locations of the source and drain regions.
  • the source and drain regions may be fabricated using a silicon alloy such as silicon germanium or silicon carbide.
  • the epitaxially deposited silicon alloy may be doped in situ with dopants such as boron, arsenic, or phosphorous.
  • the source and dram regions may be formed using one or more alternate semiconductor materials such as germanium or a group III-V material or alloy.
  • one or more layers of metal and/or metal alloys may be used to form the source and drain regions.
  • ILD interiayer dielectrics
  • the ILD layers may be formed using dielectric materials known for their applicability in integrated circuit structures, such as low-k dielectric materials. Examples of dielectric materials that may be used include, but are not limited to, silicon dioxide (Si0 2 ), carbon doped oxide (CDO), silicon nitride, organic polymers such as perfluorocvclobutane or poiytetrafiuoroethylene, fluorosilicate glass (FSG), and organosilicates such as siisesquioxane, siloxane, or organosilicate glass.
  • the ILD layers may include pores or air gaps to further reduce their dielectric constant.
  • FIG. 1 schematically illustrates a memor ' array 100 with multiple memory ceils (e.g., a memory cell 102, a memory cell 104, a memory cell 106, and a memory cell 108), wherein a TFT, e.g., a TFT 114, may be a selector of a memory cell, e.g., the memory cell 102, in accordance with various embodiments.
  • a TFT e.g., a TFT 114
  • the multiple memor ' cells may be arranged in a number of rows and columns coupled by bit lines, e.g. , bit line Bl and bit line B2, word lines, e.g., word line Wl and word line W2, and source lines, e.g., source line S I and source line S2.
  • the memory cell 102 may be coupled in series with the other memory cells of the same row, and may be coupled in parallel with the memory cells of the other rows.
  • the memory array 100 may include any suitable number of one or more memory cells. Although the memory array 100 is shown in Figure 1 with two rows that each includes two memory cells coupled in series, other embodiments may include other numbers of rows and/or numbers of memory cells within a row. In some embodiments, the number of rows may be different from the number of columns in a memory array. Each row of the memory array may have a same number of memory ceils. Additionally, or alternatively, different rows may have different numbers of memory cells.
  • multiple memory cells may have a similar configuration, such as the 1T1C configuration.
  • the memory cell 102 may include the TFT 1 14 coupled to a storage cell 1 12 that may be a capacitor.
  • a memory cell with the 1T1 C configuration e.g., the memory ceil 102, may be controlled through multiple electrical connections to read from the memory cells, write to the memory cells, and/or perform other memory operations.
  • the storage cell 112 may be another type of storage device, e.g., a RRAM cell, resulting in the 1T1R architecture for the memory cell 102.
  • the storage cell 1 12 when the storage cell 112 is a capacitor, the storage cell 1 12 may be switchable between charged or discharged states upon application of an electric current or voltage.
  • the charged or discharged states of the storage cell 112 may be taken to represent the two values of a bit, conventionally called 0 and 1.
  • the storage cell 112 may be individually controllable by the TFT 1 14 as a selector to switch between the charged or discharged states.
  • the storage cell 112 when the storage cell 112 is a RRAM cell, the storage cell 112 may be switchable between two or more resistance values upon application of an electric current or voltage.
  • the storage cell 112 may have a first resistance value to store a logic 0, and may have a second resistance value to store a logic 1.
  • the resistance difference between the two resistance values may be one or more orders of magnitude.
  • the TFT 114 may be a selector for the memory ceil 102.
  • a word line Wl of the memory array 100 may be coupled to a gate electrode 1 11 of the TFT 1 14.
  • the TFT 1 14 may select the storage cell 1 12
  • a source line S I of the memory array 100 may be coupled to an electrode 101 of the storage cell 1 12, while another electrode 107 of the storage cell 112 may be shared with the TFT 114.
  • a bit line Bl of the memory array 100 may be coupled to another electrode, e.g., an electrode 109 of the TFT 114.
  • the shared electrode 107 may be a source electrode or a drain electrode of the TFT 114, while the electrode 109 may be a drain electrode or a source electrode of the TFT 114.
  • a drain electrode and a source electrode may be used interchangeably herein.
  • a source line and a bit line may be used interchangeably herein.
  • the TFT 114 may be a top gate top electrode TFT, or a top gate bottom electrode TFT, where both can be referred to as a top-gated TFT. In some other embodiments, the TFT 114 may be a bottom gate bottom electrode TFT, or a bottom gate top electrode TFT. In the rest of the disclosure, a TFT may refer to a top-gated TFT.
  • the memory cells and the transistors, e.g., the memory cell 102 and the TFT 1 14, included in the memory array 100 may be formed in back-end- of-line (BEOL).
  • the TFT 1 14 may be illustrated as a top-gated TFT 814 shown in Figure 8 at the BEOL.
  • the memory array 100 may be formed in higher metal layers, e.g., metal layer 3 and/or metal layer 4, of the integrated circuit above the active substrate region, and may not occupy the active substrate area that is occupied by conventional transistors or memory devices.
  • FIG. 2 schematically illustrates a diagram of a top-gated TFT, e.g. , a top- gated TFT 214, having multiple channel layers including a low leakage layer, e.g., a first channel layer 225, and a high mobility layer, e.g., a second channel layer 227, in accordance with some embodiments.
  • the top-gated TFT 214 may be an example of the TFT 114 in Figure 1.
  • the structure of the top-gated TFT 214 may be for illustration purpose only and is not limiting.
  • the top-gated TFT 214 may have other configurations including more or fewer layers than are shown in Figure 2.
  • the top-gated TFT 214 may include a substrate 220, a dielectric layer 221 above the substrate 220, the first channel layer 225 above the dielectric layer 221, and the second channel layer 227 above the first channel layer 225.
  • the top-gated TFT 214 may include a source electrode 226, and a drain electrode 228 above the second channel layer 227.
  • the top-gated TFT 214 may include a gate electrode 222 above the second channel layer 227, between the source electrode 226 and the drain electrode 228.
  • a gate dielectric layer 223 below the gate electrode 222 and above the second channel layer 227, and a spacer 224 above the second channel layer 227 between the source electrode 226, or the drain electrode 228, and the gate electrode 222.
  • the substrate 220 may be a glass substrate, such as soda lime glass or borosilicate glass, a metal substrate, a plastic substrate, or another suitable substrate.
  • Other inter-metal dielectric layer may be formed on the substrate.
  • the substrate 220 may include an inter-metal dielectric layer, or other devices, not shown for clarity.
  • the dielectric layer 221, or the spacer 224 may include a silicon oxide (SiO) film, a silicon nitride (SiN) film, 0 3 -tetraethylorthosilicate (TEOS), O3- hexamethyldisiioxaiie (HMDS), plasma-TEOS oxide layer, or other suitable materials.
  • TEOS silicon nitride
  • HMDS O3- hexamethyldisiioxaiie
  • plasma-TEOS oxide layer or other suitable materials.
  • the first channel layer 225 may include a low leakage material.
  • a leakage current may refer to a relatively small amount of current that flows (or 'leaks") through the transistor when it is "turned off.” In an ideal transistor, the leakage current would be zero, but in practice, leakage current may have a finite value larger than zero.
  • the top-gated TFT 214 having the first channel layer 225 with a low leakage material may have a low leakage current, e.g., in a range of about 10 ⁇ 4 amp to about 10 " ' 2 amp.
  • the first channel layer 225 may include indium, gallium, zinc, and oxide; molybdenum and sulfur; a group-VI transition metal dichalcogenide, or other low leakage materials.
  • the first channel layer 225 may include indium gallium zinc oxide (IGZO), molybdenum disulfide (MoS 2 ), or tungsten diselenide (WSe 2 ).
  • IGZO indium gallium zinc oxide
  • MoS 2 molybdenum disulfide
  • WSe 2 tungsten diselenide
  • the first channel layer 225 may have a thickness in a range of about 0.5 nm to about 20 nm.
  • the second channel layer 227 may include a high mobility ( ⁇ ) material.
  • a mobility of a material may be a proportionality constant that relates the drift velocity to the electric field strength in a semiconductor.
  • a mobility of a material may gauge how easily current carriers (e.g., electrons, holes) may move through a piece of material.
  • the second channel layer 227 may include a material having a high mobility, e.g., a mobility in a range of about 12cm 2 /VS to about 132 cmVVS, such as, 25 cm 2 /VS.
  • the second channel layer 227 may include indium doped zinc Oxide (IZO), zinc tin oxide (ZTO), amorphous silicon (a-Si), amorphous germanium (a-Ge), low-temperature polycrystalline silicon (LTPS), transition metal dichalcogenide (TMD), yttrium-doped zinc oxide (YZO), or zinc oxide (ZnO), or other similar high mobility materials.
  • IZO indium doped zinc Oxide
  • ZTO zinc tin oxide
  • a-Si amorphous silicon
  • a-Ge amorphous germanium
  • LTPS low-temperature polycrystalline silicon
  • TMD transition metal dichalcogenide
  • YZO yttrium-doped zinc oxide
  • ZnO zinc oxide
  • the first channel layer 225 may include a material with a lower leakage than a material included in the second channel layer 227.
  • the second channel layer 227 may include a material with a higher mobility than a material included in the first channel layer 225.
  • the top-gated TFT 214 including both the first channel layer 225 and the second channel layer 227 may have high mobility, while keeping the leakage low.
  • the gate electrode 222 may be formed as a single layer or a stacked layer using one or more conductive films including a conductive material.
  • the gate electrode 222 may include gold (Au), platinum (Pi), ruthenium ( u), iridium (Ir), titanium (Ti), aluminum (Al), copper (Cu), tantalum (Ta), tungsten (W), tantalum nitride (TaN), titanium nitride (TiN), iridium-tantalum alloy (Ir-Ta), indium-tin oxide (ITO), the like, and/or a combination thereof.
  • the gate dielectric layer 223 may include silicon and oxygen; silicon and nitrogen; yttrium and oxygen; silicon, oxygen, and nitrogen; aluminum and oxygen; hafnium and oxygen; tantalum and oxygen; or titanium and oxygen.
  • the gate dielectric layer 223 may include silicon oxide (Si0 2 ), silicon nitride (SiNx), yttrium oxide (Y2O3), silicon oxynitride (SiOJM y ), aluminum oxide (Al 2 Os), haihium(IV) oxide (Hf0 2 ), tantalum oxide (Ta 2 Os), titanium dioxide (Ti0 2 ), or other dielectric materials.
  • the source electrode 226 and the drain electrode 228 may include one or more conductive films including a conductive material.
  • the source electrode 226 and the drain electrode 228 may include Ti, molybdenum (Mo), Au, Pi, Al, nickel (Ni), Cu, chromium (Cr), Ru, iridium (Ir), Ta, W, an alloy of Ti, Mo, Au, Pt, Al, Ni, Cu, Cr, Ru, Ir, Ta, W, or another conductive material.
  • FIG 3 schematically illustrates a diagram of another top-gated TFT, e.g., a top- gated TFT 314, having multiple channel layers including a low leakage layer e.g., a first channel layer 325, and a high mobility layer, e.g., a second channel layer 327, in accordance with some embodiments.
  • the top-gated TFT 314 may be an example of the TFT 1 14 in Figure 1.
  • Various layers in the top-gated TFT 314 may be similar to corresponding layers in the top-gated TFT 214 in Figure 2.
  • the structure of the top- gated TFT 314 may be for illustration purpose only and is not limiting.
  • the top-gated TFT 314 may include a substrate 320, a dielectric layer 321 above the substrate 320, the first channel layer 325 above the dielectric layer 321, and the second channel layer 327 above the first channel layer 325.
  • the top-gated TFT 314 may include a buffer layer 329 between the first channel layer 325 and the second channel layer 327.
  • the top-gated TFT 314 may include a source electrode 326, and a drain electrode 328 above the second channel layer 327.
  • the top-gated TFT 314 may include a gate electrode 322 above the second channel layer 327, between the source electrode 326 and the drain electrode 328.
  • the first channel layer 325 may include a low leakage material, similar to the first channel layer 225 in Figure 2, while the second channel layer 327 may include a high mobility (u) material, similar to the second channel layer 227 in Figure 2.
  • the first channel layer 325 may include a material with a lower leakage than a material included in the second channel layer 327.
  • the second channel layer 327 may include a material with a higher mobility than a material included in the first channel layer 325.
  • the top-gated TFT 314 including both the first channel layer 325 and the second channel layer 327 may have high mobility, while keeping the leakage low.
  • the buffer layer 329 may be between the first channel layer 325 and the second channel layer 327, providing lattice matching between the low leakage material for the first channel layer 325 and the high mobility material for the second channel layer 327.
  • the buffer layer 329 may include indium doped zinc and oxygen.
  • the buffer layer 329 may be a buried layer.
  • the buffer layer 329 may have a thickness in a range of about 0.5 nm to about 20 nm.
  • Figure 4 schematically illustrates a diagram of a memory cell, e.g., a memory cell
  • top-gated TFT 414 including a top-gated TFT, e.g., a top-gated TFT 414, coupled to a storage cell, e.g., a storage cell 412, wherein the top-gated TFT has multiple channel layers including a low leakage layer and a high mobility layer, in accordance with some embodiments.
  • the memory cell 402 may be an example of the memory cell 102 in Figure 1, while the top- gated TFT 414 may be an example of the TFT 114 in Figure 1.
  • Various layers in the top- gated TFT 414 may be similar to corresponding layers in the top-gated TFT 214 in Figure 2, or the top-gated TFT 314 in Figure 3.
  • the structure of the top-gated TFT 414 and the memory cell 402 may be for illustration purpose only and is not limiting.
  • the top-gated TFT 414 may include a substrate 420, a dielectric layer 421 above the substrate 420, the first channel layer 425 above the dielectric layer 421 , and the second channel layer 427 above the first channel layer 425.
  • the top-gated TFT 414 may include a buffer layer 429 between the first channel layer 425 and the second channel layer 427.
  • the first channel layer 425 may include a low leakage material, similar to the first channel layer 225 in Figure 2, while the second channel layer 427 may include a high mobility ( ⁇ ) material, similar to the second channel layer 227 in Figure 2.
  • the first channel layer 425 may include a material with a lower leakage than a material included in the second channel layer 427.
  • the second channel layer 427 may include a material with a higher mobility than a material included in the first channel layer 425.
  • the top-gated TFT 414 including both the first channel layer 425 and the second channel layer 427 raay have high mobilit ', while keeping the leakage low.
  • the top-gated TFT 414 may further include a buffer layer 429 between the first channel layer 425 and the second channel layer 427, where the buffer layer 429 may be similar to the buffer layer 329 in Figure 3.
  • the top-gated TFT 414 may inciude a source electrode 426, and a drain electrode 428 above the second channel layer 427.
  • the top-gated TFT 414 may include a gate electrode 422 above the second channel layer 427, between the source electrode 426 and the drain electrode 428.
  • the storage cell 412 may include a first electrode 431, a second electrode 435, and a resistive switching material layer 433 between the first electrode 431 and the second electrode 435.
  • the first electrode 431 may be coupled to the drain electrode 428 of the top-gated TFT 414, while the second electrode 435 may be coupled to a bit line of a memory array, not shown.
  • the source electrode 426 of the top- gated TFT 414 may be coupled to a source line of the memory array, and the gate electrode 422 may be coupled to a word line of the memory array.
  • the first electrode 431 and/or the second electrode 435 may include Au, Pt, Ru, Ir, Ti, Al, Cu, Ta, W, or an alloy such as Ir-Ta, ITO, TaN, TiN, TiAIN, TiW, Hf, or other conductive material.
  • the thickness of the first electrode 431 and/or the second electrode 435 may be between a range of about 100-500 nm.
  • the resistive switching material layer 433 may include hafnium and oxygen; tantalum and oxygen; hafnium, tantalum and oxygen; tellurium; germanium; silicon; or chalcogenide.
  • the resistive switching material layer 433 may include HfOx, TaOx, HfFaOx, Te, Ge, Si, chalcogenide, a transition metal oxide, or a transition metal chalcogenide.
  • the resistive switching material layer 433 may include one or more oxide of W, Ta, Ti, Ni, Co, Hf, Ru, Zr, Zn, Fe, Sn, Al, Cu, Ag, Mo, and/or Cr.
  • silicon may be included in the resistive switching material layer 433 to form a composite material.
  • the thickness of the resistive switching material layer 433 may be between a range of about 20 nm to about 100 nm.
  • the material in the resistive switching material layer 433 may be formed in an initial state with a first resistance value, e.g., a relatively low-resistance state such as 10 5 ohms.
  • a first voltage e.g., a set operating voltage, such as 3 V
  • the resistive switching material layer 433 may switch to a stable second resistance value, e.g., a high-resistance state, such as 10 ' ohms, which is maintained even after the voltage is removed.
  • This resistance switching may be reversible such that subsequent application of an appropriate current or a second voltage can serve to return the resistive material layer 433 to a stable first resistance value which is maintained even after the voltage or current is removed.
  • the first resistance value may be a high-resistance value rather than a low-resistance value.
  • FIG 5 illustrates a process 500 for forming a top-gated TFT having multiple channel layers including a low leakage layer and a high mobility layer, in accordance with some embodiments.
  • the process 500 may be applied to form the TFT 1 14 in Figure 1 , the top-gated TFT 214 in Figure 2, the top-gated TFT 314 in Figure 3, or the top-gated TFT 414 in Figure 4.
  • the process 500 may include forming a dielectric layer above a substrate.
  • the process 500 may include forming the dielectric lay er 221 above the substrate 220 as shown in Figure 2.
  • the process 500 may include forming a first channel layer including a first material above the dielectric layer.
  • the process 500 may include forming the first channel layer 225 above the dielectric layer 221 , as shown in Figure 2.
  • the first channel layer formed at the block 503 may include a low leakage material, such as indium, gallium, zinc, and oxide: molybdenum and sulfur; a group- VI transition metal dichalcogenide, or other low leakage materials.
  • the top-gated TFT with the low leakage material may have a low leakage current, e.g., in a range of about 10 " * amp to about I0 ' amp.
  • the process 500 may include forming a second channel layer including a second material above the first channel layer.
  • the process 500 may include forming the second channel layer 227 above first channel layer 225, as shown in Figure 2.
  • the second channel layer 227 may include a high mobility material, such as indium doped zinc Oxide (IZO), zinc tin oxide (ZTO), amorphous silicon ( a- Si ), amorphous germanium (a-Ge), low-temperature polycrystalline silicon (LTPS), transition metal dichalcogenide (TMD), yttrium-doped zinc oxide (YZO), or zinc oxide (ZnO).
  • IZO indium doped zinc Oxide
  • ZTO zinc tin oxide
  • a- Si amorphous silicon
  • a-Ge amorphous germanium
  • LTPS low-temperature polycrystalline silicon
  • TMD transition metal dichalcogenide
  • YZO yttrium-doped zinc oxide
  • ZnO zinc oxide
  • the first channel layer formed at the block 503 may include a material with a lower leakage than a material included in the second channel layer formed at the block 505.
  • the second channel layer formed at the block 505 may include a material with a higher mobility than a material included in the first channel layer formed at the block 503.
  • the top-gated TFT including both the first channel layer formed at the block 503 and the second channel layer formed at the block 505 may have high mobility, while keeping the leakage low.
  • the process 500 may include forming a source electrode and a drain electrode above the second channel layer.
  • the process 500 may include forming the source electrode 226 and the dram electrode 228 above the second channel layer 227.
  • the source electrode 226 or the drain electrode 228 may include Au, Pt, Ru, Ir, Ti, Al, Cu, Ta, W, Ir-Ta, or ITO.
  • the process 500 may include forming a gate electrode above the second channel layer and between the source electrode and the drain electrode.
  • the process 500 may include forming the gate electrode 222 above the second channel layer 227 and between the source electrode 226 and the drain electrode 228.
  • the process 500 may include one or more additional operations than those depicted by Figure 5.
  • the process 500 may include forming a buffer layer between the first channel layer and the second channel layer, e.g., the buffer layer 329 shown in Figure 3.
  • the process 500 may include forming a gate dielectric layer below the gate electrode and above the second channel layer, wherein the gate dielectric layer includes silicon and oxygen; silicon and nitrogen; yttrium and oxygen; silicon, oxygen, and nitrogen; aluminum and oxygen; hafnium and oxygen; tantalum and oxygen; and/or titanium and oxygen.
  • FIG 6 illustrates an interposer 600 that includes one or more embodiments of the disclosure.
  • the interposer 600 is an intervening substrate used to bridge a first substrate 602 to a second substrate 604.
  • the first substrate 602 may be, for instance, a substrate support for a TFT, e.g., the TFT 1 14 shown in Figure 1, the top-gated TFT 214 shown in Figure 2, the top-gated TFT 314 shown in Figure 3, or the top-gated TFT 414 shown in Figure 4.
  • the second substrate 604 may be, for instance, a memory module, a computer motherboard, or another integrated circuit die.
  • the second substrate 604 may be a memoi module including the memory array 100 as shown in Figure 1 .
  • an interposer 600 may couple an integrated circuit die to a ball grid array (BGA) 606 that can subsequently be coupled to the second substrate 604.
  • BGA ball grid array
  • the first and second substrates 602/604 are attached to opposing sides of the interposer 600.
  • the first and second substrates 602/604 are attached to the same side of the interposer 600.
  • three or more substrates are interconnected by way of the interposer 600.
  • the interposer 600 may be formed of an epoxy resin, a fiberglass-reinforced epoxy resin, a ceramic material, or a polymer material such as polyimide.
  • the interposer may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other group III-V and group IV materials.
  • the interposer may include metal interconnects 608 and vias 610, including but not limited to through-silicon vias (TSVs) 612.
  • the interposer 600 may further include embedded devices 614, including both passive and active devices.
  • Such devices include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, and electrostatic discharge (ESD) devices.
  • More complex devices such as radio-frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and MEMS devices may also be formed on the interposer 600.
  • RF radio-frequency
  • apparatuses or processes disclosed herein may be used in the fabrication of interposer 600.
  • FIG. 7 illustrates a computing device 700 in accordance with one embodiment of the disclosure.
  • the computing device 700 may include a number of components. In one embodiment, these components are attached to one or more motherboards. In an alternate embodiment, some or all of these components are fabricated onto a single system-on-a-chip (SoC) die, such as a SoC used for mobile devices.
  • SoC system-on-a-chip
  • the components in the computing device 700 include, but are not limited to, an integrated circuit die 702 and at least one communications logic unit 708.
  • the communications logic unit 708 is fabricated within the integrated circuit die 702 while in other implementations the communications logic unit 708 is fabricated in a separate integrated circuit chip that may be bonded to a substrate or motherboard that is shared with or electronically coupled to the integrated circuit die 702.
  • the integrated circuit die 702 may include a processor 704 as well as on-die memory 706, often used as cache memory, which can be provided by technologies such as embedded DRAM (eDRAM), or SRAM,
  • the on-die memory 706 may include the TFT 1 14 shown in Figure 1 , the top-gated TFT 214 shown in Figure 2, the top-gated TFT 3 4 shown in Figure 3, the top-gated TFT 414 shown in Figure 4, or a top-gated TFT formed according to the process 500 shown in Figure 5.
  • the computing device 700 may include a display or a touchscreen display 724, and a touchscreen display controller 726.
  • a display or the touchscreen display 724 may include a FPD, an AMOLED display, a TFT LCD, a micro light-emitting diode ( ⁇ , ⁇ ) display, or others.
  • the touchscreen display 724 may include the TFT 114 shown in Figure 1 , the top-gated TFT 214 shown in Figure 2, the top-gated TFT 314 shown in Figure 3, the top-gated TFT 414 shown in Figure 4, or a top-gated TFT formed according to the process 500 shown in Figure 5.
  • Computing device 700 may include other components that may or may not be physically and electrically coupled to the motherboard or fabricated within a SoC die. These other components include, but are not limited to, volatile memory 710 (e.g., dynamic random access memor ' (DRAM), non-volatile memory 712 (e.g., ROM or flash memory), a graphics processing unit 714 (GPU), a digital signal processor (DSP) 716, a crypto processor 742 (e.g., a specialized processor that executes cryptographic algorithms within hardware), a chipset 720, at least one antenna 722 (in some implementations two or more antenna may be used), a battery 730 or other power source, a power amplifier (not shown), a voltage regulator (not shown), a global positioning system (GPS) device 728, a compass, a motion coprocessor or sensors 732 (that may include an accelerometer, a gyroscope, and a compass), a microphone (not shown), a speaker 734, a camera
  • the computing device 700 may incorporate further transmission, telecommunication, or radio functionality not already described herein.
  • the computing device 700 includes a radio that is used to communicate over a distance by modulating and radiating electromagnetic waves in air or space.
  • the computing device 700 includes a transmitter and a receiver (or a transceiver) that is used to communicate over a distance by modulating and radiating electromagnetic waves in air or space.
  • the communications logic unit 708 enables wireless communications for the transfer of data to and from the computing device 700.
  • wireless and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not.
  • the communications logic unit 708 may implement any of a number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Infrared (IR), Near Field Communication (NFC), Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond.
  • the computing device 700 may include a plurality of communications logic units 708.
  • a first communications logic unit 708 may be dedicated to shorter range wireless communications such as Wi-Fi, NFC, and Bluetooth and a second communications logic unit 708 may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.
  • the processor 704 of the computing device 700 includes one or more devices, such as transistors.
  • the term "processor” may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.
  • the communications logic unit 708 may also include one or more devices, such as transistors.
  • the 700 may contain one or more devices, such as DRAM, that are formed in accordance with implementations of the current disclosure, e.g., the memory array 100 shown in Figure 1 , the TFT 114 shown in Figure 1, the top-gated TFT 214 shown in Figure 2, the top-gated TFT 314 shown in Figure 3, the top-gated TFT 414 shown in Figure 4, or a top- gated TFT formed according to the process 500 shown in Figure 5.
  • DRAM dynamic random access memory
  • the computing device 700 may be a laptop computer, a netbook computer, a notebook computer, an ultrabook computer, a smartphone, a dumbphone, a tablet, a tablet/laptop hybrid, a personal digital assistant (PDA), an ultra mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder.
  • the computing device 700 may be any other electronic device that processes data.
  • FIG 8 schematically illustrates a diagram of the top-gated TFT 814 having multiple channel layers including a high mobility layer and a low leakage layer formed in BEOL on a substrate 820, in accordance with some embodiments.
  • the top-gated TFT 814 may be an example of the TFT 114 in Figure 1, an example of the top-gated TFT 214 in Figure 2, or an example of the top-gated TFT 314 in Figure 3.
  • Various layers in the top-gated TFT 814 may be similar to corresponding layers in the top-gated TFT 214 in Figure 2, or the top-gated TFT 314 in Figure 3.
  • the structure of the top-gated TFT 814 may be for illustration purpose only and is not limiting.
  • the top-gated TFT 814 may be formed on the substrate 820, and may include a dielectric layer 821 above the substrate 820, a first channel layer 825 above the dielectric layer 821, and a second channel layer 827 above the first channel layer 825.
  • the first channel layer 825 may include a low leakage material, similar to the first channel layer 225 in Figure 2
  • the second channel layer 827 may include a high mobility ( ⁇ ) material, similar to the second channel layer 227 in Figure 2.
  • the top-gated TFT 814 may include a buffer layer, not shown, between the first channel layer 825 and the second channel layer 827.
  • the top-gated TFT 814 may include a source electrode 826, and a drain electrode 828 above the second channel layer 827.
  • the top-gated TFT 814 may include a gate electrode 822 above the second channel layer 827, between the source electrode 826 and the drain electrode 828.
  • the top-gated TFT 814 may be formed at the BEOL 840.
  • the BEOL 840 may further include a dielectric layer 810, where one or more vias, e.g., a via 818, may be connected to one or more interconnect, e.g., an interconnect 816, and an interconnect 812 within the dielectric layer 810.
  • the interconnect 816 and the interconnect 812 may be of different metal layers at the BEOL 840.
  • the dielectric layer 810 is shown for example only. Although not shown by Figure 8, in various embodiments there may be multiple dielectric layers included in the BEOL 840.
  • the BEOL 840 may be formed on the front-end-of-line (FEOL) 830.
  • the FEOL 830 may include the substrate 820.
  • the FEOL 830 may- include other devices, e.g., a transistor 834.
  • the transistor 834 may be a FEOL transistor, including a source 811, a drain 813, and a gate 815, with a channel 817 between the source 811 and the drain 813 under the gate 815.
  • the transistor 834 may be coupled to interconnects, e.g., the interconnect 812, through a via 819.
  • Example 1 may include a TFT, comprising: a dielectric layer above a substrate; a first channel layer including a first material above the dielectric layer; a second channel layer including a second material above the first channel layer, wherein the first material has a lower leakage than the second material, and the second material has a higher mobility than the first material; a source electrode above the second channel layer; a drain electrode above the second channel layer; and a gate electrode above the second channel layer and between the source electrode and the dram electrode.
  • a TFT comprising: a dielectric layer above a substrate; a first channel layer including a first material above the dielectric layer; a second channel layer including a second material above the first channel layer, wherein the first material has a lower leakage than the second material, and the second material has a higher mobility than the first material; a source electrode above the second channel layer; a drain electrode above the second channel layer; and a gate electrode above the second channel layer and between the source electrode and the dram electrode.
  • Example 2 may include the TFT of example 1 and/or some other examples herein, wherein the first material includes indium, gallium, zinc, and oxide; molybdenum and sulfur; or a group- VI transition metal dichalcogenide.
  • Example 3 may include the TFT of example 1 and/or some other examples herein, wherein the first channel layer has a thickness in a range of 0.5 nanometers (nm) - 20 nm, and the second channel layer has a thickness in a range of 0.5 nm - 20 nm.
  • Example 4 may include the TFT of example 1 and/or some other examples herein, wherein the second material includes indium doped zinc Oxide (IZO), zinc tin oxide (ZTO), amorphous silicon (a-Si), amorphous germanium (a-Ge), low-temperature poly cry stalline silicon (LTPS), transition metal dichalcogenide (TMD), yttrium-doped zinc oxide (YZO), or zinc oxide (ZnO).
  • IZO indium doped zinc Oxide
  • ZTO zinc tin oxide
  • a-Si amorphous silicon
  • a-Ge amorphous germanium
  • LTPS low-temperature poly cry stalline silicon
  • TMD transition metal dichalcogenide
  • YZO yttrium-doped zinc oxide
  • ZnO zinc oxide
  • Example 5 may include the TFT of example 1 and/or some other examples herein, further comprising a buffer layer between the first channel layer and the second channel layer.
  • Example 6 may include the TFT of example 5 and/or some other examples herein, wherein the buffer layer includes indium doped zinc and oxygen
  • Example 7 may include the TFT of any one of examples 1 -6 and/or some other examples herein, further comprising: a gate dielectric layer below the gate electrode and above the second channel layer, wherein the gate dielectric layer includes silicon and oxygen; silicon and nitrogen; yttrium and oxygen; silicon, oxygen, and nitrogen; aluminum and oxygen; hafnium and oxygen; tantalum and oxygen; or titanium and oxygen.
  • Example 8 may include the TFT of any one of examples 1-6 and/or some other examples herein, wherein the TFT is above an interconnect, and the interconnect is above the substrate.
  • Example 9 may include the TFT of any one of examples 1 -6 and/or some other examples herein, further comprising: a first spacer between the source electrode and the gate electrode and above the second channel layer; and a second spacer between the drain electrode and the gate electrode and above the second channel layer.
  • Example 10 may include a method for forming a TFT, the method comprising: forming a dielectric layer above a substrate; forming a first channel layer including a first material above the dielectric layer; forming a second channel layer including a second material above the first channel layer, wherein the first material has a lower leakage than the second material, and the second material has a higher mobility than the first material; forming a source electrode and a drain electrode above the second channel layer; and forming a gate electrode above the second channel layer and between the source electrode and the drain electrode.
  • Example 11 may include the method of example 10 and/or some other examples herein, wherein the first material includes indium, gallium, zinc, and oxide; molybdenum and sulfur; or a group-VI transition metal dichaicogenide.
  • Example 12 may include the method of example 10 and/or some other examples herein, wherein the first channel layer has a thickness in a range of 0.5 nanometers (nm) - 20 nm, and the second channel layer has a thickness in a range of 0.5 nm - 20 nm.
  • Example 13 may include the method of example 10 and/or some other examples herein, wherein the second material includes indium doped zinc Oxide (IZO), zinc tin oxide (ZTO), amorphous silicon (a-Si), amorphous germanium (a-Ge), low-temperature poly crystalline silicon (LTPS), transition metal dichaicogenide (TMD), yttrium-doped zinc oxide (YZO), or zinc oxide (ZnO).
  • Example 14 may include the method of example 10 and/or some other examples herein, further comprising: forming a buffer layer between the first channel layer and the second channel layer.
  • Example 15 may include the method of example 14 and/or some other examples herein, wherein the buffer layer includes indium doped zinc and oxygen.
  • Example 16 may include the method of any one of examples 10-15 and/or some other examples herein, further comprising: forming a gate dielectric layer below the gate electrode and above the second channel layer, wherein the gate dielectric layer includes silicon and oxygen; silicon and nitrogen; yttrium and oxygen; silicon, oxygen, and nitrogen; aluminum and oxygen; hafnium and oxygen; tantalum and oxygen; or titanium and oxygen.
  • Example 17 may include the method of any one of examples 10-15 and/or some other examples herein, wherein the source electrode or the drain electrode includes gold (Au), platinum (Pt), ruthenium (Ru), indium (Ir), titanium (Ti), aluminum (Al), copper (Cu), tantalum (Ta), tungsten (W), in chum-tantalum alloy (Ir-Ta), or indium-tin oxide (ITO).
  • Au gold
  • platinum Pt
  • Ir indium
  • Ti titanium
  • Al aluminum
  • Cu copper
  • Ta tantalum
  • W tungsten
  • Ir-Ta indium-tin oxide
  • Example 18 may include a computing device, comprising: a circuit board; and a memory device coupled to the circuit board and including a memory array, wherein the memory array includes a plurality of memory cells, a memory cell of the plurality of memory cells includes a transistor and a storage cell, and wherein the transistor includes: a first channel layer including a first material above a substrate; a second channel layer including a second material above the first channel lay er, wherein the first material has a lower leakage than the second material, and the second material has a higher mobility than the first matenai; a source electrode above the second channel layer and coupled to a source line of the memory array; a drain electrode above the second channel layer and coupled to a first electrode of the storage cell; and a gate electrode above the second channel layer, between the source electrode and the drain electrode, and coupled to a word line of the memory array; and the storage cell further includes a second electrode coupled to a bit line of the memory array.
  • Example 19 may include the computing device of example 18 and/or some other examples herein, wherein the storage cell further includes a resistive switching matenai layer between the first electrode and the second electrode.
  • Example 20 may include the computing device of example 19 and/or some other examples herein, wherein the resistive switching material layer includes hafnium and oxygen; tantalum and oxygen; hafnium, tantalum and oxygen; tellurium; germanium; silicon; or chalcogenide.
  • the resistive switching material layer includes hafnium and oxygen; tantalum and oxygen; hafnium, tantalum and oxygen; tellurium; germanium; silicon; or chalcogenide.
  • Example 21 may include the computing device of any one of examples 18-20 and/or some other examples herein, wherein the first material includes indium, gallium, zinc, and oxide; molybdenum and sulfur; or a group-VI transition metal di chalcogenide.
  • Example 22 may include the computing device of any one of examples 18-20 and/or some other examples herein, wherein the transistor is above an interconnect, and the interconnect is above a substrate.
  • Example 23 may include the computing device of any one of examples 1 8-20 and/or some other examples herein, wherein the second material includes indium doped zinc Oxide (IZO), zinc tin oxide ( ⁇ ), amorphous silicon (a-Si), amorphous germanium (a-Ge), low-temperature polycrystalline silicon (LTPS), transition metal dichalcogenide (TMD), yttrium-doped zinc oxide (YZO), or zinc oxide (ZnO).
  • IZO indium doped zinc Oxide
  • ⁇ zinc tin oxide
  • a-Si amorphous silicon
  • a-Ge amorphous germanium
  • LTPS low-temperature polycrystalline silicon
  • TMD transition metal dichalcogenide
  • YZO yttrium-doped zinc oxide
  • ZnO zinc oxide
  • Example 24 may include the computing device of any one of examples 18-20 and'or some other examples herein, w herein the transistor further includes a buffer lay er between the first channel layer and the second channel layer.
  • Example 25 may include the computing device of any one of examples 18-20 and-' or some other examples herein, wherein the computing device is a wearable device or a mobile computing device, the wearable device or the mobile computing device including one or more of an antenna, a touchscreen controller, a display, a battery, a processor, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, a Geiger counter, an accelerometer, a gyroscope, a speaker, or a camera coupled with the memory device.
  • the computing device is a wearable device or a mobile computing device, the wearable device or the mobile computing device including one or more of an antenna, a touchscreen controller, a display, a battery, a processor, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, a Geiger counter, an accelerometer, a gyroscope, a speaker, or a camera
  • Various embodiments may include any suitable combination of the above- described embodiments including alternative (or) embodiments of embodiments that are described in conj unctive form (and) above (e.g., the "and” may be “and/or”).
  • some embodiments may include one or more articles of manufacture (e.g., non-transitory computer-readable media) having instructions, stored thereon, that when executed result in actions of any of the above-described embodiments.
  • some embodiments may include apparatuses or systems having any suitable means for carrying out the various operations of the above-described embodiments.

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  • Thin Film Transistor (AREA)

Abstract

Des modes de réalisation de la présente invention décrivent des techniques pour un dispositif à semi-conducteur comprenant un TFT à grille supérieure ayant une mobilité élevée, tout en maintenant la fuite à un niveau faible. Des modes de réalisation peuvent comprendre une couche diélectrique au-dessus d'un substrat et de multiples couches de canal au-dessus de la couche diélectrique. Par exemple, une première couche de canal comprenant un premier matériau peut être au-dessus de la couche diélectrique, et une seconde couche de canal comprenant un second matériau peut être au-dessus de la première couche de canal, le premier matériau pouvant avoir une fuite plus faible que le second matériau, et le second matériau pouvant avoir une mobilité plus élevée que le premier matériau. Des modes de réalisation peuvent en outre comprendre une électrode de source, une électrode de drain et une électrode de grille au-dessus de la seconde couche de canal. D'autres modes de réalisation peuvent être décrits et/ou revendiqués.
PCT/US2017/025503 2017-03-31 2017-03-31 Transistors à couches minces à grille supérieure dotés de multiples couches de canal Ceased WO2018182714A1 (fr)

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CN113437144A (zh) * 2021-05-22 2021-09-24 兰州大学 一种基于二硫化铼的场效应管及其制造方法

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US20080191204A1 (en) * 2007-02-09 2008-08-14 Samsung Electronics Co., Ltd. Thin film transistors and methods of manufacturing the same
US20120012840A1 (en) * 2009-03-31 2012-01-19 Vincent Korthuis Thin-film Transistor (TFT) With A Bi-layer Channel
US20130032784A1 (en) * 2011-08-03 2013-02-07 Ignis Innovation Inc. Thin film transistor including a nanoconductor layer
US20140131698A1 (en) * 2012-11-15 2014-05-15 Samsung Electronics Co., Ltd. Channel layer and thin film transistor including the same

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US20030045037A1 (en) * 2001-08-23 2003-03-06 Ping Mei Thin film transistor memory device
US20080191204A1 (en) * 2007-02-09 2008-08-14 Samsung Electronics Co., Ltd. Thin film transistors and methods of manufacturing the same
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US20130032784A1 (en) * 2011-08-03 2013-02-07 Ignis Innovation Inc. Thin film transistor including a nanoconductor layer
US20140131698A1 (en) * 2012-11-15 2014-05-15 Samsung Electronics Co., Ltd. Channel layer and thin film transistor including the same

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* Cited by examiner, † Cited by third party
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CN113437144A (zh) * 2021-05-22 2021-09-24 兰州大学 一种基于二硫化铼的场效应管及其制造方法

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