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WO2018193760A1 - Semiconductor device and semiconductor device manufacturing method - Google Patents

Semiconductor device and semiconductor device manufacturing method Download PDF

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Publication number
WO2018193760A1
WO2018193760A1 PCT/JP2018/010087 JP2018010087W WO2018193760A1 WO 2018193760 A1 WO2018193760 A1 WO 2018193760A1 JP 2018010087 W JP2018010087 W JP 2018010087W WO 2018193760 A1 WO2018193760 A1 WO 2018193760A1
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WO
WIPO (PCT)
Prior art keywords
solder
semiconductor device
copper
solder material
electrode pattern
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2018/010087
Other languages
French (fr)
Japanese (ja)
Inventor
隆 齊藤
谷口　克己
英司 望月
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
Original Assignee
Fuji Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Electric Co Ltd filed Critical Fuji Electric Co Ltd
Priority to JP2019513270A priority Critical patent/JP7006686B2/en
Publication of WO2018193760A1 publication Critical patent/WO2018193760A1/en
Anticipated expiration legal-status Critical
Priority to JP2021182888A priority patent/JP7509358B2/en
Ceased legal-status Critical Current

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Classifications

    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K1/00—Soldering, e.g. brazing, or unsoldering
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K35/00—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting
    • B23K35/22—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting characterised by the composition or nature of the material
    • B23K35/24—Selection of soldering or welding materials proper
    • B23K35/26—Selection of soldering or welding materials proper with the principal constituent melting at less than 400 degrees C
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/52—Mounting semiconductor bodies in containers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • C—CHEMISTRY; METALLURGY
    • C22—METALLURGY; FERROUS OR NON-FERROUS ALLOYS; TREATMENT OF ALLOYS OR NON-FERROUS METALS
    • C22C—ALLOYS
    • C22C12/00—Alloys based on antimony or bismuth
    • C—CHEMISTRY; METALLURGY
    • C22—METALLURGY; FERROUS OR NON-FERROUS ALLOYS; TREATMENT OF ALLOYS OR NON-FERROUS METALS
    • C22C—ALLOYS
    • C22C13/00—Alloys based on tin
    • C—CHEMISTRY; METALLURGY
    • C22—METALLURGY; FERROUS OR NON-FERROUS ALLOYS; TREATMENT OF ALLOYS OR NON-FERROUS METALS
    • C22C—ALLOYS
    • C22C13/00—Alloys based on tin
    • C22C13/02—Alloys based on tin with antimony or bismuth as the next major constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors

Definitions

  • the present invention relates to a semiconductor device and a method for manufacturing the semiconductor device.
  • the power semiconductor module includes one or a plurality of power semiconductor chips to constitute part or all of the conversion connection, and the power semiconductor chip and the laminated substrate or the metal substrate are electrically insulated. It is a power semiconductor device with Power semiconductor modules are used in motor drive control inverters such as elevators for industrial purposes. Further, in recent years, it has been widely used for in-vehicle motor drive control inverters. In-vehicle inverters are required to have long-term reliability in high-temperature operation because they are reduced in size and weight to improve fuel efficiency and are disposed near the drive motor in the engine room.
  • the structure of a conventional power semiconductor module will be described by taking a general IGBT (Insulated Gate Bipolar Transistor) power semiconductor module structure as an example.
  • IGBT Insulated Gate Bipolar Transistor
  • FIG. 9 is a cross-sectional view showing a configuration of a power semiconductor module having a conventional structure.
  • the power semiconductor module includes a power semiconductor chip 1, an insulating substrate 2, an electrode pattern 3, a conductive plate 9 disposed on the back surface of the insulating substrate 2, a solder material 14, and a heat sink 5. And a cooling body 7, a metal wire 10, an external terminal 11, a terminal case 12, and a sealing material 13.
  • the power semiconductor chip 1 is a semiconductor element such as an IGBT or a diode chip.
  • An electrode pattern 3 and a conductive plate 9 are provided on both surfaces of the insulating substrate 2.
  • the power semiconductor chip 1 is bonded by a solder material 14 that is a bonding material.
  • the heat radiating plate 5 is joined with a solder material 14.
  • the heat radiating plate 5 is joined via a heat radiating grease 6 to a cooling body 7 provided with heat radiating fins.
  • a substrate provided with the electrode pattern 3 on at least one surface of the insulating substrate 2 is called a laminated substrate.
  • a metal wire 10 is connected to the electrode pattern 3 on the upper surface of the power semiconductor chip 1 as a wiring for electrical connection.
  • a metal external terminal 11 for external connection is provided on the upper surface of the electrode pattern 3. Further, in order to protect the power semiconductor chip 1 from insulation, the terminal case 12 is filled with a sealing material 13 such as silicon gel having a low elastic modulus and packaged with a lid (not shown).
  • a sealing material 13 such as silicon gel having a low elastic modulus
  • the in-vehicle power semiconductor module is required to be smaller and lighter than the industrial power semiconductor module due to restrictions on the installation space. Further, since the output power density for driving the motor is increased, the temperature of the semiconductor chip during operation is increased, and the demand for long-term reliability during high-temperature operation is increasing. For this reason, a power semiconductor module structure having high temperature operation and long-term reliability has been demanded.
  • the power semiconductor module having the above configuration is provided with a cooling body 7 provided with heat radiating fins, and heat generated by the power semiconductor chip 1 due to energization is transferred to the heat radiating fins to dissipate heat outside the system. If the surface of the cooling body 7 and the surface of the heat radiating plate 5 are not in close contact with each other, the contact thermal resistance between them increases and the heat dissipation performance decreases.
  • the heat sink 5 and the cooling body 7 are finished so that the surface flatness and the surface roughness are as small as possible.
  • the thermal contact resistance between the heat sink 5 and the cooling body 7 is kept low by applying a thermal compound.
  • the power semiconductor chip 1 and the electrode pattern 3 and the conductive plate 9 and the heat radiating plate 5 are joined using a solder material 14.
  • a solder material 14 For example, Pb (lead) -free solder is bonded to the lower portion of the power semiconductor chip 1 by a paste solder or flux solder containing flux.
  • solder As a Pb-free solder used in a semiconductor module, there is a composite solder having a configuration in which a metal net made of Cu (copper) is sandwiched between two solder foils and used for temperature layer connection such as die bonding of a semiconductor chip. (For example, refer to Patent Document 1).
  • the thermal conductivity of the solder material 14 used for bonding under the power semiconductor chip 1 is 40 to 60 W / m ⁇ K. This value is lower than the thermal conductivity of copper, 390 W / m ⁇ K. For this reason, since the generated heat of the power semiconductor chip 1 due to energization cannot be sufficiently transferred to the electrode pattern 3 and the generated heat cannot reach the radiation fin, there is a problem that the power semiconductor chip 1 cannot be sufficiently cooled. . Moreover, since the thermal conductivity of the solder material 14 is low, the temperature of the solder material 14 itself increases, cracks are generated in the solder material 14, the thermal resistance increases, and the heat dissipation performance further decreases.
  • the present invention can efficiently dissipate heat generated from a power semiconductor chip, and can suppress the occurrence of cracks in solder and increase in thermal resistance.
  • An object is to provide a manufacturing method.
  • a semiconductor device has the following characteristics.
  • a semiconductor device has an assembly structure in which a semiconductor element is mounted on a laminated substrate.
  • a bonding layer for bonding the semiconductor element and the electrode pattern on the laminated substrate includes a metal fiber, and a solder material in which a space between the metal fibers is filled with solder is used.
  • the solder material is used as the bonding layer for bonding the semiconductor element and the wiring for electrical connection between the semiconductor element and the electrode pattern on the multilayer substrate. It is used.
  • the assembly structure further includes a heat sink on which the multilayer substrate is mounted, and a bonding layer that joins the multilayer substrate and the heat sink is the solder. Material is used.
  • the metal fiber included in the solder material is disposed in a central portion, and a predetermined distance from an end portion of the bonding layer.
  • the metal fiber is not arranged.
  • the predetermined distance is not less than 0.1 mm and not more than 1 mm.
  • the metal fiber included in the solder material is disposed on the semiconductor element, the laminated substrate, and the heat dissipation plate side, and the metal fiber A solder having a predetermined thickness is disposed therebetween.
  • the semiconductor device according to the present invention is characterized in that, in the above-described invention, the predetermined thickness is not less than 5 ⁇ m and not more than 20 ⁇ m.
  • the predetermined thickness is 5% to 20% of the thickness of the solder material.
  • the diameter of the metal fiber is equal to or less than the thickness of the solder material.
  • the semiconductor device according to the present invention is characterized in that, in the above-described invention, the metal fiber is a copper fiber.
  • the metal fiber has a diameter of 20 ⁇ m or less in the above-described invention.
  • the semiconductor device according to the present invention is characterized in that, in the above-described invention, the metal fibers have contacts with each other.
  • the semiconductor device according to the present invention is characterized in that, in the above-described invention, the solder does not contain copper.
  • the solder is a Sn—Sb solder containing Ni or Co, a Sn—Bi solder containing Ni or Co, or Sn. -Ag-based solder containing Ni or Co.
  • the semiconductor device according to the present invention is characterized in that, in the above-described invention, the metal fiber is Ni-plated.
  • the semiconductor device according to the present invention is characterized in that, in the above-described invention, the metal fiber is Co-plated.
  • the semiconductor device according to the present invention is characterized in that, in the above-described invention, the space between the metal fibers is filled with a sintered material of Ag or Cu.
  • the semiconductor device according to the present invention is characterized in that, in the above-described invention, the solder material is formed by folding the metal fibers in two or more layers.
  • a semiconductor device manufacturing method has the following characteristics. First, a step of mounting the semiconductor element on the multilayer substrate by joining the electrode pattern on the multilayer substrate and the semiconductor element using a solder material containing metal fibers and filled with solder between the metal fibers I do. A step of assembling the laminated substrate into a laminated assembly is performed. Next, a step of electrically connecting the semiconductor element and the electrode pattern on the laminated substrate is performed. Next, a process of combining the laminated assembly with a resin case is performed.
  • the solder element in the electrically connecting step, is used to electrically connect the semiconductor element and the electrode pattern on the multilayer substrate. It is characterized by being connected.
  • the multilayer substrate in the above-described invention, is joined to a heat radiating plate of the multilayer assembly using the solder material. .
  • the joining portion that joins the power semiconductor element and the electrode pattern is a copper fiber-containing solder material that includes copper fibers and is filled with solder between the copper fibers.
  • the copper fibers have contact points with each other to form a heat path, an increase in thermal resistance can be suppressed even if cracks occur in the solder.
  • the same handling as the conventional one can be performed, and the solder thickness can be controlled more uniformly than the conventional one.
  • the semiconductor device and the method for manufacturing the semiconductor device of the present invention it is possible to efficiently dissipate the heat generated by the power semiconductor chip, and to suppress the occurrence of cracks in the solder and an increase in thermal resistance.
  • FIG. 1 is a cross-sectional view illustrating a configuration of a power semiconductor module according to an embodiment.
  • FIG. 2 is a sectional view showing details of a solder material for joining the power semiconductor chip and the electrode pattern (part 1).
  • FIG. 3 is a sectional view showing details of a solder material for joining the power semiconductor chip and the electrode pattern (part 2).
  • FIG. 4 is a table showing the results of the solder power cycle test according to the embodiment.
  • FIG. 5 is a graph showing the relationship between solder thickness and equivalent thermal conductivity.
  • FIG. 6 is a graph showing the relationship between copper occupancy and equivalent thermal conductivity.
  • FIG. 7 is a cross-sectional view showing an example of a copper fiber-containing solder material.
  • FIG. 8 is a cross-sectional view of a joint portion of an example of a copper fiber-containing solder material.
  • FIG. 9 is a cross-sectional view showing a configuration of a power semiconductor module having a conventional structure.
  • FIG. 1 is a cross-sectional view illustrating a configuration of a power semiconductor module according to an embodiment.
  • the power semiconductor module has a power semiconductor chip 1, an insulating substrate 2, an electrode pattern 3, a joint 4, a heat sink 5, a lead frame wiring 8, and a back surface of the insulating substrate 2.
  • a conductive plate 9 is provided.
  • the power semiconductor chip 1 and the electrode pattern 3 are connected using the lead frame wiring 8, but may be connected using a metal wire 10 as in the conventional structure.
  • the power semiconductor chip 1 is a semiconductor element such as an IGBT or a diode chip.
  • an insulating substrate 2 such as a ceramic substrate that ensures insulation.
  • an electrode pattern made of a conductive plate such as copper (Cu) 3 etc. are provided on the front surface (power semiconductor chip 1 side) and back surface (heat sink 5 side) of an insulating substrate 2 such as a ceramic substrate that ensures insulation.
  • surface of the insulated substrate 2 is set as a laminated substrate.
  • the power semiconductor chip 1 is bonded at the bonding portion 4.
  • a heat radiating plate 5 is joined at the joint 4.
  • the heatsink 5 is joined to a cooling body (not shown) provided with heatsink fins.
  • a conductive plate such as copper on the front surface of the multilayer substrate is referred to as an electrode pattern
  • a conductive plate such as copper on the back surface is referred to as a conductive plate.
  • one end of a lead frame wiring 8 is bonded to the upper surface of the power semiconductor chip 1 (the surface opposite to the surface in contact with the bonding portion 4) at the bonding portion 4 as a wiring for electrical connection.
  • the other end of the lead frame wiring 8 is joined to the electrode pattern 3.
  • the joint portion of the present invention is used in places where a solder material is used in a conventional semiconductor module.
  • the joint 4 is formed of a metal fiber-containing solder material including a metal fiber member.
  • the metal fiber-containing solder material includes a fibrous metal (hereinafter referred to as metal fiber), the metal fibers have contact points with each other to form a heat path, and the metal fibers are filled with solder.
  • the metal is preferably a metal having high thermal conductivity, such as copper.
  • the fibrous copper is referred to as a copper fiber
  • the joint portion 4 is referred to as a copper fiber-containing solder material 4.
  • copper fibers will be described.
  • the fibrous shape means an elongated shape, that is, a length that is extremely large with respect to the diameter. In the embodiment, the diameter of one copper fiber is preferably 20 ⁇ m or less.
  • the length of the copper fiber is preferably 50 ⁇ m or more, more preferably 1 mm or more. This is because the contact length between the copper fibers is increased and the three-dimensional structure is easily obtained when the length is set. Moreover, it is preferable that length is 10 mm or less which is the length of a copper fiber member.
  • the contact point is a point where the copper fiber of the copper fiber-containing solder material 4 is in contact with another copper fiber.
  • the copper fiber member is formed of a plurality of copper fibers.
  • the copper fiber member may have a cloth shape in which copper fibers are woven like a woven fabric, or may be formed in a net shape or a mesh shape. A plurality of these cloth-like or net-like copper fibers may be laminated. Further, a plurality of fibers may be randomly accumulated and laminated to form a sheet. Furthermore, you may pressurize the laminated sheet form and pressure-bond copper fibers. Moreover, it is preferable that these are shape
  • the thickness of the sheet-like copper fiber member is preferably 50 ⁇ m to 200 ⁇ m.
  • the space between the copper fibers may be filled with a sintered material of silver (Ag) or Cu instead of filling with solder.
  • the copper fiber-containing solder material 4 includes copper fibers having contact points and forming a heat path, and is different from a solder material including spherical copper.
  • the heat path is a path for transferring heat generated by the power semiconductor chip or the like.
  • a solder material containing spherical copper has fewer heat paths than copper fibers, has a large thermal resistance, and does not differ in bonding strength from the solder itself.
  • positions metals, such as plate-shaped or foil-shaped copper, in a solder joining strength and heat conductivity like a copper fiber member containing solder are not obtained.
  • the thickness of the solder layer itself does not change in order to obtain a predetermined bonding strength even if a copper plate or the like is arranged in the solder. That is, the thermal resistance does not change.
  • the thermal resistance is lowered and the bonding strength can be improved.
  • the copper fiber-containing solder material 4 is formed by weaving and sintering copper fibers to form a copper fiber member that is folded so that the fibers have contact with each other, and soldering the copper fiber member with solder. Wood may be used. It can be handled as sheet solder by soaking solder in advance. Specifically, a copper fiber-containing solder in which a copper fiber member is impregnated with solder is formed in advance, and the solder can be placed between the materials to be joined and heated to be joined. Further, when assembling the semiconductor module, the solder and the copper fiber member may be disposed between the materials to be joined and heated to be joined. Here, it is preferable that two or more copper fibers are folded.
  • That two or more layers are folded means that there are two or more copper fibers having contacts in the thickness direction (the direction from the power semiconductor chip 1 to the heat sink 5).
  • the copper fiber is folded into three layers.
  • the copper occupancy is higher than that processed into a mesh shape.
  • the copper and the copper fiber member have a total copper content.
  • the copper occupation ratio of the fiber member is 22 to 30% by weight. The higher the copper occupancy ratio of the copper fiber member, the better the thermal conductivity. Accordingly, the copper occupation ratio of the copper fiber members of various forms is preferably 5 to 50% by weight, and more preferably 20 to 30% by weight.
  • the thermal conductivity of the copper fiber-containing solder material 4 is improved, and the generated heat can be efficiently radiated.
  • the copper fiber is contained in the solder, even if a crack is generated in the solder, the crack is detoured and progresses, so that the bonding strength is improved.
  • copper fiber itself has intensity
  • the thickness of the copper fiber containing solder material 4 can be made uniform by using said sheet-like copper fiber member.
  • the power semiconductor chip 1 is displaced when placed on the solder material, or the solder material flows at the time of heat joining, and the thickness of the copper fiber-containing solder material 4 It was difficult to make uniform.
  • the above-described problems can be solved, and the thickness of the copper fiber-containing solder material 4 can be made uniform.
  • the copper fiber-containing solder material 4 is used under the power semiconductor chip 1, that is, in the bonding layer between the power semiconductor chip 1 and the electrode pattern 3 in order to efficiently diffuse the heat generated by the power semiconductor chip 1. Is preferred. Further, the copper fiber-containing solder material 4 may be used for a bonding layer between the conductive plate 9 and the heat sink 5 and a bonding layer between the power semiconductor chip 1 and the lead frame wiring 8.
  • the power semiconductor chip 1 is mounted on the multilayer substrate by bonding the power semiconductor chip 1 to the multilayer substrate using the copper fiber-containing solder material 4.
  • the copper fiber-containing solder material 4 may be prepared by impregnating a copper fiber member with solder before the manufacture of the power semiconductor module.
  • the copper fiber member and the solder may be overlapped, and for example, the copper fiber member may be sandwiched by the solder to produce the copper fiber-containing solder material 4.
  • the power semiconductor chip 1 and the electrode pattern 3 provided on the insulating substrate 2 are electrically connected by the lead frame wiring 8.
  • these are joined to the heat sink 5 to assemble a laminated assembly including the power semiconductor chip 1, the laminated substrate, and the heat sink 5.
  • a resin case is bonded to the laminated assembly with an adhesive such as silicon.
  • the power semiconductor chip 1 and the electrode pattern 3 provided on the insulating substrate 2 may be electrically connected with a metal wire.
  • the electrode pattern 3 and the metal external terminal 11 are connected with a metal wire, and a sealing material such as a hard resin such as epoxy is filled in the resin case.
  • a sealing material such as a hard resin such as epoxy
  • the power semiconductor module according to the embodiment shown in FIG. 1 is completed.
  • the sealing material is not a sealing material such as an epoxy resin, a lid is attached to prevent the sealing material from leaking outside.
  • Copper fiber-containing solder material 4 is disposed on substantially the entire back surface of the power semiconductor chip.
  • 2 and 3 are cross-sectional views showing details of the solder material for joining the power semiconductor chip and the electrode pattern.
  • the copper fiber member 20 is arrange
  • the solder 23 which does not contain copper fiber in the power semiconductor chip 1 or the electrode pattern 3 side.
  • the thickness of each solder 23 is preferably 25 ⁇ m to 100 ⁇ m. This is because, within this range, both joint strength and void reduction can be achieved.
  • the copper fiber member 20 has a structure in which copper fibers are bent in a complicated manner and intersect each other, and depletion exists. At the time of heat bonding, the solder is impregnated in the copper fiber member 20, but it tends to become a void in the vicinity of the depletion. However, it is presumed that the void is easily discharged by separating the predetermined distance d, and as a result, the void is reduced.
  • the distance d is preferably 0.1 mm or more and 1 mm or less regardless of the size of the power semiconductor chip 1. More preferably. It is 0.2 mm or more. This is because if it is shorter than 0.1 mm, a void is generated, the bonding property with the electrode pattern 3 is deteriorated, and the control becomes difficult.
  • the copper fiber member 20 may sandwich the solder 23 inside the copper fiber-containing solder material 4. In this case, there is a layer of solder 23 having a predetermined thickness t between the copper fiber member layers.
  • thermal conductivity improves.
  • the form of FIG. 3 is more thermally conductive than the form of FIG. 2 in which the solder 23 is present on the power semiconductor chip 1 or electrode pattern 3 side.
  • the thickness t of the central part is preferably 5 ⁇ m or more and 20 ⁇ m or less.
  • the thickness t is preferably 5% to 20% in proportion to the thickness of the copper fiber-containing solder material 4.
  • a solder having a specific composition in the solder of the copper fiber-containing solder material effects of joint strength and thermophysical properties can be produced.
  • a Cu-free solder that suppresses diffusion of copper and copper alloy of the copper fiber is preferable.
  • the portion that conducts heat decreases and the thermal conductivity decreases, so that the diffusion of copper and copper alloy can be suppressed.
  • Nickel (Ni), cobalt (Co) Is preferably put into the solder. Note that Cu-free means that Cu is not included except for the degree of impurities.
  • Sn— (5-10) Sb— (0.1-1) Ni, Co solder in which Ni and Co are added to Sn—Sb (antimony) solder (Example 1) Is preferably used.
  • the unit here is% by weight (wt%).
  • Sb is contained in the solder.
  • Ni and Co have the same effect, only Ni or Co may be included.
  • Ni and Co are more preferably contained in the solder in an amount of 0.2 to 0.5% by weight.
  • Sn- (40-70) Bi- (0.1-1) Ni, Co solder (Example 2) in which Ni and Co are added to Sn-Bi (bismuth) solder. Since the solder having this composition is brittle, it cannot normally be used for joining the power semiconductor chip 1. However, it has sufficient strength when used together with the copper fiber member as in the embodiment, so that the power semiconductor chip 1 can be joined. Can be used. Ni and Co are the same as the Sn—Sb solder.
  • Sn— (1-6) Ag— (0.1-1) Ni, Co solder (Example 3) in which Ni and Co are added to Sn—Ag (silver) solder. Ni and Co are the same as the Sn—Sb solder.
  • FIG. 4 is a table showing the results of the power cycle test of the solder according to the embodiment.
  • Sn—Sb—Cu—Ni based solder was also tested as a comparative example.
  • Ni and Co were contained by 0.4 weight% in solder.
  • the number of times the thermal resistance increased by 20% or more from the initial stage was measured by repeatedly turning on / off the power source.
  • Example 1 to Example 3 the thermal resistance did not increase by 20% or more from the initial stage even when the power was turned on / off 100,000 times or more.
  • the thermal resistance did not increase by 20% or more from the initial stage even after repeating 200,000 times or more.
  • the thermal resistance increased by 20% or more from the initial stage after repeating 50,000 times or less.
  • FIG. 5 is a graph showing the relationship between solder thickness and equivalent thermal conductivity.
  • the horizontal axis represents the total thickness of the upper and lower solders, the unit is ⁇ m, the vertical axis is the equivalent thermal conductivity, and the unit is W / m ⁇ K.
  • the equivalent thermal conductivity is a thermal conductivity that is given by considering a component composed of a plurality of materials as one block.
  • the distance d from the edge part of the copper fiber containing solder material 4 to the edge of a copper fiber member was 0.5 mm.
  • the thermal conductivity of solder is 40 W / m ⁇ K
  • the thermal conductivity of copper is 390 W / m ⁇ K
  • the copper occupation ratio of the copper fiber member is 22%
  • the thickness of the copper fiber member is 100 ⁇ m. It is a calculation result in the case.
  • FIG. 6 is a graph showing the relationship between copper occupancy and equivalent thermal conductivity.
  • the horizontal axis represents the copper occupancy, the unit is weight%, the vertical axis is the equivalent thermal conductivity, and the unit is W / m ⁇ K.
  • the copper occupation ratio is the weight% of copper contained in the copper fiber member, and the remainder is the weight of solder.
  • the straight line ⁇ represents the copper occupancy x and the equivalent heat conduction when the upper solder thickness, the copper fiber member thickness, and the lower solder thickness are 10 ⁇ m, 100 ⁇ m, and 10 ⁇ m, respectively.
  • y 3.25x + 6.6667 It is represented by
  • FIG. 7 is a cross-sectional view showing an example of the copper fiber-containing solder material 4.
  • the copper fiber-containing solder material 4 includes a copper fiber portion 22 that is folded so that the copper fibers have contact with each other, and a solder immersion portion 21 in which solder has soaked between the copper fiber members 20. It consists of.
  • FIG. 8 is a cross-sectional view of a joint portion of an example of a copper fiber-containing solder material.
  • the right figure is an enlargement of the center of the left figure.
  • the copper fibers 20 have contact points with each other and the space between the copper fibers 20 is filled with the solder 23.
  • the thermal conductivity of the copper fiber-containing solder material thus prepared is 72.2 W / m ⁇ K in calculation.
  • the thermal conductivity is about 40 W / m ⁇ K only with the Sn—Sb solder, but the thermal conductivity is up to 75.8 W / m ⁇ K with the copper fiber-containing solder material.
  • the laser flash method is to obtain a thermal diffusivity by uniformly heating the surface of a flat sample placed in an adiabatic vacuum and observing a one-dimensional thermal diffusion phenomenon from the front surface to the back surface. Is the method.
  • the joining portion that joins the power semiconductor element and the electrode pattern includes the copper fiber, and the copper fiber-containing portion is filled with the solder between the copper fibers.
  • It is a solder material.
  • the copper fibers have contact points with each other to form a heat path, an increase in thermal resistance can be suppressed even if cracks occur in the solder.
  • the same handling as the conventional one can be performed, and the solder thickness can be controlled more uniformly than the conventional one.
  • the copper fiber-containing solder material has an internal copper fiber arranged in the center, the internal copper fiber is arranged away from the power semiconductor element and the electrode pattern, and the copper fiber-containing solder material has an copper fiber at the end. Is not placed. Thereby, the generated heat of the power semiconductor chip can be dissipated from the central portion where the copper fibers are arranged, the voids can be reduced, and the bondability can be improved.
  • the copper fiber-containing solder material is joined by sandwiching the solder between the copper fibers, and the copper fibers are arranged on the power semiconductor chip or electrode pattern side.
  • thermal conductivity further improves.
  • the thermal conductivity is improved by about 5% as compared with the above result where the copper fiber member is sandwiched between the solder.
  • the copper fiber member and the solder had the same thickness.
  • voids are less likely to occur in the vicinity of the copper fiber.
  • the composition of the solder contained in the copper fiber-containing solder material is Sn- (5-10) Sb- (0.1-1) Ni, Co, Sn- (40-70) Sb- (0.1-1). ) Ni, Co, or Sn- (1-6) Sb- (0.1-1) Ni, Co. Ni and Co can suppress the diffusion of copper and copper alloy of the copper fiber, and can suppress a decrease in thermal conductivity. Furthermore, by using these solders, effects of bonding strength and thermophysical properties can be produced.
  • Ni plating or Co plating may be applied to the copper fiber.
  • Ni and Co can suppress the diffusion of copper and copper alloy of the copper fiber, and can suppress a decrease in thermal conductivity.
  • the semiconductor device and the method for manufacturing the semiconductor device according to the present invention are useful for power conversion devices such as inverters, power supply devices such as various industrial machines, and power semiconductor devices used for automobile igniters. is there.

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Abstract

A semiconductor device comprising an assembly structure in which a semiconductor element (1) is mounted on a laminated substrate. The semiconductor element (1) and an electrode pattern (3) on the laminated substrate are bonded by means of a bonding layer. The bonding layer comprises a solder material which includes metal fibers and in which gaps between the metal fibers are filled with solder. The metal fibers (20) have mutually contacting points. The assembly structure may include a heatsink (5) on which the laminated substrate is mounted.

Description

半導体装置および半導体装置の製造方法Semiconductor device and manufacturing method of semiconductor device

　この発明は、半導体装置および半導体装置の製造方法に関する。 The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device.

　パワー半導体モジュールは、１つまたは複数のパワー半導体チップを内蔵して変換接続の一部または全体を構成し、かつ、パワー半導体チップと積層基板または金属基板との間が電気的に絶縁された構造を持つパワー半導体デバイスである。パワー半導体モジュールは、産業用途としてエレベータなどのモータ駆動制御インバータなどに使われている。さらに近年では、車載用モータ駆動制御インバータに広く用いられるようになっている。車載用インバータでは、燃費向上のため小型・軽量化や、エンジンルーム内の駆動用モータ近傍に配置されることから、高温動作での長期信頼性が求められる。 The power semiconductor module includes one or a plurality of power semiconductor chips to constitute part or all of the conversion connection, and the power semiconductor chip and the laminated substrate or the metal substrate are electrically insulated. It is a power semiconductor device with Power semiconductor modules are used in motor drive control inverters such as elevators for industrial purposes. Further, in recent years, it has been widely used for in-vehicle motor drive control inverters. In-vehicle inverters are required to have long-term reliability in high-temperature operation because they are reduced in size and weight to improve fuel efficiency and are disposed near the drive motor in the engine room.

　従来のパワー半導体モジュールの構造を、一般的なＩＧＢＴ（Ｉｎｓｕｌａｔｅｄ　Ｇａｔｅ　Ｂｉｐｏｌａｒ　Ｔｒａｎｓｉｓｔｏｒ）パワー半導体モジュール構造を例にとって説明する。 The structure of a conventional power semiconductor module will be described by taking a general IGBT (Insulated Gate Bipolar Transistor) power semiconductor module structure as an example.

　図９は、従来構造のパワー半導体モジュールの構成を示す断面図である。図９に示すように、パワー半導体モジュールは、パワー半導体チップ１と、絶縁基板２と、電極パターン３と、絶縁基板２の裏面に配置される導電性板９、はんだ材１４と、放熱板５と、冷却体７と、金属ワイヤ１０と、外部端子１１と、端子ケース１２と、封止材料１３と、を備える。 FIG. 9 is a cross-sectional view showing a configuration of a power semiconductor module having a conventional structure. As shown in FIG. 9, the power semiconductor module includes a power semiconductor chip 1, an insulating substrate 2, an electrode pattern 3, a conductive plate 9 disposed on the back surface of the insulating substrate 2, a solder material 14, and a heat sink 5. And a cooling body 7, a metal wire 10, an external terminal 11, a terminal case 12, and a sealing material 13.

　パワー半導体チップ１は、ＩＧＢＴあるいはダイオードチップ等の半導体素子である。絶縁基板２の両面には、電極パターン３と導電性板９が設けられている。電極パターン３上には、接合材であるはんだ材１４にてパワー半導体チップ１が接合される。裏面の導電性板９上には、はんだ材１４にて放熱板５が接合される。放熱板５は、放熱グリス６を介して放熱フィンが設けられた冷却体７に接合される。なお、絶縁基板２の少なくとも片面に電極パターン３が設けられた基板を積層基板という。また、パワー半導体チップ１の上面には、電気接続用の配線として金属ワイヤ１０が電極パターン３との間を接続している。電極パターン３の上面には、外部接続用の金属外部端子１１が設けられている。また、パワー半導体チップ１の絶縁保護のため、端子ケース１２内には低弾性率のシリコンゲル等の封止材料１３が充填され、蓋（不図示）にてパッケージされている。 The power semiconductor chip 1 is a semiconductor element such as an IGBT or a diode chip. An electrode pattern 3 and a conductive plate 9 are provided on both surfaces of the insulating substrate 2. On the electrode pattern 3, the power semiconductor chip 1 is bonded by a solder material 14 that is a bonding material. On the conductive plate 9 on the back surface, the heat radiating plate 5 is joined with a solder material 14. The heat radiating plate 5 is joined via a heat radiating grease 6 to a cooling body 7 provided with heat radiating fins. A substrate provided with the electrode pattern 3 on at least one surface of the insulating substrate 2 is called a laminated substrate. A metal wire 10 is connected to the electrode pattern 3 on the upper surface of the power semiconductor chip 1 as a wiring for electrical connection. On the upper surface of the electrode pattern 3, a metal external terminal 11 for external connection is provided. Further, in order to protect the power semiconductor chip 1 from insulation, the terminal case 12 is filled with a sealing material 13 such as silicon gel having a low elastic modulus and packaged with a lid (not shown).

　ここで、車載用パワー半導体モジュールは、産業用パワー半導体モジュールに比べ、設置空間の制約から小型、軽量化が求められる。また、モータを駆動するための出力パワー密度が高くなるため、運転時における半導体チップ温度が高くなるとともに、高温動作時の長期信頼性の要求も高まってきている。このため、高温動作・長期信頼性を有したパワー半導体モジュール構造が要求されてきている。 Here, the in-vehicle power semiconductor module is required to be smaller and lighter than the industrial power semiconductor module due to restrictions on the installation space. Further, since the output power density for driving the motor is increased, the temperature of the semiconductor chip during operation is increased, and the demand for long-term reliability during high-temperature operation is increasing. For this reason, a power semiconductor module structure having high temperature operation and long-term reliability has been demanded.

　上記構成のパワー半導体モジュールは、放熱フィンが設けられた冷却体７が取り付けられ、通電に伴うパワー半導体チップ１の発生熱を放熱フィンに伝熱させて系外に放熱するようにしている。冷却体７の表面と放熱板５の表面との間が密着していないと両者間の接触熱抵抗が増して放熱性が低下する。 The power semiconductor module having the above configuration is provided with a cooling body 7 provided with heat radiating fins, and heat generated by the power semiconductor chip 1 due to energization is transferred to the heat radiating fins to dissipate heat outside the system. If the surface of the cooling body 7 and the surface of the heat radiating plate 5 are not in close contact with each other, the contact thermal resistance between them increases and the heat dissipation performance decreases.

　そこで、従来の半導体装置では、高い放熱性能を確保するために放熱板５および冷却体７の表面平坦度、表面粗さができるだけ小さくなるように仕上げ、さらに冷却体７の表面に放熱グリス６等のサーマルコンパウンドを塗布するなどして放熱板５と冷却体７間の接触熱抵抗を低く抑えるようにしている。 Therefore, in the conventional semiconductor device, in order to ensure high heat dissipation performance, the heat sink 5 and the cooling body 7 are finished so that the surface flatness and the surface roughness are as small as possible. The thermal contact resistance between the heat sink 5 and the cooling body 7 is kept low by applying a thermal compound.

　また、パワー半導体チップ１と電極パターン３との間、および、導電性板９と放熱板５との間を、はんだ材１４を用いて接合している。例えば、パワー半導体チップ１の下の接合には、Ｐｂ（鉛）フリーはんだを、フラックス含有したペーストはんだ、または、板はんだで接合している。 Further, the power semiconductor chip 1 and the electrode pattern 3 and the conductive plate 9 and the heat radiating plate 5 are joined using a solder material 14. For example, Pb (lead) -free solder is bonded to the lower portion of the power semiconductor chip 1 by a paste solder or flux solder containing flux.

　半導体モジュールに用いるＰｂフリーはんだとして、半導体チップのダイボンドなどの温度階層接続に用いられる、Ｃｕ（銅）からなる金属網が２枚のはんだ箔によって挟まれて圧着された構成からなる複合はんだがある（例えば、特許文献１参照。）。 As a Pb-free solder used in a semiconductor module, there is a composite solder having a configuration in which a metal net made of Cu (copper) is sandwiched between two solder foils and used for temperature layer connection such as die bonding of a semiconductor chip. (For example, refer to Patent Document 1).

特開２００４－１７４５２２号公報JP 2004-174522 A

　ここで、パワー半導体チップ１の下の接合に用いられるはんだ材１４の熱伝導率は４０～６０Ｗ／ｍ・Ｋである。この値は、銅の熱伝導率３９０Ｗ／ｍ・Ｋと比較すると低い値である。このため、通電に伴うパワー半導体チップ１の発生熱を電極パターン３に十分伝熱できず、発生熱が放熱フィンに到達できないため、パワー半導体チップ１を十分に冷却することができないという課題がある。また、はんだ材１４の熱伝導率が低いため、はんだ材１４自身の温度が上昇し、はんだ材１４中にクラックが発生して熱抵抗が上昇し、放熱性能がさらに低下するという課題がある。 Here, the thermal conductivity of the solder material 14 used for bonding under the power semiconductor chip 1 is 40 to 60 W / m · K. This value is lower than the thermal conductivity of copper, 390 W / m · K. For this reason, since the generated heat of the power semiconductor chip 1 due to energization cannot be sufficiently transferred to the electrode pattern 3 and the generated heat cannot reach the radiation fin, there is a problem that the power semiconductor chip 1 cannot be sufficiently cooled. . Moreover, since the thermal conductivity of the solder material 14 is low, the temperature of the solder material 14 itself increases, cracks are generated in the solder material 14, the thermal resistance increases, and the heat dissipation performance further decreases.

　この発明は、上述した従来技術による問題点を解消するため、パワー半導体チップの発生熱を効率よく放熱でき、はんだにクラックが発生して熱抵抗が上昇することを抑制できる半導体装置および半導体装置の製造方法を提供することを目的とする。 In order to solve the above-described problems caused by the prior art, the present invention can efficiently dissipate heat generated from a power semiconductor chip, and can suppress the occurrence of cracks in solder and increase in thermal resistance. An object is to provide a manufacturing method.

　上述した課題を解決し、本発明の目的を達成するため、この発明にかかる半導体装置は、次の特徴を有する。半導体装置は、半導体素子を積層基板に搭載した組立構造を有する。前記半導体素子と前記積層基板上の電極パターンとを接合する接合層は、金属繊維を含み、前記金属繊維間がはんだで充填されているはんだ材が使用される。 In order to solve the above-described problems and achieve the object of the present invention, a semiconductor device according to the present invention has the following characteristics. A semiconductor device has an assembly structure in which a semiconductor element is mounted on a laminated substrate. A bonding layer for bonding the semiconductor element and the electrode pattern on the laminated substrate includes a metal fiber, and a solder material in which a space between the metal fibers is filled with solder is used.

　また、この発明にかかる半導体装置は、上述した発明において、前記半導体素子と、前記半導体素子と前記積層基板上の電極パターンとの電気接続用の配線とを接合する接合層は、前記はんだ材が使用されることを特徴とする。 Further, in the semiconductor device according to the present invention, in the above-described invention, the solder material is used as the bonding layer for bonding the semiconductor element and the wiring for electrical connection between the semiconductor element and the electrode pattern on the multilayer substrate. It is used.

　また、この発明にかかる半導体装置は、上述した発明において、前記組立構造は、前記積層基板を搭載した放熱板をさらに有し、前記積層基板と前記放熱板とを接合する接合層は、前記はんだ材が使用されることを特徴とする。 In the semiconductor device according to the present invention, in the above-described invention, the assembly structure further includes a heat sink on which the multilayer substrate is mounted, and a bonding layer that joins the multilayer substrate and the heat sink is the solder. Material is used.

　また、この発明にかかる半導体装置は、上述した発明において、前記接合層では、前記はんだ材に含まれる前記金属繊維は中央部に配置され、前記接合層の端部から所定の距離の間、前記金属繊維が配置されないことを特徴とする。 Further, in the semiconductor device according to the present invention, in the above-described invention, in the bonding layer, the metal fiber included in the solder material is disposed in a central portion, and a predetermined distance from an end portion of the bonding layer. The metal fiber is not arranged.

　また、この発明にかかる半導体装置は、上述した発明において、前記所定の距離は、０．１ｍｍ以上１ｍｍ以下であることを特徴とする。 In the semiconductor device according to the present invention, the predetermined distance is not less than 0.1 mm and not more than 1 mm.

　また、この発明にかかる半導体装置は、上述した発明において、前記接合層では、前記はんだ材に含まれる前記金属繊維は、前記半導体素子、前記積層基板および前記放熱板側に配置され、前記金属繊維間に、所定の厚さのはんだが配置されることを特徴とする。 In the semiconductor device according to the present invention, in the above-described invention, in the bonding layer, the metal fiber included in the solder material is disposed on the semiconductor element, the laminated substrate, and the heat dissipation plate side, and the metal fiber A solder having a predetermined thickness is disposed therebetween.

　また、この発明にかかる半導体装置は、上述した発明において、前記所定の厚さは、５μｍ以上２０μｍ以下であることを特徴とする。 The semiconductor device according to the present invention is characterized in that, in the above-described invention, the predetermined thickness is not less than 5 μm and not more than 20 μm.

　また、この発明にかかる半導体装置は、上述した発明において、前記所定の厚さは、前記はんだ材の厚さの５％から２０％であることを特徴とする。 In the semiconductor device according to the present invention, the predetermined thickness is 5% to 20% of the thickness of the solder material.

　また、この発明にかかる半導体装置は、上述した発明において、前記金属繊維の直径は、前記はんだ材の厚さ以下であることを特徴とする。 Further, in the semiconductor device according to the present invention as set forth in the invention described above, the diameter of the metal fiber is equal to or less than the thickness of the solder material.

　また、この発明にかかる半導体装置は、上述した発明において、前記金属繊維は、銅繊維であることを特徴とする。 The semiconductor device according to the present invention is characterized in that, in the above-described invention, the metal fiber is a copper fiber.

　また、この発明にかかる半導体装置は、上述した発明において、前記金属繊維の直径は、２０μｍ以下であることを特徴とする。 In the semiconductor device according to the present invention, the metal fiber has a diameter of 20 μm or less in the above-described invention.

　また、この発明にかかる半導体装置は、上述した発明において、前記金属繊維は、互いに接点を有することを特徴とする。 Further, the semiconductor device according to the present invention is characterized in that, in the above-described invention, the metal fibers have contacts with each other.

　また、この発明にかかる半導体装置は、上述した発明において、前記はんだは銅を含まないことを特徴とする。 The semiconductor device according to the present invention is characterized in that, in the above-described invention, the solder does not contain copper.

　また、この発明にかかる半導体装置は、上述した発明において、前記はんだは、Ｓｎ－Ｓｂ系はんだにＮｉまたはＣｏを含有したもの、Ｓｎ－Ｂｉ系はんだにＮｉまたはＣｏを含有したもの、または、Ｓｎ－Ａｇ系はんだにＮｉまたはＣｏを含有したものであることを特徴とする。 In the semiconductor device according to the present invention, in the above-described invention, the solder is a Sn—Sb solder containing Ni or Co, a Sn—Bi solder containing Ni or Co, or Sn. -Ag-based solder containing Ni or Co.

　また、この発明にかかる半導体装置は、上述した発明において、前記金属繊維は、Ｎｉめっきがされていることを特徴とする。 The semiconductor device according to the present invention is characterized in that, in the above-described invention, the metal fiber is Ni-plated.

　また、この発明にかかる半導体装置は、上述した発明において、前記金属繊維は、Ｃｏめっきがされていることを特徴とする。 Further, the semiconductor device according to the present invention is characterized in that, in the above-described invention, the metal fiber is Co-plated.

　また、この発明にかかる半導体装置は、上述した発明において、前記金属繊維間は、ＡｇまたはＣｕの焼結材で充填されていることを特徴とする。 Further, the semiconductor device according to the present invention is characterized in that, in the above-described invention, the space between the metal fibers is filled with a sintered material of Ag or Cu.

　また、この発明にかかる半導体装置は、上述した発明において、前記はんだ材は、前記金属繊維が２層以上折り重ねられていることを特徴とする。 Further, the semiconductor device according to the present invention is characterized in that, in the above-described invention, the solder material is formed by folding the metal fibers in two or more layers.

　上述した課題を解決し、本発明の目的を達成するため、この発明にかかる半導体装置の製造方法は、次の特徴を有する。まず、金属繊維を含み、前記金属繊維間がはんだで充填されているはんだ材を用いて、積層基板上の電極パターンと半導体素子とを接合して、前記積層基板に前記半導体素子を搭載する工程を行う。前記積層基板を積層組立体に組み立てる工程を行う。次に、前記半導体素子と、前記積層基板上の電極パターンとを、電気的に接続する工程を行う。次に、前記積層組立体に、樹脂ケースを組み合わせる工程を行う。 In order to solve the above-described problems and achieve the object of the present invention, a semiconductor device manufacturing method according to the present invention has the following characteristics. First, a step of mounting the semiconductor element on the multilayer substrate by joining the electrode pattern on the multilayer substrate and the semiconductor element using a solder material containing metal fibers and filled with solder between the metal fibers I do. A step of assembling the laminated substrate into a laminated assembly is performed. Next, a step of electrically connecting the semiconductor element and the electrode pattern on the laminated substrate is performed. Next, a process of combining the laminated assembly with a resin case is performed.

　また、この発明にかかる半導体装置の製造方法は、上述した発明において、前記電気的に接続する工程では、前記はんだ材を用いて、前記半導体素子と、前記積層基板上の電極パターンとを、電気的に接続することを特徴とする。 In the method for manufacturing a semiconductor device according to the present invention, in the above-described invention, in the electrically connecting step, the solder element is used to electrically connect the semiconductor element and the electrode pattern on the multilayer substrate. It is characterized by being connected.

　また、この発明にかかる半導体装置の製造方法は、上述した発明において、前記組み立てる工程では、前記積層基板を、前記はんだ材を用いて、前記積層組立体の放熱板に接合することを特徴とする。 In the semiconductor device manufacturing method according to the present invention, in the above-described invention, in the assembling step, the multilayer substrate is joined to a heat radiating plate of the multilayer assembly using the solder material. .

　上述した発明によれば、パワー半導体素子と電極パターンとを接合する接合部は、銅繊維を含み、銅繊維間がはんだで充填されている銅繊維含有はんだ材である。これにより、熱伝導率が、フラックスを含有したペーストはんだや板はんだより向上するため、パワー半導体チップの発生熱を効率よく放熱できる。また、はんだの中に銅繊維が含まれているため、はんだ中にクラックが発生しても、クラックが迂回して進展するため、はんだの寿命が向上する。さらに、はんだの中に銅繊維が含まれているため、フィレットが発生することを防止でき、はんだが脇にはみ出ることが少なくなる。また、銅繊維が互いに接点を有し熱パスを形成しているため、はんだにクラックが発生しても熱抵抗の上昇を抑制できる。また、銅繊維部材に、はんだをしみこませて板はんだとすることで、従来と同様の取り扱いができ、従来よりもはんだ厚さを均一に制御することが可能になる。 According to the above-described invention, the joining portion that joins the power semiconductor element and the electrode pattern is a copper fiber-containing solder material that includes copper fibers and is filled with solder between the copper fibers. Thereby, since heat conductivity improves from the paste solder and board solder containing a flux, the heat generated by a power semiconductor chip can be efficiently radiated. Moreover, since the copper fiber is contained in the solder, even if a crack occurs in the solder, the crack progresses in a detour, so the life of the solder is improved. Furthermore, since the copper fiber is contained in the solder, it is possible to prevent the fillet from being generated, and the solder is less likely to protrude to the side. Moreover, since the copper fibers have contact points with each other to form a heat path, an increase in thermal resistance can be suppressed even if cracks occur in the solder. Moreover, by making solder into a copper fiber member and making it into a sheet solder, the same handling as the conventional one can be performed, and the solder thickness can be controlled more uniformly than the conventional one.

　本発明にかかる半導体装置および半導体装置の製造方法によれば、パワー半導体チップの発生熱を効率よく放熱でき、はんだにクラックが発生して熱抵抗が上昇することを抑制できるという効果を奏する。 According to the semiconductor device and the method for manufacturing the semiconductor device of the present invention, it is possible to efficiently dissipate the heat generated by the power semiconductor chip, and to suppress the occurrence of cracks in the solder and an increase in thermal resistance.

図１は、実施の形態にかかるパワー半導体モジュールの構成を示す断面図である。FIG. 1 is a cross-sectional view illustrating a configuration of a power semiconductor module according to an embodiment. 図２は、パワー半導体チップと電極パターンを接合するはんだ材の詳細を示す断面図である（その１）。FIG. 2 is a sectional view showing details of a solder material for joining the power semiconductor chip and the electrode pattern (part 1). 図３は、パワー半導体チップと電極パターンを接合するはんだ材の詳細を示す断面図である（その２）。FIG. 3 is a sectional view showing details of a solder material for joining the power semiconductor chip and the electrode pattern (part 2). 図４は、実施の形態にかかるはんだのパワーサイクル試験の結果を示す表である。FIG. 4 is a table showing the results of the solder power cycle test according to the embodiment. 図５は、はんだ厚と等価熱伝導率との関係を示すグラフである。FIG. 5 is a graph showing the relationship between solder thickness and equivalent thermal conductivity. 図６は、銅占有率と等価熱伝導率との関係を示すグラフである。FIG. 6 is a graph showing the relationship between copper occupancy and equivalent thermal conductivity. 図７は、銅繊維含有はんだ材の実施例を示す断面図である。FIG. 7 is a cross-sectional view showing an example of a copper fiber-containing solder material. 図８は、銅繊維含有はんだ材の実施例の接合部の断面図である。FIG. 8 is a cross-sectional view of a joint portion of an example of a copper fiber-containing solder material. 図９は、従来構造のパワー半導体モジュールの構成を示す断面図である。FIG. 9 is a cross-sectional view showing a configuration of a power semiconductor module having a conventional structure.

　以下に添付図面を参照して、この発明にかかる半導体装置および半導体装置の製造方法の好適な実施の形態を詳細に説明する。図１は、実施の形態にかかるパワー半導体モジュールの構成を示す断面図である。 Hereinafter, preferred embodiments of a semiconductor device and a method for manufacturing the semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings. FIG. 1 is a cross-sectional view illustrating a configuration of a power semiconductor module according to an embodiment.

（実施の形態）
　図１に示すように、パワー半導体モジュールは、パワー半導体チップ１と、絶縁基板２と、電極パターン３と、接合部４と、放熱板５と、リードフレーム配線８と、絶縁基板２の裏面に配置される導電性板９、を備える。ここでは、従来構造のパワー半導体モジュールと同様のため、冷却体７、外部端子１１、端子ケース１２、封止材料１３等の記載は省略する。図１では、リードフレーム配線８を用いて、パワー半導体チップ１と電極パターン３とを接続しているが、従来構造と同様に金属ワイヤ１０を用いて接続してもよい。 (Embodiment)
As shown in FIG. 1, the power semiconductor module has a power semiconductor chip 1, an insulating substrate 2, an electrode pattern 3, a joint 4, a heat sink 5, a lead frame wiring 8, and a back surface of the insulating substrate 2. A conductive plate 9 is provided. Here, since it is the same as that of the power semiconductor module of the conventional structure, description of the cooling body 7, the external terminal 11, the terminal case 12, the sealing material 13, etc. is abbreviate | omitted. In FIG. 1, the power semiconductor chip 1 and the electrode pattern 3 are connected using the lead frame wiring 8, but may be connected using a metal wire 10 as in the conventional structure.

　パワー半導体チップ１は、ＩＧＢＴあるいはダイオードチップ等の半導体素子である。絶縁性を確保するセラミック基板等の絶縁基板２のおもて面（パワー半導体チップ１側）および裏面（放熱板５側）には、銅（Ｃｕ）等の導電性の板などからなる電極パターン３等が設けられている。なお、絶縁基板２の少なくとも片面に電極パターン３が設けられた基板を積層基板とする。電極パターン３上には、接合部４にてパワー半導体チップ１が接合される。裏面の導電性板９上には、接合部４にて放熱板５が接合される。放熱板５は、放熱フィンが設けられた冷却体（不図示）に接合される。なお、積層基板のおもて面の銅などの導電性板を電極パターンといい、裏面の銅等の導電性板を導電性板という。また、パワー半導体チップ１の上面（接合部４と接する面と反対側の面）には、電気接続用の配線としてリードフレーム配線８の一端が接合部４にて接合される。リードフレーム配線８の他端は、電極パターン３と接合される。また、上述の箇所以外においても、従来の半導体モジュールにおいてはんだ材が用いられる箇所において、本発明の接合部は用いられる。 The power semiconductor chip 1 is a semiconductor element such as an IGBT or a diode chip. On the front surface (power semiconductor chip 1 side) and back surface (heat sink 5 side) of an insulating substrate 2 such as a ceramic substrate that ensures insulation, an electrode pattern made of a conductive plate such as copper (Cu) 3 etc. are provided. In addition, the board | substrate with which the electrode pattern 3 was provided in the at least single side | surface of the insulated substrate 2 is set as a laminated substrate. On the electrode pattern 3, the power semiconductor chip 1 is bonded at the bonding portion 4. On the conductive plate 9 on the back surface, a heat radiating plate 5 is joined at the joint 4. The heatsink 5 is joined to a cooling body (not shown) provided with heatsink fins. Note that a conductive plate such as copper on the front surface of the multilayer substrate is referred to as an electrode pattern, and a conductive plate such as copper on the back surface is referred to as a conductive plate. In addition, one end of a lead frame wiring 8 is bonded to the upper surface of the power semiconductor chip 1 (the surface opposite to the surface in contact with the bonding portion 4) at the bonding portion 4 as a wiring for electrical connection. The other end of the lead frame wiring 8 is joined to the electrode pattern 3. In addition to the above-mentioned places, the joint portion of the present invention is used in places where a solder material is used in a conventional semiconductor module.

　接合部４は、金属繊維部材を含んだ金属繊維含有はんだ材により形成される。金属繊維含有はんだ材は、繊維状の金属（以下、金属繊維と称する）を含み、その金属繊維が互いに接点を有し熱パスを形成し、さらに、金属繊維間がはんだで充填されている。金属としては、熱伝導率の高い金属、例えば銅であることが好ましい。以下、繊維状の銅を銅繊維と称し、接合部４を銅繊維含有はんだ材４と称する。以降は銅繊維について説明する。なお、ここで、繊維状とは、細長い形状、つまり直径に対して長さがきわめて大きいものをいう。実施の形態では、１本の銅繊維の直径が２０μｍ以下であることが好ましい。また、銅繊維の長さは５０μｍ以上が好ましく、１ｍｍ以上がより好ましい。前記長さであると、銅繊維間の接触がより多くなり、３次元的な構造になり易いからである。また、長さは銅繊維部材の長さ程度である１０ｍｍ以下であることが好ましい。 The joint 4 is formed of a metal fiber-containing solder material including a metal fiber member. The metal fiber-containing solder material includes a fibrous metal (hereinafter referred to as metal fiber), the metal fibers have contact points with each other to form a heat path, and the metal fibers are filled with solder. The metal is preferably a metal having high thermal conductivity, such as copper. Hereinafter, the fibrous copper is referred to as a copper fiber, and the joint portion 4 is referred to as a copper fiber-containing solder material 4. Hereinafter, copper fibers will be described. Here, the fibrous shape means an elongated shape, that is, a length that is extremely large with respect to the diameter. In the embodiment, the diameter of one copper fiber is preferably 20 μm or less. The length of the copper fiber is preferably 50 μm or more, more preferably 1 mm or more. This is because the contact length between the copper fibers is increased and the three-dimensional structure is easily obtained when the length is set. Moreover, it is preferable that length is 10 mm or less which is the length of a copper fiber member.

　また、接点とは、銅繊維含有はんだ材４の銅繊維が、他の銅繊維と接触している点のことである。銅繊維部材は、複数の銅繊維により形成される。銅繊維部材は、織物のように銅繊維が織られた布状でもよく、網状またはメッシュ状に形成されても良い。これらの、布状または網状の銅繊維が複数枚積層されてもよい。また、複数の繊維がランダムに集積され積層されてシート状に形成されていてもよい。さらに、積層されたシート状を加圧し、銅繊維同士を圧着してもよい。また、これらはシート状に成形されていることが好ましい。シート状の銅繊維部材の厚さは、５０μｍから２００μｍが好ましい。５０μｍより厚くすると所定の接合強度を得られるためである。また、２００μｍ以上にすると熱抵抗自体が増加するとともに、ボイドが発生し、熱伝導率が低下し、熱抵抗を増加させてしまう。なお、銅繊維間は、はんだで充填するのではなく、銀（Ａｇ）またはＣｕの焼結材で充填してもよい。 Also, the contact point is a point where the copper fiber of the copper fiber-containing solder material 4 is in contact with another copper fiber. The copper fiber member is formed of a plurality of copper fibers. The copper fiber member may have a cloth shape in which copper fibers are woven like a woven fabric, or may be formed in a net shape or a mesh shape. A plurality of these cloth-like or net-like copper fibers may be laminated. Further, a plurality of fibers may be randomly accumulated and laminated to form a sheet. Furthermore, you may pressurize the laminated sheet form and pressure-bond copper fibers. Moreover, it is preferable that these are shape | molded in the sheet form. The thickness of the sheet-like copper fiber member is preferably 50 μm to 200 μm. This is because if the thickness is greater than 50 μm, a predetermined bonding strength can be obtained. On the other hand, when the thickness is 200 μm or more, the thermal resistance itself increases, voids are generated, the thermal conductivity is lowered, and the thermal resistance is increased. The space between the copper fibers may be filled with a sintered material of silver (Ag) or Cu instead of filling with solder.

　このように、実施の形態の銅繊維含有はんだ材４は、互いに接点を有し熱パスを形成した銅繊維を含み、球状の銅を含んだはんだ材とは異なる。なお、熱パスとは、パワー半導体チップ等の発生熱を伝熱するための経路である。球状の銅を含んだはんだ材は、銅繊維に比べて熱パスが少なく、熱抵抗は大きく、接合強度もはんだ自体と変わらない。なお、単に板状あるいは箔状の銅などの金属をはんだ中に配置しても、銅繊維部材含有はんだのような接合強度や熱伝導率は得られない。銅板等をはんだ中に配置しても、所定の接合強度を得るためには、はんだ層自体の厚さは変わらないからである。つまり、熱抵抗は変わらない。３次元的な銅繊維間にはんだが含浸することにより、熱抵抗は低下し、さらに接合強度も向上することができる。 As described above, the copper fiber-containing solder material 4 according to the embodiment includes copper fibers having contact points and forming a heat path, and is different from a solder material including spherical copper. The heat path is a path for transferring heat generated by the power semiconductor chip or the like. A solder material containing spherical copper has fewer heat paths than copper fibers, has a large thermal resistance, and does not differ in bonding strength from the solder itself. In addition, even if it arrange | positions metals, such as plate-shaped or foil-shaped copper, in a solder, joining strength and heat conductivity like a copper fiber member containing solder are not obtained. This is because the thickness of the solder layer itself does not change in order to obtain a predetermined bonding strength even if a copper plate or the like is arranged in the solder. That is, the thermal resistance does not change. When the solder is impregnated between the three-dimensional copper fibers, the thermal resistance is lowered and the bonding strength can be improved.

　銅繊維含有はんだ材４は、銅繊維を織り込み、焼結させて繊維間が互いに接点を有するよう折り重ねられている銅繊維部材を形成し、銅繊維部材に、はんだをしみこませて形成したはんだ材でもよい。予め、はんだをしみこませることで、板はんだとして取り扱うことができる。具体的には、予め、銅繊維部材にはんだを含浸させた銅繊維含有はんだを形成し、それを被接合材間に配置し、加熱し接合することができる。また、半導体モジュールを組み立てる際に、はんだと銅繊維部材を被接合材の間に配置して、加熱し接合してもよい。ここで、銅繊維は２層以上折り重ねられていることが好ましい。２層以上折り重ねられているとは、厚み方向（パワー半導体チップ１から放熱板５への方向）に互いに接点を有する銅繊維が２本以上存在することである。図１の例では、銅繊維は３層に折り重ねられている。ここで、銅が繊維状で折り重なっているために、メッシュ状に加工したものより、銅占有率が高く、例えば、銅繊維含有はんだ材４では、はんだと銅繊維部材の総量に対して、銅繊維部材の銅占有率は２２～３０重量％である。銅繊維部材の銅占有率は高い方が熱伝導性が優れるが、はんだの含浸量が少ないと接合性が悪くなる。従って、様々な形態の銅繊維部材の銅占有率は５～５０重量％が好ましく、更に好ましくは、２０～３０重量％である。 The copper fiber-containing solder material 4 is formed by weaving and sintering copper fibers to form a copper fiber member that is folded so that the fibers have contact with each other, and soldering the copper fiber member with solder. Wood may be used. It can be handled as sheet solder by soaking solder in advance. Specifically, a copper fiber-containing solder in which a copper fiber member is impregnated with solder is formed in advance, and the solder can be placed between the materials to be joined and heated to be joined. Further, when assembling the semiconductor module, the solder and the copper fiber member may be disposed between the materials to be joined and heated to be joined. Here, it is preferable that two or more copper fibers are folded. That two or more layers are folded means that there are two or more copper fibers having contacts in the thickness direction (the direction from the power semiconductor chip 1 to the heat sink 5). In the example of FIG. 1, the copper fiber is folded into three layers. Here, since copper is fibrous and folded, the copper occupancy is higher than that processed into a mesh shape. For example, in the copper fiber-containing solder material 4, the copper and the copper fiber member have a total copper content. The copper occupation ratio of the fiber member is 22 to 30% by weight. The higher the copper occupancy ratio of the copper fiber member, the better the thermal conductivity. Accordingly, the copper occupation ratio of the copper fiber members of various forms is preferably 5 to 50% by weight, and more preferably 20 to 30% by weight.

　このように、銅繊維部材がはんだ中に配置されることにより、銅繊維含有はんだ材４の熱伝導率は向上し、発生熱を効率よく放熱することができる。また、はんだの中に銅繊維が含まれているため、はんだ中にクラックが発生しても、クラックが迂回して進展するため、接合強度は向上する。また、銅繊維自体に強度があるため、接合強度は高い。ひいては、はんだの寿命が向上する。また、上記のシート状の銅繊維部材を用いることにより、銅繊維含有はんだ材４の厚さを均一にすることができる。従来のはんだ材のみの接合の場合、パワー半導体チップ１をはんだ材上に配置する際に位置ずれをおこしたり、加熱接合時にはんだ材が流れてしまったりし、銅繊維含有はんだ材４の厚さを均一にすることが難しかった。しかし、銅繊維部材を導入することで、上記の不具合が解消され、銅繊維含有はんだ材４の厚さを均一にすることができる。 Thus, by arranging the copper fiber member in the solder, the thermal conductivity of the copper fiber-containing solder material 4 is improved, and the generated heat can be efficiently radiated. Moreover, since the copper fiber is contained in the solder, even if a crack is generated in the solder, the crack is detoured and progresses, so that the bonding strength is improved. Moreover, since copper fiber itself has intensity | strength, joining strength is high. As a result, the life of the solder is improved. Moreover, the thickness of the copper fiber containing solder material 4 can be made uniform by using said sheet-like copper fiber member. In the case of joining only a conventional solder material, the power semiconductor chip 1 is displaced when placed on the solder material, or the solder material flows at the time of heat joining, and the thickness of the copper fiber-containing solder material 4 It was difficult to make uniform. However, by introducing the copper fiber member, the above-described problems can be solved, and the thickness of the copper fiber-containing solder material 4 can be made uniform.

　また、銅繊維含有はんだ材４は、パワー半導体チップ１の発生熱を効率よく拡散するために、パワー半導体チップ１の下、つまり、パワー半導体チップ１と電極パターン３との接合層に使用することが好ましい。また、銅繊維含有はんだ材４は、導電性板９と放熱板５との接合層、パワー半導体チップ１とリードフレーム配線８との接合層に使用してもよい。 Further, the copper fiber-containing solder material 4 is used under the power semiconductor chip 1, that is, in the bonding layer between the power semiconductor chip 1 and the electrode pattern 3 in order to efficiently diffuse the heat generated by the power semiconductor chip 1. Is preferred. Further, the copper fiber-containing solder material 4 may be used for a bonding layer between the conductive plate 9 and the heat sink 5 and a bonding layer between the power semiconductor chip 1 and the lead frame wiring 8.

　パワー半導体モジュールの製造方法では、まず、銅繊維含有はんだ材４を用いて、パワー半導体チップ１を積層基板に接合することで、積層基板にパワー半導体チップ１を実装する。ここで、銅繊維含有はんだ材４は、パワー半導体モジュールの製造より前に、銅繊維部材に、はんだをしみこませて作成しておいてもよい。また、パワー半導体チップ１を積層基板に接合する際、銅繊維部材とはんだを重ねて、例えば、銅繊維部材をはんだで挟むようにして、銅繊維含有はんだ材４を作成するようにしてもよい。 In the method for manufacturing a power semiconductor module, first, the power semiconductor chip 1 is mounted on the multilayer substrate by bonding the power semiconductor chip 1 to the multilayer substrate using the copper fiber-containing solder material 4. Here, the copper fiber-containing solder material 4 may be prepared by impregnating a copper fiber member with solder before the manufacture of the power semiconductor module. Moreover, when joining the power semiconductor chip 1 to the laminated substrate, the copper fiber member and the solder may be overlapped, and for example, the copper fiber member may be sandwiched by the solder to produce the copper fiber-containing solder material 4.

　次に、パワー半導体チップ１と、絶縁基板２上に設けられた電極パターン３とを、リードフレーム配線８で電気的に接続する。次に、銅繊維含有はんだ材４を用いて、これらを放熱板５に接合して、パワー半導体チップ１、積層基板および放熱板５からなる積層組立体を組み立てる。この積層組立体に樹脂ケースをシリコンなどの接着剤で接着する。なお、金属ワイヤで、パワー半導体チップ１と、絶縁基板２上に設けられた電極パターン３と、を電気的に接続してもよい。 Next, the power semiconductor chip 1 and the electrode pattern 3 provided on the insulating substrate 2 are electrically connected by the lead frame wiring 8. Next, using a copper fiber-containing solder material 4, these are joined to the heat sink 5 to assemble a laminated assembly including the power semiconductor chip 1, the laminated substrate, and the heat sink 5. A resin case is bonded to the laminated assembly with an adhesive such as silicon. The power semiconductor chip 1 and the electrode pattern 3 provided on the insulating substrate 2 may be electrically connected with a metal wire.

　次に、金属ワイヤで電極パターン３と金属外部端子１１との間を接続し、樹脂ケース内にエポキシなどの硬質樹脂等の封止材料を充填する。これにより、図１に示す実施の形態にかかるパワー半導体モジュールが完成する。なお、封止材料がエポキシ樹脂等の封止材料でない場合、封止材料が外に漏れないようにするため、蓋を取り付けるようにする。 Next, the electrode pattern 3 and the metal external terminal 11 are connected with a metal wire, and a sealing material such as a hard resin such as epoxy is filled in the resin case. Thereby, the power semiconductor module according to the embodiment shown in FIG. 1 is completed. When the sealing material is not a sealing material such as an epoxy resin, a lid is attached to prevent the sealing material from leaking outside.

　次に、銅繊維含有はんだ材４について説明する。パワー半導体チップの裏面のほぼ全面に銅繊維含有はんだ材４が配置される。図２、図３は、パワー半導体チップと電極パターンを接合するはんだ材の詳細を示す断面図である。図２に示すように、銅繊維含有はんだ材４の内部に銅繊維部材２０を中央部に配置される。また、銅繊維を含まないはんだ２３をパワー半導体チップ１や電極パターン３側に配置してもよい。この場合のそれぞれのはんだ２３の厚さは、２５μｍから１００μｍが好ましい。この範囲にすることで、接合強度とボイドの低減を両立できるからである。これは、パワー半導体チップ１の発生熱が、銅繊維部材２０が配置された中央部から放熱されるためである。ここで、銅繊維部材２０を銅繊維含有はんだ材４の端部から所定の距離ｄだけ離すことで、ボイドを低減し、接合性も向上させることができる。銅繊維部材２０は銅繊維が複雑に折れ曲がり、互いに交差した構造で、空乏が存在する。加熱接合する際に、はんだは、銅繊維部材２０中に含浸するが、前記空乏近傍でボイドになりやすい。しかし、所定の距離ｄだけ離すことで、ボイドが排出されやすく、結果としてボイドが低減されると推定される。距離ｄは、パワー半導体チップ１のサイズに関係なく、０．１ｍｍ以上１ｍｍ以下であることが好ましい。より好ましくは。０．２ｍｍ以上である。これは、０．１ｍｍより短いと、ボイドが生じ、電極パターン３との接合性が悪化し、制御も困難になるためである。 Next, the copper fiber-containing solder material 4 will be described. Copper fiber-containing solder material 4 is disposed on substantially the entire back surface of the power semiconductor chip. 2 and 3 are cross-sectional views showing details of the solder material for joining the power semiconductor chip and the electrode pattern. As shown in FIG. 2, the copper fiber member 20 is arrange | positioned in the center part inside the copper fiber containing solder material 4. As shown in FIG. Moreover, you may arrange | position the solder 23 which does not contain copper fiber in the power semiconductor chip 1 or the electrode pattern 3 side. In this case, the thickness of each solder 23 is preferably 25 μm to 100 μm. This is because, within this range, both joint strength and void reduction can be achieved. This is because the heat generated by the power semiconductor chip 1 is dissipated from the central portion where the copper fiber member 20 is disposed. Here, by separating the copper fiber member 20 from the end portion of the copper fiber-containing solder material 4 by a predetermined distance d, voids can be reduced and bondability can be improved. The copper fiber member 20 has a structure in which copper fibers are bent in a complicated manner and intersect each other, and depletion exists. At the time of heat bonding, the solder is impregnated in the copper fiber member 20, but it tends to become a void in the vicinity of the depletion. However, it is presumed that the void is easily discharged by separating the predetermined distance d, and as a result, the void is reduced. The distance d is preferably 0.1 mm or more and 1 mm or less regardless of the size of the power semiconductor chip 1. More preferably. It is 0.2 mm or more. This is because if it is shorter than 0.1 mm, a void is generated, the bonding property with the electrode pattern 3 is deteriorated, and the control becomes difficult.

　また、図３に示すように、銅繊維含有はんだ材４の内部に銅繊維部材２０ではんだ２３を挟んで配置してもよい。この場合、銅繊維部材の層の間に所定の厚さｔのはんだ２３の層がある。この形態では、パワー半導体チップ１や電極パターン３側に銅繊維部材２０が配置されるため熱伝導性が向上する。例えば、図３の形態は、はんだ２３がパワー半導体チップ１や電極パターン３側に存在する図２の形態よりも熱伝導性が向上する。また、この構造とすることで、銅繊維部材２０近傍でボイドが生じにくくなる。中央部の厚さｔは、５μｍ以上２０μｍ以下であることが好ましい。２０μｍ以上だと熱抵抗が増し、５μｍ以下だとボイドが生じやすいためである。また、厚さｔは、銅繊維含有はんだ材４の厚さに対する比率が、５％から２０％であることが好ましい。 Further, as shown in FIG. 3, the copper fiber member 20 may sandwich the solder 23 inside the copper fiber-containing solder material 4. In this case, there is a layer of solder 23 having a predetermined thickness t between the copper fiber member layers. In this form, since the copper fiber member 20 is arrange | positioned at the power semiconductor chip 1 or the electrode pattern 3 side, thermal conductivity improves. For example, the form of FIG. 3 is more thermally conductive than the form of FIG. 2 in which the solder 23 is present on the power semiconductor chip 1 or electrode pattern 3 side. Moreover, by setting it as this structure, it becomes difficult to produce a void in the copper fiber member 20 vicinity. The thickness t of the central part is preferably 5 μm or more and 20 μm or less. This is because if it is 20 μm or more, the thermal resistance increases, and if it is 5 μm or less, voids are likely to occur. The thickness t is preferably 5% to 20% in proportion to the thickness of the copper fiber-containing solder material 4.

　また、銅繊維含有はんだ材のはんだにおいて、特定の組成のはんだを用いることで、接合強度および熱物性の効果を生じさせることができる。例えば、銅繊維含有はんだ材４のはんだでは、銅繊維により伝熱するため、銅繊維の銅および銅合金の拡散を抑制するＣｕフリーのはんだが好ましい。例えば、銅繊維の銅がスズ（Ｓｎ）と合金化して拡散すると伝熱する部分が減少し、熱伝導率が下がるため、銅および銅合金の拡散を抑制できるニッケル（Ｎｉ）、コバルト（Ｃｏ）をはんだに入れることが好ましい。なお、Ｃｕフリーとは、不純物程度以外にＣｕを含まないということである。 In addition, by using a solder having a specific composition in the solder of the copper fiber-containing solder material, effects of joint strength and thermophysical properties can be produced. For example, in the solder of the copper fiber-containing solder material 4, heat is transferred by the copper fiber, and therefore, a Cu-free solder that suppresses diffusion of copper and copper alloy of the copper fiber is preferable. For example, when copper in copper fiber is alloyed and diffused with tin (Sn), the portion that conducts heat decreases and the thermal conductivity decreases, so that the diffusion of copper and copper alloy can be suppressed. Nickel (Ni), cobalt (Co) Is preferably put into the solder. Note that Cu-free means that Cu is not included except for the degree of impurities.

　具体的なはんだの組成として、Ｓｎ－Ｓｂ（アンチモン）系のはんだにＮｉ、Ｃｏを入れたＳｎ－（５～１０）Ｓｂ－（０．１～１）Ｎｉ、Ｃｏのはんだ（実施例１）を用いることが好ましい。ここでの単位は、重量％（ｗｔ％）である。例えば、実施例１では、Ｓｂは、はんだ中に５～１０重量％含まれる。また、Ｎｉ、Ｃｏは、同様の効果を有するため、Ｎｉのみを入れてもよいし、Ｃｏのみを入れてもよい。さらに、Ｎｉ、Ｃｏは、はんだ中に０．２～０．５重量％含まれるのがより好ましい。 As a specific solder composition, Sn— (5-10) Sb— (0.1-1) Ni, Co solder in which Ni and Co are added to Sn—Sb (antimony) solder (Example 1) Is preferably used. The unit here is% by weight (wt%). For example, in Example 1, 5 to 10% by weight of Sb is contained in the solder. Moreover, since Ni and Co have the same effect, only Ni or Co may be included. Further, Ni and Co are more preferably contained in the solder in an amount of 0.2 to 0.5% by weight.

　また、Ｓｎ－Ｂｉ（ビスマス）系のはんだにＮｉ、Ｃｏを入れたＳｎ－（４０～７０）Ｂｉ－（０．１～１）Ｎｉ、Ｃｏのはんだ（実施例２）を用いることも好ましい。この組成のはんだは、脆いため通常ではパワー半導体チップ１の接合に用いることはできないが、実施の形態のように銅繊維部材と一緒に用いることで十分な強度を持ち、パワー半導体チップ１の接合に用いることができる。また、Ｎｉ、Ｃｏに関しては、Ｓｎ－Ｓｂ系のはんだと同様である。 It is also preferable to use Sn- (40-70) Bi- (0.1-1) Ni, Co solder (Example 2) in which Ni and Co are added to Sn-Bi (bismuth) solder. Since the solder having this composition is brittle, it cannot normally be used for joining the power semiconductor chip 1. However, it has sufficient strength when used together with the copper fiber member as in the embodiment, so that the power semiconductor chip 1 can be joined. Can be used. Ni and Co are the same as the Sn—Sb solder.

　また、Ｓｎ－Ａｇ（銀）系のはんだにＮｉ、Ｃｏを入れたＳｎ－（１～６）Ａｇ－（０．１～１）Ｎｉ、Ｃｏのはんだ（実施例３）を用いることも好ましい。また、Ｎｉ、Ｃｏに関しては、Ｓｎ－Ｓｂ系のはんだと同様である。 It is also preferable to use Sn— (1-6) Ag— (0.1-1) Ni, Co solder (Example 3) in which Ni and Co are added to Sn—Ag (silver) solder. Ni and Co are the same as the Sn—Sb solder.

　また、上記でははんだにＮｉ、Ｃｏを入れることにより、銅繊維の銅および銅合金の拡散を抑制していたが、銅繊維にＮｉめっきまたはＣｏめっきをすることにより、同様の効果を得ることができる。 In addition, in the above, the diffusion of copper and copper alloy of copper fibers was suppressed by adding Ni and Co to the solder, but the same effect can be obtained by performing Ni plating or Co plating on the copper fibers. it can.

　図４は、実施の形態にかかるはんだのパワーサイクル試験の結果を示す表である。上記の実施例１から実施例３のはんだに加え、比較例として、Ｓｎ－Ｓｂ－Ｃｕ－Ｎｉ系のはんだも試験した。また、実施例１の場合は、Ｎｉ、Ｃｏが、はんだ中に０．４重量％含まれる場合も試験した。パワーサイクル試験は、電源のオン／オフを繰り返して、熱抵抗が初期より２０％以上上昇した回数を測定した。 FIG. 4 is a table showing the results of the power cycle test of the solder according to the embodiment. In addition to the solders of Examples 1 to 3 above, Sn—Sb—Cu—Ni based solder was also tested as a comparative example. Moreover, in the case of Example 1, it tested also when Ni and Co were contained by 0.4 weight% in solder. In the power cycle test, the number of times the thermal resistance increased by 20% or more from the initial stage was measured by repeatedly turning on / off the power source.

　図４に示すように、実施例１から実施例３の場合、電源のオン／オフを１０万回以上繰り返しても、熱抵抗が初期より２０％以上上昇しなかった。特に、Ｎｉ、Ｃｏが、はんだ中に０．４重量％含まれる場合は、２０万回以上繰り返しても、熱抵抗が初期より２０％以上上昇しなかった。これに対して、比較例の場合、５万回以下の繰り返しで熱抵抗が初期より２０％以上上昇した。これにより、実施例１から実施例３のはんだを用いることで、接合強度および熱物性の効果を生じさせることがわかった。 As shown in FIG. 4, in the case of Example 1 to Example 3, the thermal resistance did not increase by 20% or more from the initial stage even when the power was turned on / off 100,000 times or more. In particular, when Ni and Co were contained by 0.4% by weight in the solder, the thermal resistance did not increase by 20% or more from the initial stage even after repeating 200,000 times or more. On the other hand, in the case of the comparative example, the thermal resistance increased by 20% or more from the initial stage after repeating 50,000 times or less. Thus, it was found that the use of the solders of Examples 1 to 3 produced effects of joint strength and thermophysical properties.

　次に、本発明の効果を実際の例により確かめた。まず、銅繊維部材２０に、はんだを上下から挟んで形成する際のはんだの厚さを決定する。図５は、はんだ厚と等価熱伝導率との関係を示すグラフである。横軸は、上下のはんだの厚さの合計であり、単位はμｍであり、縦軸は等価熱伝導率であり、単位は、Ｗ／ｍ・Ｋである。ここで、等価熱伝導率とは、複数の材質で構成される部品を、１つのブロックとみなして与える熱伝導率のことである。なお、銅繊維含有はんだ材４の端部から銅繊維部材の端までの距離ｄは０．５ｍｍとした。 Next, the effect of the present invention was confirmed by actual examples. First, the thickness of the solder when forming the copper fiber member 20 by sandwiching the solder from above and below is determined. FIG. 5 is a graph showing the relationship between solder thickness and equivalent thermal conductivity. The horizontal axis represents the total thickness of the upper and lower solders, the unit is μm, the vertical axis is the equivalent thermal conductivity, and the unit is W / m · K. Here, the equivalent thermal conductivity is a thermal conductivity that is given by considering a component composed of a plurality of materials as one block. In addition, the distance d from the edge part of the copper fiber containing solder material 4 to the edge of a copper fiber member was 0.5 mm.

　図５は、はんだの熱伝導率を４０Ｗ／ｍ・Ｋ、銅の熱伝導率を３９０Ｗ／ｍ・Ｋとして、銅繊維部材の銅占有率を２２％、銅繊維部材の厚さを１００μｍにした場合の計算結果である。図５に示すように、等価熱伝導率ｙと上下のはんだの厚さの合計ｘとの関係は、
　ｙ＝１１３．０４ｘ-0.151
で表される。例えば、上側のはんだの厚さ、銅繊維部材の厚さ、下側のはんだの厚さをそれぞれ、１０μｍ、１００μｍ、１０μｍとした場合、等価熱伝導率は約８０Ｗ／ｍ・Ｋとなり、はんだ単体の４０Ｗ／ｍ・Ｋの約２倍となる。また、それぞれ２０μｍ、１００μｍ、２０μｍとした場合、等価熱伝導率は約７２Ｗ／ｍ・Ｋとなる。 In FIG. 5, the thermal conductivity of solder is 40 W / m · K, the thermal conductivity of copper is 390 W / m · K, the copper occupation ratio of the copper fiber member is 22%, and the thickness of the copper fiber member is 100 μm. It is a calculation result in the case. As shown in FIG. 5, the relationship between the equivalent thermal conductivity y and the total thickness x of the upper and lower solders is
y = 113.04x -0.151
It is represented by For example, if the thickness of the upper solder, the thickness of the copper fiber member, and the thickness of the lower solder are 10 μm, 100 μm, and 10 μm, respectively, the equivalent thermal conductivity is about 80 W / m · K. Is about twice that of 40 W / m · K. In addition, when the thickness is 20 μm, 100 μm, and 20 μm, respectively, the equivalent thermal conductivity is about 72 W / m · K.

　図６は、銅占有率と等価熱伝導率との関係を示すグラフである。横軸は、銅占有率であり、単位は重量％であり、縦軸は等価熱伝導率であり、単位は、Ｗ／ｍ・Ｋである。ここで、銅占有率とは、銅繊維部材に含まれる銅の重量％であり、残りは、はんだの重量である。図６において、●の直線は、上側のはんだの厚さ、銅繊維部材の厚さ、下側のはんだの厚さをそれぞれ、１０μｍ、１００μｍ、１０μｍとした場合の銅占有率ｘと等価熱伝導率ｙとの関係であり、この場合、
　ｙ＝３．２５ｘ＋６．６６６７
で表される。また、○の直線は、それぞれ、５０μｍ、１００μｍ、５０μｍとした場合の銅占有率ｘと等価熱伝導率ｙとの関係であり、この場合、
　ｙ＝１．９５ｘ＋２０
で表される。図６より、●の直線の場合で、銅占有率を２２重量％にすると等価熱伝導率は約８０Ｗ／ｍ・Ｋとなることがわかる。 FIG. 6 is a graph showing the relationship between copper occupancy and equivalent thermal conductivity. The horizontal axis represents the copper occupancy, the unit is weight%, the vertical axis is the equivalent thermal conductivity, and the unit is W / m · K. Here, the copper occupation ratio is the weight% of copper contained in the copper fiber member, and the remainder is the weight of solder. In FIG. 6, the straight line ● represents the copper occupancy x and the equivalent heat conduction when the upper solder thickness, the copper fiber member thickness, and the lower solder thickness are 10 μm, 100 μm, and 10 μm, respectively. In this case,
y = 3.25x + 6.6667
It is represented by In addition, the ◯ straight lines are the relationship between the copper occupation ratio x and the equivalent thermal conductivity y when 50 μm, 100 μm, and 50 μm, respectively,
y = 1.95x + 20
It is represented by FIG. 6 shows that the equivalent thermal conductivity is about 80 W / m · K when the copper occupancy is 22 wt% in the case of the straight line ●.

　以上の結果に基づいて、厚さ１００μｍの銅繊維部材２０に、それぞれ厚さ１０μｍのＳｎ－Ｓｂ系のはんだを上下から挟んで形成した結果を示す。図７は、銅繊維含有はんだ材４の実施例を示す断面図である。図７に示すように、銅繊維含有はんだ材４は、銅繊維間が互いに接点を有するよう折り重ねられている銅繊維部２２と、銅繊維部材２０の間にはんだがしみこんだはんだ浸漬部２１とからなる。 Based on the above results, the results are shown in which a 10 μm thick Sn—Sb solder is formed on the copper fiber member 20 of 100 μm thickness from above and below. FIG. 7 is a cross-sectional view showing an example of the copper fiber-containing solder material 4. As shown in FIG. 7, the copper fiber-containing solder material 4 includes a copper fiber portion 22 that is folded so that the copper fibers have contact with each other, and a solder immersion portion 21 in which solder has soaked between the copper fiber members 20. It consists of.

　図８は、銅繊維含有はんだ材の実施例の接合部の断面図である。図８において、右図は左図の中央を拡大したものである。図８に示すように、銅繊維２０は互いに接点を持ち、銅繊維２０間がはんだ２３で充填されていることがわかる。このように作成した銅繊維含有はんだ材の熱伝導率は、計算上で７２．２Ｗ／ｍ・Ｋである。レーザーフラッシュ法により実測した結果、Ｓｎ－Ｓｂ系のはんだのみでは、熱伝導率が約４０Ｗ／ｍ・Ｋであるところ、銅繊維含有はんだ材では、熱伝導率が７５．８Ｗ／ｍ・Ｋまで向上したことを確認した。ここで、レーザーフラッシュ法とは、断熱真空中に置かれた平板状試料の表面を均一にパルス加熱し、表面から裏面への１次元の熱拡散現象を観測することにより、熱拡散率を求める方法である。 FIG. 8 is a cross-sectional view of a joint portion of an example of a copper fiber-containing solder material. In FIG. 8, the right figure is an enlargement of the center of the left figure. As shown in FIG. 8, it can be seen that the copper fibers 20 have contact points with each other and the space between the copper fibers 20 is filled with the solder 23. The thermal conductivity of the copper fiber-containing solder material thus prepared is 72.2 W / m · K in calculation. As a result of actual measurement by the laser flash method, the thermal conductivity is about 40 W / m · K only with the Sn—Sb solder, but the thermal conductivity is up to 75.8 W / m · K with the copper fiber-containing solder material. Confirmed improvement. Here, the laser flash method is to obtain a thermal diffusivity by uniformly heating the surface of a flat sample placed in an adiabatic vacuum and observing a one-dimensional thermal diffusion phenomenon from the front surface to the back surface. Is the method.

　以上、説明したように、実施の形態にかかる半導体装置によれば、パワー半導体素子と電極パターンとを接合する接合部は、銅繊維を含み、銅繊維間がはんだで充填されている銅繊維含有はんだ材である。これにより、熱伝導率が、フラックスを含有したペーストはんだや板はんだより向上するため、パワー半導体チップの発生熱を効率よく放熱できる。また、はんだの中に銅繊維が含まれているため、はんだ中にクラックが発生しても、クラックが迂回して進展するため、はんだの寿命が向上する。さらに、はんだの中に銅繊維が含まれているため、フィレットが発生することを防止でき、はんだが脇にはみ出ることが少なくなる。また、銅繊維が互いに接点を有し熱パスを形成しているため、はんだにクラックが発生しても熱抵抗の上昇を抑制できる。また、銅繊維部材に、はんだをしみこませて板はんだとすることで、従来と同様の取り扱いができ、従来よりもはんだ厚さを均一に制御することが可能になる。 As described above, according to the semiconductor device according to the embodiment, the joining portion that joins the power semiconductor element and the electrode pattern includes the copper fiber, and the copper fiber-containing portion is filled with the solder between the copper fibers. It is a solder material. Thereby, since heat conductivity improves from the paste solder and board solder containing a flux, the heat generated by a power semiconductor chip can be efficiently radiated. Moreover, since the copper fiber is contained in the solder, even if a crack occurs in the solder, the crack progresses in a detour, so the life of the solder is improved. Furthermore, since the copper fiber is contained in the solder, it is possible to prevent the fillet from being generated, and the solder is less likely to protrude to the side. Moreover, since the copper fibers have contact points with each other to form a heat path, an increase in thermal resistance can be suppressed even if cracks occur in the solder. Moreover, by making solder into a copper fiber member and making it into a sheet solder, the same handling as the conventional one can be performed, and the solder thickness can be controlled more uniformly than the conventional one.

　また、銅繊維含有はんだ材は、内部の銅繊維を中央部に配置し、内部の銅繊維がパワー半導体素子および電極パターンから離れて配置され、銅繊維含有はんだ材の端部には、銅繊維が配置されない。これにより、パワー半導体チップの発生熱を、銅繊維が配置された中央部から放熱し、ボイドを低減し、接合性も向上させることができる。 In addition, the copper fiber-containing solder material has an internal copper fiber arranged in the center, the internal copper fiber is arranged away from the power semiconductor element and the electrode pattern, and the copper fiber-containing solder material has an copper fiber at the end. Is not placed. Thereby, the generated heat of the power semiconductor chip can be dissipated from the central portion where the copper fibers are arranged, the voids can be reduced, and the bondability can be improved.

　また、銅繊維含有はんだ材は、銅繊維ではんだを挟んで接合し、パワー半導体チップや電極パターン側に銅繊維が配置される。これにより、熱伝導性がさらに向上する。銅繊維部材ではんだを挟んだ構造にした場合、はんだで銅繊維部材を挟んだ上記の結果に比べて、熱伝導率は約５％向上した。なお、銅繊維部材およびはんだを同じ厚さとした。また、銅繊維近傍でボイドが生じにくくなる。 Also, the copper fiber-containing solder material is joined by sandwiching the solder between the copper fibers, and the copper fibers are arranged on the power semiconductor chip or electrode pattern side. Thereby, thermal conductivity further improves. When the structure is such that the solder is sandwiched between the copper fiber members, the thermal conductivity is improved by about 5% as compared with the above result where the copper fiber member is sandwiched between the solder. Note that the copper fiber member and the solder had the same thickness. In addition, voids are less likely to occur in the vicinity of the copper fiber.

　また、銅繊維含有はんだ材に含まれるはんだの組成は、Ｓｎ－（５～１０）Ｓｂ－（０．１～１）Ｎｉ、Ｃｏ、Ｓｎ－（４０～７０）Ｓｂ－（０．１～１）Ｎｉ、Ｃｏ、または、Ｓｎ－（１～６）Ｓｂ－（０．１～１）Ｎｉ、Ｃｏである。Ｎｉ、Ｃｏにより銅繊維の銅および銅合金の拡散を抑制することができ、熱伝導率が下がることを抑制できる。さらに、これらのはんだを用いることで、接合強度および熱物性の効果を生じさせることができる。 The composition of the solder contained in the copper fiber-containing solder material is Sn- (5-10) Sb- (0.1-1) Ni, Co, Sn- (40-70) Sb- (0.1-1). ) Ni, Co, or Sn- (1-6) Sb- (0.1-1) Ni, Co. Ni and Co can suppress the diffusion of copper and copper alloy of the copper fiber, and can suppress a decrease in thermal conductivity. Furthermore, by using these solders, effects of bonding strength and thermophysical properties can be produced.

　また、銅繊維にＮｉめっきまたはＣｏめっきをしてもよい。Ｎｉ、Ｃｏにより銅繊維の銅および銅合金の拡散を抑制することができ、熱伝導率が下がることを抑制できる。 Further, Ni plating or Co plating may be applied to the copper fiber. Ni and Co can suppress the diffusion of copper and copper alloy of the copper fiber, and can suppress a decrease in thermal conductivity.

　以上のように、本発明にかかる半導体装置および半導体装置の製造方法は、インバータなどの電力変換装置や種々の産業用機械などの電源装置や自動車のイグナイタなどに使用されるパワー半導体装置に有用である。 As described above, the semiconductor device and the method for manufacturing the semiconductor device according to the present invention are useful for power conversion devices such as inverters, power supply devices such as various industrial machines, and power semiconductor devices used for automobile igniters. is there.

　１　パワー半導体チップ
　２　絶縁基板
　３　電極パターン
　４　接合部（銅繊維含有はんだ材）
　５　放熱板
　６　放熱グリス
　７　冷却体
　８　リードフレーム配線
　９　導電性板
１０　金属ワイヤ
１１　外部端子
１２　端子ケース
１３　封止材料
１４　はんだ材
２０　銅繊維部材
２１　はんだ浸漬部
２２　銅繊維部
２３　はんだ DESCRIPTION OF SYMBOLS 1 Power semiconductor chip 2 Insulating substrate 3 Electrode pattern 4 Joint part (copper fiber containing solder material)
5 Heat Dissipation Plate 6 Heat Dissipation Grease 7 Cooling Body 8 Lead Frame Wiring 9 Conductive Plate 10 Metal Wire 11 External Terminal 12 Terminal Case 13 Sealing Material 14 Solder Material 20 Copper Fiber Member 21 Solder Dipping Portion 22 Copper Fiber Portion 23 Solder

Claims (21)

　半導体素子を積層基板に搭載した組立構造を有する半導体装置において、
　前記半導体素子と前記積層基板上の電極パターンとを接合する接合層は、金属繊維を含み、前記金属繊維間がはんだで充填されているはんだ材が使用されることを特徴とする半導体装置。 In a semiconductor device having an assembly structure in which a semiconductor element is mounted on a multilayer substrate,
The bonding layer for bonding the semiconductor element and the electrode pattern on the laminated substrate includes a metal material, and a solder material in which a space between the metal fibers is filled with solder is used. 　前記半導体素子と、前記半導体素子と前記積層基板上の電極パターンとの電気接続用の配線とを接合する接合層は、前記はんだ材が使用されることを特徴とする請求項１に記載の半導体装置。 2. The semiconductor according to claim 1, wherein the solder material is used for a joining layer that joins the semiconductor element and wiring for electrical connection between the semiconductor element and an electrode pattern on the multilayer substrate. apparatus. 　前記組立構造は、前記積層基板を搭載した放熱板をさらに有し、
　前記積層基板と前記放熱板とを接合する接合層は、前記はんだ材が使用されることを特徴とする請求項１または２に記載の半導体装置。 The assembly structure further includes a heat sink on which the multilayer substrate is mounted,
The semiconductor device according to claim 1, wherein the solder material is used for a bonding layer that bonds the multilayer substrate and the heat dissipation plate. 　前記接合層では、前記はんだ材に含まれる前記金属繊維は中央部に配置され、
　前記接合層の端部から所定の距離の間、前記金属繊維が配置されないことを特徴とする請求項１～３のいずれか一つに記載の半導体装置。 In the bonding layer, the metal fiber contained in the solder material is disposed in a central portion,
4. The semiconductor device according to claim 1, wherein the metal fiber is not disposed for a predetermined distance from an end portion of the bonding layer. 　前記所定の距離は、０．１ｍｍ以上１ｍｍ以下であることを特徴とする請求項４に記載の半導体装置。 5. The semiconductor device according to claim 4, wherein the predetermined distance is not less than 0.1 mm and not more than 1 mm. 　前記接合層では、前記はんだ材に含まれる前記金属繊維は、前記半導体素子、前記積層基板および前記放熱板側に配置され、前記金属繊維間に、所定の厚さのはんだが配置されることを特徴とする請求項１～３のいずれか一つに記載の半導体装置。 In the bonding layer, the metal fibers included in the solder material are disposed on the semiconductor element, the laminated substrate, and the heat dissipation plate side, and solder having a predetermined thickness is disposed between the metal fibers. The semiconductor device according to any one of claims 1 to 3, characterized in that: 　前記所定の厚さは、５μｍ以上２０μｍ以下であることを特徴とする請求項６に記載の半導体装置。 7. The semiconductor device according to claim 6, wherein the predetermined thickness is not less than 5 μm and not more than 20 μm. 　前記所定の厚さは、前記はんだ材の厚さの５％から２０％であることを特徴とする請求項６に記載の半導体装置。 7. The semiconductor device according to claim 6, wherein the predetermined thickness is 5% to 20% of the thickness of the solder material. 　前記金属繊維の直径は、前記はんだ材の厚さ以下であることを特徴とする請求項１～８のいずれか一つに記載の半導体装置。 9. The semiconductor device according to claim 1, wherein a diameter of the metal fiber is equal to or less than a thickness of the solder material. 　前記金属繊維は、銅繊維であることを特徴とする請求項１～９のいずれか一つに記載の半導体装置。 10. The semiconductor device according to claim 1, wherein the metal fiber is a copper fiber. 　前記金属繊維の直径は、２０μｍ以下であることを特徴とする請求項１０に記載の半導体装置。 The semiconductor device according to claim 10, wherein a diameter of the metal fiber is 20 μm or less. 　前記金属繊維は、互いに接点を有することを特徴とする請求項１～１１のいずれか一つに記載の半導体装置。 12. The semiconductor device according to claim 1, wherein the metal fibers have contacts with each other. 　前記はんだは銅を含まないことを特徴とする請求項１～１２のいずれか一つに記載の半導体装置。 13. The semiconductor device according to claim 1, wherein the solder does not contain copper. 　前記はんだは、Ｓｎ－Ｓｂ系はんだにＮｉまたはＣｏを含有したもの、Ｓｎ－Ｂｉ系はんだにＮｉまたはＣｏを含有したもの、または、Ｓｎ－Ａｇ系はんだにＮｉまたはＣｏを含有したものであることを特徴とする請求項１～１３のいずれか一つに記載の半導体装置。 The solder is a Sn—Sb solder containing Ni or Co, a Sn—Bi solder containing Ni or Co, or a Sn—Ag solder containing Ni or Co. The semiconductor device according to any one of claims 1 to 13, wherein: 　前記金属繊維は、Ｎｉめっきがされていることを特徴とする請求項１～１４のいずれか一つに記載の半導体装置。 The semiconductor device according to any one of claims 1 to 14, wherein the metal fiber is plated with Ni. 　前記金属繊維は、Ｃｏめっきがされていることを特徴とする請求項１～１５のいずれか一つに記載の半導体装置。 The semiconductor device according to any one of claims 1 to 15, wherein the metal fiber is plated with Co. 　前記金属繊維間は、ＡｇまたはＣｕの焼結材で充填されていることを特徴とする請求項１～１６のいずれか一つに記載の半導体装置。 The semiconductor device according to any one of claims 1 to 16, wherein a space between the metal fibers is filled with a sintered material of Ag or Cu. 　前記はんだ材は、前記金属繊維が２層以上折り重ねられていることを特徴とする請求項１～１７のいずれか一つに記載の半導体装置。 The semiconductor device according to any one of claims 1 to 17, wherein the solder material includes two or more layers of the metal fibers folded. 　金属繊維を含み、前記金属繊維間がはんだで充填されているはんだ材を用いて、積層基板上の電極パターンと半導体素子とを接合して、前記積層基板に前記半導体素子を搭載する工程と、
　前記積層基板を積層組立体に組み立てる工程と、
　前記半導体素子と、前記積層基板上の電極パターンとを、電気的に接続する工程と、
　前記積層組立体に、樹脂ケースを組み合わせる工程と、
　を含むことを特徴とする半導体装置の製造方法。 A step of mounting the semiconductor element on the multilayer substrate by bonding the electrode pattern and the semiconductor element on the multilayer substrate using a solder material containing metal fibers and filled with solder between the metal fibers;
Assembling the laminated substrate into a laminated assembly;
Electrically connecting the semiconductor element and the electrode pattern on the laminated substrate;
Combining the resin case with the laminated assembly;
A method for manufacturing a semiconductor device, comprising: 　前記電気的に接続する工程では、前記はんだ材を用いて、前記半導体素子と、前記積層基板上の電極パターンとを、電気的に接続することを特徴とする請求項１９に記載の半導体装置の製造方法。 The semiconductor device according to claim 19, wherein in the electrically connecting step, the semiconductor element and the electrode pattern on the multilayer substrate are electrically connected using the solder material. Production method. 　前記組み立てる工程では、前記積層基板を、前記はんだ材を用いて、前記積層組立体の放熱板に接合することを特徴とする請求項１９または２０に記載の半導体装置の製造方法。 21. The method of manufacturing a semiconductor device according to claim 19, wherein, in the assembling step, the multilayer substrate is joined to a heat radiating plate of the multilayer assembly using the solder material.
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