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WO2018103275A1 - Puce soc comprenant un mécanisme de sécurité d'interface de débogage, et procédé - Google Patents

Puce soc comprenant un mécanisme de sécurité d'interface de débogage, et procédé Download PDF

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Publication number
WO2018103275A1
WO2018103275A1 PCT/CN2017/085624 CN2017085624W WO2018103275A1 WO 2018103275 A1 WO2018103275 A1 WO 2018103275A1 CN 2017085624 W CN2017085624 W CN 2017085624W WO 2018103275 A1 WO2018103275 A1 WO 2018103275A1
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WO
WIPO (PCT)
Prior art keywords
password
debug
debug interface
chip
port
Prior art date
Application number
PCT/CN2017/085624
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English (en)
Chinese (zh)
Inventor
王健
杨灿华
Original Assignee
上海新微技术研发中心有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 上海新微技术研发中心有限公司 filed Critical 上海新微技术研发中心有限公司
Publication of WO2018103275A1 publication Critical patent/WO2018103275A1/fr

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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
    • G06F21/71—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
    • G06F21/72—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information in cryptographic circuits
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/30—Authentication, i.e. establishing the identity or authorisation of security principals
    • G06F21/31—User authentication
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/60—Protecting data
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
    • G06F21/71—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
    • G06F21/74—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information operating in dual or compartmented mode, i.e. at least one secure mode
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2221/00—Indexing scheme relating to security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F2221/21—Indexing scheme relating to G06F21/00 and subgroups addressing additional information or applications relating to security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F2221/2141—Access rights, e.g. capability lists, access control lists, access tables, access matrices

Definitions

  • the invention belongs to the field of system on chip, and relates to a SOC chip and method with a debugging interface security mechanism.
  • SOC System on Chip
  • SOC is the core of information system integration, is the integration of key components of the system on a chip; in a broad sense, SOC is a micro-mini system, which will Microprocessors, analog IP cores, digital IP cores, and memory (or off-chip memory control interfaces) are integrated on a single chip and are typically custom-tailored or standard-oriented for specific applications.
  • the hardware debug interface provides an effective method for system testing and on-chip debugging of the SoC chip, but it also poses a security risk.
  • the current SoC chip will be integrated with the debug interface for chip testing and system debugging. Users can use the PC software for application development or use the programmer to program user programs. However, it provides convenience and brings security risks.
  • the debug interface has been called the "back door" in the industry, that is, by applying specific incentives to the debug port, the purpose of acquiring and modifying the internal resources of the chip and the memory data can be achieved.
  • an object of the present invention is to provide a SOC chip and method having a debug interface security mechanism for solving the problem of high security risk of the SOC chip in the prior art.
  • the present invention provides a SOC chip and method having a debug interface security mechanism, including:
  • Microprocessor including debug interface
  • a storage unit configured to pre-store a debug interface security access password
  • a security control unit connected between the debug port and the debug interface, for monitoring an input timing of an external device connected to the debug port; when the input timing is correct, the password is entered and the debug interface is securely accessed.
  • the password is compared; if the comparison result is consistent, the channel between the debug port and the debug interface is opened; if the comparison result is inconsistent, the channel between the debug port and the debug interface is closed.
  • the security control unit includes:
  • a first password register connected to the storage unit, for receiving and temporarily storing a debug interface secure access password from the storage unit after the chip is powered on and completing the reset operation;
  • a second password register for temporarily storing an input password from the external device
  • An input timing monitoring unit connected to the debug port and the second password register for monitoring an input timing of an external device connected to the debug port, and writing an input password to the second when the input timing is correct Password register
  • a comparator wherein the two inputs of the comparator are respectively connected to the first password register and the second password register, and are used for comparing the input password with the debug interface security access password.
  • the debug interface secure access password from the storage unit is written to the first password register by pure hardware logic, and the first password register cannot be Processor access.
  • the security control unit is configured to lock the chip when the number of password comparisons exceeds a preset number of times.
  • the security control unit is configured to lock the chip.
  • the password comparison data is no longer received, and only the memory erase command is received.
  • the preset number of times is 1 to 10.
  • the debug interface security access password is 128 bits.
  • the storage unit is a non-volatile memory.
  • the external device is a host computer or a programmer.
  • the invention also provides a method for debugging an interface security mechanism, which is applied to a SOC chip with a debug interface security mechanism according to any of the preceding claims, the method comprising:
  • the debug interface security access password pre-stored in the storage unit is written into the first password register by pure hardware logic, and the first password register cannot be used by the microprocessor. access;
  • the security control unit constantly monitors an input timing of an external device connected to the debug port, and when the timing is correct, writes an input password to the password register;
  • the security control unit compares the input password with the debug interface secure access password
  • the channel between the debug port and the debug interface is opened; if the comparison result is inconsistent, the channel between the debug port and the debug interface is closed.
  • the SOC chip and method having the debug interface security mechanism of the present invention have the following beneficial effects: the present invention adopts a digital circuit architecture to implement secure access of the debug interface, and adds security between the physical debug port and the internal debug interface.
  • Control unit isolated from the physical connection.
  • the debug port can be physically connected to the internal debug interface only by entering a timing waveform signal containing the correct password on the debug port to gain access to internal resources.
  • the security control unit is responsible for verifying the password and counting the number of comparisons. If the number of comparisons exceeds 3, it is automatically locked. After the chip is locked, the security control unit no longer receives the password comparison data and only receives the NVM memory erase command. The user can only regain the chip control right after executing the NVM memory erase command, and the user data stored in the NVM memory has been erased at this time, thereby realizing the purpose of protecting the user data in the NVM memory unit.
  • FIG. 1 is a schematic diagram showing the structure of a SOC chip with a debug interface security mechanism according to the present invention.
  • Fig. 2 is a circuit diagram showing the safety control unit.
  • FIG. 3 is a schematic flow chart showing a method for debugging an interface security mechanism according to the present invention.
  • the present invention provides a SOC chip and method having a debug interface security mechanism.
  • a schematic structural diagram of the SOC chip is shown, including a debug port 1, a microprocessor 2, and a microprocessor.
  • the storage unit 3 is configured to pre-store the debug interface security access password, and the chip production provider is responsible for maintenance.
  • the storage unit 3 uses a non-volatile memory (NVM), and when the power is turned off, the stored data does not disappear.
  • the debug interface secure access password is 128 bits.
  • the security control unit 4 is connected between the debug port 1 and the debug interface 201 for monitoring an input timing of an external device 5 connected to the debug port 1; when the input timing is correct, a password is input. Comparing with the debug interface security access password; if the comparison result is consistent, the channel between the debug port 1 and the debug interface 201 is opened; if the comparison result is inconsistent, the debug port 1 is closed to the debug The channel between the interfaces 201.
  • the external device includes but is not limited to a programmer or a host computer.
  • the invention adopts a digital circuit architecture to realize secure access of the debug interface, and a security control unit is added between the physical debug port and the internal debug interface, and the debug interface of the SOC chip is isolated from the internal debug interface of the chip from the physical connection.
  • the debug port can be physically connected to the internal debug interface only by entering a timing waveform signal containing the correct password on the debug port to gain access to internal resources.
  • FIG. 2 a circuit configuration diagram of the security control unit 4 is shown in FIG. 2, which includes a first password register 401, a second password register 402, an input timing detection unit 403, and a comparator 404;
  • the first password register 401 is connected to the storage unit 3 for receiving and temporarily storing the debug interface secure access password from the storage unit 3 after the chip is powered on and the reset operation is completed.
  • the debug interface security access password stored in the storage unit 3 can be written into the specific register by the hardware logic only after the system is powered on, and the CPU and the debug interface cannot access the storage unit 3 and The first password register 401.
  • the second password register 402 is used to temporarily store an input password from the external device 1.
  • the input timing monitoring unit 403 and the debug port 1 and the second password register 402 Connected for monitoring the input timing of an external device connected to the debug port 1, and writing an input password to the second password register 402 when the input timing is correct.
  • the two inputs of the comparator 404 are respectively connected to the first password register 401 and the second password register 402 for comparing the input password with the debug interface secure access password.
  • the security control unit 4 is configured to count the number of comparisons when verifying the password, and lock the chip when the number of password comparisons exceeds a preset number of times.
  • the preset number of times may be 1 to 10.
  • the preset number of times is preferably 3, that is, when the password comparison fails more than 3 times, the chip is automatically locked.
  • the security control unit 4 is further configured to receive no password comparison data and only receive the memory erase command after the chip is locked. That is, the user can only regain the control of the chip after executing the memory erase command, and the user data stored in the memory has been erased at this time, even if the chip is illegally acquired, only the "white film” is obtained, thereby The purpose of protecting the user program in the memory is achieved.
  • FIG. 3 is a schematic flow chart of a method for modulating an interface security mechanism according to the present invention, where the method includes:
  • Step S1 After the chip is powered on and the reset operation is completed, the debug interface security access password pre-stored in the storage unit 3 is written into the first password register by pure hardware logic, and the first password register cannot be used. Microprocessor 2 access;
  • Step S2 The security control unit 4 monitors the input timing of the external device 5 connected to the debug port 1 at a time, and when the timing is correct, writes the input password into the second password register;
  • Step S3 After the input password is received, the security control unit 4 compares the input password with the debug interface security access password;
  • Step S4 If the comparison result is consistent, the channel between the debug port 1 and the debug interface 201 is opened; if the comparison result is inconsistent, the channel between the debug port 1 and the debug interface 201 is closed.
  • the method for modulating the interface security mechanism of the present invention saves the 128-bit debug interface secure access password in a specific non-volatile memory, and the system configuration phase can be written into the specific password register by the hardware logic after the chip is powered on, the CPU and the debug The interface cannot access the non-volatile memory and the password register.
  • the password comparison fails more than a certain number of times, the chip is locked. After the chip is locked, the security control unit no longer accepts the password comparison data, and only accepts the non-volatile memory wipe. In addition to instructions, it is possible to effectively prevent illegal acquisition and modification of internal resources of the chip as well as memory data.
  • the SOC chip and method with the internal data anti-tampering mechanism of the invention adopts a digital circuit architecture to implement secure access of the debug interface, and a security control unit is added between the physical debug port and the internal debug interface, and the physical connection is obtained. Isolated on.
  • the debug port can be physically connected to the internal debug interface only by entering a timing waveform signal containing the correct password on the debug port to gain access to internal resources.
  • the security control unit is responsible for verifying the password and counting the number of comparisons. If the number of comparisons exceeds 3, it is automatically locked. After the chip is locked, the security control unit no longer receives the password comparison data and only receives the NVM memory erase command.
  • the present invention effectively overcomes various shortcomings in the prior art and has high industrial utilization value.

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computer Security & Cryptography (AREA)
  • Software Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Health & Medical Sciences (AREA)
  • General Health & Medical Sciences (AREA)
  • Bioethics (AREA)
  • Storage Device Security (AREA)
  • Microcomputers (AREA)

Abstract

L'invention concerne une puce SOC comprenant un mécanisme de sécurité d'interface de débogage, ainsi qu'un procédé. La puce comprend : un port de débogage ; un microprocesseur comprenant une interface de débogage ; une unité de stockage permettant de pré-stocker un mot de passe d'accès de sécurité de l'interface de débogage ; et une unité de commande de sécurité connectée entre le port de débogage et l'interface de débogage et permettant de surveiller une synchronisation d'entrée d'un dispositif externe connecté au port de débogage. Lorsque la synchronisation d'entrée est correcte, un mot de passe d'entrée est comparé au mot de passe d'accès de sécurité de l'interface de débogage ; si le résultat de la comparaison est cohérent, un canal allant du port de débogage à l'interface de débogage est ouvert ; et si le résultat de la comparaison est incohérent, le canal est fermé. L'invention ajoute une unité de commande de sécurité entre un port de débogage physique et une interface de débogage interne de façon à les isoler en termes de connexion physique. Le port de débogage et l'interface de débogage interne peuvent être connectés physiquement uniquement lorsqu'un signal de forme d'onde de synchronisation comprenant un mot de passe correct est saisi sur le port de débogage, ce qui permet d'acquérir un droit d'accès à une ressource interne.
PCT/CN2017/085624 2016-12-09 2017-05-24 Puce soc comprenant un mécanisme de sécurité d'interface de débogage, et procédé WO2018103275A1 (fr)

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Application Number Priority Date Filing Date Title
CN201611126402.1A CN108460296A (zh) 2016-12-09 2016-12-09 一种具有调试接口安全机制的soc芯片及方法
CN201611126402.1 2016-12-09

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CN112788382A (zh) * 2020-12-31 2021-05-11 成都长虹网络科技有限责任公司 一种具有安全调试功能的机顶盒
CN116756781A (zh) * 2023-08-23 2023-09-15 菁音核创科技(厦门)有限公司 一种芯片的加密保护方法、装置、设备及存储介质

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CN109977023A (zh) * 2019-04-03 2019-07-05 北京智芯微电子科技有限公司 支持调试权限控制的cpu芯片仿真器
CN113918392B (zh) * 2020-07-10 2023-10-13 珠海格力电器股份有限公司 一种调试保护系统及调试处理模块
CN112100691A (zh) * 2020-09-11 2020-12-18 浪潮(北京)电子信息产业有限公司 一种硬件调试接口的保护方法、保护系统及可编程控制器
CN112380119B (zh) * 2020-11-12 2024-08-16 上海东软载波微电子有限公司 芯片、编程调试器、系统及锁定编程调试入口的方法
CN115906123A (zh) * 2022-12-06 2023-04-04 合肥大唐存储科技有限公司 一种实现访问权限认证的方法、芯片及终端

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CN103324506A (zh) * 2013-06-24 2013-09-25 上海天奕达电子科技有限公司 一种控制Android应用程序安装的方法及手机
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Publication number Priority date Publication date Assignee Title
CN112788382A (zh) * 2020-12-31 2021-05-11 成都长虹网络科技有限责任公司 一种具有安全调试功能的机顶盒
CN116756781A (zh) * 2023-08-23 2023-09-15 菁音核创科技(厦门)有限公司 一种芯片的加密保护方法、装置、设备及存储介质
CN116756781B (zh) * 2023-08-23 2023-11-14 菁音核创科技(厦门)有限公司 一种芯片的加密保护方法、装置、设备及存储介质

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