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WO2018109473A1 - Régulateur de tension - Google Patents

Régulateur de tension Download PDF

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Publication number
WO2018109473A1
WO2018109473A1 PCT/GB2017/053737 GB2017053737W WO2018109473A1 WO 2018109473 A1 WO2018109473 A1 WO 2018109473A1 GB 2017053737 W GB2017053737 W GB 2017053737W WO 2018109473 A1 WO2018109473 A1 WO 2018109473A1
Authority
WO
WIPO (PCT)
Prior art keywords
effect
transistor
field
voltage
circuit portion
Prior art date
Application number
PCT/GB2017/053737
Other languages
English (en)
Inventor
Erlend STRANDVIK
Original Assignee
Nordic Semiconductor Asa
Samuels, Adrian James
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nordic Semiconductor Asa, Samuels, Adrian James filed Critical Nordic Semiconductor Asa
Publication of WO2018109473A1 publication Critical patent/WO2018109473A1/fr

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Classifications

    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current 
    • G05F1/46—Regulating voltage or current  wherein the variable actually regulated by the final control device is DC
    • G05F1/56—Regulating voltage or current  wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices
    • G05F1/575—Regulating voltage or current  wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices characterised by the feedback circuit
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current 
    • G05F1/46—Regulating voltage or current  wherein the variable actually regulated by the final control device is DC
    • G05F1/56—Regulating voltage or current  wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices

Definitions

  • the present invention relates to voltage regulators, particularly low-dropout voltage regulators.
  • Low-dropout (or LDO) voltage regulators are linear DC voltage regulators that are capable of operating with very low input-output differential voltages.
  • the advantages of such regulators with respect to other types of voltage regulators include having a lower minimum operating voltage, higher power efficiency and lower heat dissipation.
  • a conventional LDO voltage regulator consists of an error amplifier and a pass field- effect-transistor or "pass-FET".
  • the error amplifier compares the output voltage (or a voltage derived therefrom) being generated by the LDO to a reference voltage and alters the conductivity of the pass-FET in order to drive the output voltage to the desired value.
  • the error amplifier of an LDO regulator has an associated transfer function which describes the frequency response of the circuit.
  • the transfer function typically has a pole located at a particular frequency known as a corner frequency. Once the frequency of the lowest frequency or "dominant" pole has been reached, the gain of the circuit begins to decrease at a rate of 20 dB/decade (i.e. for every ten-fold increase in frequency, the gain drops by 20 dB). Any subsequent poles will then increase this rate by a further 20 dB/decade. Each pole will also introduce a 90 degree phase shift. Thus with two poles, the output is then in antiphase (i.e.
  • the gain should drop to unity at a frequency lower than that of the second (or any subsequent) pole (i.e. the first "non-dominant" pole).
  • the first pole arises from the capacitance of a (typically large) output capacitor and the output resistance of the pass-FET while the second pole arises from the gate capacitance of the pass-FET and the output resistance of the error amplifier.
  • a source follower stage is placed at the output of the error amplifier.
  • Such a source follower stage drives the gate of the pass-FET and pushes the second pole to a relatively high frequency with a view to improving the stability of the LDO voltage regulator.
  • the bias current required to drive the second pole up to such high frequencies increases dramatically, increasing the current consumption of the device as a whole.
  • the present invention provides a low-dropout voltage regulator arranged to convert an input voltage to an output voltage, the low- dropout voltage regulator comprising:
  • a pass field-effect-transistor having a first terminal connected to the input voltage and a second terminal arranged to produce the output voltage
  • an error amplifier circuit portion arranged to produce an error signal proportional to a difference between a feedback voltage and a reference voltage, said feedback voltage being derived from the output voltage, wherein the error amplifier circuit portion is arranged to apply the error signal to the gate terminal of the pass field-effect-transistor via an error amplifier output terminal;
  • a low-dropout (LDO) voltage regulator arranged such that the output impedance of the error amplifier circuit portion scales with the output current due to the diode-connected field-effect- transistor (FET) connected to its output.
  • the scaling output current of the error amplifier drives the pole due to the output impedance of the error amplifier (and the gate capacitance of the pass-FET) to much higher frequencies than the unity gain frequency. This improves the overall stability of the LDO regulator across a wider range of load currents compared to conventional LDO voltage regulators.
  • diode- connected transistor refers to a field-effect-transistor having its drain and gate terminals connected together so as to effectively form a two-terminal device from the three-terminal transistor.
  • diode-connected transistor One characteristic of a diode-connected transistor is that it always operates in the saturation region.
  • the diode-connected field-effect-transistor comprises a p-channel metal-oxide-semiconductor field-effect-transistor (pMOSFET), wherein the source terminal of the diode-connected field-effect-transistor is connected to the input voltage.
  • pMOSFET metal-oxide-semiconductor field-effect-transistor
  • the pass field-effect-transistor comprises a p-channel metal-oxide-semiconductor field-effect-transistor, wherein the source terminal of the pass field-effect-transistor is connected to the input voltage.
  • the error amplifier is arranged such that the feedback voltage is applied to a non-inverting input of said error amplifier and the reference voltage is applied to an inverting input of said error amplifier.
  • the error amplifier is arranged to detect if the feedback voltage has fallen to the reference voltage and if so decrease its output voltage such that the conductivity of the pMOS pass-FET increases.
  • the pass field- effect-transistor comprises an n-channel metal-oxide-semiconductor field-effect- transistor (nMOSFET), wherein the drain terminal of the pass field-effect-transistor is connected to the input voltage.
  • nMOSFET metal-oxide-semiconductor field-effect- transistor
  • the error amplifier is arranged such that the reference voltage is applied to a non-inverting input of said error amplifier and the feedback voltage is applied to an inverting input of said error amplifier.
  • the error amplifier is arranged to detect if the feedback voltage has fallen to the reference voltage and if so increase its output voltage such that the conductivity of the nMOS pass-FET increases.
  • the pass field-effect-transistor is connected in series with a potential divider circuit portion comprising at least first and second resistors, wherein the feedback voltage comprises the voltage at a node between said first and second resistors.
  • the potential divider circuit portion acts as a feedback for the error amplifier. The feedback voltage taken from this node will be proportional to the output voltage and will depend on the ratio between the resistance of the first resistor and the resistance of the second resistor. While the resistance of these resistors may be fixed, in some embodiments the potential divider circuit has an adjustable resistance ratio.
  • an adjustable resistance ratio i.e. the ratio between the resistance of the first resistor and the resistance of the second resistor
  • This may be achieved using a physically variable resistor (e.g. a potentiometer), however in practice this is more readily achieved by using an array of fixed resistors that can be "switched in and out", e.g. using a control signal.
  • the error amplifier comprises:
  • a differential pair circuit portion comprising first and second differential field- effect-transistors
  • bias current circuit portion connected to the source terminals of said first and second differential field-effect-transistors arranged to provide a bias current thereto;
  • the current mirror load comprises first and second mirror field-effect-transistors, wherein:
  • the drain terminal of the first mirror field-effect-transistor is connected to the drain terminal of the first differential field-effect-transistor
  • drain terminal of the second mirror field-effect-transistor is connected to the drain terminal of the second differential field-effect-transistor
  • the gate terminal of the first mirror field-effect-transistor is connected to the drain terminal of the first mirror field-effect-transistor and the gate terminal of the second mirror field-effect-transistor.
  • the bias current circuit portion comprises a current source connected between the source terminals of the first and second differential field- effect-transistors and ground. Such a current source provides a constant, static bias current to the LDO voltage regulator.
  • the bias current circuit portion comprises an adaptive bias circuit portion arranged to increase the bias current in response to an increase in the error voltage.
  • the adaptive bias circuit portion comprises:
  • a scaling field-effect transistor having its gate terminal connected to the output of the error amplifier output terminal
  • an adaptive bias current mirror circuit portion comprising first and second adaptive bias mirror field-effect-transistors, wherein:
  • the drain terminal of the first adaptive bias mirror field-effect-transistor is connected to the gate terminal of the first and second adaptive bias mirror field-effect-transistors and to the drain terminal of the scaling field-effect-transistor; and the drain terminal of the second adaptive bias mirror field-effect-transistor is connected to the source terminals of the first and second differential field-effect- transistors;
  • the source terminal of the second adaptive bias mirror field-effect-transistor is connected to ground.
  • the present invention provides a low-dropout voltage regulator arranged to convert an input voltage to an output voltage, the low-dropout voltage regulator comprising:
  • an error amplifier circuit portion arranged to produce an error signal proportional to a difference between a feedback voltage and a reference voltage, said feedback voltage being derived from the output voltage; and an impedance scaling circuit portion arranged to vary an output impedance of the error amplifier circuit portion in response to an output current of the low- dropout voltage regulator.
  • the impedance scaling circuit portion comprises a diode-connected filed-effect-transistor connected to an output of the error amplifier circuit portion.
  • the impedance scaling circuit portion comprises a diode-connected filed-effect-transistor connected to an output of the error amplifier circuit portion.
  • Fig. 1 shows a circuit diagram of a low-dropout voltage regulator in accordance with an embodiment of the present invention
  • Fig. 2 shows a simulation of the voltages at various nodes within the regulator of Fig. 1 as a function of load current
  • Fig. 3 shows a comparative simulation of the transient step response of the regulator of Fig. 1 to a step in the load current.
  • Fig. 1 shows a low-dropout (LDO) voltage regulator 102 in accordance with an embodiment of the present invention. While it will be appreciated that the LDO voltage regulator 102 would typically be implemented as a single integrated circuit, it has been divided into several logical circuit portions for illustrative purposes only.
  • the LDO voltage regulator 102 comprises: an error amplifier circuit portion 104; an adaptive bias circuit portion 106; an output circuit portion 108; and a variable output impedance circuit portion 1 10. Each of these circuit portions will be described in turn below.
  • the error amplifier circuit portion 104 is constructed as a "long tailed pair" and comprises a differential pair of n-channel metal-oxide-semiconductor field-effect- transistors (nMOSFETs) M0, M1 arranged such that their respective source terminals are connected together and are further connected to a current source 112. The current source 1 12 is also connected to ground.
  • the error amplifier circuit portion 104 further comprises a current mirror load constructed from two p- channel metal-oxide-semiconductor field-effect-transistors (pMOSFETs) M2, M3. The respective gate terminals these two pMOSFETs M2, M3 are connected to the respective drain terminals of M1 and M2. The drain terminal of M3 is connected to the drain terminal of MO.
  • the source terminals of both M2 and M3 are connected to the input voltage 114.
  • the gate terminals of the differential pair nMOSFETs MO, M1 are connected to a reference voltage V ref and a feedback voltage respectively as will be described in further detail below.
  • the error amplifier circuit portion 104 also comprises an output terminal 1 16 which is connected to the adaptive bias circuit portion 106 and the output circuit portion 108 as will also be described in further detail below.
  • the adaptive bias circuit portion 106 comprises a scaling pMOSFET M6 arranged such that its gate terminal is connected to the output terminal 1 16 of the error amplifier circuit portion 104.
  • the adaptive bias circuit portion 106 further comprises a current mirror arrangement constructed from a first adaptive bias mirror nMOSFET M7 and a second adaptive bias mirror nMOSFET M8.
  • the first adaptive bias current mirror nMOSFET M7 is arranged as a diode-connected transistor, i.e. its gate and drain terminals are connected together.
  • the gate and drain terminals of M7 are further connected to the gate terminal of M8 and to the drain terminal of M6 while the source terminal of M7 is connected to ground.
  • the source terminal of M8 is also connected to ground, however the drain terminal of M8 is connected to the source terminals of the differential pair transistors M0 and M1 in the error amplifier circuit portion 104.
  • the adaptive bias circuit portion 106 provides an additional current to the error amplifier circuit portion 104 that depends on the voltage at the output terminal 1 16.
  • the output circuit portion 108 comprises a buffer nMOSFET M5 and an output drive pMOSFET MP.
  • the buffer transistor M5 is arranged such that its drain terminal is connected to the input voltage 1 14 and its source terminal is connected to ground via a current source 118.
  • the gate terminal of the buffer transistor M5 is connected to the output terminal 116 of the error amplifier circuit portion 104.
  • the source terminal of the buffer transistor M5 is further connected to the gate terminal of the output drive transistor MP.
  • the source terminal of the output drive transistor MP is connected to the input voltage 1 14 while its drain terminal is connected to ground via a load capacitor CL.
  • the output voltage V ou t of the LDO regulator 102 is taken from a regulator output terminal 120 at the drain of MOP.
  • the feedback voltage ⁇ 3 ⁇ 4 applied to the gate terminal of M1 is also taken from this regulator output terminal 120, however it will be appreciated that in practice a potential divider (not shown) could be connected between this regulator output terminal 120 and the gate terminal of M1.
  • the variable output impedance circuit portion 110 comprises a diode-connected pMOSFET M4 arranged such that its source terminal is connected to the input voltage 114 and its gate and drain terminals are connected to the output terminal 116 of the error amplifier circuit portion 104. As will be described in further detail below, it is this diode-connected transistor M4 that provides the error amplifier circuit portion 104 with an output resistance that varies with the load current l
  • FIG. 1 Also shown in Fig. 1 are the illustrative labels that show where the poles of the system arise, i.e. a position corresponding to the respective positions where the output resistance and capacitance associated with the components of the LDO voltage regulator 102 that give rise to each of the poles can be observed.
  • a first pole P ota arising from the output resistance of the error amplifier circuit portion 104 and the gate capacitance of M5 is shown at the output terminal 116 of the error amplifier circuit portion 104.
  • a second pole P uf arising from the output resistance of the buffer transistor M5 and the gate capacitance of the output drive transistor MP is shown at the source terminal of the buffer transistor M5 and the gate terminal of the output drive transistor MP.
  • a pole P ou t arising from the output resistance of the output drive transistor MP and the load capacitor CL is shown at the regulator output terminal 120. It is this third pole P ou t that is the dominant pole of the LDO regulator 102.
  • the LDO regulator 102 is to deliver 150 mA of current, the size of the output drive transistor MP needs to be relatively large e.g.
  • the buffer transistor M5 helps to isolate the output of the error amplifier circuit portion 104 from the large gate capacitance of MP. This helps to provide a larger possible signal swing at the gate terminal of the output drive transistor MP.
  • the output resistance of a source follower buffer such as the buffer transistor M5 is sufficiently low (1/g m ) such that the pole P Uf at the gate terminal of the output drive transistor MP is raised to a sufficiently high frequency in order to obtain stability of the voltage regulator.
  • the output drive transistor MP is so large that in order to move the pole P Uf to such high frequencies, the buffer transistor M5 requires relatively high bias currents or its size must also be increased substantially.
  • its gate capacitance would also increase pushing the pole P ota at the output terminal 1 16 of the error amplifier circuit portion 104 to lower frequencies which may cause further instability.
  • the Applicant has appreciated that the resistance in the bond wires connected to the output terminal 120 of the LDO voltage regulator 102 and the equivalent series resistance of the load capacitor CL cause a zero in the transfer function that increases the unity gain frequency of the LDO voltage regulator 102. It is known in the art per se to place the pole P ota at the output of the error amplifier circuit portion 104 so as to cancel this zero, however since the gate capacitance of the output drive transistor MP is so large, it is difficult to push the pole P uf to high frequencies and therefore the Applicant has appreciated that it is advantageous to place the pole P uf such that it cancels with this zero instead.
  • the diode-connected transistor M4 is placed parallel to the output 116 of the error amplifier circuit portion 104 in order to reduce the output resistance of the error amplifier circuit portion 104. This pushes the pole P ota at the output 116 of the error amplifier circuit portion 104 to much higher frequencies than the unity gain frequency. If the load current l
  • the adaptive biasing circuit portion 106 provides an increase in the
  • transconductance of the differential pair of transistors M0, M1 increases the gain of the error amplifier circuit portion 104 in order to compensate for some of the loss gain caused by the decreased output impedance at higher load current l
  • Fig. 2 shows a simulation of the voltages at various nodes within the regulator of Fig. 1 as a function of load current l
  • transconductance g m of the diode-connected transistor M4 which in turn lowers the output resistance of the error amplifier circuit portion 104.
  • the output drive transistor MP moves into the strong inversion operating region.
  • This transition from weak to strong inversion causes the sudden change in V 116 , V M PGATE and l M4 when l
  • the abrupt change shown in Fig. 2 is due to limitations of the simulation software used to produce the plots, and in reality (or with higher simulation accuracy) the transition is typically more smooth.
  • the voltage- current relationship is exponential, while in strong inversion it is quadratic.
  • Fig. 3 shows a comparative simulation of the transient step response of the regulator of Fig. 1 to a step in the load current l

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Automation & Control Theory (AREA)
  • Continuous-Control Power Sources That Use Transistors (AREA)

Abstract

L'invention concerne un régulateur de tension à faible chute de tension (102) conçu pour convertir une tension d'entrée en une tension de sortie Vout et comprend un transistor à effet de champ de chute (MP) ayant une première borne connectée à la tension d'entrée (114) et une seconde borne agencée pour produire la tension de sortie Vout. Une partie de circuit d'amplificateur d'erreur (104) est agencée pour produire un signal d'erreur proportionnel à une différence entre une tension de rétroaction Vfb et une tension de référence Vref, la tension de rétroaction Vfb étant dérivée de la tension de sortie. La partie de circuit d'amplificateur d'erreur (104) est agencée pour appliquer le signal d'erreur à la borne de gâchette du transistor à effet de champ de chute (MP) par l'intermédiaire d'une borne de sortie d'amplificateur d'erreur (116). Un transistor à effet de champ (M4) connecté à une diode est connecté à la borne de sortie d'amplificateur d'erreur (116).
PCT/GB2017/053737 2016-12-16 2017-12-13 Régulateur de tension WO2018109473A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GB1621487.6 2016-12-16
GB1621487.6A GB2558877A (en) 2016-12-16 2016-12-16 Voltage regulator

Publications (1)

Publication Number Publication Date
WO2018109473A1 true WO2018109473A1 (fr) 2018-06-21

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Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/GB2017/053737 WO2018109473A1 (fr) 2016-12-16 2017-12-13 Régulateur de tension

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GB (1) GB2558877A (fr)
TW (1) TW201823902A (fr)
WO (1) WO2018109473A1 (fr)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI717006B (zh) * 2018-10-14 2021-01-21 新唐科技股份有限公司 用於電壓調節之電子電路及其方法
CN115857604A (zh) * 2023-03-03 2023-03-28 上海维安半导体有限公司 一种适用于低压差线性稳压器的自适应电流跃变电路
CN117155123A (zh) * 2023-11-01 2023-12-01 江苏帝奥微电子股份有限公司 一种适用于ldo的瞬态跳变过冲抑制电路及其控制方法

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI683200B (zh) * 2018-12-21 2020-01-21 新唐科技股份有限公司 動態偏壓控制系統
US10942536B1 (en) * 2019-09-20 2021-03-09 Texas Instruments Incorporated Pre-regulator for an LDO
US11402265B2 (en) 2019-11-05 2022-08-02 Texas Instruments Incorporated Apparatus for integrated offset voltage for photodiode current amplifier
CN110957981B (zh) * 2019-11-28 2024-03-15 上海磐启微电子有限公司 一种增益与阻抗匹配分离的无电感低噪声放大器
US11361644B2 (en) 2019-12-18 2022-06-14 Texas Instruments Incorporated Duty cycle tuning in self-resonant piezo buzzer
US11468756B2 (en) 2020-04-02 2022-10-11 Texas Instruments Incorporated Integrated circuit for smoke detector having compatibility with multiple power supplies
CN113867466B (zh) * 2021-10-14 2023-03-14 上海安路信息科技股份有限公司 稳压器电路

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020130646A1 (en) * 2001-01-26 2002-09-19 Zadeh Ali Enayat Linear voltage regulator using adaptive biasing
CN101354595A (zh) * 2007-07-26 2009-01-28 盛群半导体股份有限公司 提升线性与负载调节率特性的低压降稳压器
CN102298408A (zh) * 2011-04-22 2011-12-28 上海宏力半导体制造有限公司 稳压电路
US20120326696A1 (en) * 2011-06-24 2012-12-27 Yen-An Chang Variable voltage generation circuit
US9223329B2 (en) * 2013-04-18 2015-12-29 Stmicroelectronics S.R.L. Low drop out voltage regulator with operational transconductance amplifier and related method of generating a regulated voltage

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2818762B1 (fr) * 2000-12-22 2003-04-04 St Microelectronics Sa Regulateur de tension a gain statique en boucle ouverte reduit
FR2896051B1 (fr) * 2006-01-09 2008-04-18 St Microelectronics Sa Regulateur de tension serie a faible tension d'insertion
US7710091B2 (en) * 2007-06-27 2010-05-04 Sitronix Technology Corp. Low dropout linear voltage regulator with an active resistance for frequency compensation to improve stability
IT1392262B1 (it) * 2008-12-15 2012-02-22 St Microelectronics Des & Appl "regolatore lineare di tipo low-dropout con efficienza migliorata e procedimento corrispondente"
US8471538B2 (en) * 2010-01-25 2013-06-25 Sandisk Technologies Inc. Controlled load regulation and improved response time of LDO with adaptive current distribution mechanism

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020130646A1 (en) * 2001-01-26 2002-09-19 Zadeh Ali Enayat Linear voltage regulator using adaptive biasing
CN101354595A (zh) * 2007-07-26 2009-01-28 盛群半导体股份有限公司 提升线性与负载调节率特性的低压降稳压器
CN102298408A (zh) * 2011-04-22 2011-12-28 上海宏力半导体制造有限公司 稳压电路
US20120326696A1 (en) * 2011-06-24 2012-12-27 Yen-An Chang Variable voltage generation circuit
US9223329B2 (en) * 2013-04-18 2015-12-29 Stmicroelectronics S.R.L. Low drop out voltage regulator with operational transconductance amplifier and related method of generating a regulated voltage

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI717006B (zh) * 2018-10-14 2021-01-21 新唐科技股份有限公司 用於電壓調節之電子電路及其方法
CN115857604A (zh) * 2023-03-03 2023-03-28 上海维安半导体有限公司 一种适用于低压差线性稳压器的自适应电流跃变电路
CN117155123A (zh) * 2023-11-01 2023-12-01 江苏帝奥微电子股份有限公司 一种适用于ldo的瞬态跳变过冲抑制电路及其控制方法
CN117155123B (zh) * 2023-11-01 2023-12-29 江苏帝奥微电子股份有限公司 一种适用于ldo的瞬态跳变过冲抑制电路及其控制方法

Also Published As

Publication number Publication date
GB2558877A (en) 2018-07-25
TW201823902A (zh) 2018-07-01
GB201621487D0 (en) 2017-02-01

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