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WO2018120363A1 - 基于Si衬底的GaN基增强型HEMT器件及其制造方法 - Google Patents

基于Si衬底的GaN基增强型HEMT器件及其制造方法 Download PDF

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WO2018120363A1
WO2018120363A1 PCT/CN2017/073541 CN2017073541W WO2018120363A1 WO 2018120363 A1 WO2018120363 A1 WO 2018120363A1 CN 2017073541 W CN2017073541 W CN 2017073541W WO 2018120363 A1 WO2018120363 A1 WO 2018120363A1
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layer
algan
gan
substrate
electrode
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王洪
周泉斌
李祈昕
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South China University of Technology SCUT
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South China University of Technology SCUT
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Priority claimed from CN201611269252.XA external-priority patent/CN106711212B/zh
Priority claimed from CN201611269244.5A external-priority patent/CN107068750B/zh
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Priority to US16/089,374 priority Critical patent/US10580879B2/en
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/015—Manufacture or treatment of FETs having heterojunction interface channels or heterojunction gate electrodes, e.g. HEMT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02494—Structure
    • H01L21/02496—Layer structure
    • H01L21/02505—Layer structure consisting of more than two layers
    • H01L21/02507—Alternating layers, e.g. superlattice
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/40—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels
    • H10D30/47—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having 2D charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/40—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels
    • H10D30/47—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having 2D charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
    • H10D30/471—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT]
    • H10D30/475—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT] having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/82—Heterojunctions
    • H10D62/824—Heterojunctions comprising only Group III-V materials heterojunctions, e.g. GaN/AlGaN heterojunctions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02455—Group 13/15 materials
    • H01L21/02458—Nitrides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02494—Structure
    • H01L21/02496—Layer structure
    • H01L21/02505—Layer structure consisting of more than two layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02538—Group 13/15 materials
    • H01L21/0254—Nitrides
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/85—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs
    • H10D62/8503—Nitride Group III-V materials, e.g. AlN or GaN
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/512—Disposition of the gate electrodes, e.g. buried gates
    • H10D64/513—Disposition of the gate electrodes, e.g. buried gates within recesses in the substrate, e.g. trench gates, groove gates or buried gates

Definitions

  • the invention belongs to the field of microelectronics and relates to a semiconductor device, in particular to a GaN-based enhanced HEMT based on a Si substrate.
  • the device and its manufacturing method can be used in high voltage and high power applications as well as the basic unit of the digital circuit.
  • GaN-based materials have large forbidden band width, high electron saturation drift velocity, high critical breakdown field strength, high thermal conductivity, good stability, corrosion resistance, and radiation resistance. For the production of high temperature, high frequency and high power electronic devices.
  • GaN also has excellent electronic properties, and can form a doped AlGaN/GaN heterostructure with AlGaN, which can achieve electron mobility higher than 1500cm 2 /Vs at room temperature, and up to 3 ⁇ 10 7 cm /s peak electron velocity and 2x10 7 cm/s saturated electron velocity, and obtain a higher two-dimensional electron gas density than the second-generation compound semiconductor heterostructure, which is known as an ideal material for developing microwave power devices. . Therefore, the high electron mobility transistor HEMT based on AlGaN/GaN heterojunction has a very good application prospect in microwave high power devices.
  • GaN is a typical representative of the third generation of semiconductor materials, with wide band gap, high breakdown electric field, high frequency, high efficiency and other excellent properties, GaN Base materials and devices are the development direction of the power electronics industry. To replace existing Si-based power electronics, GaN-based high-voltage materials and devices need to significantly reduce production costs while maintaining high performance. In large size Fabrication of GaN-based epitaxial materials and devices on Si substrates is the best solution for balancing performance and cost.
  • the thermal mismatch between the GaN-based material and the Si substrate will grow at high temperatures.
  • a large tensile stress >1G Pascal
  • This tensile stress due to thermal mismatch causes the epitaxial wafer to be strongly warped or even cracked.
  • the cracking of the epitaxial material when the GaN-based material is grown on the substrate reduces the warpage of the GaN-based epitaxial material on the large-sized Si substrate, which is the most important technical difficulty in the field.
  • GaN-based heterojunction structures Growth and optimization of GaN-based heterojunction structures on large-sized Si substrates.
  • GaN-based heterojunction structures AlGaN barrier layers are exposed.
  • the tensile stress applied by the GaN channel layer introduces various defects into the heterojunction, which causes the electrical performance degradation and reliability of the GaN-based high-voltage switching device.
  • GaN on the Si substrate The growth of the heterojunction structure is more difficult because the GaN-based material on the Si substrate has higher defect density (including dislocations and background impurities), and GaN
  • the base material is subjected to greater stress, which is additive with the stress in the heterojunction structure. More defects and greater stress promote GaN on the Si substrate. The accelerated release of stress in the heterojunction structure causes reliability problems in the device.
  • the object of the present invention is to overcome the above drawbacks of the prior art, and propose a GaN based on Si substrate from the perspective of optimization of the longitudinal structure of the device.
  • the object of the invention is achieved at least by one of the following technical solutions.
  • Si substrate AlGaN/GaN heterojunction enhanced HEMT device including Si stacked in order from at least Substrate, AN nucleation layer, AlGaN transition layer, AlGaN buffer layer, low temperature AlN insertion layer, AlGaN main buffer layer, AlGaN/GaN superlattice layer, GaN Channel layer, AlGaN barrier functional layer;
  • HEMT device has a source electrode and a drain electrode on both sides of the top end, and a gate electrode in the middle of the top end;
  • a passivation protective layer is deposited on the AlGaN barrier functional layer, AlGaN A barrier is formed in the middle of the barrier functional layer and the passivation protective layer, and a bottom of the recess is connected to the GaN channel layer, and a passivation protective layer and a dielectric layer are deposited on the bottom, and the gate electrode is on the dielectric layer.
  • the passivation protective layer on both sides of the AlGaN barrier functional layer is etched into a source electrode window and a drain electrode window, and the source electrode window and the drain electrode window are respectively used to form a source electrode and a drain electrode by evaporation.
  • the Si substrate has a size of 2 inches to 10 inches.
  • the AlGaN transition layer has a total of three layers, wherein the molar content of the Al elements in each layer from bottom to top is x, y, and z, respectively. And satisfy the relationship of 1 > x > y > z > 0.
  • the AlGaN transition layer has a total of three layers, and the thicknesses thereof are h1, h2, and h3 from bottom to top, and satisfy the 300nm > h3 > h2 > h1 > 50nm relationship.
  • the molar contents of the Al elements in the AlGaN buffer layer and the AlGaN main buffer layer are m and n, respectively. , satisfying the relations m>0 and n>0 .
  • a low temperature AlN is interposed between the AlGaN buffer layer and the AlGaN main buffer layer Layer to reduce the cumulative stress of the material.
  • an AlGaN/GaN superlattice layer is formed under the GaN channel layer, and the superlattice period is greater than 5 cycles.
  • a channel of a high concentration two-dimensional electron gas (2DEG) formed at the interface between the GaN channel layer and the AlGaN barrier functional layer.
  • the AlGaN barrier functional layer is etched through the formed recess, and the bottom of the recess is in contact with the GaN channel layer.
  • a passivation protective layer is deposited on the bottom of the recess as a gate insulating medium to form an MIS structure.
  • the passivation protective layer and the gate dielectric layer are deposited by a PVD method or a sputtering method.
  • the alloy metal used for the electrode metal of the source electrode and the drain electrode on both sides of the tip end is a gold-free system metal.
  • a method of preparing an enhanced HEMT device of the Si substrate AlGaN/GaN heterojunction comprising the steps of:
  • the AlGaN transition layer is epitaxially grown on the basis of the AlN nucleation layer, and the total content of the Al element is decreased in turn, and the thickness is sequentially increased;
  • An epitaxial AlGaN buffer layer and an AlGaN main buffer layer are used as the main layer of the device material on the basis of the AlGaN transition layer, wherein the Al composition is greater than zero, and the low temperature AlN layer is interposed to reduce the cumulative stress of the material;
  • the AlGaN barrier functional layer of the etch material and the GaN channel layer are mesa-isolated, and the respective devices are separated, and the etching depth is 200 nm to 500 nm;
  • the AlGaN barrier functional layer is engraved to form a recess, and the bottom of the recess is connected to the GaN channel layer;
  • Electrode beam evaporation is used to vaporize the Schottky contact metal and the ohmic contact metal in the gate, source and drain windows, and after stripping and annealing, forming a gate electrode and source and drain contact electrodes;
  • Photolithography has formed the surface of the device of the source, drain and gate, obtaining a thickened electrode pattern, and thickening the electrode by electron beam evaporation technology to complete the device fabrication.
  • the annealing treatment temperature was 1100 ° C for 15 minutes.
  • the low-temperature AlN insertion layer and the AlGaN/GaN superlattice layer alleviate the mismatch stress of the lattice accumulation and improve the crystal quality of the material.
  • the present invention has the following advantages and technical effects:
  • the device is a GaN-based enhancement HEMT device based on Si substrate, which makes it easier to implement CMOS-compatible GaN electronic device processes.
  • An insulating film growth technique is used to prepare an enhanced MIS-HEMT on a depletion type epitaxial material.
  • the material failure is suppressed
  • the film quality is improved, and the interface state of the semiconductor/dielectric layer is improved, a high-quality insulated gate dielectric is fabricated, the surface state is reduced, and a large gate voltage level is realized.
  • the device prepared by the invention has high threshold voltage, high breakdown voltage, high current density, and excellent pinch-off characteristics, and has the advantages of simple manufacturing process and good repeatability, and is suitable for applications such as high voltage and high power electronic devices.
  • Figure 1 is a schematic view showing the structure of a GaN-based enhancement type HEMT device based on a Si substrate of the present invention.
  • 2a to 2n are GaN-based enhanced HEMTs based on Si substrates in an example of the present invention Schematic diagram of the preparation process of the device.
  • Figure 3 is a current-voltage curve of the present invention and a conventional structure.
  • a GaN-based enhancement type HEMT device based on a Si substrate includes: a Si substrate 101, AlN nucleation layer 102, AlGaN transition layer 103-105, AlGaN buffer layer 106, low temperature AlN insertion layer 107, AlGaN main buffer layer 108, AlGaN/GaN superlattice layer 109, GaN channel layer 110, AlGaN barrier functional layer 111; HEMT device has source electrodes on both sides of the top end 112 And the drain electrode 113, the middle of the top is the gate electrode 116; the AlGaN barrier functional layer 111 is deposited with a passivation protective layer 114, an AlGaN barrier functional layer 111 and a passivation protective layer 114 is engraved to form a groove, the bottom of the groove is connected to the GaN channel layer 110, and a passivation protective layer 114 and a dielectric layer 115 are deposited on the bottom, and the gate electrode 116 is above the dielectric layer
  • the passivation protective layer 114 on both sides of the AlGaN barrier functional layer 111 is etched into a source electrode 112 window and a drain electrode 113 window, and the source electrode 112
  • the window and drain electrode 113 windows are respectively used to form the source electrode 112 and the drain electrode 113 by evaporation.
  • the AlN nucleation layer 102 is epitaxially grown on the Si substrate 101; the Al x Ga (1-x) N transition layer (103-105) is epitaxially formed on the nucleation layer 102, and has a total of three layers, and the molar contents of the Al elements are sequentially from bottom to top.
  • the values of the drop are 0.75, 0.40 and 0.2 respectively, and the thickness h of the single layer increases sequentially, which is 140 nm, 190 nm and 240 nm respectively.
  • the Al m Ga 1-m N buffer layer 106 is epitaxially extended in the Al x Ga (1-x) N transition.
  • the Al element has a molar content of 7% and a thickness of 200 nm; the low temperature AlN insertion layer 107 is epitaxially grown on the Al m Ga (1-m) N buffer layer 106 to a thickness of 10 nm; Al n Ga ( 1-n) N main buffer layer 108 is epitaxially deposited on the low temperature AlN intercalation layer 107 with a molar content of Al of 5% and a thickness of 1.2 ⁇ m; the Al i Ga (1-i) N/GaN superlattice layer 109 is epitaxially On the main buffer layer 108 of Al n Ga (1-n) N, the superlattice period is 8 cycles, wherein the thicknesses of Al i Ga (1-i) N and GaN are 5 nm and 10 nm, respectively, Al i Ga (1 -i) N is the molar content of Al element was 10%; GaN channel layer 110 in the epitaxial Al i Ga (1-i) N
  • the Al k Ga (1-k) N barrier functional layer 111 is etched through to form a recess, and the bottom of the recess is connected to the GaN channel layer 110; a 20 nm SiO 2 gate insulating layer is deposited by PECVD; magnetron sputtering is employed.
  • a thickened electrode pattern is obtained, and the electrode is thickened by electron beam evaporation technology to complete the device fabrication.
  • step one the substrate is annealed at a temperature of 1100 degrees Celsius for 15 minutes;
  • Step 2 the AlN nucleation layer 102 is epitaxially grown on the Si substrate 101;
  • Step 3 the Al x Ga ( 1-x ) N transition layer ( 103-105 ) is epitaxially formed on the nucleation layer 102 , and the total molar content of the Al element is sequentially decreased by 0.75, 0.40 and 0.2, respectively.
  • the thickness h increases sequentially, and the values are 140 nm, 190 nm, and 240 nm, respectively;
  • Step 4 the Al m Ga ( 1-m ) N buffer layer 106 is epitaxially formed on the Al x Ga ( 1-x ) N transition layer ( 103-105 ), and has a molar content of Al of 7% and a thickness of 200 nm;
  • Step 5 the low temperature AlN insertion layer 107 is epitaxially grown on the Al m Ga ( 1-m ) N buffer layer 106 with a thickness of 10 nm;
  • Step 6 the Al n Ga ( 1-n ) N main buffer layer 108 is epitaxially deposited on the low temperature AlN insertion layer 107 , and has a molar content of Al of 5% and a thickness of 1.2 ⁇ m;
  • Step 7 the Al i Ga ( 1-i ) N/GaN superlattice layer 109 is epitaxially grown on the Al n Ga ( 1-n ) N main buffer layer 108 , and the superlattice period is 8 cycles, wherein Al i Ga ( The monolayer thickness of 1-i) N and GaN is 5 nm and 10 nm, respectively, and the molar content of Al in Al i Ga ( 1-i ) N is 10%;
  • Step VIII the GaN channel layer 110 is epitaxially formed on the Al i Ga ( 1-i ) N/GaN superlattice layer 109 with a thickness of 2.4 ⁇ m;
  • Step IX the Al k Ga ( 1-k ) N barrier functional layer 111 is epitaxially grown on the GaN channel layer 110 , and has an Al element molar content of 27% and a thickness of 27 nm ;
  • Step 10 The AlGaN layer and the GaN layer of the etched material are mesa-isolated, and the respective devices are separated, and the etching depth is 200 nm. ;
  • Step 11 passivation protection, using a PECVD method to deposit 200 nm SiO 2 as a passivation layer to passivate the device;
  • Step 12 Etching the passivation layer of the 200 nm SiO 2 in the intermediate region and the barrier functional layer Al k Ga (1-k) to form a gate recess, the Al k Ga (1-k) N barrier functional layer 111
  • the groove is cut through to form a groove, and the bottom of the groove is connected to the GaN channel layer 110;
  • Step 13 depositing 20 nm of SiO 2 by a PECVD method to form a gate insulating medium
  • Step 14 depositing 100 nm TiN as a gate dielectric layer in the early trench by magnetron sputtering;
  • Step fifteen after etching, etching a passivation layer of 220 nm SiO 2 at both ends to form a source window and a drain window;
  • the four layers of metal are respectively used as a Schottky contact and an ohmic contact metal, and after being stripped and annealed, a gate electrode and source and drain contact electrodes are formed;
  • Step 17 Photolithography has formed the surface of the device of the source, drain, and gate, obtaining a thickened electrode pattern, and thickening the electrode by electron beam evaporation to complete the device fabrication.
  • the device is a GaN-based enhancement HEMT device based on Si substrate, making it easier to implement CMOS compatible GaN electronic device process.
  • the MIS and HECVD insulating film growth technology in CMOS is used to prepare the enhanced MIS-HEMT on the depletion epitaxial material. .

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Abstract

一种基于Si衬底的GaN基增强型HEMT器件及其制造方法。该器件包括：Si衬底(101)、AlN成核层(102)、AlGaN过渡层(103-105)、AlGaN缓冲层(106)、低温AlN插入层(107)、AlGaN主缓冲层(108)、AlGaN/GaN超晶格层(109)、GaN沟道层(110)、AlGaN势垒功能层(111)，顶端两侧是源电极(112)和漏电极(113)、顶端中间是栅电极(116)，中间AlGaN势垒功能层(111)被刻穿形成凹槽，凹槽的底部与GaN沟道层(110)相接触，凹槽底部淀积有钝化保护层(114)和栅介质层(115)，栅介质层(115)上面是栅电极(116)。该器件具有高阈值电压、高击穿电压、高电流密度、以及优良的夹断特性，而且制造工艺简单，重复性好的特点，适用于高压大功率电子器件等应用。

Description

基于 Si 衬底的 GaN 基增强型 HEMT 器件及其制造方法
技术领域
本发明属于微电子技术领域，涉及半导体器件，具体的说是一种基于 Si 衬底的 GaN 基增强型 HEMT 器件及其制造方法，可用于高压大功率应用场合以及构成数字电路基本单元。
背景技术
随着现代武器装备和航空航天、核能、通信技术、汽车电子、开关电源的发展，对半导体器件的性能提出了更高的要求。作为宽禁带半导体材料的典型代表， GaN 基材料具有禁带宽度大、电子饱和漂移速度高、临界击穿场强高、热导率高、稳定性好、耐腐蚀、抗辐射等特点，可用于制作高温、高频及大功率电子器件。另外， GaN 还具有优良的电子特性，可以和 AlGaN 形成调制掺杂的 AlGaN/GaN 异质结构，该结构在室温下可以获得高于 1500cm2/Vs 的电子迁移率，以及高达 3×107cm/s 的峰值电子速度和 2×107cm/s 的饱和电子速度，并获得比第二代化合物半导体异质结构更高的二维电子气密度，被誉为是研制微波功率器件的理想材料。因此，基于 AlGaN/GaN 异质结的高电子迁移率晶体管 HEMT 在微波大功率器件方面具有非常好的应用前景。
GaN 是第三代半导体材料的典型代表，具有宽禁带、高击穿电场、高频、高效等优异性质， GaN 基材料和器件是电力电子行业发展的方向。为了替代现有的 Si 基电力电子器件， GaN 基高压材料和器件需要在保持高性能的前提下极大地降低生产成本。在大尺寸 Si 衬底上制备 GaN 基外延材料和器件，是平衡性能和成本的最佳解决方案。目前，国内大量的高科技公司和科研单位希望可以在大尺寸（ 6 英寸及以上） Si 衬底上生长平整、无龟裂的高质量 GaN 基高压外延材料，同时结合 Si 基器件 CMOS 工艺开发，研制 600V 和 1200V 高压开关器件，探索影响器件性能和可靠性的关键物理机制， 并对所制作的器件进行应用验证和产品开发。
大尺寸 Si 衬底上生长平整的 GaN 基外延材料由于 GaN 和 Si 衬底之间存在巨大的晶格失配（ -17% ）和热失配（ 116% ），在 Si 衬底上生长 GaN 基材料单晶是非常困难的。特别是 GaN 基材料和 Si 衬底之间的热失配会在高温生长 GaN 基外延材料结束后，在降温过程中引入大的张应力（ >1G 帕斯卡），这个由于热失配引起的张应力会导致外延片强烈翘曲甚至龟裂。如何避免 Si 衬底上生长 GaN 基材料时外延材料的龟裂，降低大尺寸 Si 衬底上 GaN 基外延材料的翘曲，是该领域最重大的技术难点。
大尺寸 Si 衬底上 GaN 基异质结结构的生长和优化 GaN 基异质结结构中， AlGaN 势垒层受到了 GaN 沟道层施加的张应力，应力的释放会在异质结中引入各种缺陷，从而造成 GaN 基高压开关器件电学性能的下降和可靠性的问题。而 Si 衬底上 GaN 基异质结结构的生长则更为困难，因为 Si 衬底上 GaN 基材料具有更高的缺陷密度（包括位错和背景杂质），而且 GaN 基材料受到更大的应力，此应力会与异质结结构中的应力累加，更多的缺陷和更大的应力会促使 Si 衬底上 GaN 基异质结结构中应力的加速释放，造成器件的可靠性问题。
发明内容
本发明的目的在于克服上述已有技术的缺陷，从器件纵向结构的优化角度提出一种基于 Si 衬底的 GaN 基增强型 HEMT 器件及其制造方法，以降低工艺难度，提高器件的可靠性。
本发明的目的至少通过如下技术方案之一实现。
Si 衬底 AlGaN/ GaN 异质结基的增强型 HEMT 器件，其包括从下至少上依次层叠的 Si 衬底、 AN 成核层、 AlGaN 过渡层、 AlGaN 缓冲层、低温 AlN 插入层、 AlGaN 主缓冲层、 AlGaN/GaN 超晶格层、 GaN 沟道层、 AlGaN 势垒功能层； HEMT 器件的顶端两侧是源电极和漏电极，顶端中间是栅电极； AlGaN 势垒功能层上淀积有钝化保护层， AlGaN 势垒功能层和钝化保护层中间被刻穿形成凹槽，凹槽的底部与 GaN 沟道层相连，底部还淀积有钝化保护层和介质层，介质层上面是所述栅电极，形成 MIS 结构， AlGaN 势垒功能层上方两侧的钝化保护层被刻蚀成源电极窗口和漏电极窗口，源电极窗口和漏电极窗口分别用于通过蒸发形成源电极、漏电极。
进一步地， Si 衬底尺寸为 2inch-10inch 。
进一步地， AlGaN 过渡层总共三层，其中从下至上每层的 Al 元素摩尔含量依次为 x 、 y 和 z ，并满足关 1 ＞ x ＞ y ＞ z ＞ 0 的关系。
进一步地， AlGaN 过渡层总共三层，从下至上其厚度依次为 h1 、 h2 和 h3 ，并满足关 300nm ＞ h3 ＞ h2 ＞ h1 ＞ 50nm 的关系。
进一步地， AlGaN 缓冲层和 AlGaN 主缓冲层中的 Al 元素摩尔含量分别为 m 和 n ，满足关系式 m>0 和 n>0 。
进一步地， AlGaN 缓冲层和 AlGaN 主缓冲层中间穿插低温 AlN 层，以降低材料累积应力。
进一步地， GaN 沟道层下有 AlGaN/GaN 超晶格层，超晶格周期大于 5 个周期。
进一步地， GaN 沟道层和 AlGaN 势垒功能层界面处形成的高浓度二维电子气（ 2DEG ）的沟道。
进一步地， AlGaN 势垒功能层被刻穿形成的凹槽，凹槽的底部与 GaN 沟道层相接触。
进一步地，凹槽底部淀积有钝化保护层作为栅绝缘介质，形成 MIS 结构。
进一步地，钝化保护层和栅介质层采用 PVD 方法或是溅射方法淀积形成。
进一步地，顶端两侧的源电极和漏电极的电极金属采用的合金金属为无金体系金属。
制备所述Si衬底AlGaN/GaN异质结基的增强型HEMT器件的方法，包括如下步骤:
1) 在反应室中对Si衬底表面进行退火处理；
2) 在衬底上外延AlN成核层，为后续生长提供成核节点；
3) 在AlN成核层的基础上外延生长AlGaN过渡层，共三层，其Al元素的摩尔含量依次下降，厚度依次增加；
4) 在AlGaN过渡层基础上外延AlGaN缓冲层和AlGaN主缓冲层作为器件材料的主干层，其中Al组分大于零，中间穿插低温AlN层以降低材料累积应力；
5) 在AlGaN主缓冲层基础上外延AlGaN/GaN超晶格层，超晶格周期大于5个周期；
6) 外延生长GaN沟道层；
7) 外延生长AlkGa(1-k)N势垒功能层，其Al元素的摩尔含量k满足0.5>k>0.2；
8) 刻蚀材料的AlGaN势垒功能层和GaN沟道层进行台面隔离，将各个器件分隔开，刻蚀深度为200nm~500nm；
9) 钝化保护，采用PVD方法进行钝化层淀积，对器件进行钝化保护；
10) 刻蚀出栅极凹槽，AlGaN势垒功能层被刻穿形成凹槽，凹槽的底部与GaN沟道层相连；
11) 采用PVD方法，在凹槽处淀积SiO2钝化层，同时作为栅绝缘层；
12) 采用溅射方法在凹槽内进行栅极介质层的淀积；
13) 光刻后刻蚀出源极和漏极窗口；
14) 采用电子束蒸发技术子在栅极、源极和漏极窗口蒸发肖特基接触金属和欧姆接触金属，并通过剥离、退火后，形成栅电极和源、漏接触电极；
15) 光刻已形成源、漏、栅极的器件表面，获得加厚电极图形，并采用电子束蒸发技术加厚电极，完成器件制作。
进一步地，所述退火处理的温度为1100摄氏度，时间15分钟。
进一步地，所述低温AlN插入层和AlGaN/GaN超晶格层，缓解晶格累积的失配应力的同时，提高材料的结晶质量。
与现有技术相比，本发明具有如下优点和技术效果：
该器件是基于Si衬底的GaN基增强型HEMT器件，可以更为容易的实现CMOS兼容的GaN电子器件工艺。同时采用CMOS中成熟的ALD和 LPCVD 绝缘薄膜生长技术，在耗尽型外延材料上制备增强型MIS-HEMT。通过优化工艺条件，一方面抑制材料失效，另一方面提高薄膜质量，同时改善半导体/介质层的界面态，制作高质量绝缘栅介质，减小表面态，实现大的栅电压等级。采用发明制备的器件具有高阈值电压、高击穿电压、高电流密度、以及优良的夹断特性，而且制造工艺简单，重复性好的特点，适用于高压大功率电子器件等应用。
附图说明
图 1 是本发明实例基于 Si 衬底的 GaN 基增强型 HEMT 器件 的结构示意图。
图 2a~ 图 2n 是本发明实例中基于 Si 衬底的 GaN 基增强型 HEMT 器件的制备过程示意图。
图 3 是本发明和传统结构的电流 - 电压曲线。
具体实施方式
以下结合附图和实例对本发明的具体实施作进一步说明，但本发明的实施和保护不限于此，需指出的是，以下若有未特别详细说明之过程或工艺参数，均是本领域技术人员可参照现有技术实现的。
参照图 1 ，基于 Si 衬底的 GaN 基增强型 HEMT 器件，包括： Si 衬底 101 、 AlN 成核层 102 、 AlGaN 过渡层 103-105 、 AlGaN 缓冲层 106 、低温 AlN 插入层 107 、 AlGaN 主缓冲层 108 、 AlGaN/GaN 超晶格层 109 、 GaN 沟道层 110 、 AlGaN 势垒功能层 111 ； HEMT 器件的顶端两侧是源电极 112 和漏电极 113 ，顶端中间是栅电极 116 ； AlGaN 势垒功能层 111 上淀积有钝化保护层 114 ， AlGaN 势垒功能层 111 和钝化保护层 114 中间被刻穿形成凹槽，凹槽的底部与 GaN 沟道层 110 相连，底部还淀积有钝化保护层 114 和介质层 115 ，介质层上面是所述栅电极 116 ，形成 MIS 结构， AlGaN 势垒功能层 111 上方两侧的钝化保护层 114 被刻蚀成源电极 112 窗口和漏电极 113 窗口，源电极 112 窗口和漏电极 113 窗口分别用于通过蒸发形成源电极 112 、漏电极 113 。
AlN 成核层 102 外延在 Si 衬底 101 上面； AlxGa （1-x） N 过渡层（ 103-105 ）外延在成核层 102 上面，一共三层，从下至上其 Al 元素摩尔含量依次下降，分别取值 0.75 、 0.40 和 0.2 ，单层厚度 h 依次增加，分别取值为 140nm 、 190nm 和 240nm ； AlmGa1-mN 缓冲层 106 外延在 AlxGa （1-x） N 过渡层（ 103-105 ）上面，其 Al 元素摩尔含量为 7% ，厚度为 200nm ；低温 AlN 插入层 107 外延在 AlmGa （1-m） N 缓冲层 106 上面，厚度为 10nm ； AlnGa （1-n） N 主缓冲层 108 外延在低温 AlN 插入层 107 上面，其 Al 元素摩尔含量为 5% ，厚度为 1.2µm ； AliGa （1-i） N/GaN 超晶格层 109 外延在 AlnGa （1-n） N 主缓冲层 108 上面，超晶格周期为 8 个周期，其中 AliGa （1-i） N 和 GaN 单层厚度分别为 5nm 和 10nm ， AliGa （1-i） N 中的 Al 元素摩尔含量为 10% ； GaN 沟道层 110 外延在 AliGa （1-i） N/GaN 超晶格层 109 上面，厚度为 2.4µm ； AlkGa （1-k） N 势垒功能层 111 外延在 GaN 沟道层 110 上面，其 Al 元素摩尔含量为 27% ，厚度为 27nm ；刻蚀材料的 AlGaN 层和 GaN 层进行台面隔离，将各个器件分隔开，刻蚀深度为 200nm ；钝化保护，采用 PECVD 方法淀积 200nm SiO2 作为钝化层，对器件进行钝化保护；刻蚀掉中间区域的 200nm SiO2 的钝化层和势垒功能层 AlkGa(1-k) 形成栅极凹槽。
AlkGa （1-k） N 势垒功能层 111 被刻穿形成凹槽，凹槽的底部与 GaN 沟道层 110 相连；采用 PECVD 淀积 20nm SiO2 栅极绝缘层；采用磁控溅射方法淀积 100nm TiN 作为栅极介质层；光刻后刻蚀两端区域的 220nm SiO2 的钝化层形成出源极和漏极窗口；采用电子束蒸发技术在栅极、源极和漏极窗口蒸发 Ti/Al/Ti/TiN=20nm/130nm/25nm/70nm 四层金属分别作为肖特基接触和欧姆接触金属，并通过剥离、退火后，形成栅极和源、漏接触电极；光刻已形成源、漏、栅极的器件表面，获得加厚电极图形，并采用电子束蒸发技术加厚电极，完成器件制作。
仅作为举例，如图 2a~ 图 2n ，具体实施步骤如下：
步骤一，对衬底进行退火处理 , 温度 1100 摄氏度，时间 15 分钟；
步骤二， AlN 成核层 102 外延在 Si 衬底 101 上面；
步骤三， AlxGa （ 1-x ） N 过渡层（ 103-105 ）外延在成核层 102 上面，一共三层，其 Al 元素摩尔含量依次下降，分别取值 0.75 、 0.40 和 0.2 ，单层厚度 h 依次增加，分别取值为 140nm 、 190nm 和 240nm ；
步骤四， AlmGa （ 1-m ） N 缓冲层 106 外延在 AlxGa （ 1-x ） N 过渡层（ 103-105 ）上面，其 Al 元素摩尔含量为 7%, 厚度为 200nm ；
步骤五，低温 AlN 插入层 107 外延在 AlmGa （ 1-m ） N 缓冲层 106 上面，厚度为 10nm ；
步骤六， AlnGa （ 1-n ） N 主缓冲层 108 外延在低温 AlN 插入层 107 上面，其 Al 元素摩尔含量为 5%, 厚度为 1.2µm ；
步骤七， AliGa （ 1-i ） N/GaN 超晶格层 109 外延在 AlnGa （ 1-n ） N 主缓冲层 108 上面，超晶格周期为 8 个周期，其中 AliGa （ 1-i ） N 和 GaN 单层厚度分别为 5nm 和 10nm ， AliGa （ 1-i ） N 中的 Al 元素摩尔含量为 10% ；
步骤八， GaN 沟道层 110 外延在 AliGa （ 1-i ） N/GaN 超晶格层 109 上面，厚度为 2.4µm ；
步骤九， AlkGa （ 1-k ） N 势垒功能层 111 外延在 GaN 沟道层 110 上面，其 Al 元素摩尔含量为 27% ，厚度为 27nm ；
步骤十，刻蚀材料的 AlGaN 层和 GaN 层进行台面隔离，将各个器件分隔开，刻蚀深度为 200nm ；
步骤十一，钝化保护，采用 PECVD 方法淀积 200nm SiO2 作为钝化层，对器件进行钝化保护；
步骤十二，刻蚀掉中间区域的 200nm SiO2 的钝化层和势垒功能层 AlkGa(1-k) 形成栅极凹槽， AlkGa(1-k)N 势垒功能层 111 被刻穿形成凹槽，凹槽的底部与 GaN 沟道层 110 相连；
步骤十三，采用 PECVD 方法淀积 20nm 的 SiO2 ，形成栅绝缘介质；
步骤十四，采用磁控溅射方法早凹槽中淀积 100nm TiN 作为栅极介质层；
步骤十五，光刻后刻蚀两端区域的 220nm SiO2 的钝化层形成出源极窗口和漏极窗口；
步骤十六，采用电子束蒸发技术在栅极介质层、源极窗口和漏极窗口蒸发 Ti/Al/Ti/TiN=20nm/130nm/25nm/70nm 四层金属分别作为肖特基接触和欧姆接触金属，并通过剥离、退火后，形成栅极和源、漏接触电极；
步骤十七，光刻已形成源、漏、栅极的器件表面，获得加厚电极图形，并采用电子束蒸发技术加厚电极，完成器件制作。
该器件是基于 Si 衬底的 GaN 基增强型 HEMT 器件，可以更为容易的实现 CMOS 兼容的 GaN 电子器件工艺。同时采用 CMOS 中成熟的 ALD 和 LPCVD 绝缘薄膜生长技术，在耗尽型外延材料上制备增强型 MIS-HEMT 。通过优化工艺条件，一方面抑制材料失效，另一方面提高薄膜质量，同时改善半导体 / 介质层的界面态，制作高质量绝缘栅介质，减小表面态，实现大的栅电压等级，因而 具有高阈值电压、高击穿电压、高电流密度、以及优良的夹断特性，而且制造工艺简单，重复性好的特点，适用于高压大功率电子器件等应用。本发明和传统结构相比，漏电流明显减小，如图 3 所示。
上述实施例仅本发明的优选实例，不构成对本发明的任何限制，显然对于本领域的专业人员来说，在了解了本发明内容和原理后，能够在不背离本发明的原理和范围的情况下，根据本发明的方法进行形式和细节上的各种修正和改变，但是这些基于本发明的修正和改变仍在本发明的权利要求保护范围之内。

Claims (10)

  1. 基于Si衬底的GaN基增强型HEMT器件，其特征在于包括从下至上依次层叠的Si衬底（101）、AN成核层（102）、AlGaN过渡层（103-105）、AlGaN缓冲层（106）、低温AlN插入层（107）、AlGaN主缓冲层（108）、AlGaN/GaN超晶格层（109）、GaN沟道层（110）、AlGaN势垒功能层（111）；HEMT器件的顶端两侧是源电极（112）和漏电极（113），顶端中间是栅电极（116）；AlGaN势垒功能层（111）上淀积有钝化保护层（114），AlGaN势垒功能层（111）和钝化保护层（114）中间被刻穿形成凹槽，凹槽的底部与GaN沟道层（110）相连，底部还淀积有钝化保护层（114）和介质层（115），介质层上面是所述栅电极（116），形成MIS结构，AlGaN势垒功能层（111）上方两侧的钝化保护层（114）被刻蚀成源电极（112）窗口和漏电极（113）窗口，源电极（112）窗口和漏电极（113）窗口分别用于通过蒸发形成源电极（112）、漏电极（113）。
  2. 根据权利要求1所述的基于Si衬底的GaN基增强型HEMT器件，其特征在于Si衬底尺寸为2inch-10inch。
  3. 根据权利要求1所述的基于Si衬底的GaN基增强型HEMT器件，其特征在于AlGaN过渡层（103-105）总共三层，其中从下至上每层的Al元素的摩尔含量依次为x、y和z，并满足关1＞x＞y＞z＞0的关系，从下至上每层的厚度依次为h1、h2和h3，并满足关300nm＞h3＞h2＞h1＞50nm的关系。
  4. 根据权利要求1的基于Si衬底的GaN基增强型HEMT器件，其特征在于AlGaN缓冲层（106）和AlGaN主缓冲层（108）中的Al元素摩尔含量分别为m和n，满足关系式m>0和n>0。
  5. 根据权利要求1的基于Si衬底的GaN基增强型HEMT器件，其特征在于AlGaN缓冲层（106）和AlGaN主缓冲层（108）中间穿插低温AlN层（107）。
  6. 根据权利要求1的基于Si衬底的GaN基增强型HEMT器件，其特征在于GaN沟道层（110）下有AlGaN/GaN超晶格层，超晶格周期大于5个周期。
  7. 根据权利要求1的基于Si衬底的GaN基增强型HEMT器件，其特征在于GaN沟道层（110）和AlGaN势垒功能层（111）界面处形成高浓度二维电子气（2DEG）的沟道。
  8. 根据权利要求1的基于Si衬底的GaN基增强型HEMT器件，其特征在于，其特征在于AlGaN势垒功能层（111）被刻穿形成的凹槽，凹槽的底部与GaN沟道层（110）相接触；凹槽底部淀积有钝化保护层（114）作为栅绝缘介质，形成MIS结构。
  9. 根据权利要求1的基于Si衬底的GaN基增强型HEMT器件，其特征在于，
    顶端两侧的源电极（112）和漏电极（113）的电极金属采用的合金金属为无金体系金属。
  10. 制备权利要求1~9任一项所述基于Si衬底的GaN基增强型HEMT器件的方法，其特征在于包括如下步骤：
    1) 在反应室中对Si衬底表面进行退火处理，温度1100摄氏度，时间15分钟；
    2) 在衬底上外延AlN成核层（102），为后续生长提供成核节点；
    3) 在AlN成核层的基础上外延生长AlGaN过渡层（103-105），共三层，其Al元素的摩尔含量依次下降，厚度依次增加；
    4) 在AlGaN过渡层（103-105）基础上外延AlGaN缓冲层（106）和AlGaN主缓冲层（108）作为器件材料的主干层，其中Al组分大于零，中间穿插低温AlN层（107）以降低材料累积应力；
    5) 在AlGaN主缓冲层（108）基础上外延AlGaN/GaN超晶格层（109），超晶格周期大于5个周期；
    6) 外延生长GaN沟道层（110）；
    7) 外延生长AlkGa(1-k)N势垒功能层（111），其Al元素的摩尔含量k满足0.5>k>0.2；
    8) 刻蚀材料的AlGaN势垒功能层（111）和GaN沟道层（110）进行台面隔离，将各个器件分隔开，刻蚀深度为200nm~500nm；
    9) 钝化保护，采用PVD方法或溅射方法进行钝化层淀积，对器件进行钝化保护；
    10) 刻蚀出栅极凹槽，AlGaN势垒功能层（111）被刻穿形成凹槽，凹槽的底部与GaN沟道层（110）相连；
    11) 采用PVD方法，在凹槽处淀积SiO2钝化层，同时作为栅绝缘层；
    12) 采用溅射方法在凹槽内进行栅极介质层（115）的淀积；
    13) 光刻后刻蚀SiO2钝化保护层，露出源极和漏极窗口；
    14) 采用电子束蒸发技术，在栅极、源极和漏极窗口蒸发肖特基接触金属和欧姆接触金属，并通过剥离、退火后，形成栅电极和源、漏接触电极；
    15) 光刻已形成源、漏、栅极的器件表面，获得加厚电极图形，并采用电子束蒸发技术加厚电极，完成器件制作。
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