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WO2018120555A1 - Circuit d'interpolation de phases et procédé d'amélioration de la linéarité de celui-ci - Google Patents

Circuit d'interpolation de phases et procédé d'amélioration de la linéarité de celui-ci Download PDF

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Publication number
WO2018120555A1
WO2018120555A1 PCT/CN2017/082609 CN2017082609W WO2018120555A1 WO 2018120555 A1 WO2018120555 A1 WO 2018120555A1 CN 2017082609 W CN2017082609 W CN 2017082609W WO 2018120555 A1 WO2018120555 A1 WO 2018120555A1
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WIPO (PCT)
Prior art keywords
port
circuit
switch tube
phase interpolator
signal input
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PCT/CN2017/082609
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English (en)
Chinese (zh)
Inventor
易生涛
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深圳市中兴微电子技术有限公司
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Publication of WO2018120555A1 publication Critical patent/WO2018120555A1/fr

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/135—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of time reference signals, e.g. clock signals

Definitions

  • the present invention relates to a phase interpolator circuit, and more particularly to a phase interpolator circuit and a method thereof for improving linearity.
  • phase interpolator (PI) circuit is widely used in high-speed digital-analog hybrid circuits (such as phase-locked loop (PLL) circuits, clock data recovery (CDR) circuits, and the like.
  • PLL phase-locked loop
  • CDR clock data recovery
  • Integral nonlinearity (INL, Integral Nonlinearity) and differential nonlinearity (DNL) of the output phase of the ordinary phase interpolator circuit tend to be greater than 1 LSB (Least Significant Bit), affecting the phase interpolator circuit The normal operation of the latter circuit. How to reduce the INL and DNL of the output phase of the phase interpolator circuit is an urgent problem to be solved.
  • an embodiment of the present invention provides a phase interpolator circuit and a method for improving linearity thereof.
  • a phase interpolator circuit provided by an embodiment of the present invention includes N phase interpolator units, N ⁇ 2; the phase interpolator unit includes: a differential switching transistor circuit, a current control circuit, and a bias current circuit, wherein
  • the differential switch tube circuit includes a first switch tube and a second switch tube; the first switch tube is connected to the clock signal input end through its first port, and is connected to the negative signal output end through its second port. And connected to the current control circuit through its own third port; the second switch tube is connected to the clock signal input end through its first port, and is connected to the positive signal output end through its second port, and Connected to the current control circuit through its third port;
  • the current control circuit is connected to the control signal input end through its first port, connected to the differential switch tube circuit through its second port, and connected to the bias current circuit through its third port;
  • the bias current circuit is connected to the reference signal input terminal through its first port, connected to the current control circuit through its second port, and connected to the ground through its own third port.
  • the phase interpolator unit includes four sets of differential switch tube circuits
  • a first port of the first switch tube of the first group of differential switch transistors is connected to the first clock signal input end, and a first port of the second switch tube is connected to the second clock signal input end;
  • the first port of the first switch tube of the second group of differential switch transistors is connected to the third clock signal input end, and the first port of the second switch tube is connected to the fourth clock signal input end;
  • the first port of the first switch tube of the third group of differential switch transistors is connected to the second clock signal input end, and the first port of the second switch tube is connected to the first clock signal input end;
  • the first port of the first switch tube of the fourth group of differential switch transistors is connected to the fourth clock signal input end, and the first port of the second switch tube is connected to the third clock signal input end.
  • the phase interpolator unit includes four sets of current control circuits
  • a first port of the first set of current control circuits is coupled to the first control signal input
  • a first port of the second group of current control circuits is coupled to the second control signal input terminal
  • the first port of the third group of current control circuits is connected to the third control signal input end;
  • the first port of the fourth group of current control circuits is coupled to the fourth control signal input.
  • the negative signal output ends respectively connected to the four sets of differential switch tube circuits are connected together, and the positive signal output ends respectively connected to the four sets of differential switch tube circuits are connected together.
  • the current control circuit is connected to the differential switch tube circuit through its second port, specifically:
  • the current control circuit is respectively connected to the third port of the first switch tube and the third port of the second switch tube in the differential switch tube circuit through its second port.
  • the first switch tube, the second switch tube, the current control circuit, and the bias current circuit are all N-type metal-oxide-semiconductor field effects (NMOS, N-Metal) -Oxide-Semiconductor) tube.
  • NMOS N-type metal-oxide-semiconductor field effects
  • the phase interpolator circuit further includes: a first resistor and a second resistor, wherein
  • the first end of the first resistor is connected to the power source, and the second end is connected to the negative signal output end;
  • the first end of the second resistor is connected to the power source, and the second end is connected to the positive signal output end.
  • phase interpolator circuit When the phase adjustment is performed by the phase interpolator circuit, the weights of the different quadrants are adjusted, wherein the phase interpolator circuit comprises N phase interpolator units, N ⁇ 2;
  • the phase is adjusted by N phase interpolator units in the phase interpolator circuit.
  • the phase interpolator unit includes: a differential switch transistor circuit, a current control circuit, and a bias current circuit, wherein
  • the differential switch tube circuit includes a first switch tube and a second switch tube; the first switch tube Connected to the clock signal input terminal through its first port, connected to the negative signal output terminal through its second port, and connected to the current control circuit through its own third port; the second switch tube passes The first port of the self is connected to the clock signal input end, is connected to the positive signal output end through its second port, and is connected to the current control circuit through its third port;
  • the current control circuit is connected to the control signal input end through its first port, connected to the differential switch tube circuit through its second port, and connected to the bias current circuit through its third port;
  • the bias current circuit is connected to the reference signal input terminal through its first port, connected to the current control circuit through its second port, and connected to the ground through its own third port.
  • the phase interpolator circuit includes N phase interpolator units, N ⁇ 2; the phase interpolator unit includes: a differential switch transistor circuit, a current control circuit, and a bias current circuit, wherein
  • the differential switching transistor circuit includes a first switching transistor and a second switching transistor; the first switching transistor is connected to the clock signal input terminal through its first port, and is connected to the negative signal output terminal through its second port, and Connected to the current control circuit through its own third port;
  • the second switch tube is connected to the clock signal input terminal through its first port, and is connected to the positive signal output terminal through its second port, and passes through The third port of the self is connected to the current control circuit;
  • the current control circuit is connected to the control signal input terminal through its first port, and is connected to the differential switch transistor circuit through its second port, and passes through itself a third port is coupled to the bias current circuit;
  • the bias current circuit passes through its first port and the reference signal input Then, by its second port to the current control circuit, and is connected through its own third port and
  • the independent phase interpolator unit has small parasitics, the current can be quickly stabilized. Increase each time or By reducing an independent phase interpolator unit, the change in current is linear and the phase change is linear.
  • the number of independent phase interpolator units connected in parallel is increased or decreased. In fact, there is no difference between the phase jumps in the quadrant. In this way, the linearity of the phase interpolator is greatly improved, and a smooth change in the phase of the output signal is ensured.
  • Figure 1 is a circuit diagram of a conventional phase interpolator
  • FIG. 2 is a schematic structural diagram of a phase interpolator circuit according to an embodiment of the present invention.
  • FIG. 3 is a circuit diagram of a PI CELL according to an embodiment of the present invention.
  • FIG. 4 is a general diagram of a PI circuit according to an embodiment of the present invention.
  • FIG. 5 is a schematic flow chart of a method for improving linearity of a phase interpolator circuit according to an embodiment of the present invention.
  • the ordinary phase interpolator circuit is affected by the nonlinearity of the current source.
  • the phase of the output clock is nonlinear, and the phase INL and DNL are often greater than 1LSB.
  • the embodiment of the present invention provides a phase interpolator circuit and a method for improving linearity thereof, which greatly reduces the INL and DNL of the phase phase of the phase interpolator, thereby improving the performance of the phase interpolator.
  • a conventional phase interpolator circuit includes a metal-oxide-semiconductor (MOS) tube 101. Up to 108, digital to analog converter (IDAC) 111, resistors 114, 115.
  • the IDAC output current varies linearly with the PIctrl signal, adjusting the current levels of the four sets of differential switching transistors 101 and 102, 103 and 104, 105 and 106, 107 and 108, and controlling CLK0, CLK90, CLK180, and CLK270 in the output clocks OUTP, OUTN. Weight, the function of phase adjustment.
  • the phase of the output clock is primarily determined by the weight of the four pairs of differential switch currents flowing through.
  • Phase interpolators with a speed exceeding GHz have a relatively large current consumption, so the tail current will be relatively large, and the size of the four pairs of differential switching tubes will increase accordingly. This will cause the parasitic capacitance of nodes A, B, C, and D to be large.
  • phase adjustment especially quadrant hopping, it is expected that the potentials of the four points A, B, C, and D can quickly jump from a very low voltage to several hundred mV, or from several hundred mV to a low voltage. Due to the influence of parasitic, the voltage change requires a certain response time, and the adjustment current will cause a deviation, which will cause the phase to be changed in time, which seriously affects the linearity of the phase interpolator.
  • the differential switch tubes 101 to 108 and IDAC 111 of the conventional phase interpolator circuit of FIG. 1 are split into N independent units.
  • the size of the tube of each individual unit is 1/N of the total size.
  • the phase of the phase interpolator is determined by the current weight of each quadrant, which is the number of cells.
  • phase interpolator circuit includes N phase interpolator units 21, N ⁇ 2; the phase interpolator unit 21 includes a differential switch transistor circuit 211, a current control circuit 212, and a bias current circuit 213, wherein
  • the differential switch transistor circuit 211 includes a first switch tube and a second switch tube; the first switch tube is connected to the clock signal input terminal through its first port, and is connected to the negative signal output terminal through its second port. And connected to the current control circuit 212 through its own third port; the second switch tube is connected to the clock signal input terminal through its first port, and is connected to the positive signal output terminal through its second port And through its third port with the electricity
  • the flow control circuit 212 is connected;
  • the current control circuit 212 is connected to the control signal input terminal through its first port, and is connected to the differential switch transistor circuit 211 through its second port, and passes through its own third port and the bias current circuit 213. connection;
  • the bias current circuit 213 is connected to the reference signal input terminal through its own first port, connected to the current control circuit 212 through its second port, and connected to the ground through its own third port.
  • the phase interpolator unit 21 includes four sets of differential switch tube circuits 211;
  • the first port of the first switch of the first set of differential switch circuit 211 is connected to the first clock signal input end, and the first port of the second switch tube is connected to the second clock signal input end;
  • the first port of the first switch tube of the second group of differential switch tube circuits 211 is connected to the third clock signal input end, and the first port of the second switch tube is connected to the fourth clock signal input end;
  • the first port of the first switch tube of the third group of differential switch tube circuits 211 is connected to the second clock signal input end, and the first port of the second switch tube is connected to the first clock signal input end;
  • the first port of the first switch tube of the fourth group of differential switch transistors 211 is connected to the fourth clock signal input end, and the first port of the second switch tube is connected to the third clock signal input end.
  • the phase interpolator unit 21 includes four sets of current control circuits 212;
  • the first port of the first set of current control circuit 212 is coupled to the first control signal input;
  • the first port of the second group of current control circuits 212 is coupled to the second control signal input terminal
  • the first port of the third group of current control circuits 212 is coupled to the third control signal input terminal;
  • the first port of the fourth set of current control circuits 212 is coupled to the fourth control signal input.
  • the negative signal output ends respectively connected to the four sets of differential switch tube circuits 211 are connected together, and the positive signal output ends respectively connected to the four sets of differential switch tube circuits 211 are respectively connected. connected.
  • the current control circuit 212 is connected to the differential switch transistor circuit 211 through its second port, specifically:
  • the current control circuit 212 is respectively connected to the third port of the first switch tube and the third port of the second switch tube in the differential switch tube circuit 211 through its second port.
  • the first switch tube, the second switch tube, the current control circuit 212, and the bias current circuit 213 are all N-type NMOS tubes.
  • the phase interpolator circuit further includes: a first resistor 22 and a second resistor 23, wherein
  • the first end of the first resistor 22 is connected to the power source, and the second end is connected to the negative signal output end;
  • the first end of the second resistor 23 is connected to the power source, and the second end is connected to the positive signal output end.
  • FIG. 3 is a circuit diagram of a PI CELL according to an embodiment of the present invention, wherein substrates of all NMOS transistors are connected to ground.
  • the drain of the NMOS transistor 101 is connected to the positive output terminal OUTN of the phase interpolator, the gate is connected to the phase interpolator input signal CLK0, and the source is connected to A.
  • the drain of the NMOS transistor 102 is connected to the negative output terminal OUTP of the phase interpolator, and the gate and phase interpolator input signal CLK180 Connected, the source is connected to A.
  • the drain of the NMOS transistor 103 is connected to the positive output terminal OUTN of the phase interpolator, the gate is connected to the phase interpolator input signal CLK90, and the source is connected to B.
  • the drain of the NMOS transistor 104 is connected to the negative output terminal OUTP of the phase interpolator, the gate is connected to the phase interpolator input signal CLK270, and the source is connected to B.
  • the drain of the NMOS transistor 105 is connected to the positive output terminal OUTN of the phase interpolator, the gate is connected to the phase interpolator input signal CLK180, and the source is connected to C.
  • the drain of the NMOS transistor 106 is connected to the negative output terminal OUTP of the phase interpolator, the gate is connected to the phase interpolator input signal CLK0, and the source is connected to C.
  • the drain of the NMOS transistor 107 is connected to the positive output terminal OUTN of the phase interpolator, the gate is connected to the phase interpolator input signal CLK270, and the source is connected to D.
  • the drain of the NMOS transistor 108 is connected to the negative output terminal OUTP of the phase interpolator, the gate is connected to the phase interpolator input signal CLK0, and the source is connected to D.
  • the gate of the NMOS transistor 109 is connected to ctrl0, the drain is connected to A, and the source is E.
  • the gate of the NMOS transistor 110 is connected to ctrl90, the drain is connected to B, and the source is connected to E.
  • the gate of the NMOS transistor 111 is connected to ctrl180, the drain is connected to C, and the source is connected to E.
  • the gate of the NMOS transistor 112 is connected to ctrl270, the drain is connected to D, and the source is connected to E.
  • the gate of the NMOS transistor 113 is connected to vref, the drain is connected to E, and the source is grounded.
  • FIG. 4 is a general diagram of a PI circuit according to an embodiment of the present invention.
  • the PI circuit is composed of a resistor and N PI CELLs. All PI CELL's OUTP and OUTN are connected together. PI ctrl is controlled by the digital circuit output.
  • One end of the resistor 114 is connected to the power supply, and the other end is connected to the output terminal OUTN of the phase interpolator.
  • One end of the resistor 115 is connected to the power supply, and the other end is connected to the output terminal OUTP of the phase interpolator.
  • FIG. 5 is a schematic flowchart of a method for improving linearity of a phase interpolator circuit according to an embodiment of the present invention. As shown in FIG. 5, the method includes:
  • Step 501 Adjust the weights of different quadrants when the phase adjustment is performed by the phase interpolator circuit, wherein the phase interpolator circuit includes N phase interpolator units, N ⁇ 2.
  • Step 502 Adjust the phase by the N phase interpolator units 21 in the phase interpolator circuit.
  • the phase interpolator unit 21 includes: a differential switch transistor circuit 211, a current control circuit 212, and a bias current circuit 213, where
  • the differential switch transistor circuit 211 includes a first switch tube and a second switch tube; the first switch tube is connected to the clock signal input terminal through its first port, and is connected to the negative signal output terminal through its second port. And connected to the current control circuit 212 through its own third port; the second switch tube is connected to the clock signal input terminal through its first port, and is connected to the positive signal output terminal through its second port And connected to the current control circuit 212 through its third port;
  • the current control circuit 212 is connected to the control signal input terminal through its first port, and is connected to the differential switch transistor circuit 211 through its second port, and passes through its own third port and the bias current circuit 213. connection;
  • the bias current circuit 213 is connected to the reference signal input terminal through its own first port, connected to the current control circuit 212 through its second port, and connected to the ground through its own third port.
  • phase interpolator circuit in this embodiment can be understood with reference to the phase interpolator circuit shown in FIGS. 1-3.

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Networks Using Active Elements (AREA)
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Abstract

La présente invention concerne un circuit d'interpolation de phases et un procédé d'amélioration de la linéarité de celui-ci, le circuit d'interpolation de phases comprenant N unités d'interpolation de phases, où N ≥ 2. Une unité d'interpolation de phases comprend un circuit de tubes de commutation différentiels, un circuit de régulation de courant, et un circuit de courant de polarisation, le circuit de tubes de commutation différentiels comprenant un premier tube de commutation et un second tube de commutation, le premier tube de commutation étant connecté à une borne d'entrée de signal d'horloge, à une borne de sortie de signal négatif et au circuit de régulation de courant, tandis que le second tube de commutation est connecté à la borne d'entrée de signal d'horloge, à une borne de sortie de signal positif et au circuit de régulation de courant. Le circuit de régulation de courant est connecté à une borne d'entrée de signal de commande, au circuit de tubes de commutation différentiels et au circuit de courant de polarisation. Le circuit de courant de polarisation est connecté à une borne d'entrée de signal de référence, au circuit de régulation de courant et à la terre.
PCT/CN2017/082609 2016-12-28 2017-04-28 Circuit d'interpolation de phases et procédé d'amélioration de la linéarité de celui-ci WO2018120555A1 (fr)

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CN201611239678.0 2016-12-28
CN201611239678.0A CN108259026B (zh) 2016-12-28 2016-12-28 一种相位插值器电路及其提升线性度的方法

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CN111697950B (zh) * 2020-06-23 2021-07-09 上海安路信息科技股份有限公司 本征线性相位插值器
CN114079459A (zh) * 2020-08-12 2022-02-22 上海钫铖微电子有限公司 高速串行接口芯片的非线性度测试方法及其装置
CN112165315A (zh) * 2020-09-25 2021-01-01 北京智芯微电子科技有限公司 线性相位插值器、线性相位插值芯片及数据时钟恢复电路

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CN1761184A (zh) * 2004-10-12 2006-04-19 美国博通公司 高速时钟和数据恢复系统
CN103297004A (zh) * 2012-02-15 2013-09-11 株式会社巨晶片 相位插值器
CN103795404A (zh) * 2012-10-31 2014-05-14 中兴通讯股份有限公司 一种相位插值器电路及相位插值信号处理方法
CN105991112A (zh) * 2015-07-06 2016-10-05 龙迅半导体（合肥）股份有限公司 一种数据时钟恢复电路及其相位插值器

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Publication number Priority date Publication date Assignee Title
CN106027037B (zh) * 2016-03-03 2019-01-25 北京大学 一种高线性度的数控相位插值器

Patent Citations (4)

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Publication number Priority date Publication date Assignee Title
CN1761184A (zh) * 2004-10-12 2006-04-19 美国博通公司 高速时钟和数据恢复系统
CN103297004A (zh) * 2012-02-15 2013-09-11 株式会社巨晶片 相位插值器
CN103795404A (zh) * 2012-10-31 2014-05-14 中兴通讯股份有限公司 一种相位插值器电路及相位插值信号处理方法
CN105991112A (zh) * 2015-07-06 2016-10-05 龙迅半导体（合肥）股份有限公司 一种数据时钟恢复电路及其相位插值器

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