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WO2018120731A1 - Procédé de fabrication d'une tranche épitaxiale de silicium - Google Patents

Procédé de fabrication d'une tranche épitaxiale de silicium Download PDF

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Publication number
WO2018120731A1
WO2018120731A1 PCT/CN2017/091796 CN2017091796W WO2018120731A1 WO 2018120731 A1 WO2018120731 A1 WO 2018120731A1 CN 2017091796 W CN2017091796 W CN 2017091796W WO 2018120731 A1 WO2018120731 A1 WO 2018120731A1
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WO
WIPO (PCT)
Prior art keywords
layer
growth
silicon
flow rate
slm
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Application number
PCT/CN2017/091796
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English (en)
Chinese (zh)
Inventor
刘勇
金龙
谭卫东
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南京国盛电子有限公司
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Publication of WO2018120731A1 publication Critical patent/WO2018120731A1/fr

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    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B25/00—Single-crystal growth by chemical reaction of reactive gases, e.g. chemical vapour-deposition growth
    • C30B25/02—Epitaxial-layer growth
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
    • C30B29/02—Elements
    • C30B29/06—Silicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD

Definitions

  • the invention relates to a silicon epitaxial wafer, that is, a method for manufacturing an ultrathin layer low resistance epitaxial wafer.
  • the monolithic atmospheric pressure epitaxial device with SiHCl 3 as the silicon source tends to have a growth rate of more than 2 ⁇ m/min, while for the 8-inch ultra-thin layer epitaxy with an epitaxial layer thickness of less than 2 ⁇ m, the faster growth rate leads to poor uniformity of the epitaxial layer thickness.
  • the transition region between the epitaxial layer and the substrate is wider, which reduces the effective thickness of the epitaxial layer and cannot meet the requirements of the device end (the theoretical longitudinal resistivity distribution of the device end requirement is shown in FIG. 2).
  • thin layer epitaxy of less than 2 ⁇ m for 8-inch silicon epitaxial products often uses decompression epitaxy or replacement of other silicon sources such as silane (SiH 4 ), which requires additional production costs and reduces the compatibility of atmospheric pressure epitaxy equipment.
  • SiH 4 silane
  • the invention proposes a novel manufacturing method of the epitaxial wafer, which can be optimized compared with the conventional epitaxial method.
  • Epitaxial layer thickness and resistivity uniformity optimize the transition region width of the substrate and epitaxial layer.
  • the present invention can adopt the following technical solutions:
  • a method for manufacturing a silicon epitaxial wafer comprising the steps of:
  • First layer epitaxial growth an intrinsic layer is grown on the surface of the substrate to encapsulate the surface of the substrate;
  • Second layer epitaxial growth When the second layer is epitaxially grown, HCl and TCS are simultaneously introduced, wherein 0.5-1 slm of HCl, 2-5 g of TCS, and 120-180 slm of H2 are introduced.
  • the method for fabricating the epitaxial wafer of the present invention can optimize the thickness and resistivity uniformity of the 8-inch ultra-thin epitaxial layer and optimize the transition region width of the substrate and the epitaxial layer as compared with the conventional epitaxial method.
  • HCl and TCS are simultaneously introduced during the epitaxial growth of the two layers, in order to reduce the growth thickness of the epitaxial layer and suppress the self-doping effect of the silicon wafer, which plays a key role in achieving the above technical effects.
  • the susceptor is cooled to 850 °C.
  • the baking temperature is 1150-1180 ° C
  • the baking time is 40 seconds
  • the H 2 flow rate is 120-180 slm.
  • the appropriate epitaxial conditions for the first layer epitaxial growth are: baking temperature 1150-1180 ° C, baking main H 2 flow rate is 120-180 slm; first layer epitaxy, growth temperature 1100-1130 ° C, precipitation The product rate is 0.8-1.0 ⁇ m/min; when the second layer is epitaxially grown, the temperature is 1100-1130 ° C, and the deposition rate is 0.4-0.6 ⁇ m/min.
  • the first layer is epitaxially grown without doping
  • the second layer is doped epitaxially grown with an H2 flow rate of 120-180 slm.
  • the deposition is selected to be: a growth temperature of 1100-1130 ° C, a growth silicon source flow rate of 2-5 g, a growth HCl flow rate of 0.5-1 slm, and a growth main H 2 flow rate of 120-180 slm.
  • the substrate sheet is selected: an 8-inch heavy-doped phosphorus-silicon polished sheet is used, the resistivity is ⁇ 0.001 ⁇ cm, the partial flatness of the substrate sheet is ⁇ 1.5 m (10 mm ⁇ 10 mm); the silicon dioxide back sealing layer (LTO) ) + Polysilicon back seal (Poly) back seal.
  • LTO silicon dioxide back sealing layer
  • Poly Polysilicon back seal
  • Figure 1 is a process flow diagram of an 8-inch thin layer epitaxy
  • FIG. 2 is a schematic view showing the longitudinal structure of an 8-inch thin layer epitaxial layer
  • Figure 3 is a structural diagram of the ASM E2000 reaction chamber
  • Figure 4 shows the measured longitudinal carrier distribution of an 8-inch thin-layer epitaxial layer.
  • the invention discloses a method for manufacturing an epitaxial wafer, which is preferably suitable for the manufacture of an 8-inch ultra-thin layer low-resistance epitaxial wafer.
  • Embodiment 1 is a diagrammatic representation of Embodiment 1:
  • the manufacturing method of an 8-inch ultra-thin layer low-resistance epitaxial wafer of this embodiment comprises the following steps:
  • the device used in the invention is the American ASM E2000 silicon epitaxial growth system. As shown in FIG. 3, the high-purity graphite base is used as the infrared heating body, and the purity of the main carrier gas H2 is 99.9999% or more.
  • Reaction chamber cleaning The quartz bell and the quartz parts used in the reaction chamber must be carefully cleaned before the epitaxy to completely remove the deposition residue on the inner wall of the quartz bell jar and the quartz piece.
  • the first step high temperature treatment of the reaction chamber: before each epitaxial growth, the graphite pedestal must be subjected to high temperature treatment of HC1 to remove residual reactants on the susceptor and deposit a layer of intrinsic polycrystalline silicon.
  • the second step cooling the reaction chamber to a low temperature (850 ° C), loading the substrate wafer.
  • the third step heating to 1150 ° C, H 2 flow 100slm, and holding for 30 seconds for wafer baking, reducing epitaxial layer defects.
  • the fourth step the first intrinsic epitaxial layer, 1100 ° C, 2 g of silicon source, 120 slm of main H2, deposition rate of 0.8 ⁇ m / min, growth time of 7 seconds.
  • Step 5 The temperature is set to 1100 ° C, H 2 is 120 slm, and the blow is performed for 10 seconds.
  • the sixth step the second layer growth temperature is 1100 ° C, the HCl flow rate is 0.5 slm, and the silicon source is 2 g. At this time, the HCl and the silicon source are simultaneously introduced for growth, the main H2 is 120 slm, and the deposition rate is 0.4-0.6 ⁇ m/min. The growth time is 82 seconds.
  • the first three steps are the same as those described in the first embodiment.
  • the fourth step the first intrinsic epitaxial layer, 1120 ° C, 3 g of silicon source, 150 slm of main H2, deposition rate of 0.8 ⁇ m / min, growth time of 7 seconds.
  • Step 5 The temperature is set to 1130 ° C, H 2 is 150 slm, and the blow is performed for 90 seconds.
  • the sixth step the second layer growth temperature is 1120 ° C, the HCl flow rate is 0.8 slm, and the silicon source is 3 g. At this time, the HCl and the silicon source are simultaneously introduced for growth, the main H2 is 150 slm, and the deposition rate is 0.4-0.6 ⁇ m/min. The growth time is 82 seconds.
  • the first three steps are the same as those described in the first embodiment.
  • the fourth step the first intrinsic epitaxial layer, 1130 ° C, 5 g of silicon source, 180 slm of main H2, deposition rate of 0.8 ⁇ m / min, growth time of 7 seconds.
  • Step 5 The temperature is set to 1150 ° C, H 2 is 120 slm, and the blow is performed for 120 seconds.
  • the sixth step the second layer growth temperature is 1130 ° C, the HCl flow rate is 1 slm, and the silicon source is 5 g. At this time, the HCl and the silicon source are simultaneously introduced for growth, the main H2 is 180 slm, and the deposition rate is 0.4-0.6 ⁇ m/min. The growth time is 82 seconds.
  • the prepared silicon epitaxial wafer After testing the silicon epitaxial wafer manufactured by the methods of Embodiments 1, 2 and 3, the prepared silicon epitaxial wafer has a good lattice structure, the surface is bright and has no fine spots, no warping and edge crystallization, and enters the gas phase. The impurity is less, the self-doping effect is reduced, the dislocation is ⁇ 100/cm 2 , and the stacking fault is ⁇ 10/cm 2 .
  • the epitaxial thickness is less than 0.7 ⁇ m
  • the epitaxial transition region is less than 0.2 ⁇ m
  • the longitudinal resistivity distribution diagram is as shown in the figure. 4, fully meet the requirements of device fabrication.

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  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Materials Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)

Abstract

L'invention concerne un procédé de fabrication d'une tranche épitaxiale de silicium, comprenant le processus technique suivant : tout d'abord, un appareil monolithique d'épitaxie du silicium à pression atmosphérique est utilisé et un débit d'H2, une température et une durée appropriés sont sélectionnés pour effectuer un traitement de cuisson sur une tranche de silicium de substrat pour éliminer une couche d'oxyde naturelle sur la surface et assurer la qualité de la surface avant l'épitaxie. Une première couche est obtenue par croissance épitaxiale : une couche intrinsèque non dopée est développée sur la surface du substrat fortement dopé pour encapsuler la surface du substrat, et la température de croissance, la vitesse de croissance et le temps de croissance de la couche intrinsèque sont régulés pour obtenir un effet d'encapsulation souhaitable. Une seconde couche est obtenue par croissance épitaxiale : du SiHCl3 est utilisé en tant que source de silicium, le débit d'H2 principal est augmenté, et du HCl alimenté à un débit approprié, de façon à réduire le taux de croissance pour faire croître une couche épitaxiale plus mince ayant une épaisseur satisfaisant à une exigence pour un dispositif.
PCT/CN2017/091796 2016-12-26 2017-07-05 Procédé de fabrication d'une tranche épitaxiale de silicium WO2018120731A1 (fr)

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* Cited by examiner, † Cited by third party
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CN113808916A (zh) * 2021-07-30 2021-12-17 中国电子科技集团公司第五十五研究所 一种n型重掺杂薄层氮化镓材料的二次外延方法
CN115305566A (zh) * 2022-10-12 2022-11-08 广州粤芯半导体技术有限公司 外延层的制备方法以及含外延层的半导体
CN116005254A (zh) * 2022-12-26 2023-04-25 西安奕斯伟材料科技有限公司 外延生长方法及外延硅片
CN116525419A (zh) * 2023-06-09 2023-08-01 中电科先进材料技术创新有限公司 一种coolmos用硅外延片的制备方法
CN116525418A (zh) * 2023-06-09 2023-08-01 中电科先进材料技术创新有限公司 基于111晶向的硅外延片制备方法、硅外延片及半导体器件
CN119433693A (zh) * 2024-10-28 2025-02-14 国芯半导体(仪征)有限公司 一种半导体硅外延片材料及其制备方法

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CN108054082A (zh) * 2017-12-06 2018-05-18 上海华力微电子有限公司 一种cis之衬底结构及其制备方法
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CN110592665A (zh) * 2019-08-09 2019-12-20 上海新昇半导体科技有限公司 一种半导体薄膜平坦度改善的方法
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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4592792A (en) * 1985-01-23 1986-06-03 Rca Corporation Method for forming uniformly thick selective epitaxial silicon
CN101245489A (zh) * 2007-02-14 2008-08-20 北京行者多媒体科技有限公司 纳米晶硅的形成方法
CN101256958A (zh) * 2008-04-08 2008-09-03 南京国盛电子有限公司 一种igbt硅外延片的制造方法
CN103541001A (zh) * 2013-10-31 2014-01-29 中国电子科技集团公司第四十六研究所 一种改善外延片电阻率和厚度一致性的制备方法
CN104947183A (zh) * 2015-05-29 2015-09-30 中国电子科技集团公司第四十六研究所 一种肖特基器件用重掺薄磷衬底上硅外延层的制备方法
CN106757324A (zh) * 2016-12-26 2017-05-31 南京国盛电子有限公司 一种硅外延片的制造方法

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100390937C (zh) * 2006-04-17 2008-05-28 南京国盛电子有限公司 5英寸功率mos管用硅外延片的制造方法
CN100449692C (zh) * 2007-04-11 2009-01-07 河北普兴电子科技股份有限公司 一种重掺砷衬底的硅外延方法
CN101333677A (zh) * 2007-06-25 2008-12-31 北京有色金属研究总院 300mm薄层外延工艺
CN102254796B (zh) * 2010-05-20 2014-05-21 上海华虹宏力半导体制造有限公司 形成交替排列的p型和n型半导体薄层的方法
CN102468133A (zh) * 2010-11-15 2012-05-23 上海华虹Nec电子有限公司 一种具有沟槽的半导体结构的形成方法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4592792A (en) * 1985-01-23 1986-06-03 Rca Corporation Method for forming uniformly thick selective epitaxial silicon
CN101245489A (zh) * 2007-02-14 2008-08-20 北京行者多媒体科技有限公司 纳米晶硅的形成方法
CN101256958A (zh) * 2008-04-08 2008-09-03 南京国盛电子有限公司 一种igbt硅外延片的制造方法
CN103541001A (zh) * 2013-10-31 2014-01-29 中国电子科技集团公司第四十六研究所 一种改善外延片电阻率和厚度一致性的制备方法
CN104947183A (zh) * 2015-05-29 2015-09-30 中国电子科技集团公司第四十六研究所 一种肖特基器件用重掺薄磷衬底上硅外延层的制备方法
CN106757324A (zh) * 2016-12-26 2017-05-31 南京国盛电子有限公司 一种硅外延片的制造方法

Cited By (8)

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CN113808916A (zh) * 2021-07-30 2021-12-17 中国电子科技集团公司第五十五研究所 一种n型重掺杂薄层氮化镓材料的二次外延方法
CN113808916B (zh) * 2021-07-30 2024-03-08 中国电子科技集团公司第五十五研究所 一种n型重掺杂薄层氮化镓材料的二次外延方法
CN115305566A (zh) * 2022-10-12 2022-11-08 广州粤芯半导体技术有限公司 外延层的制备方法以及含外延层的半导体
CN116005254A (zh) * 2022-12-26 2023-04-25 西安奕斯伟材料科技有限公司 外延生长方法及外延硅片
CN116525419A (zh) * 2023-06-09 2023-08-01 中电科先进材料技术创新有限公司 一种coolmos用硅外延片的制备方法
CN116525418A (zh) * 2023-06-09 2023-08-01 中电科先进材料技术创新有限公司 基于111晶向的硅外延片制备方法、硅外延片及半导体器件
CN116525419B (zh) * 2023-06-09 2024-02-13 中电科先进材料技术创新有限公司 一种coolmos用硅外延片的制备方法
CN119433693A (zh) * 2024-10-28 2025-02-14 国芯半导体(仪征)有限公司 一种半导体硅外延片材料及其制备方法

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