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WO2018121369A1 - Transistor à semiconducteur composé et amplificateur de puissance ayant le transistor - Google Patents

Transistor à semiconducteur composé et amplificateur de puissance ayant le transistor Download PDF

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Publication number
WO2018121369A1
WO2018121369A1 PCT/CN2017/117362 CN2017117362W WO2018121369A1 WO 2018121369 A1 WO2018121369 A1 WO 2018121369A1 CN 2017117362 W CN2017117362 W CN 2017117362W WO 2018121369 A1 WO2018121369 A1 WO 2018121369A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
collector
compound semiconductor
thickness
semiconductor transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2017/117362
Other languages
English (en)
Chinese (zh)
Inventor
颜志泓
王江
朱庆芳
魏鸿基
窦永铭
许燕丽
李斌
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Xiamen Sanan Integrated Circuit Co Ltd
Original Assignee
Xiamen Sanan Integrated Circuit Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from CN201611215467.3A external-priority patent/CN106683993A/zh
Priority claimed from CN201611216552.1A external-priority patent/CN106653826B/zh
Application filed by Xiamen Sanan Integrated Circuit Co Ltd filed Critical Xiamen Sanan Integrated Circuit Co Ltd
Publication of WO2018121369A1 publication Critical patent/WO2018121369A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y30/00—Nanotechnology for materials or surface science, e.g. nanocomposites
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D10/00—Bipolar junction transistors [BJT]
    • H10D10/80—Heterojunction BJTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies

Definitions

  • the present invention relates to semiconductor technology, and more particularly to a compound semiconductor transistor.
  • the heterojunction bipolar transistor epitaxial structure is selected in the collector layer design to form a so-called single heterojunction or double heterojunction transistor with a homogenous or heterogeneous material of the base layer.
  • the sub-collector layer is designed to form a collector ohmic metal contact in a highly viscous concentration mode or a thicker thickness mode. Therefore, the stray resistance of the collector is determined by the high concentration and thickness of the sub-collector layer, and the metal annealing process in the subsequent process; the design of the device layout from the collector to the base is also Its stray resistance has an effect. The presence of stray resistance affects the performance of heterojunction bipolar transistors.
  • Common methods for reducing stray collector resistance include: (1) Optimal design of device layout from collector to base distance, but this method has a certain distance limitation, and the distance is at least 1 to 1.8 micrometers. (2) increasing the thickness of the secondary collector layer and the high concentration, but the method increases the thickness of the secondary collector layer, which increases the difficulty in the chip process stage, including the device morphology during the wet etching process.
  • a compound semiconductor heterojunction bipolar transistor comprising a collector layer, a sub-collector layer, and an intermediate portion between the collector layer and the sub-collector layer
  • the collector layer and the sub-collector layer are respectively composed of GaAs
  • the intermediate layer includes a material having an energy gap smaller than GaAs.
  • the intermediate layer is composed of InxGaAs, where 0 ⁇ x ⁇ 0.4.
  • the thickness of the intermediate layer is 0.5% to 1% of the thickness of the collector layer.
  • the intermediate layer is composed of an InxGaAs/GaAs superlattice structure, where 0 ⁇ x ⁇ 0.4.
  • the period of the superlattice structure ranges from 1 to 100.
  • the secondary collector layer has a higher concentration than the collector layer, or the secondary collector layer has a thickness greater than the collector layer; and the secondary collector layer has a set formed thereon. Electrode electrode.
  • a base layer disposed on the collector layer and composed of GaAs disposed on the collector layer and composed of GaAs
  • an emitter layer disposed on the base layer and composed of InGaP An emitter contact gap layer formed on the emitter layer and composed of GaAs
  • a low energy gap material is introduced between the collector layer and the sub-collector layer to form an intermediate layer, and the thickness and the impurity concentration of the sub-collector are under ordinary conditions, and the stray resistance of the collector can be reduced.
  • the value of the DC power consumption of the amplifier component based on the compound semiconductor heterojunction bipolar transistor power is improved, and the additional power efficiency of the device is improved.
  • the power amplifier based on the above structure is applied to a handheld device such as a mobile phone, and the standby time can be increased.
  • a method of fabricating a transistor ohmic contact electrode comprising the steps of:
  • the metal layer further includes a first Ti layer formed on the first Pt layer and having a thickness of 20-60 nm; and a second Pt layer formed on the first Ti layer , a thickness of 10-50 nm; an Au layer formed on the second Pt layer, having a thickness of 20-500
  • the semiconductor substrate further includes a protective layer disposed on the InGaP layer, the photoresist is applied to the surface of the protective layer; and in step 2), further including etching to remove the display A protective layer in the region exposes the surface of the InGaP layer.
  • the protective layer is SiN.
  • the p-type GaAs layer forms at least a portion of a base of the heterojunction bipolar transistor
  • the In GaP layer forms at least a portion of an emitter of the heterojunction bipolar transistor
  • the electrode forms a different At least a portion of the base electrode of the bipolar transistor.
  • the semiconductor substrate further comprises a GaAs layer, wherein the p-type GaAs layer is disposed on the GaAs layer; and the GaAs layer forms at least a portion of a collector of the heterojunction bipolar transistor.
  • the above method uses a superalloy process to make the metal have a sufficient diffusion depth to diffuse through the InGaP layer and achieve ohmic contact with the p-type GaAs layer, thereby reducing the step of etching the InGaP layer, so that the whole
  • the process is simple, economical, and the controllability is greatly improved, avoiding various problems that may be caused by etching at this step, improving product yield and production efficiency; forming ohmic contact contact resistance, thermal stability High surface quality, especially suitable for the production process of HBT, BIFET, BIHEMT and other products.
  • Embodiment 1 is a schematic view showing an epitaxial structure of Embodiment 1 of the present invention.
  • Embodiment 2 is a schematic diagram showing a partial epitaxial structure of Embodiment 2 of the present invention.
  • Embodiment 3 is a schematic flow chart of Embodiment 3 of the present invention.
  • FIG. 4 is a schematic structural view of a metal layer in FIG. 3;
  • Embodiment 4 is a schematic flow chart of Embodiment 4 of the present invention.
  • an epitaxial structure of a compound semiconductor heterojunction bipolar transistor includes a substrate 1, a sub-collector layer 2, an intermediate layer 3, which are sequentially stacked from bottom to top.
  • the collector layer 4 the base layer 5, the emitter layer 6, the emitter contact gap layer 7, and the emitter contact layer 8.
  • the substrate 1 is semi-insulating GaAs; the sub-collector layer 2 and the collector layer 4 are n-type GaAs, and the sub-collector layer 2 has a higher concentration than the collector layer 4;
  • the intermediate layer 3 is InxGaAs, where 0 ⁇ x ⁇ 0.4;
  • the base layer 5 is p-type GaAs, the emitter layer 6 is InGaP, and a heterojunction is formed therebetween;
  • the emitter contact gap layer 7 is n-type GaAs, emission
  • the contact layer 8 is InGaAs.
  • the epitaxial structure is formed by crystal growth by MOCVD (Organic Metal Chemical Vapor Growth) or MBE (Molecular Beam Epitaxy), and a collector electrode and a base are formed on the sub-collector layer 2 by etching, metal deposition, or the like, respectively.
  • a base electrode is formed on layer 5 and an emitter electrode is formed on emitter contact layer 8.
  • the intermediate layer 3 is an InxGaAs having a smaller energy gap than GaAs, and the thickness is 0.5% to 1% of the collector layer 4. Specifically, the thickness of the intermediate layer 3 is not exceeded after the stress compensation according to the Mattews and Blakeslee model. Calculating the critical thickness, by changing the barrier layer of the energy band in the semiconductor technology, the collector stray resistance and the ohmic contact resistance of the collector metal can be reduced without increasing the thickness of the sub-collector layer 2 or Degree, only need to follow the conventional annealing conditions. For example, the thickness of the conventional sub-collector layer is 0.3 to 0.8 ⁇ , and the thickness of the collector layer is 0.5 to 1.2 ⁇ m.
  • an InxGaAs intermediate layer having a thickness of 3 to 15 ⁇ is formed therebetween.
  • the purpose of lowering the barrier can be significantly reduced, and as the composition of In increases (X value becomes larger), the barrier layer becomes lower, and the effect is more remarkable.
  • the HBT of the present embodiment can be applied to a 3G/4G power amplifier.
  • additional power efficiency (PAE) is an important parameter.
  • the PAE is defined as the ratio of the difference between the output power Pout and the input power Pin to the DC input power Pdc: (P OU t-Pin) / Pd C .
  • the PAE is a pointer indicating the quality of efficiency, and the larger the value, the more the power consumption of the power amplifier can be suppressed.
  • the stray resistance value of the collector layer is lowered by the arrangement of the intermediate layer 3, that is, the DC power of the device is lowered, the PAE is improved, and the overall performance is improved.
  • the above 3G/4G power amplifier is applied to a handheld device such as a mobile phone to increase standby time.
  • the difference between the HBT epitaxial structure of Embodiment 2 and Embodiment 1 is that the intermediate layer 9 is composed of an InxGa As/GaAs superlattice structure, where 0 ⁇ x ⁇ 0.4.
  • the InxGaAs/GaAs superlattice structure is a multilayer film in which an InxGaAs thin layer 91 and a GaAs thin layer 92 are alternately grown and maintained strictly periodic, each of which has a thickness ranging from several nanometers to several tens of nanometers.
  • the thickness of the InxGaAs thin layer 91 in the superlattice structure is not more than the critical thickness calculated according to the Mattews and Blakeslee model after stress compensation.
  • the superlattice structure of the intermediate layer 9 has a thin layer 91 of InxGaAs at both ends, and the period ranges from 1 to 100.
  • the quantum well is formed by the InxGaAs/Ga As superlattice structure, and the carrier concentration in the quantum well is increased by the increase of the In composition, thereby reducing the collector stray resistance and the collector metal ohmic contact resistance.
  • the x values of the respective InxGaAs thin layers 91 may be the same or different.
  • a heterojunction bipolar transistor generally includes a collector layer, a base layer, and an emitter layer which are sequentially stacked.
  • a base electrode is formed, and an etch process is required to even the emitter layer.
  • Part of the base layer is removed by exposing the base layer with a germanium window, and then depositing metal on the exposed base layer and forming a low resistance, stable contact ohmic contact between the metal and the base layer.
  • etching methods include dry etching and wet etching.
  • the dry etching is performed by plasma bombardment of the surface of the emitter layer that is not covered by the photoresist, and the wet etching is performed by using chemistry.
  • the solution removes the surface of the emitter that is not covered by the photoresist by dissolution or reaction, thereby reaching a portion The purpose of removal.
  • the following embodiment discloses a method of fabricating a transistor ohmic contact electrode that overcomes the deficiencies of the prior art described above.
  • the following examples are specifically described by taking the preparation method of the HBT base electrode as an example.
  • a semiconductor substrate of an HBT is first provided or formed.
  • the semiconductor substrate includes a collector layer-GaAs layer 11 stacked in order from bottom to top, a base layer-heavy p-type GaAs layer 12, and an emitter.
  • InGaP/GaAs HBTs are characterized by high power density and high efficiency and are widely used in power amplifiers.
  • a photoresist 14 is coated on the surface of the InGaP layer 13, and a conventional process such as exposure, development, and the like is performed to form a display region a at a predetermined base electrode position, and a bottom portion of the display region a is formed. InGaP bare.
  • the metal is then deposited and the photoresist and the metal over the photoresist are removed by lift-off to form a metal layer 15 corresponding to the exposed region a.
  • the method of deposition is generally physical vapor deposition. This metal deposition method gives a better metal tearing effect.
  • the metal layer 15 includes at least Pt which is in direct contact with the InGaP layer 13 and has a thickness of 20 to 50 nm.
  • the metal layer 15 is a stacked structure of Pt/i/Pt/Au/Ti, from bottom to top: first Pt layer 51, thickness 20-50 nm; first Ti Layer 52, having a thickness of 20-60 nm; a second Pt layer 53, having a thickness of 10-50 nm; an Au layer 54, having a thickness of 20-500 nm; and a second Ti layer 55 having a thickness of 5-20 nm.
  • the first Pt layer 51 diffuses through the InGaP layer 13 and at least partially enters the p-type GaAs layer 12, forming a high impurity layer at the contact interface, thereby forming an ohmic contact with the p-type GaAs layer 12, completing the base electrode Production.
  • Pt as the underlying metal, the work function is large, which is convenient to reduce the contact barrier height, and the diffusion performance is also better.
  • the alloying process is preferably carried out under the protection of an inert atmosphere to avoid other unnecessary reactions such as metal oxidation. During the heat preservation process, metals and semiconductors can significantly reduce the barrier height of the gold half-contact region by a series of physical and chemical reactions, and electrons easily pass through the gold half-contact region, thereby forming Low resistance and high stability ohmic contact.
  • the semiconductor substrate further includes a protective layer 16 disposed over the InG aP layer 13.
  • the photoresist 14 is applied to the surface of the protective layer 16. After a conventional process such as exposure, development, or the like is performed on the photoresist 14, a germanium region a is formed at a predetermined base electrode position, the protective layer within the germanium region a is removed by etching to expose the InGaP layer 13 and then deposited with a metal.
  • Metal layer 15 is disposed over the InG aP layer 13.
  • the protective layer 16 is specifically SiN, which is formed by magnetron sputtering, ion evaporation, arc ion evaporation, chemical vapor deposition, etc., to isolate the influence of water vapor and corrosive substances on the InGaP layer 13, and further improve the stability of the transistor.

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  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Nanotechnology (AREA)
  • Manufacturing & Machinery (AREA)
  • Composite Materials (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Materials Engineering (AREA)
  • Bipolar Transistors (AREA)

Abstract

L'invention concerne un transistor à semiconducteur composé et un amplificateur de puissance ayant le transistor. Le transistor comprend une couche collectrice (4), une couche collectrice secondaire (2), et une couche intermédiaire (3) disposée entre la couche collectrice (4) et la couche collectrice secondaire (2). La couche collectrice (4) et la couche collectrice secondaire (2) sont respectivement constituées de GaAs. La couche intermédiaire (3) comprend un matériau ayant une bande interdite inférieure à celle du GaAs.
PCT/CN2017/117362 2016-12-26 2017-12-20 Transistor à semiconducteur composé et amplificateur de puissance ayant le transistor Ceased WO2018121369A1 (fr)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
CN201611215467.3A CN106683993A (zh) 2016-12-26 2016-12-26 一种晶体管欧姆接触电极的制备方法
CN201611216552.1A CN106653826B (zh) 2016-12-26 2016-12-26 一种化合物半导体异质接面双极晶体管
CN201611215467.3 2016-12-26
CN201611216552.1 2016-12-26

Publications (1)

Publication Number Publication Date
WO2018121369A1 true WO2018121369A1 (fr) 2018-07-05

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PCT/CN2017/117362 Ceased WO2018121369A1 (fr) 2016-12-26 2017-12-20 Transistor à semiconducteur composé et amplificateur de puissance ayant le transistor

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1667836A (zh) * 2004-03-08 2005-09-14 松下电器产业株式会社 异质结双极型晶体管及其制造方法
US20050199909A1 (en) * 2004-03-09 2005-09-15 Keiichi Murayama Heterojunction bipolar transistor and manufacturing method thereof
CN101533841A (zh) * 2008-03-13 2009-09-16 松下电器产业株式会社 半导体器件及其制造方法
CN106653826A (zh) * 2016-12-26 2017-05-10 厦门市三安集成电路有限公司 一种化合物半导体异质接面双极晶体管
CN106683993A (zh) * 2016-12-26 2017-05-17 厦门市三安光电科技有限公司 一种晶体管欧姆接触电极的制备方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1667836A (zh) * 2004-03-08 2005-09-14 松下电器产业株式会社 异质结双极型晶体管及其制造方法
US20050199909A1 (en) * 2004-03-09 2005-09-15 Keiichi Murayama Heterojunction bipolar transistor and manufacturing method thereof
CN101533841A (zh) * 2008-03-13 2009-09-16 松下电器产业株式会社 半导体器件及其制造方法
CN106653826A (zh) * 2016-12-26 2017-05-10 厦门市三安集成电路有限公司 一种化合物半导体异质接面双极晶体管
CN106683993A (zh) * 2016-12-26 2017-05-17 厦门市三安光电科技有限公司 一种晶体管欧姆接触电极的制备方法

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