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WO2018121469A1 - Système et procédé d'étalonnage de retard d'horloge de haute précision - Google Patents

Système et procédé d'étalonnage de retard d'horloge de haute précision Download PDF

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Publication number
WO2018121469A1
WO2018121469A1 PCT/CN2017/118233 CN2017118233W WO2018121469A1 WO 2018121469 A1 WO2018121469 A1 WO 2018121469A1 CN 2017118233 W CN2017118233 W CN 2017118233W WO 2018121469 A1 WO2018121469 A1 WO 2018121469A1
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Prior art keywords
output
multiplexer
processing module
calibration
delay
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Ceased
Application number
PCT/CN2017/118233
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English (en)
Chinese (zh)
Inventor
叶立平
唐可信
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shenzhen Akusense Technology Co Ltd
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Shenzhen Akusense Technology Co Ltd
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Publication of WO2018121469A1 publication Critical patent/WO2018121469A1/fr
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/135—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of time reference signals, e.g. clock signals

Definitions

  • the invention belongs to the technical field of computers, and in particular relates to a system and method for high precision delayed clock calibration.
  • precise delay is the key to the whole system, but the actual value of the delay is affected by the external environment such as temperature.
  • the MC100EP196 of ON Semiconductor has a large temperature drift effect. Time calibration is an important measure to improve the accuracy of the entire system.
  • a second object of the present invention is to provide a delayed clock calibration method that solves the technical problem of delayed clock calibration.
  • a system for delaying clock calibration comprising a NAND gate, an AND gate, a delay chip, a multiplexer and a processing module, the multiplexer comprising a calibration output and a clock output, the processing module including a delay Control terminal, selection control terminal and control switch terminal;
  • the two input ends of the AND gate are respectively connected to the output end of the NAND gate and the clock input end; the output end of the AND gate is connected to the input end of the multiplexer via the delay chip, and the delay of the processing module
  • the control end and the selection control end are respectively connected to the control end of the delay chip and the control end of the multiplexer, and the two input ends of the NAND gate are respectively connected to the control switch end of the processing module and the calibration of the multiplexer Output
  • the selection control end of the processing module and the control switch end have the same output logic.
  • the multiplexer When the selection control end of the processing module outputs a high level, the multiplexer outputs a calibration signal through the calibration output end, and at the selection control end of the processing module When the output is low, the multiplexer outputs a clock signal through the clock output.
  • a frequency divider is further included, and the calibration output of the multiplexer is electrically connected to the processing module through a frequency divider.
  • the multiplexer is a two-way selector.
  • the model of the time delay chip is MC100EP196.
  • the present invention also provides a system for delay clock calibration, comprising a NOT gate, an AND gate, a delay chip, a multiplexer and a processing module, the multiplexer including a calibration output and a clock output.
  • the processing module includes a delay control terminal and a selection control terminal;
  • the two input ends of the AND gate are respectively connected to the output terminal of the NOT gate and the clock input terminal;
  • the output end of the AND gate is connected to the input end of the multiplexer via a delay chip, and the delay control of the processing module
  • the terminal and the selection control terminal are respectively connected to the control end of the delay chip and the control end of the multiplexer, and the input terminals of the NOT gate are respectively connected to the control switch end of the processing module and the calibration output end of the multiplexer;
  • the multiplexer When the selection control terminal of the processing module outputs a high level, the multiplexer outputs a calibration signal through the calibration output terminal, and when the selection control terminal of the processing module outputs a low level, the multiplexer outputs a clock signal through the clock output terminal.
  • a frequency divider is further included, and the calibration output of the multiplexer is electrically connected to the processing module through a frequency divider.
  • the present invention also provides a delay clock calibration method, including the following steps:
  • the preset range is K.
  • the invention adopts the pulse oscillation counting method to realize the pulse width measurement, and then performs the delay calculation, and finally adjusts the delay chip to achieve the purpose of the delay calibration.
  • the method is economical to use, can be calibrated in real time, and excludes temperature and other external delays. The effect of the chip, thus achieving the effect of high-precision measurement.
  • 1 is a block diagram showing the structure of a system for high-precision delayed clock of the first embodiment
  • Figure 2 is a circuit diagram of Figure 1;
  • FIG. 3 is a structural block diagram of a system for high-precision delayed clock of the second embodiment
  • FIG. 4 is a flow chart of a method of accurately delaying a clock of the present invention.
  • Embodiment 1 is a diagrammatic representation of Embodiment 1:
  • the embodiment provides a delay clock calibration system, including a NAND gate, an AND gate, a delay chip, a multiplexer, a frequency divider, and a processing module, where the multiplexer includes calibration.
  • the processing module includes a delay control terminal, a selection control terminal, and a control switch terminal, wherein the multiplexer is a two-way selector in this embodiment;
  • the output end of the AND gate is electrically connected to the input end of the multiplexer through a delay chip, and the calibration end of the multiplexer is electrically connected to the processing module through a frequency divider, and the delay of the processing module
  • the control end is electrically connected to the delay chip, and the selection control end of the processing module is electrically connected to the multiplexer, the control switch end of the processing module is connected to the NAND gate, and the selection control end of the processing module is The output logic of the control switch end is consistent.
  • the multiplexer calibration end is electrically connected to the processing module, and the control switch end of the processing module is electrically connected to the input end of the NAND gate, and the output end of the NAND gate and the input end of the AND gate are electrically connected. Connected, the input of the AND gate receives the clock input signal.
  • the premise of the whole system work is that the duty cycle of the clock input is fixed. This is true for most clock circuits.
  • the whole system works in two modes, one is the calibration mode, and the other is Output mode, both modes are controlled by the logic of the processing module output.
  • the processing module controls the multiplexer to select the calibration terminal, and the clock forms a closed loop
  • the output when the clock input is low, the output is low; when the clock input is high, the output will have an oscillating square wave, and the oscillation period is delayed by the delay chip.
  • the multiplexer delay and the NAND gate delay are determined.
  • the frequency divider divides the oscillating waveform when the system is operating in the high speed mode (such as 100M), and the pulse width is within the capability of the processor to count. .
  • the processing module controls the multiplexer to select the output.
  • the clock output logic is equal to the clock input logic, and the entire system outputs normally.
  • Embodiment 2 is a diagrammatic representation of Embodiment 1:
  • the difference between this embodiment and the first embodiment is that the NAND gate in the first embodiment is replaced by a NAND gate, and there are some differences in the circuit structure setting, and the calibration end of the multiplexer is different.
  • the input of the gate is electrically connected; the same effect exists in the actual logic output.
  • the present invention provides a high-precision delayed clock calibration method, which includes the following steps: since the oscillation period is fixed, the processing module can obtain the pulse width width by counting the number of pulses, and the calibration process can be as follows: Method is carried out:
  • S2 Set the delay of the delay chip to a unit setting value, and calculate the number of pulses N; the number of N at this time is a unit setting value of the delay chip delay, the multiplexer delay and The delay of the inverter is determined;
  • S3 Calculate the difference between M and N to obtain S. This value is the number of oscillations generated by the unit set value. Since only a certain set of data will produce a certain error, different levels of calibration can be performed. First, we Perform a rough calibration;
  • the coarse calibration can only calibrate the error greater than one unit set value
  • the error of less than one unit set value can be adjusted by the analog control of the delay chip MC100EP196 to make fine adjustment, so that K100 is closer to 100 times K, through the above In the step we can get an accurate delay value of 100 units.

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Pulse Circuits (AREA)

Abstract

La présente invention concerne un système et un procédé d'étalonnage de retard d'horloge de haute précision. Le système d'étalonnage comprend une porte NON-ET, une porte ET, une puce à retard temporel, un multiplexeur et un module de traitement ; le multiplexeur comprenant une extrémité d'étalonnage et une extrémité de sortie, le module de traitement comprenant une extrémité de commande de retard temporel, une extrémité de commande de sélection et une extrémité de commutateur de commande ; l'extrémité de sortie de la porte ET étant électriquement connectée à l'extrémité d'entrée du multiplexeur au moyen de la puce à retard temporel, l'extrémité de commande de retard temporel du module de traitement étant électriquement connectée à la puce à retard temporel, l'extrémité de commande de sélection du module de traitement étant électriquement connectée au multiplexeur, l'extrémité de commutateur de commande du module de traitement étant électriquement connectée à l'extrémité d'entrée de la porte NON-ET, et l'extrémité de sortie de la porte NON-ET étant électriquement connectée à l'extrémité d'entrée de la porte ET. La présente invention utilise un procédé de comptage d'oscillations d'impulsion pour mesurer une largeur d'impulsion, puis calcule le retard temporel, avant de régler finalement la puce à retard temporel de manière à atteindre l'objectif d'étalonnage de retard temporel ; le système peut effectuer l'étalonnage en temps réel, empêchant la puce à retard temporel d'être affectée par la température et d'autres facteurs externes, ce qui permet d'obtenir un effet de mesure de haute précision.
PCT/CN2017/118233 2016-12-30 2017-12-25 Système et procédé d'étalonnage de retard d'horloge de haute précision Ceased WO2018121469A1 (fr)

Applications Claiming Priority (2)

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CN201611265841.0 2016-12-30
CN201611265841.0A CN106612111B (zh) 2016-12-30 2016-12-30 一种高精度延迟时钟校准的系统及方法

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CN114598302A (zh) * 2022-03-16 2022-06-07 上海东软载波微电子有限公司 时钟占空比校准装置
CN115001646A (zh) * 2022-08-01 2022-09-02 杭州加速科技有限公司 一种适用于多板卡的时钟同步校准方法及装置
CN116633325A (zh) * 2023-05-11 2023-08-22 北京伽略电子股份有限公司 一种可编程长延迟电路
WO2024125371A1 (fr) * 2022-12-13 2024-06-20 上海领帆微电子有限公司 Circuit à retard à autoréglage, puce de micro-traitement et système de commande de moteur
CN118300578A (zh) * 2024-05-16 2024-07-05 浙江大学舟山海洋研究中心 相控阵超声发射精确延时及脉宽调节的控制系统及方法

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CN107820678B (zh) * 2017-09-27 2021-03-19 深圳市汇顶科技股份有限公司 脉宽修正电路、脉宽修正方法及电子设备
CN107591172B (zh) * 2017-10-27 2023-10-20 长鑫存储技术有限公司 延时调制电路和包含延时调制电路的半导体存储器
CN107863967B (zh) * 2017-11-15 2021-04-30 中国电子科技集团公司第四十一研究所 一种多通道同步输出校准装置及方法
CN109194458B (zh) * 2018-08-22 2020-12-15 上海星秒光电科技有限公司 延时校准输出装置及方法
CN111327298B (zh) * 2020-03-12 2021-03-30 湖南毂梁微电子有限公司 一种超高精度数字脉冲信号产生电路及方法
CN114629476A (zh) * 2020-12-08 2022-06-14 华大半导体有限公司 高分辨率脉冲宽度调制信号产生电路
CN112737725B (zh) * 2020-12-28 2022-09-23 上海翎沃电子科技有限公司 一种时钟校准方法、装置、计算机设备、存储介质及应用
CN120214423B (zh) * 2025-05-28 2025-08-19 成都津研科技有限公司 基于高速serdes的连续高精度脉冲宽度测量方法及系统

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CN103916102A (zh) * 2014-03-10 2014-07-09 北京时代民芯科技有限公司 一种fpga内嵌全数字低功耗时钟产生电路
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CN114598302A (zh) * 2022-03-16 2022-06-07 上海东软载波微电子有限公司 时钟占空比校准装置
CN114598302B (zh) * 2022-03-16 2024-04-26 上海东软载波微电子有限公司 时钟占空比校准装置
CN115001646A (zh) * 2022-08-01 2022-09-02 杭州加速科技有限公司 一种适用于多板卡的时钟同步校准方法及装置
CN115001646B (zh) * 2022-08-01 2022-11-18 杭州加速科技有限公司 一种适用于多板卡的时钟同步校准方法及装置
WO2024125371A1 (fr) * 2022-12-13 2024-06-20 上海领帆微电子有限公司 Circuit à retard à autoréglage, puce de micro-traitement et système de commande de moteur
CN116633325A (zh) * 2023-05-11 2023-08-22 北京伽略电子股份有限公司 一种可编程长延迟电路
CN118300578A (zh) * 2024-05-16 2024-07-05 浙江大学舟山海洋研究中心 相控阵超声发射精确延时及脉宽调节的控制系统及方法

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