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WO2018125045A1 - Déverminage ciblé sur un circuit intégré - Google Patents

Déverminage ciblé sur un circuit intégré Download PDF

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Publication number
WO2018125045A1
WO2018125045A1 PCT/US2016/068690 US2016068690W WO2018125045A1 WO 2018125045 A1 WO2018125045 A1 WO 2018125045A1 US 2016068690 W US2016068690 W US 2016068690W WO 2018125045 A1 WO2018125045 A1 WO 2018125045A1
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WO
WIPO (PCT)
Prior art keywords
resistors
integrated circuit
burn
substrate
regions
Prior art date
Application number
PCT/US2016/068690
Other languages
English (en)
Inventor
Dhruv Singh
Indrajith Rajapaksa
Junho Song
Original Assignee
Intel Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corporation filed Critical Intel Corporation
Priority to PCT/US2016/068690 priority Critical patent/WO2018125045A1/fr
Publication of WO2018125045A1 publication Critical patent/WO2018125045A1/fr

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Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G01R31/2855—Environmental, reliability or burn-in testing
    • G01R31/2856—Internal circuit aspects, e.g. built-in test features; Test chips; Measuring material aspects, e.g. electro migration [EM]
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G01R31/2855—Environmental, reliability or burn-in testing
    • G01R31/2872—Environmental, reliability or burn-in testing related to electrical or environmental aspects, e.g. temperature, humidity, vibration, nuclear radiation
    • G01R31/2874—Environmental, reliability or burn-in testing related to electrical or environmental aspects, e.g. temperature, humidity, vibration, nuclear radiation related to temperature
    • G01R31/2875—Environmental, reliability or burn-in testing related to electrical or environmental aspects, e.g. temperature, humidity, vibration, nuclear radiation related to temperature related to heating

Definitions

  • the present disclosure relates to the field of integrated circuits. More specifically, the present disclosure is related to targeted burn-in on an integrated circuit.
  • the traditional solution to address these manufacturing defects is to implement "burn-in" to drive early life failures within the manufacturing plant by subjecting chips to high stress conditions. This may be achieved using large expensive burn-in ovens with high temperatures up to 125 Celsius and high voltage stress. To save cost and time, the oven process may be applied to a batch, and all units in the oven may be subject to the same voltage and temperature. Conditions of the oven burn-in, such as temperature and voltage, may be determined through projections of defect distributions.
  • Figure 1 is an illustration of a system for targeted burn-in on an integrated circuit.
  • Figure 2 is a flow chart of a process for targeted burn-in on an integrated circuit.
  • Figure 3 is a flow chart of a process for designing an integrated circuit for targeted burn-in.
  • Figure 4 is an illustration of selection circuitry in another system for targeted burn-in on an integrated circuit, according to various embodiments.
  • Figure 5 is an illustration of an interposer implementing one or more
  • Figure 6 is an illustration of a computing device built in accordance with an embodiment of the present disclosure. Detailed Description
  • Described herein are systems and methods of targeted burn-in on an integrated circuit.
  • various aspects of the illustrative implementations will be described using terms commonly employed by those skilled in the art to convey the substance of their work to others skilled in the art.
  • the embodiments described herein may be practiced with only some of the described aspects.
  • specific numbers, materials and configurations are set forth in order to provide a thorough understanding of the illustrative implementations.
  • the described embodiments may be practiced without the specific details.
  • well-known features are omitted or simplified in order not to obscure the illustrative implementations.
  • over refers to a relative position of one material layer or component with respect to other layers or components.
  • one layer disposed over or under another layer may be directly in contact with the other layer or may have one or more intervening layers.
  • one layer disposed between two layers may be directly in contact with the two layers or may have one or more intervening layers.
  • a first layer “on” a second layer is in direct contact with that second layer.
  • one feature disposed between two features may be in direct contact with the adjacent features or may have one or more intervening layers.
  • Implementations of the disclosed embodiments may be formed or carried out on a substrate, such as a semiconductor substrate.
  • a substrate such as a semiconductor substrate.
  • semiconductor substrate may be a crystalline substrate formed using a bulk silicon or a silicon-on-insulator substructure.
  • the semiconductor substrate may be formed using alternate materials, which may or may not be combined with silicon, that include but are not limited to germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, indium gallium arsenide, gallium antimonide, or other combinations of group lll-V or group IV materials.
  • MOSFET metal-oxide-semiconductor field-effect transistors
  • the MOS transistors may be planar transistors, nonplanar transistors, or a combination of both.
  • Nonplanar transistors include FinFET transistors such as double-gate transistors and tri-gate transistors, and wrap-around or all-around gate transistors such as nanoribbon and nanowire transistors.
  • Each MOS transistor includes a gate stack formed of at least two layers, a gate dielectric layer and a gate electrode layer.
  • the gate dielectric layer may include one layer or a stack of layers.
  • the one or more layers may include silicon oxide, silicon dioxide (SiO 2 ) and/or a high-k dielectric material.
  • the high-k dielectric material may include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc.
  • high-k materials that may be used in the gate dielectric layer include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate.
  • an annealing process may be carried out on the gate dielectric layer to improve its quality when a high-k material is used.
  • the gate electrode layer is formed on the gate dielectric layer and may consist of at least one P-type workfunction metal or N-type workf unction metal, depending on whether the transistor is to be a PMOS or an NMOS transistor. In some
  • the gate electrode layer may consist of a stack of two or more metal layers, where one or more metal layers are workfunction metal layers and at least one metal layer is a fill metal layer. Further metal layers may be included for other purposes, such as a barrier layer.
  • metals that may be used for the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, and oxygen- containing metal alloys such as conductive metal oxides, e.g., ruthenium oxide.
  • a P-type metal layer will enable the formation of a PMOS gate electrode with a workfunction that is between about 4.9 eV and about 5.2 eV.
  • metals that may be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbon-containing metal alloys such as metal carbides of these metals, for example hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide.
  • An N-type metal layer will enable the formation of an NMOS gate electrode with a workfunction that is between about 3.9 eV and about 4.2 eV.
  • the gate electrode when viewed as a cross-section of the transistor along the source-channel-drain direction, may consist of a "U"-shaped structure that includes a bottom portion substantially parallel to the surface of the substrate and two sidewall portions that are substantially perpendicular to the top surface of the substrate.
  • at least one of the metal layers that form the gate electrode may simply be a planar layer that is substantially parallel to the top surface of the substrate and does not include sidewall portions substantially perpendicular to the top surface of the substrate.
  • the gate electrode may consist of a combination of U-shaped structures and planar, non-U-shaped structures.
  • the gate electrode may consist of one or more U-shaped metal layers formed atop one or more planar, non-U- shaped layers.
  • a pair of sidewall spacers may be formed on opposing sides of the gate stack that bracket the gate stack.
  • the sidewall spacers may be formed from materials such as silicon, nitrogen, carbon, and oxygen, for example silicon nitride, silicon oxide, silicon carbide, silicon nitride doped with carbon, and silicon oxynitride. Processes for forming sidewall spacers are well known in the art and generally include deposition and etching process steps. In an alternate implementation, a plurality of spacer pairs may be used, for instance, two pairs, three pairs, or four pairs of sidewall spacers may be formed on opposing sides of the gate stack.
  • source and drain regions are formed within the substrate adjacent to the gate stack of each MOS transistor.
  • the source and drain regions are generally formed using either an implantation/diffusion process or an etching/deposition process.
  • dopants such as boron, aluminum, antimony, phosphorous, or arsenic may be ion-implanted into the substrate to form the source and drain regions.
  • An annealing process that activates the dopants and causes them to diffuse further into the substrate typically follows the ion implantation process.
  • the substrate may first be etched to form recesses at the locations of the source and drain regions.
  • An epitaxial deposition process may then be carried out to fill the recesses with material that is used to fabricate the source and drain regions.
  • the source and drain regions may be fabricated using a silicon alloy such as silicon germanium or silicon carbide.
  • the epitaxially deposited silicon alloy may be doped in situ with dopants such as boron, arsenic, or phosphorous.
  • the source and drain regions may be formed using one or more alternate semiconductor materials such as germanium or a group lll-V material or alloy.
  • one or more layers of metal and/or metal alloys may be used to form the source and drain regions.
  • ILD interlayer dielectrics
  • the ILD layers may be formed using dielectric materials known for their applicability in integrated circuit structures, such as low-k dielectric materials.
  • the dielectric materials may include elements such as silicon, oxygen, carbon, nitrogen, fluorine, and hydrogen. Examples of dielectric materials that may be used include, but are not limited to, silicon dioxide (Si0 2 ), carbon doped oxide (CDO), silicon nitride, organic polymers such as perfluorocyclobutane or polytetrafluoroethylene, fluorosilicate glass (FSG), and organosilicates such as silsesquioxane, siloxane, or organosilicate glass.
  • the ILD layers may include pores or air gaps to further reduce their dielectric constant.
  • conditions such as temperature and voltage
  • the oven may apply uniform stress conditions for all units when units with low defects do not require high stress burn-in.
  • defects are may not be randomly distributed across various types and spatially on the die even though stresses may be applied uniformly in the oven.
  • an oven burn-in for the entire chip may lead to significant performance degradation of healthy transistors.
  • an integrated circuit may be fabricated with first resistors of a metal layer below a substrate on which active circuitry may be formed (e.g., back-end precision template resistors) and/or second resistors on the substrate (e.g., front-end resistors such as poly resistors).
  • the second resistors may be placed circumferentially around selected circuits/cells of the active circuitry (such as those cells with high activity and/or systematic layout defects) in order to provide highly localized temperature and voltage acceleration.
  • This temperature and voltage acceleration can be used to eliminate the need for oven burn-in or can be used in combination with a different oven burn-in, e.g., a shorter total duration and/or lower temperature oven burn-in.
  • These resistors may be developed and validated extensively for each process technology certification and reliably used for various elements of the integrated circuit.
  • the selected circuits/cells may be of relatively high activity regions, relatively high power consumption regions, local hotspot regions and/or regions with high defect density.
  • these regions may include high density clock circuits, data inverters and/or input/out speed paths operating at high frequency and/or high activity.
  • Such regions may draw high power and/or suffer from locally high temperatures in use, and accordingly may undergo disproportionately higher stress from a reliability perspective.
  • the higher stress time may result in higher probability of early life failure than rest of the circuits in the chip (e.g., circuits with low to moderate activity factors).
  • these cells/circuits may be a graphics logic block, a core logic block, a memory logic block, and/or any other block associated with high defect density due to local layout specific systematic defects and use of complex lithographic elements.
  • targeted burn-in may be utilized with considerations to local layout and distribution within specific blocks.
  • Whole die burn-in stresses devices on the entire die, which may accelerate the degradation of devices with high defects but may also cause undesirable degradation to devices with no defects - devices that make up a majority of the chip.
  • targeted burn-in may target the stress to only high activity and/or high defect circuits, thus reducing degradation to the rest of the devices.
  • targeted burn-in With whole-die burn-in there is no ability to target the systematic defects that arise purely out of layout specific lithographic patterning.
  • some of the associated circuitry for targeted burn-in may be fabricated around pre-identified systematic defect layouts in regions of the chip treating their burn-in independent from the rest of the chip. Since each die is different due to the position on the wafer and process variations, each die may receive a different amount of burn-in.
  • targeted burn-in may utilize a feedback mechanism from die temperature to the burn-in control.
  • targeted burn-in using feedback may allow precise control of temperature acceleration with accurately characterized precision resistors whose local temperature is a function of voltage and current.
  • Targeted burn-in may be used in addition to or instead of whole die burn-in.
  • the use of whole die burn-in and targeted burn-in at the same time or in sequence may provide superior performance by reducing total burn-in time compared to whole die burn-in alone. This may significantly reduce the burn-in time in the oven by treating region-specific burn-in as part of sort test.
  • the impact of temperature gradients may be reduced by building resistor layouts to generate hotspots.
  • Figure 1 is an illustration of a system 100 for targeted burn-in on an integrated circuit 110.
  • the system 100 includes a number of resistors 1-N (N may be two or more) to receive current for targeted burn-in.
  • a first resistor of the resistors 1-N may receive current to heat a corresponding region 130 of the integrated circuit 110 to a first predetermined burn-in temperature.
  • An Nth resistor of the resistors 1-N may receive current to heat a different corresponding region 139 of the integrated circuit 110 to a second predetermined burn-in temperature (e.g., a different predetermined burn-in temperature).
  • the resistors 1-N may be used for targeted burn-in on the integrated circuit 110.
  • targeted burn-in better reliability may be achieved because each region may be burned-in using independent burn-in parameters (e.g., temperature, time) that are based on properties of the region (e.g., based on components of that region as opposed to a uniform burn-in temperature/time across all regions.
  • Targeted burn- in may provide a reduction in net burn-in time.
  • Targeting specific regions may reduce the imposed stress on devices overall in the chip, for example realizing less degradation in gate dielectric and/or transistor threshold voltage before the chip is used in the field (thus leading to better performance).
  • Targeted burn-in may improve quality, reliability and/or performance of the outgoing products, and it also may significantly reduce burn-in time and cost, particularly for server products which may have required one hour of oven burn-in without targeted burn-in.
  • inputs into the selection circuitry 101 may include a signal 111 to select a subset of the resistors 1- N to be activated (e.g., an address line(s) corresponding to selected resistor(s) 1-N and a burn-in enable signal).
  • the selection circuitry 101 may also receive current 113 from a burn-in voltage supply via, for instance, a burn-in voltage rail.
  • Selection circuitry 101 may be used to burn-in different regions at different times and/or to selectively switch on circuitry of the regions 130 and 139 at various stages of targeted burn-in to identify systematic marginal defects.
  • Some embodiments may include a programmable cell specific burn-in voltage supply 105 to generate the signal 111 to select the subset of the resistors 1-N to receive current 113.
  • the programmable cell specific burn-in voltage supply 105 may receive a feedback 115, such as a temperature readout line.
  • the feedback 115 may be based on measurements output from sensors 131 and 138, which may be thermal diodes in some embodiments.
  • the sensors 131 and 138 may output measurements indicating characteristics of the corresponding regions 130 and 139. The characteristics may be a temperature reading or information that can be used to derive a temperature reading.
  • a processing device (not shown) of the integrated circuit 110 or the programmable cell specific burn-in voltage supply 105 may calculate temperatures of the different regions based on changes in the resistance of the resistors 1-N.
  • the sensors 131 and 138 may be current sensors and the changes the in the resistance of the resistors may be detected by current sensing.
  • the programmable cell specific burn-in voltage supply 105 may change the signal 111 and/or 113 to stress the integrated circuit 110 differently based on the feedback 115. For instance, the programmable cell specific burn-in voltage supply 105 may increase the current 113 delivered to an active one of the resistors 1-N in order to heat the selected region to a predetermined burn-in temperature if the feedback 115 indicates that the predetermined burn-in temperature has not been reached. In another example, the programmable cell specific burn-in voltage supply 105 may decrease the current 113 delivered to an active one of the resistors 1-N if the feedback 115 indicates that a duration for applying the predetermined temperature is complete.
  • the resistors 1-N include a number of low resistance pathways to provide direct circuit access from a high voltage local burn-in rail to circuits of the regions 130 and 139 for voltage acceleration and/or to generate a local uniform hotspot for temperature acceleration. In some embodiments, the resistors 1-N may each consume less than 0.5 mW in response to application of the current 113.
  • the selection circuitry 101 may be an on-die multiplexor or some other component to select a burn-in resistance pathway to receive current 113. Some embodiments may use feedback 115 for accurate temperature and/or voltage control.
  • FIG. 2 is a flow chart of a process 200 for targeted burn-in on an integrated circuit, such as the integrated circuit 110 (FIG. 1).
  • a subset of different active circuitry regions of an integrated circuit are selected to heat to at least a predetermined burn-in temperature for a period of time. The selection may be based on the identification of systematic defects.
  • current is delivered to resistive element(s) associated with region(s) of the selected subset in order to cause the resistive element(s) to heat only the region(s) of the selected subset to at least the predetermined burn-in temperature for the period of time.
  • Current may be delivered to the resistive element(s) corresponding at least some of the selected active circuitry regions concurrently (e.g., fully
  • current may be delivered at different times.
  • a duration of current delivery may be different for different resistive elements and/or different region(s) of the selected subset may be heated to different predetermined temperatures.
  • current delivery may be coupled with a feedback mechanism to indicate temperature, and current passing through a given resistor may be tuned based on this feedback.
  • an operability of the integrated circuit may be tested. Since no external oven or other stimulus is needed to perform the locally tunable burn-in described above, sort-test and power on may be performed in parallel (e.g., partially or fully in parallel) with targeted burn-in if the burn-in rail is powered at an appropriate voltage.
  • circuit areas may be individually burned in, and test patterns may be run to excessively stress the localized burn-in area driving it to failure that would be seen early in use life due to existing manufacturing or material defects. This may be repeated for different areas, and the failures may be recorded in order to measure systematic defects.
  • the resistive element(s) may be permanently disconnected from a burn-in rail used to deliver the current.
  • a single fuse of selection circuitry similar to the selection circuitry 101 of FIG. 1 may be blown out and/or fuses of resistive element(s) may be blown out.
  • oven burn-in of the integrated circuit may be performed to heat the active circuitry regions differently than the targeted heating of the region(s) of the selected subset.
  • Some of the problematic regions e.g., a majority of the problematic regions, may have been identified from targeted burn-in, which may result in a shorter duration and/or lower temperature for oven burn-in (thus minimizing an effect of oven burn-in on regions with low defects, reducing active use time of the oven, and/or enabling improvements in total manufacture time).
  • Oven burn-in may be associated with separate operability testing in connection with the oven burn-in.
  • Figure 3 is a flow chart of a process 300 for designing an integrated circuit for targeted burn-in.
  • the process 300 may be used with a hybrid burn-in scheme (e.g., a scheme that includes targeted burn-in for high risk cells and another different burn-in, such as oven burn-in).
  • a hybrid burn-in scheme e.g., a scheme that includes targeted burn-in for high risk cells and another different burn-in, such as oven burn-in.
  • FIG. 6 illustrates a computing device 1200 in accordance with various embodiments of the present disclosure.
  • the computing device 1200 may include a number of components. In one embodiment, these components are attached to one or more motherboards. In an alternate embodiment, some or all of these components are fabricated onto a single system-on-a-chip (SoC) die, such as an SoC used for mobile devices.
  • SoC system-on-a-chip
  • the components in the computing device 1200 include, but are not limited to, an integrated circuit die 1202 and at least one communications logic unit 1208.
  • the communications logic unit 1208 is fabricated within the integrated circuit die 1202 while in other implementations the communications logic unit 1208 is fabricated in a separate integrated circuit chip that may be bonded to a substrate or motherboard that is shared with or electronically coupled to the integrated circuit die 1202.
  • the integrated circuit die 1202 may include a CPU 1204 as well as on-die memory 1206, often used as cache memory, that can be provided by technologies such as embedded DRAM (eDRAM), SRAM, or spin-
  • Computing device 1200 may include other components that may or may not be physically and electrically coupled to the motherboard or fabricated within an SoC die. These other components include, but are not limited to, volatile memory 1210 (e.g., DRAM), non-volatile memory 1212 (e.g., ROM or flash memory), a graphics processing unit 1214 (GPU), a digital signal processor 1216, a crypto processor 1242 (e.g., a specialized processor that executes cryptographic algorithms within hardware), a chipset 1220, at least one antenna 1222 (in some implementations two or more antenna may be used), a display or a touchscreen display 1224, a touchscreen controller 1226, a battery 1228 or other power source, a power amplifier (not shown), a voltage regulator (not shown), a global positioning system (GPS) device 1228, a compass 1230, a motion coprocessor or sensors 1232 (that may include an accelerometer, a gyroscope, and a compass), a microphone (not shown),
  • another component housed within the computing device 1200 may contain one or more devices, such as transistors or metal
  • a digital thermal sensor DTS (implemented using standard IC elements or using a thermal diode) may be placed in the cell to measure the local temperature generated by precision resistors (also controlled using the burn-in supply voltage).
  • the proportionality constant used may be process and/or integrated circuit dependent, and calibrated through test chips.
  • Example 2 may include the subject matter of example 1 and/or any other example herein, and the different regions of the integrated circuit are formed above a substrate and at least one of the resistors are located below the substrate.
  • Example 4 may include the subject matter of any of examples 1-3 and/or any other example herein, and sensors to identify respective temperatures of the different regions of the integrated circuit.
  • Example 5 may include the subject matter of any of examples 1-4 and/or any other example herein, and a current generator coupled to the sensors and to generate the current based on sensor data of one of the sensors that corresponds to the selected resistor.
  • Example 6 may include the subject matter of any of examples 1-5 and/or any other example herein, and wherein the sensors comprise thermal diodes.
  • Example 15 may include the subject matter of any of examples 11-14 and/or any other example herein, and a first terminal of each of the resistors is coupled to the selection circuitry and a second terminal of at least one of the resistors is coupled to at least one of a cell or circuit of its corresponding region.
  • Example 20 may include the subject matter of any of examples 16-19 and/or any other example herein, and a first terminal of each of the resistors is coupled to the selection circuitry and a second terminal of at least one of the resistors is coupled to at least one of a cell or circuit of its corresponding region.

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Abstract

Les modes de réalisation de l'invention comprennent des techniques pour l'agencement d'un réseau de diodes dans un circuit intégré. Un CI (circuit intégré) peut comprendre un substrat; des circuits formés sur le substrat; des résistances couplées à différentes zones respectives des circuits; et des circuits de sélection pour sélectionner une des résistances en vue de l'alimenter en courant pour l'amener à chauffer une zone correspondante desdites zones à une température de déverminage prédéterminée.
PCT/US2016/068690 2016-12-27 2016-12-27 Déverminage ciblé sur un circuit intégré WO2018125045A1 (fr)

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PCT/US2016/068690 WO2018125045A1 (fr) 2016-12-27 2016-12-27 Déverminage ciblé sur un circuit intégré

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040012404A1 (en) * 2002-07-19 2004-01-22 Delta Design, Inc. Thermal control of a DUT using a thermal contro substrate
US20070051951A1 (en) * 2003-09-24 2007-03-08 Prasad Chaparala Method for testing metal-insulator-metal capacitor structures under high temperature at wafer level
US20110273186A1 (en) * 2010-05-06 2011-11-10 Texas Instruments Incorporated Circuit for controlling temperature and enabling testing of a semiconductor chip
US20120049874A1 (en) * 2010-08-25 2012-03-01 International Business CorporationA Semiconductor test chip device to mimic field thermal mini-cycles to assess reliability
US20140210498A1 (en) * 2005-08-04 2014-07-31 Micron Technology, Inc. Electronic apparatus having ic temperature control

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040012404A1 (en) * 2002-07-19 2004-01-22 Delta Design, Inc. Thermal control of a DUT using a thermal contro substrate
US20070051951A1 (en) * 2003-09-24 2007-03-08 Prasad Chaparala Method for testing metal-insulator-metal capacitor structures under high temperature at wafer level
US20140210498A1 (en) * 2005-08-04 2014-07-31 Micron Technology, Inc. Electronic apparatus having ic temperature control
US20110273186A1 (en) * 2010-05-06 2011-11-10 Texas Instruments Incorporated Circuit for controlling temperature and enabling testing of a semiconductor chip
US20120049874A1 (en) * 2010-08-25 2012-03-01 International Business CorporationA Semiconductor test chip device to mimic field thermal mini-cycles to assess reliability

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