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WO2018125063A1 - Encapsulation d'intervalles d'air dans des interconnexions - Google Patents

Encapsulation d'intervalles d'air dans des interconnexions Download PDF

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Publication number
WO2018125063A1
WO2018125063A1 PCT/US2016/068757 US2016068757W WO2018125063A1 WO 2018125063 A1 WO2018125063 A1 WO 2018125063A1 US 2016068757 W US2016068757 W US 2016068757W WO 2018125063 A1 WO2018125063 A1 WO 2018125063A1
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WO
WIPO (PCT)
Prior art keywords
metal traces
air gap
metal
adjacent
dielectric material
Prior art date
Application number
PCT/US2016/068757
Other languages
English (en)
Inventor
Manish Chandhok
Sudipto NASKAR
Jasmeet S. Chawla
Original Assignee
Intel Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corporation filed Critical Intel Corporation
Priority to PCT/US2016/068757 priority Critical patent/WO2018125063A1/fr
Publication of WO2018125063A1 publication Critical patent/WO2018125063A1/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/764—Air gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/7682—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing the dielectric comprising air gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors

Definitions

  • FIG. 1 illustrates a cross-sectional view of an integrated circuit device with encapsulation of air gaps in interconnects, according to some embodiments
  • Figs. 2 ⁇ -2 ⁇ illustrate cross-sectional views of manufacturing steps of
  • FIG. 3 illustrates a diagram of an example semiconductor manufacturing equipment, according to some embodiments.
  • FIG. 4 illustrates a flowchart of a method of forming an integrated circuit device with encapsulation of air gaps in interconnects, in accordance with some embodiments.
  • Fig. 5 illustrates a smart device or a computer system or a SoC (System-on-Chip) which includes an integrated circuit device with encapsulation of air gaps in interconnects, according to some embodiments.
  • SoC System-on-Chip
  • Encapsulation of air gaps in interconnects are generally presented.
  • embodiments of the present invention enable opposite surfaces of adjacent interconnects to be free from dielectric material.
  • these air gaps may enable finer feature sizes compared to typical air gaps lined with dielectric material, due to issues with the latter of inter-metal capacitance. Additionally, these air gaps with clean sidewalls having no deposition may reduce cross talk and power dissipation without the need for lower It- value dielectric.
  • signals are represented with lines. Some lines may be thicker, to indicate more constituent signal paths, and/or have arrows at one or more ends, to indicate primary information flow direction. Such indications are not intended to be limiting. Rather, the lines are used in connection with one or more exemplary embodiments to facilitate easier understanding of a circuit or a logical unit. Any represented signal, as dictated by design needs or preferences, may actually comprise one or more signals that may travel in either direction and may be implemented with any suitable type of signal scheme.
  • connection means a direct connection, such as electrical, mechanical, or magnetic connection between the things that are connected, without any intermediary devices.
  • coupled means a direct or indirect connection, such as a direct electrical, mechanical, or magnetic connection between the things that are connected or an indirect connection, through one or more passive or active intermediary devices.
  • circuit or “module” may refer to one or more passive and/or active components that are arranged to cooperate with one another to provide a desired function.
  • signal may refer to at least one current signal, voltage signal, magnetic signal, or data/clock signal.
  • the meaning of "a,” “an,” and “the” include plural references.
  • the meaning of "in” includes “in” and "on.”
  • phrases “A and/or B” and “A or B” mean (A), (B), or (A and B).
  • phrase “A, B, and/or C” means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B and C).
  • the terms “left,” “right,” “front,” “back,” “top,” “bottom,” “over,” “under,” and the like in the description and in the claims, if any, are used for descriptive purposes and not necessarily for describing permanent relative positions.
  • Fig. 1 illustrates a cross-sectional view of an integrated circuit device with encapsulation of air gaps in interconnects, according to some embodiments.
  • device 100 includes interconnect layers 102, circuit substrate 104, metal 106, dielectric 108, air gaps 110, substrate 112, circuits 114, and contacts 116.
  • Interconnect layers 102 may provide electrical connections between components of circuit substrate 104 and contacts 116, which may be lands, bumps, pins, etc., to couple device 100 with external substrates, interposers, packages, sockets, etc. Interconnect layers 102 may be formed iteratively on separate planes above circuit substrate 104. In some embodiments, interconnect layers 102 includes metal 106, such as copper, that may be plated into etched trenches and vias, then polished back to create metal trenches, planes, and vias, for example to communicate power and signals to and from circuit substrate 104. Metal 106 in interconnect layers 102 may be interspersed with dielectric 108, which has insulative properties.
  • dielectric 108 represents an interlay er dielectric (TLD) material, such as carbon doped oxide (CDO), deposited conformally across metal 106 structures to a thickness at least equivalent to a thickness of an interconnect structure including wiring lines and subsequent level conductive vias.
  • TLD interlay er dielectric
  • CDO carbon doped oxide
  • Circuit substrate 104 may include integrated circuits in a circuits 114 layer on a substrate 112.
  • circuits 114 include semiconductor transistors, switches, gates, relays, and/or memory components.
  • Circuits 114 may include millions of circuit devices or components that each include an input, an output, and/or a power signal communicated through interconnect layers 102.
  • Substrate 112 may be made of silicon, other semiconductor material, and/or other non-semiconductor material.
  • Air gaps 110 may be formed between adjacent metal traces in various ways.
  • air gaps 110, and surrounding metal traces increase in height and width in interconnect layers 102 further away from circuit substrate 104.
  • air gaps 1 10 in higher interconnect layers 102 may have widths of up to about 80 nm and heights of up to about 50 nm, while air gaps 1 10 in lower interconnect layers 102 may have widths of as low as about 20 nm and heights of as low as about 15 nm. In other embodiments, different size ranges may be utilized for air gaps 1 10 in any of interconnect layers 102.
  • FIGS. 2A-2I illustrate cross-sectional views of manufacturing steps of
  • assembly 200 includes circuit substrate 202, interconnect layers 204, and metal traces 206.
  • Interconnect layers 204 may represent any number of layers, for example interconnect layers 102, that have been built up on circuit substrate 202.
  • Metal traces 206 may have been plated into etched trenches and vias, then polished back to create metal trenches to form adjacent metal traces 206.
  • Metal traces 206 may be electrically coupled with structures in interconnect layers 204 and circuit substrate 202 through vias, not shown. While shown as having straight sides, metal traces 206 may have curved and/or irregular sides.
  • Fig. 2B shows assembly 210, which may include dielectric 208 deposited on a
  • Dielectric 208 may be deposited by atomic layer deposition (ALD), chemical vapour deposition (CVD), plasma enhanced CVD (PECVD), or by other means. In some embodiments, dielectric 208 is deposited as described in further detail hereinafter to prevent dielectric 208 from being deposited on other (sidewall) surfaces of metal traces 206.
  • ALD atomic layer deposition
  • CVD chemical vapour deposition
  • PECVD plasma enhanced CVD
  • dielectric 208 is deposited as described in further detail hereinafter to prevent dielectric 208 from being deposited on other (sidewall) surfaces of metal traces 206.
  • assembly 220 has had some of dielectric 208 removed, for example through etching.
  • dielectric 208 has been removed from over trench 212 between adjacent metal traces 206.
  • dielectric 208 has edges substantially parallel with edges of metal traces 206.
  • assembly 230 may include additional dielectric 208 that has been deposited on metal traces 206.
  • additional dielectric 208 overhangs above trench 212.
  • Fig. 2E shows assembly 240, which may have had some of dielectric 208 removed from over trench 212, such that edges of dielectric 208 extend substantially straight beyond edges of metal traces 206.
  • Fig. 2F for assembly 250 the steps of depositing and removing dielectric 208 may have been repeated any number of times to result in dielectric 208 extending a height 214 on metal traces 206. In some embodiments, height 214 can result in adding greater depth to trench 212.
  • assembly 260 may include dielectric 208 deposited on metal traces 206 to form helmets that extend outwardly over the space between metal traces 206.
  • Fig. 2H shows assembly 270, which may include dielectric 216 closing off the space between adjacent metal traces 206 and forming air gaps 218.
  • Air gaps 218 may extend, initially, substantially straight beyond the edges of adjacent metal traces 206 adjacent dielectric 216.
  • facing surfaces of adjacent metal traces 206 are completely void of dielectric material.
  • dielectric 216 has edges 222 substantially parallel with, or analogous to, edges of metal traces 206.
  • air gaps 218 may have a height of between about 15 nm and 50 nm.
  • air gaps 218 may have a width of between about 20 nm and 80 nm.
  • assembly 280 includes sealing material 224 over dielectric
  • sealing material 224 may provide a hermetic seal for air gaps 218.
  • sealing material 224 may include SiCN, AI2O3, or SiN.
  • sealing material 224 may include a thickness of between about 4 nm and 25 nm.
  • Fig. 3 illustrates a diagram of an example semiconductor manufacturing equipment, according to some embodiments.
  • equipment 300 includes deposition chamber 302, etch chamber 304, substrate 306, pedestal 308, precursor control 310, etch control 312 and access 314.
  • Substrate 306 may represent intermediary assemblies of an integrated circuit device, such as any of the assemblies depicted in Figs. 2A-2I.
  • Pedestal 308 may support substrate 306 and may be used to transport substrate 306 between deposition chamber 302 and etch chamber 304, for example through access 314, which may represent a sliding door.
  • Deposition chamber 302 may be used to deposit dielectric material, such as dielectric 208 or 216, on metal traces 206.
  • Deposition chamber 302 may perform any type of deposition, including, but not limited to, ALD, CVD, PECVD, etc.
  • precursor control 310 controls the deposition process by controlling the supply of precursor molecules necessary for deposition to occur.
  • precursor control 310 may provide precursor molecules at a relatively high speed perpendicular to metal traces 206 to prevent dielectric from being deposited in trench 212 along sidewalls of metal traces 206.
  • pedestal 308 rotates substrate 306 during a deposition to further prevent dielectric from being deposited in trench 212 along sidewalls of metal traces 206.
  • Etch chamber 304 may be used to selectively remove dielectric material, for example, dielectric 208 that overhangs trench 212.
  • Etch control 312 may control the etch process by directing etchants, for example chemical etchants, to the material to be removed.
  • etch control 312 includes masking of material to be preserved.
  • Fig. 4 illustrates a flowchart of a method of forming an integrated circuit device with encapsulation of air gaps in interconnects, in accordance with some embodiments.
  • the blocks in the flowchart with reference to Fig. 4 are shown in a particular order, the order of the actions can be modified. Thus, the illustrated embodiments can be performed in a different order, and some actions/blocks may be performed in parallel. Some of the blocks and/or operations listed in Fig. 4 are optional in accordance with certain embodiments. The numbering of the blocks presented is for the sake of clarity and is not intended to prescribe an order of operations in which the various blocks must occur. Additionally, operations from the various flows may be utilized in a variety of combinations.
  • Method 400 begins with forming (402) interconnects, for example in a plane on a dielectric layer on a substrate, such as metal traces 206.
  • deposition is performed (404).
  • dielectric 208 may be formed on metal traces 206 in deposition chamber 302.
  • precursor control 310 may injected precursor molecules at relatively high velocity while pedestal 308 rotates assembly 210 to prevent dielectric from being deposited along sidewalls of metal traces 206.
  • excess material for example dielectric 208 that overhangs trench 212, may be etched (406) in etch chamber 304 by chemical or other means.
  • any number of iterative depositions and etches may be performed (408) for example as shown in assemblies 230 and 240.
  • the method continues with depositing (410) dielectric 216 to close air gaps 218.
  • Fig. 5 illustrates a smart device or a computer system or a SoC (System-on-Chip)
  • computing device 500 which includes an integrated circuit device with encapsulation of air gaps in interconnects, according to some embodiments.
  • computing device 500 represents a mobile computing device, such as a computing tablet, a mobile phone or smart-phone, a wireless-enabled e-reader, or other wireless mobile device. It will be understood that certain components are shown generally, and not all components of such a device are shown in computing device 500.
  • one or more components of computing device 500 for example processor 510 and/or memory subsystem 560, include an integrated circuit device with encapsulation of air gaps in interconnects as described above.
  • the transistors in various circuits and logic blocks described here are metal oxide semiconductor (MOS) transistors or their derivatives, where the MOS transistors include drain, source, gate, and bulk terminals.
  • MOS transistors include drain, source, gate, and bulk terminals.
  • the transistors and/or the MOS transistor derivatives also include Tri-Gate and FinFET transistors, Gate All Around Cylindrical Transistors, Tunneling FET (TFET), Square Wire, or Rectangular Ribbon
  • Transistors ferroelectric FET (FeFETs), or other devices implementing transistor functionality like carbon nanotubes or spintronic devices.
  • MOSFET symmetrical source and drain terminals i.e., are identical terminals and are interchangeably used here.
  • a TFET device on the other hand, has asymmetric Source and Drain terminals.
  • BJT PNP/NPN Bi-polar junction transistors
  • BiCMOS BiCMOS
  • CMOS complementary metal oxide
  • etc. may be used without departing from the scope of the disclosure.
  • computing device 500 includes a first processor 510.
  • the various embodiments of the present disclosure may also comprise a network interface within 570 such as a wireless interface so that a system embodiment may be incorporated into a wireless device, for example, cell phone or personal digital assistant.
  • processor 510 can include one or more physical devices, such as microprocessors, application processors, microcontrollers, programmable logic devices, or other processing means.
  • the processing operations performed by processor 510 include the execution of an operating platform or operating system on which applications and/or device functions are executed.
  • the processing operations include operations related to I/O
  • the processing operations may also include operations related to audio I/O and/or display I/O.
  • computing device 500 includes audio subsystem 520, which represents hardware (e.g., audio hardware and audio circuits) and software (e.g., drivers, codecs) components associated with providing audio functions to the computing device. Audio functions can include speaker and/or headphone output, as well as microphone input. Devices for such functions can be integrated into computing device 500, or connected to the computing device 500. In one embodiment, a user interacts with the computing device 500 by providing audio commands that are received and processed by processor 510.
  • audio subsystem 520 represents hardware (e.g., audio hardware and audio circuits) and software (e.g., drivers, codecs) components associated with providing audio functions to the computing device. Audio functions can include speaker and/or headphone output, as well as microphone input. Devices for such functions can be integrated into computing device 500, or connected to the computing device 500. In one embodiment, a user interacts with the computing device 500 by providing audio commands that are received and processed by processor 510.
  • Display subsystem 530 represents hardware (e.g., display devices) and software
  • Display subsystem 530 includes display interface 532, which includes the particular screen or hardware device used to provide a display to a user.
  • display interface 532 includes logic separate from processor 510 to perform at least some processing related to the display.
  • display subsystem 530 includes a touch screen (or touch pad) device that provides both output and input to a user.
  • I/O controller 540 represents hardware devices and software components related to interaction with a user. I/O controller 540 is operable to manage hardware that is part of audio subsystem 520 and/or display subsystem 530. Additionally, I/O controller 540 illustrates a connection point for additional devices that connect to computing device 500 through which a user might interact with the system. For example, devices that can be attached to the computing device 500 might include microphone devices, speaker or stereo systems, video systems or other display devices, keyboard or keypad devices, or other I/O devices for use with specific applications such as card readers or other devices.
  • I/O controller 540 can interact with audio subsystem 520 and/or display subsystem 530.
  • input through a microphone or other audio device can provide input or commands for one or more applications or functions of the computing device 500.
  • audio output can be provided instead of, or in addition to display output.
  • display subsystem 530 includes a touch screen
  • the display device also acts as an input device, which can be at least partially managed by I/O controller 540.
  • I/O controller 540 manages devices such as accelerometers, cameras, light sensors or other environmental sensors, or other hardware that can be included in the computing device 500.
  • the input can be part of direct user interaction, as well as providing environmental input to the system to influence its operations (such as filtering for noise, adjusting displays for brightness detection, applying a flash for a camera, or other features).
  • computing device 500 includes power management 550 that manages battery power usage, charging of the battery, and features related to power saving operation.
  • Memory subsystem 560 includes memory devices for storing information in computing device 500. Memory can include nonvolatile (state does not change if power to the memory device is interrupted) and/or volatile (state is indeterminate if power to the memory device is interrupted) memory devices. Memory subsystem 560 can store application data, user data, music, photos, documents, or other data, as well as system data (whether long-term or temporary) related to the execution of the applications and functions of the computing device 500.
  • Elements of embodiments are also provided as a machine-readable medium (e.g., memory 560) for storing the computer-executable instructions.
  • the machine-readable medium e.g., memory 560
  • embodiments of the disclosure may be downloaded as a computer program (e.g., BIOS) which may be transferred from a remote computer (e.g., a server) to a requesting computer (e.g., a client) by way of data signals via a communication link (e.g., a modem or network connection).
  • BIOS a computer program
  • a remote computer e.g., a server
  • a requesting computer e.g., a client
  • a communication link e.g., a modem or network connection
  • Connectivity 570 includes hardware devices (e.g., wireless and/or wired connectors and communication hardware) and software components (e.g., drivers, protocol stacks) to enable the computing device 500 to communicate with external devices.
  • the computing device 500 could be separate devices, such as other computing devices, wireless access points or base stations, as well as peripherals such as headsets, printers, or other devices.
  • Connectivity 570 can include multiple different types of connectivity. To generalize, the computing device 500 is illustrated with cellular connectivity 572 and wireless connectivity 574.
  • Cellular connectivity 572 refers generally to cellular network connectivity provided by wireless carriers, such as provided via GSM (global system for mobile
  • Wireless connectivity (or wireless interface) 574 refers to wireless connectivity that is not cellular, and can include personal area networks (such as Bluetooth, Near Field, etc.), local area networks (such as Wi-Fi), and/or wide area networks (such as WiMax), or other wireless communication.
  • Peripheral connections 580 include hardware interfaces and connectors, as well as software components (e.g., drivers, protocol stacks) to make peripheral connections. It will be understood that the computing device 500 could both be a peripheral device ("to” 582) to other computing devices, as well as have peripheral devices ("from” 584) connected to it.
  • the computing device 500 commonly has a "docking" connector to connect to other computing devices for purposes such as managing (e.g., downloading and/or uploading, changing, synchronizing) content on computing device 500. Additionally, a docking connector can allow computing device 500 to connect to certain peripherals that allow the computing device 500 to control content output, for example, to audiovisual or other systems.
  • the computing device 500 can make peripheral connections 580 via common or standards-based connectors.
  • Common types can include a Universal Serial Bus (USB) connector (which can include any of a number of different hardware interfaces), DisplayPort including MiniDisplayPort (MDP), High Definition Multimedia Interface (HDMI), Firewire, or other types.
  • USB Universal Serial Bus
  • MDP MiniDisplayPort
  • HDMI High Definition Multimedia Interface
  • Firewire or other types.
  • an apparatus comprising: a plurality of interconnect layers on different planes on a semiconductor substrate; a first metal trace and a second metal trace adjacent to the first metal trace in one of the plurality of interconnect layers; and an air gap between the first and the second metal traces, wherein the air gap extends along an entirety of facing surfaces of the first and the second metal traces.
  • the air gap extends substantially straight beyond the edges of the metal traces adjacent dielectric material. Some embodiments also include a third metal trace adjacent the second metal trace and a second air gap between the second and third metal traces. Some embodiments also include a third metal trace adjacent to a fourth metal trace and a second air gap between the third and fourth metal traces in a different plane from the first air gap. In some embodiments, an air gap height comprises between about 15 nm and 50 nm. In some embodiments, an air gap width comprises between about 20 nm and 80 nm.
  • an integrated circuit device comprising: a semiconductor substrate; a plurality of interconnect layers on different planes on the substrate; a plurality of metal traces in one of the plurality of interconnect layers; and a plurality of air gaps between adjacent metal traces, wherein the air gaps extend along an entirety of facing surfaces of the adjacent metal traces.
  • the air gaps extend substantially straight beyond the edges of the metal traces adjacent dielectric material. Some embodiments also include dielectric material adjacent one side of the air gaps, and a layer of sealing material covering the dielectric material. In some embodiments, the sealing material is chosen from the group consisting of: SiCN, AI2O3, and SiN. In some embodiments, an air gap height comprises between about 15 nm and 50 nm. In some embodiments, an air gap width comprises between about 20 nm and 80 nm.
  • a system comprising: a display subsystem; a wireless communication interface; and an integrated circuit device, the integrated circuit device comprising: a semiconductor substrate; a plurality of interconnect layers on different planes on the substrate; a plurality of metal traces in a first of the plurality of interconnect layers; a plurality of metal traces in a second of the plurality of interconnect layers further from the substrate than the first interconnect layer; and a plurality of air gaps in the first and second interconnect layers between adjacent metal traces, wherein the air gaps extend along an entirety of facing surfaces of the adjacent metal traces.
  • the air gaps extend substantially straight beyond the edges of the metal traces adjacent dielectric material.
  • air gaps in the second interconnect layer are deeper than air gaps in the first interconnect layer.
  • air gaps in the second interconnect layer are wider than air gaps in the first interconnect layer.
  • an air gap height comprises between about 15 nm and 50 nm.
  • an air gap width comprises between about 20 nm and 80 nm.
  • a method comprising: forming a first metal trace and a second metal trace adjacent to the first metal trace on a plane on a semiconductor substrate; and forming an air gap between the first and the second metal traces, wherein the air gap extends along an entirety of facing surfaces of the first and the second metal traces.
  • forming an air gap between the first and the second metal traces comprises: depositing dielectric material on the first and second metal traces; etching dielectric material that was deposited beyond the edges of the first and second metal traces; and depositing further dielectric material to enclose the air gap.
  • depositing dielectric material comprises performing atomic layer deposition (ALD) while rotating the substrate.
  • depositing dielectric material further comprises injecting precursor molecules at relatively high velocity.
  • Some embodiments also include depositing a layer of material over the dielectric material to form a hermetic seal.
  • forming an air gap comprises iteratively performing two or more in situ etchs between helmet depositions to remove dielectric material that was deposited beyond the edges of the first and second metal traces.
  • Some embodiments also include forming additional interconnect and dielectric layers on the substrate to form an integrated circuit device.
  • an integrated circuit device with encapsulation of air gaps in interconnects comprising: a plurality of circuit means; a plurality of external contact means; a plurality of interconnect means to conductively couple the circuit means with the external contact means; and a plurality of air gap means between adjacent interconnect means, wherein the air gap means extend along an entirety of facing surfaces of the adjacent
  • the air gap means extend substantially straight beyond the edges of the interconnect means adjacent dielectric means. Some embodiments also include dielectric means adjacent one side of the air gap means, and a layer of sealing means covering the dielectric means. In some embodiments, the sealing means is chosen from the group consisting of: SiCN, AI2O3, and SiN. In some embodiments, an air gap height comprises between about 15 nm and 50 nm. In some embodiments, an air gap width comprises between about 20 nm and 80 nm.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

L'invention concerne un appareil qui comprend : une pluralité de couches d'interconnexion sur différents plans sur un substrat en semiconducteur, une pluralité de couches diélectriques qui séparent la pluralité de couches d'interconnexion, une première piste métallique et une deuxième piste métallique adjacente à la première piste métallique dans l'une de la pluralité de couches d'interconnexion, et un intervalle d'air entre les première et deuxième pistes métalliques, l'intervalle d'air s'étendant le long d'une totalité des surfaces opposées des première et deuxième pistes métalliques. L'invention concerne également d'autres modes de réalisation.
PCT/US2016/068757 2016-12-27 2016-12-27 Encapsulation d'intervalles d'air dans des interconnexions WO2018125063A1 (fr)

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PCT/US2016/068757 WO2018125063A1 (fr) 2016-12-27 2016-12-27 Encapsulation d'intervalles d'air dans des interconnexions

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PCT/US2016/068757 WO2018125063A1 (fr) 2016-12-27 2016-12-27 Encapsulation d'intervalles d'air dans des interconnexions

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090263951A1 (en) * 2007-11-12 2009-10-22 Panasonic Corporation Method for fabricating semiconductor device
JP2010050118A (ja) * 2008-08-19 2010-03-04 Renesas Technology Corp 半導体装置およびその製造方法
US20140110850A1 (en) * 2012-10-24 2014-04-24 Kabushiki Kaisha Toshiba Semiconductor device and method for manufacturing the same
US20140131880A1 (en) * 2010-03-10 2014-05-15 International Business Machines Corporation Methods for fabrication of an air gap-containing interconnect structure
US20140342548A1 (en) * 2012-03-02 2014-11-20 Samsung Electronics Co., Ltd Integrated Circuit Devices Including Interconnections Insulated by Air Gaps and Methods of Fabricating the Same

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090263951A1 (en) * 2007-11-12 2009-10-22 Panasonic Corporation Method for fabricating semiconductor device
JP2010050118A (ja) * 2008-08-19 2010-03-04 Renesas Technology Corp 半導体装置およびその製造方法
US20140131880A1 (en) * 2010-03-10 2014-05-15 International Business Machines Corporation Methods for fabrication of an air gap-containing interconnect structure
US20140342548A1 (en) * 2012-03-02 2014-11-20 Samsung Electronics Co., Ltd Integrated Circuit Devices Including Interconnections Insulated by Air Gaps and Methods of Fabricating the Same
US20140110850A1 (en) * 2012-10-24 2014-04-24 Kabushiki Kaisha Toshiba Semiconductor device and method for manufacturing the same

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