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WO2018132321A1 - Procédés de diagnostic pour les classificateurs et les défauts capturés par des outils optiques - Google Patents

Procédés de diagnostic pour les classificateurs et les défauts capturés par des outils optiques Download PDF

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Publication number
WO2018132321A1
WO2018132321A1 PCT/US2018/012684 US2018012684W WO2018132321A1 WO 2018132321 A1 WO2018132321 A1 WO 2018132321A1 US 2018012684 W US2018012684 W US 2018012684W WO 2018132321 A1 WO2018132321 A1 WO 2018132321A1
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Prior art keywords
wafer
inspection results
interest
processor
inspection
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PCT/US2018/012684
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English (en)
Inventor
Martin Plihal
Erfan Soltanmohammadi
Saravanan Paramasivam
Sairam Ravu
Ankit Jain
Prasanti Uppaluri
Vijay Ramachandran
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Kla-Tencor Corporation
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Priority claimed from US15/835,399 external-priority patent/US11237119B2/en
Application filed by Kla-Tencor Corporation filed Critical Kla-Tencor Corporation
Priority to KR1020197023546A priority Critical patent/KR102557181B1/ko
Publication of WO2018132321A1 publication Critical patent/WO2018132321A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B19/00—Programme-control systems
    • G05B19/02—Programme-control systems electric
    • G05B19/418—Total factory control, i.e. centrally controlling a plurality of machines, e.g. direct or distributed numerical control [DNC], flexible manufacturing systems [FMS], integrated manufacturing systems [IMS] or computer integrated manufacturing [CIM]
    • G05B19/41875—Total factory control, i.e. centrally controlling a plurality of machines, e.g. direct or distributed numerical control [DNC], flexible manufacturing systems [FMS], integrated manufacturing systems [IMS] or computer integrated manufacturing [CIM] characterised by quality surveillance of production
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N7/00—Computing arrangements based on specific mathematical models
    • G06N7/01—Probabilistic graphical models, e.g. probabilistic networks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67242—Apparatus for monitoring, sorting or marking
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
    • H01L22/24—Optical enhancement of defects or not directly visible states, e.g. selective electrolytic deposition, bubbles in liquids, light emission, colour change
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B2219/00—Program-control systems
    • G05B2219/30—Nc systems
    • G05B2219/37—Measurements
    • G05B2219/37224—Inspect wafer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/10—Measuring as part of the manufacturing process
    • H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P90/00—Enabling technologies with a potential contribution to greenhouse gas [GHG] emissions mitigation
    • Y02P90/02—Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS]

Definitions

  • the present disclosure relates to defect detection.
  • Fabricating semiconductor devices typically includes processing a semiconductor wafer using a large number of fabrication processes to form various features and multiple levels of the semiconductor devices.
  • lithography is a semiconductor fabrication process that involves transferring a pattern from a reticle to a photoresist arranged on a semiconductor wafer.
  • Additional examples of semiconductor fabrication processes include, but are not limited to, chemical-mechanical polishing (CMP), etch, deposition, and ion implantation.
  • CMP chemical-mechanical polishing
  • etch etch
  • deposition deposition
  • ion implantation ion implantation
  • Algorithms can be used to detect defects on a wafer.
  • machine learning algorithms are used to create defect classifiers and nuisance filters, the algorithms tend to be considered as black box solutions that are not tuned or diagnosed.
  • Assessment of an inspection recipe typically waited until observing a new set of labeled data received for the assessment or, alternatively, not using some part of the labeled data and reserving it for the validation. Both of these techniques wasted resources.
  • the overall performance assessment may be done based on the quality of the data used to train the classifier and the classifier's ability to learn and extract the information from the data. If the quality of the data is poor and the real defects and nuisance do not have a clear separation boundary, then any classifier will likely fail.
  • the performance of each recipe is evaluated using two measures: discriminability and reliability.
  • discriminability measures There are many discriminability measures.
  • One is the confusion matrix of the training data, which consists of a set of conditional error rates. From these conditional error rates, the cap rate and nuisance rate may be important to semiconductor manufacturers.
  • Cap rate is the ratio of the number of defects of interest (DOI) that are classified correctly to the total number of DOI in the wafer.
  • the nuisance rate is the number of nuisance that are classified as DOI to the total number of defects that are classified as DOI.
  • a higher cap rate and a lower nuisance rate mean a better recipe. However, nuisance rate and cap rate could only previously be evaluated for the training data set that included the actual labels of data.
  • Reliability is a measure that shows how certain the classifier is about the decision it makes. It is a function of the estimation of posteriors done by the classifier. Previously, the classifier reliability was evaluated through the confidence calculation for each defect. [0009] Although discriminability and reliability can be important measures, discriminability and reliability can cover up the reality if the underlying distributions of DOI and nuisance have certain characteristics. This can be referred to as a shadowing effect.
  • the confusion matrix of the training set typically is not sufficient to understand the behavior of the recipe on the entire wafer. If the defects in the training set have been selected in certain way (which normally is done in order to reduce the number of defects for scanning electron microscope (SEM) review and manual classification), then the confusion matrix of the training set is biased toward those defects and is not be a good estimator of the classifier performance over the entire wafer.
  • SEM scanning electron microscope
  • Previous solutions retrain a binary classifier (e.g., nuisance vs. DOI) based on manual classification obtained during process monitoring (production sampling). These previous solutions used the updated classifier to create new DOI/nuisance separation on the subsequent wafer and used the new bins to generate production sample, which in turn was used to tune the next classifier. 50% of the previous solutions' sample is random sampling from the DOI bin of the latest classifier, and the other 50% is random sampling from the entire population. The two samples are used to compare the statistical process control (SPC) of the two inspections, and the second sample also provides "sub-threshold" defects to be used for retraining of the classifier.
  • SPC statistical process control
  • a system for detecting defects of interest in a plurality of wafers comprises a central storage media configured to store a plurality of classified inspection results and an initial defect classifier; a wafer inspection tool; an image data acquisition system; and a processor in electronic communication with the central storage media, the wafer inspection tool, and the image data acquisition system.
  • the processor is configured to execute the instructions of: an inspection engine; a sampling engine, and a tuning engine.
  • the inspection engine instructs the processor to receive inspection results of a first wafer from the wafer inspection tool.
  • the sampling engine instructs the processor to: retrieve the initial defect classifier from the central storage media; filter the inspection results based on the initial defect classifier; review locations of interest on the first wafer from the image data acquisition system based on the filtered inspection results; classify the filtered inspection results based on the initial defect classifier; store the classified filtered inspection results in the central storage media; and identify defects of interest in the first wafer based on the classified filtered inspection results.
  • the tuning engine instructs the processor to update the initial defect classifier based on the stored classified filtered inspection results in the central storage media. For each remaining wafer, the inspection engine instructs the processor to receive inspection results of a next wafer from the wafer inspection tool.
  • the sampling engine instructs the processor to: filter the inspection results of the next wafer based on the initial defect classifier; review locations of interest on the next wafer, using the image data acquisition system based on the filtered inspection results of the next wafer and historical analysis sampling; classify the filtered inspection results of the next wafer based on the reviewed locations of interest on the next wafer; store the classified filtered inspection results for the next wafer in the central storage media; update the defect classifier, using the processor, based on the stored classified filtered inspection results for the next wafer in the central storage media; and identify defects of interest in the next wafer based on the classified filtered inspection results for the next wafer.
  • the tuning engine can instruct the processor to update the defect classifier, using the processor, based on the stored classified filtered inspection results for the next wafer in the central storage media.
  • the sampling engine can instruct the processor to perform the filtering step based on the updated defect classifier.
  • the image data acquisition system can be an SEM review tool.
  • the wafer inspection tool can perform a hot scan to capture inspection results.
  • the wafer inspection tool can be a broadband plasma inspection tool.
  • the defect classifier can send defect of interest data and nuisance data for retraining of the defect classifier.
  • the step of identifying defects of interest can comprise: sampling near a classification boundary of a most recent defect classifier; obtaining information about classifier stability based on fluctuations in the defect classifier; observing a movement in the classification boundary; and identifying the defects of interest based on the predicted movement in the classification boundary.
  • the inspection results or reviewed locations of interest can be stored in the central storage media.
  • a method for identifying defects of interest in a plurality of wafers comprises receiving, at a processor, inspection results of a first wafer from a wafer inspection tool. Using the processor, the inspection results are filtered based on an initial defect classifier. Locations of interest on the first wafer are reviewed, using an image data acquisition system, based on the filtered inspection results. The filtered inspection results are classified, using the processor, based on the reviewed locations of interest on the first wafer. The classified filtered inspection results are stored in a central storage media. Defects of interest in the first wafer are identified based on the classified filtered inspection results.
  • the method comprises receiving, at the processor, inspection results of a next wafer from the wafer inspection tool.
  • the inspection results are filtered based on the initial defect classifier. Locations of interest on the next wafer are reviewed, using the image data acquisition system, based on the filtered inspection results of the next wafer and historical analysis sampling.
  • the filtered inspection results of the next wafer are classified, using the processor, based on the reviewed locations of interest on the next wafer.
  • the classified filtered inspection results for the next wafer are stored in the central storage media.
  • the defect classifier is updated, using the processor, based on the stored classified filtered inspection results for the next wafer in the central storage media. Defects of interest in the next wafer are identified based on the classified filtered inspection results for the next wafer.
  • the image data acquisition system can be an SEM review tool.
  • the wafer inspection tool can perform a hot scan to capture inspection results.
  • the wafer inspection tool can be a broadband plasma inspection tool.
  • the defect classifier can send defect of interest data and nuisance data for retraining of the defect classifier.
  • the step of identifying defects of interest can comprise: sampling near a classification boundary of a most recent defect classifier; obtaining information about classifier stability based on fluctuations in the defect classifier; observing a movement in the classification boundary; and identifying the defects of interest based on the predicted movement in the classification boundary.
  • the method can comprise updating the defect classifier, using the processor, based on the stored classified filtered inspection results for the next wafer in the central storage media.
  • the filtering step can be performed based on the updated defect classifier.
  • the inspection results or reviewed locations of interest can be stored in the central storage media.
  • the step of updating the defect classifier based on the stored classified filtered inspection results in the central storage media can comprise: estimating a cap rate based on a calculated training confusion matrix and estimating a nuisance rate based on the defect classifier in the central storage media, the classified filtered inspection results for the next wafer, and the estimated cap rate.
  • the calculated training confusion matrix is based on the stored classified filtered inspection results for the next wafer in the central storage media.
  • the filtered inspection results can have at least two thresholds associated with the filtered inspection results. A first of the at least two thresholds is for an inspection used for monitoring processes and defects. A second of the at least two thresholds is less than the first threshold and is configured to capture sub-threshold defects during inspection.
  • Figure 1 includes flowcharts (a) and (b) of previous techniques
  • Figure 2 includes charts (a), (b), and (c) of a cap rate versus cutline curve, a nuisance rate versus cutline curve, and a cap rate versus nuisance rate curve, respectively;
  • Figure 3 includes distributions (a), (b), and (c);
  • Figure 4 includes distributions (a) and (b);
  • FIG. 5 is a flowchart of an embodiment of a shadow detect algorithm in accordance with the present disclosure
  • Figure 6 includes charts of accuracy versus number of defects in the pool for an ordinary wafer (a) and a shadowed wafer (b);
  • Figure 7 is a flowchart of an embodiment of a diagnostic model in accordance with the present disclosure.
  • FIG. 8 is a flowchart of an embodiment in accordance with the present disclosure.
  • Figure 9 is a block diagram of a system in accordance with the present disclosure.
  • Figure 10 is a diagram of a dynamic classifier with dynamic sampling and stability analysis in accordance with the present disclosure.
  • Figure 11 is a diagram of a static classifier with dynamic sampling and stability analysis in accordance with the present disclosure.
  • the embodiments disclosed herein address new systems and methods for dealing with process and wafer instability in the early stages of an integrated circuit manufacturing process.
  • One embodiment of the present disclosure is based on the idea of producing a small sample on productions lots in addition to the production sampling, aggregating the sample over several wafers to build an up-to-date classifier, and using classifier to produce new updated samples on the next wafer.
  • the embodiments disclosed herein may be particularly advantageous over existing methods for at least the following reasons.
  • the presently disclosed systems and methods utilize a supplemental (augmented) sample which is generated using the latest known process conditions and is well-suited for returning a superior classifier.
  • the latest known process conditions and defects are far more useful for this purpose than the random samples currently used.
  • the supplemental sample can be automatically tuned to match those process conditions.
  • disclosed systems and methods allow for more relevant broadband plasma inspection with more stable nuisance rate and DOI capture rates.
  • the disclosed systems and methods allow for faster discovery of newly appearing defects occurring during the manufacturing process, and allow for an analysis of the stability of the manufacturing process.
  • One embodiment relies solely on data from the central storage media and the systems and methods leverage the manual classification of defects in the classifier performance on the rest of the inspection. These embodiments cause the classifier to be one wafer behind what is currently being inspected.
  • Another embodiment adds the ability to update the classifier on the current wafer by performing sampling on the wafer defect review tool and then producing the supplemental sample the central storage media.
  • One advantage of this embodiments is that the latest wafer condition is also included in the classifier.
  • the cap rate and the nuisance rate can be estimated for the data where the actual labels are not available.
  • the expected values for the cap rate and the nuisance rate can be provided.
  • the techniques show that all the estimations of cap rate, nuisance rate, posteriors, and confidence are accurate or that the data has the shadowed distribution.
  • Data produced by algorithms can provide diagnostics information that is not available with manually created classifiers such as inline defect organizer (iDO).
  • iDO inline defect organizer
  • a recipe can be assessed.
  • ROC receiver operating curve
  • DOI cap rate true positive rate
  • nuisance rate which is not false positive rate
  • Two outputs from the classifier can be used to build the diagnostic tools.
  • decisions which are the classification results provided by the classifier, can be used.
  • posteriors for each defect can be used. There are different ways that a classifier might find posteriors. Distance from each class centroid or probabilistic measures of accuracy are two examples.
  • the ratio of the number of the DOIs that are correctly classified to the total number of DOIs in the training set can be used. This can be applied to the test set to find the estimation of the number of the DOI potentially missed in the test data.
  • Snm is the set of all defects that originally belongs to class m and classified as class n.
  • SDD is the set of defects that are classified as DOI and are actually DOI.
  • SND is the set of defects that are classified as nuisance and are actually DOI.
  • SDN is the set of defects that are classified as DOI and are actually nuisance.
  • SNN is the set of defects that are classified as nuisance and are also actually nuisance.
  • Equation 1
  • denotes the size (cardinality) of set S.
  • denotes the size (cardinality) of set S.
  • SD is the set of defects that are classified as DOI.
  • SN is the set of defects that are classified as nuisance. Assuming the posterior for the nuisance class associated to defect i is pi, the nuisance rate would be calculated as shown in Equation 2.
  • SD is the set of defects that are classified as DOI.
  • pi is the posterior probability for the nuisance class associated to defect i.
  • denotes the size of set SD.
  • the cap rate can be increased with higher nuisance. This can be done by, for example, moving the cut lines in the confidence histogram and changing the class codes of the defects with lower confidence.
  • the cap rate and nuisance rate can be evaluated for all the possible values of the cutline. Then the three plots can be shown, three examples of which are shown in Figure 2.
  • Chart (a) in Figure 2 shows cap rate versus cutline value.
  • Chart (b) in Figure 2 shows nuisance rate versus cutline value.
  • Chart (c) in Figure 2 shows ROC.
  • An ROC can be a useful representation of the performance of a classifier on a given data set. The user can find what is going to be the nuisance rate for a desired capture rate, and vice versa. With these curves, a user can decide if the values of cutline worthwhile.
  • well-separated distributions may be the ones with short overlap as shown in Figure 3(a), (b), and (c). Data can be well-separated as if a clear boundary can be draw between the two distributions as shown in Figure 3 (a) and (b). Distributions can be well- separated and have multiple regions in the space and be separated using multiple boundaries as shown in Figure 3(c). [0046] Most classifiers can learn this situation. In this scenario, the performance of the classifier is ordinary. Such Probability Density Functions (PDFs) are the ones that normally appears in the wafer, but this is not always the case. A big part of one distribution may have been shadowed.
  • PDFs Probability Density Functions
  • Shadowing effect is a situation when a large part of one class distribution is under the PDF of another class. This situation can happen as mistakes during manual or automated labeling or as a result of not having good attributes to distinguish the shadowed part from the other class. Charts (a) and (b) in Figure 4 are two examples of this situation.
  • the detection of the first case ((a) in Figure 4) is relatively easy because, just by observing the training confusion matrix, it can be determined that the accuracy for one class is poor. Detecting the second case ((b) in Figure 4) is more difficult. This situation can mislead a user about the data on the wafer where big portion of one class will not be detected, no matter what kind of the classifier is used. The misclassification here is not due to the poor performance of the classifier, but may be due to the poor quality of features or labeling.
  • a classifier can be trained with the training set. Then, the training can be sorted to set ascendingly from the confidence values the defects obtained from the classifier. An empty pool can be created and defects can be added one by one from lowest confidence to highest confidence to the pool. After adding each defect, the confusion matrix of the defects in the pool can be calculated and the accuracies of the classes and the number of defects in the pool can be saved. Accuracy for each class can be defined as the number of correctly classified defects of that class to the total number of defects from that class. After using all the defects in the training set, the accuracies versus the number of defects in the pool can be compared. An example of this algorithm is shown in Figure 5.
  • (a) of Figure 6 is from a wafer without shadowed DOI and both DOI and nuisance accuracies improve with the number of defects.
  • the plot (b) in Figure 6 shows a wafer which a DOI class observes a shadowing effect.
  • the DOI bin does not improve with the number of defects. It indicates that high confidence defect are added, but these are being classified incorrectly, which is an indication of the shadowing effect.
  • Figure 7 shows a flow chart for the algorithm of estimating nuisance rate and capture rate and detection of the shadow effect.
  • the training set is used to create the classifier.
  • the classifier is applied to the defects in the test set.
  • the classifier is used to evaluate the confidence and posteriors for all the defects (both in the training set and test set).
  • the estimation of the nuisance rate is done using the posteriors.
  • the estimation of the capture rate is done using the confusion matrix obtained from the training set. Finally, a check is done to find out if the data is under the shadow effect or not. If it is not, then the estimates are trustable.
  • Figure 8 is a flowchart of a method 100 for identifying defects of interest in a plurality of wafers.
  • inspection results of a first wafer are received, such as at a processor, from a wafer inspection tool, which may be a BBP tool or another inspection device.
  • the inspection results are filtered based on an initial defect classifier, such as using the processor.
  • locations of interest on the first wafer are reviewed based on the filtered inspection results, such as using an image data acquisition system.
  • the image data acquisition system may be an SEM review tool or another measurement, inspection, or metrology tool.
  • the filtered inspection results are classified, such as using the processor, based on the reviewed locations of interest on the first wafer.
  • the classified inspection results are stored in a central storage media.
  • defects of interest are identified based on the classified filtered inspection results, such as using the processor. Filtered inspection results may be kept separate, such as for each wafer that is sampled.
  • inspection results of the next wafer are received, such as at the processes, from the wafer inspection tool at 107.
  • the inspection results are filtered based on the initial defect classifier, such as using the processor at 108.
  • locations of interest on the next wafer are reviewed, such as using the image data acquisition system, based on the filtered inspection results and historical analysis sampling.
  • the filtered inspection results are classified, such as using the processor, based on the reviewed locations of interest on the next wafer.
  • the classified filtered results are stored in the central storage media.
  • the defect classifier is updated, such as using the processor, based on the stored classified results in the central storage media.
  • defects of interest in the next wafer are identified, such as using the processor, based on the classified filtered inspection results for the next wafer.
  • Next wafer can refer to the next sequential wafer, but also can mean a second, third, fourth, fifth or later wafer.
  • identifying defects of interest can include sampling near a classification boundary of a most recent defect classifier. Information can be obtained about classifier stability based on fluctuations in the defect classifier. Movement of the classification boundary can be predicted. Defects of interest can be identified based on the predicted movement in the classification boundary.
  • the wafer inspection tool may perform a hot scan to capture inspection results using the method 100.
  • the defect classifier may send defect of interest data and nuisance data to be used for retraining of the defect classifier.
  • the defect classifier can be updated, such as using the processor, based on the stored classified results in the central storage media.
  • the filtering step may be performed based on the updated defect classifier.
  • Inspection results or reviewed locations of interest can be stored in the central storage media.
  • Updating the defect classifier based on the stored classified results in the central storage media can include estimating a cap rate based on a calculated training confusion matrix.
  • the calculated training confusion matrix may be based on the stored classified filtered inspection results for the next wafer in the central storage media.
  • a nuisance rate can be estimated based on the defect classifier in the central storage media, the classified filtered inspection results for the next wafer, and the estimated cap rate.
  • a confidence value also can be calculated based on the initial defect classifier.
  • updating the defect classifier based on the stored classified results in the central storage media further can further include detecting a shadowing effect based on the defect classifier and the calculated confidence value.
  • the filtered inspection results can have at least two thresholds associated with the filtered inspection results.
  • a first of the at least two thresholds is for an inspection may be used for monitoring processes and defects.
  • a second of the at least two thresholds is less than the first threshold and may be configured to capture sub-threshold defects during inspection. This enables sampling on both sides of the threshold to allow changing the classification boundary in both directions.
  • This technique provides multiple advantages. It provides a fast cap rate estimator. Normally, the estimation of the cap rate is an expensive and/or inaccurate task. A user must sample a huge number of defects from a nuisance bin, review them with a tool (e.g., a SEM tool), classify them, and try to come up with an estimate of the number of DOI in the nuisance bin. This method is not feasible most of the time because the number of defects in the DOI bin is extremely large. Embodiments disclosed herein do not need any sample, which makes it extremely fast. A faster nuisance rate estimation is also provided. Normally to estimate the nuisance rate, the users randomly sample from the DOI bin and then SEM review them, and classify them. This extra time for sampling, SEM reviewing, and classification can be removed using techniques disclosed herein.
  • a tool e.g., a SEM tool
  • the estimate of the ROC curve on the entire wafer can be a helpful tool for the semiconductor manufacturers to tune the recipe and to identify the optimal conditions for the inspection given the desired outcome.
  • the disclosed techniques also provide a detection method for shadowing effect.
  • FIG. 9 is a block diagram of a system 200 for detecting defects of interest in a plurality of wafers.
  • the system 200 includes a wafer inspection tool 201, an image data acquisition system 204, a central storage media 203, and a processor 202.
  • the image data acquisition system 204 may be an SEM review tool.
  • the wafer inspection tool 201 may be a BBP inspection tool, which can be configured to perform a hot scan to capture inspection results.
  • the wafer inspection tool 201 also may be an LS tool or an unpatterned wafer surface inspection system, such as the Surfscan SPx manufactured by KLA-Tencor Corporation.
  • the central storage media 203 is configured to store a plurality of classified inspection results and an initial defect classifier.
  • the processor 202 is in electronic communication with the central storage media 203, the wafer inspection tool 201, and the image data acquisition system 204. [0067]
  • the processor 202 is configured to execute the instructions of an inspection engine, a sampling engine, and a tuning engine.
  • the inspection engine instructs the processor to receive inspection results of a first wafer from the wafer inspection tool.
  • the sampling engine instructs the processor to: retrieve the initial defect classifier from the central storage media; filter the inspection results based on the initial defect classifier; review locations of interest on the first wafer from the image data acquisition system based on the filtered inspection results; classify the filtered inspection results based on the initial defect classifier; store the classified filtered inspection results in the central storage media; and identify defects of interest in the first wafer based on the classified filtered inspection results.
  • the tuning engine instructs the processor to update the initial defect classifier based on the stored classified results in the central storage media. [0068] For each remaining wafer, the inspection engine instructs the processor to: receive inspection results of a next wafer from the wafer inspection tool.
  • the sampling engine instructs the processor to: filter the inspection results based on the initial defect classifier; review locations of interest on the next wafer, using the image data acquisition system, based on the filtered inspection results and historical analysis sampling; classify the filtered inspection results based on the reviewed locations of interest on the next wafer; store the classified results in the central storage media; update the defect classifier, using the processor, based on the stored classified results in the central storage media; and identify defects of interest in the next wafer based on the classified filtered inspection results for the next wafer.
  • the tuning engine can instruct the processor to update the defect classifier, using the processor, based on the stored classified results in the central storage media.
  • the sampling engine can instruct the processor to perform the filtering step based on the updated defect classifier.
  • the number of results or number of wafers used to update the defect classifier may be decided by the algorithm and can be controlled by setup. These numbers may depend on the use case and on the inspections. For research and development applications, only a few most recent wafers might be used. In a more mature high volume manufacturing process, the training data could come from more wafers. It may be time-bound and data- sufficiency bound.
  • the defect classifier can send defect of interest data and nuisance data to be used for retraining of the defect classifier.
  • the step of identifying defects of interest can include sampling near a
  • classification boundary of a most recent defect classifier obtaining information about classifier stability based on fluctuations in the defect classifier; observing a movement in the classification boundary; and identifying defects of interest based on the predicted movement in the
  • the inspection results or reviewed locations of interest can be stored in the central storage media 203, which may include a database.
  • a central storage media 203 can store the classified defects along with the rest of the inspection population.
  • a tuning and analysis engine can operate on the stored data after each new data is added to the database.
  • a sampling engine can retrieve the latest classifier from the central server to identify the most suitable defects. This is done by one or more of the following techniques. First, leveraging the latest classifier to sample near the classification boundaries of the model (as both sides of the boundary). Second, using the information about classifier stability obtained from the classification fluctuations on recent wafers.
  • processor 202 and central storage media 203 are illustrated as separate, these may be part of the same control unit. Both the processor 202 and central storage media 203 may be part of the wafer inspection tool 201 or the image data acquisition system 204, or another device. In an example, the processor 202 may be a standalone control unit or in a centralized quality control unit. Multiple processors 202 and/or central storage media 203 may be used. For example three processors 202 may be used for the inspection engine, sampling engine, and tuning engine. [0075] The processor 202 may be implemented in practice by any combination of hardware, software, and firmware.
  • controller readable storage media such as a memory in the central storage media 203 or other memory.
  • the processor 202 and central storage media 203 may be coupled to the components of the system 200 in any suitable manner (e.g., via one or more transmission media, which may include wired and/or wireless transmission media) such that the processor 202 and central storage media 203 can receive the output generated by the system 200.
  • the processor 202 may be configured to perform a number of functions using the output.
  • the processor 202 and central storage media 203, other system(s), or other subsystem(s) described herein may be part of various systems, including a personal computer system, image computer, mainframe computer system, workstation, network appliance, internet appliance, or other device.
  • the subsystem(s) or system(s) may also include any suitable processor known in the art, such as a parallel processor.
  • the subsystem(s) or system(s) may include a platform with high speed processing and software, either as a standalone or a networked tool.
  • the different subsystems may be coupled to each other such that images, data, information, instructions, etc. can be sent between the subsystems.
  • one subsystem may be coupled to additional subsystem(s) by any suitable transmission media, which may include any suitable wired and/or wireless transmission media known in the art.
  • Two or more of such subsystems may also be effectively coupled by a shared computer-readable storage medium (not shown).
  • An additional embodiment relates to a non-transitory computer-readable medium storing program instructions executable on a controller for performing a computer-implemented method of an embodiment disclosed herein.
  • the processor 202 can be coupled to a memory in the central storage media 203 or other electronic data storage medium with non- transitory computer-readable medium that includes program instructions executable on the processor 202.
  • the computer- implemented method may include any step(s) of any method(s) described herein.
  • the processor 202 may be programmed to perform some or all of the steps of Figure 8.
  • the memory in the central storage media 203 or other electronic data storage medium may be a storage medium such as a magnetic or optical disk, a magnetic tape, or any other suitable non-transitory computer-readable medium known in the art.
  • the program instructions may be implemented in any of various ways, including procedure-based techniques, component-based techniques, and/or object-oriented techniques, among others.
  • the program instructions may be implemented using ActiveX controls, C++ objects, JavaBeans, Microsoft Foundation Classes (MFC), SSE (Streaming SIMD Extension), or other technologies or methodologies, as desired.
  • MFC Microsoft Foundation Classes
  • SSE Streaming SIMD Extension
  • each of the steps of the method may be performed as described herein.
  • the methods also may include any other step(s) that can be performed by the controller and/or computer subsystem(s) or system(s) described herein.
  • the steps can be performed by one or more computer systems, which may be configured according to any of the embodiments described herein.
  • the methods described above may be performed by any of the system embodiments described herein.

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Abstract

L'invention concerne une inspection de tranche à taux de nuisance et à taux de capture de défauts d'intérêt stables. La présente technique peut être utilisée pour la découverte de défauts nouvellement apparus qui surviennent pendant le processus de fabrication. Par rapport à une première tranche, des défauts d'intérêt sont identifiés sur la base des résultats d'inspection filtrés classifiés. Pour chaque tranche restante, le classificateur de défauts est mis à jour et les défauts d'intérêt de la tranche suivante sont identifiés sur la base des résultats d'inspection filtrés classifiés.
PCT/US2018/012684 2017-01-10 2018-01-05 Procédés de diagnostic pour les classificateurs et les défauts capturés par des outils optiques WO2018132321A1 (fr)

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US201762581378P 2017-11-03 2017-11-03
US62/581,378 2017-11-03
US15/835,399 US11237119B2 (en) 2017-01-10 2017-12-07 Diagnostic methods for the classifiers and the defects captured by optical tools
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CN113169089A (zh) * 2018-12-18 2021-07-23 科磊股份有限公司 用于多模半导体检验的光学模式选择
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CN114174812A (zh) * 2019-08-01 2022-03-11 科磊股份有限公司 用于具有光学检验的工艺监测的方法
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CN115088125A (zh) * 2020-03-20 2022-09-20 舍弗勒技术股份两合公司 用于检查电化学电池、尤其燃料电池的双极板的方法和检查设施
CN115951619A (zh) * 2023-03-09 2023-04-11 山东拓新电气有限公司 基于人工智能的掘进机远程智能控制系统

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