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WO2018133927A1 - Circuit de convertisseur numérique-analogique comportant deux principes de codage - Google Patents

Circuit de convertisseur numérique-analogique comportant deux principes de codage Download PDF

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Publication number
WO2018133927A1
WO2018133927A1 PCT/EP2017/050944 EP2017050944W WO2018133927A1 WO 2018133927 A1 WO2018133927 A1 WO 2018133927A1 EP 2017050944 W EP2017050944 W EP 2017050944W WO 2018133927 A1 WO2018133927 A1 WO 2018133927A1
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WO
WIPO (PCT)
Prior art keywords
subcell
dac
encoding scheme
conversion cell
dac circuit
Prior art date
Application number
PCT/EP2017/050944
Other languages
English (en)
Inventor
Patrick Vandenameele
Sofia VATTI
Johannes SAMSOM
Koen Cornelissens
Paul STYNEN
Enrico ROVERATO
Marko Kosunen
Jussi Ryynänen
Original Assignee
Huawei Technologies Co., Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Huawei Technologies Co., Ltd. filed Critical Huawei Technologies Co., Ltd.
Priority to PCT/EP2017/050944 priority Critical patent/WO2018133927A1/fr
Priority to CN201780083874.XA priority patent/CN110192345B/zh
Publication of WO2018133927A1 publication Critical patent/WO2018133927A1/fr

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/66—Digital/analogue converters
    • H03M1/74—Simultaneous conversion
    • H03M1/742—Simultaneous conversion using current sources as quantisation value generators

Definitions

  • the present disclosure relates to a Digital-to-Analog Converter (DAC) circuit, in particular a Radio Frequency DAC circuit, with two encoding schemes.
  • the disclosure further relates to a digital transmitter, in particular an all-digital RF transmitter including such a DAC circuit.
  • the disclosure particularly relates to a method to dynamically trade off linearity and power efficiency in digital transmitters.
  • RF-DACs Radio Frequency Digital to Analog Converters
  • RF-DACs are one of the most important building blocks of digital transmitters.
  • RF-DACs are implemented using conversion cells which can be resistors, capacitors or more commonly switches and current sources (called current steering RF-DACs). These conversion cells are arbitrarily weighted according to the application requirements and their number increases with increase in the number of system bits or resolution.
  • the RF-DAC is implemented and used in one hardware configuration that is either tuned to be power efficient with the disadvantage of reducing linearity or tuned to be high linear with the disadvantage of improved power consumption.
  • DAC digital-to-analog converter
  • RF-DAC RF-to-analog converter
  • a basic idea of the invention is to use a digital encoder that produces a digital encoded output, capable of supporting two encoding schemes, such as fully differential and pseudo differential encoding schemes, by controlling the switches in such a way that they can be turned on or off according to the encoding scheme implementation of the RF-DAC.
  • This gives the freedom to choose between the first, e.g. fully differential or the second, e.g. pseudo differential RF-DAC within the same single hardware implementation according to the dynamically changing linearity and power consumption needs.
  • the disclosed approach solves the limitation of mutually exclusive hardware implementation of fully differential and pseudo differential RF-DACs.
  • Fully differential RF-DACs always keep all the conversion cells turned on whereas pseudo differential RF-DACs have the ability to turn certain conversion cells off if their contribution to the output is not needed.
  • the two encoding schemes represent a trade-off between power and linearity.
  • the fully differential scheme has the advantage of being more linear but consumes more power when compared to the pseudo differential scheme, which has the disadvantage of being relatively less linear but consumes lesser power.
  • One of the reasons the implementation of fully differential and pseudo differential RF- DACs on a single hardware sharing arrangement is useful is the power and linearity tradeoff between the two. In the fully differential RF-DAC the output is more linear, however the RF-DAC is quite power consuming as compared to the pseudo differential RF-DAC.
  • the power saved in pseudo differential RF-DAC is dependent on the input signal used, and is found to be equal to the PAPR (Peak-to-Average Power Ratio) for a full-scale input signal.
  • PAPR Peak-to-Average Power Ratio
  • This disclosure resolves the above described implementation limitation and presents a DAC circuit and a method to implement both the fully differential and pseudo differential RF-DACs in a single hardware sharing implementation. Since the hardware requirements are same for both the implementations, as will be evident shortly, the idea here is to modify the digital encoding process before the RF-DAC in such a way that the RF-DAC can accommodate both the fully differential and pseudo differential types.
  • This hardware sharing implementation of RF-DACs is desirable because it gives the ability to dynamically change requirements on linearity according to the application needs without changing any hardware.
  • the invention relates to a digital-to-analog converter (DAC) circuit, comprising: a plurality of conversion cells, each conversion cell comprising a pair of subcells, each subcell comprising a current source and a switch which is configured to switch the corresponding current source to an output of the subcell; and a digital encoder, configured to generate a digitally encoded output signal for controlling the switches of the pair of subcells of the conversion cells, wherein the digital encoder is configured to selectively generate the digitally encoded output signal according to a first encoding scheme or according to a second encoding scheme.
  • DAC digital-to-analog converter
  • Such a DAC circuit can flexibly implement two different encoding schemes in one hardware implementation.
  • a first encoding scheme may be applied to provide a highly linear DAC while a second encoding scheme may be applied to save power consumption.
  • the first encoding scheme is a fully differential encoding scheme
  • the second encoding scheme is a pseudo-differential encoding scheme
  • each conversion cell is configured to adopt a ternary output state comprising a high state, a low state and a zero state when the second encoding scheme is selected, wherein the ternary output state is based on a switching state of the switches of the conversion cell.
  • each conversion cell is configured to adopt only two of the three output states at any given time.
  • the second encoding scheme e.g. the pseudo-differential encoding scheme
  • to represent positive RF-DAC output only high and zero output states of conversion cells will be used, and to represent a negative RF-DAC output only low and zero output states of conversion cells will be used.
  • the high and low states are not simultaneously allowed at a given time. This way, the waste in power consumption of the RF-DAC can be minimized, since positive and negative conversion cell contributions will never cancel each other at the RF-DAC output.
  • each conversion cell is configured to: generate a positive output signal when a first subcell of the conversion cell is turned on and a second subcell of the conversion cell is turned off, generate a negative output signal when the first subcell is turned off and the second subcell is turned on, and generate a zero output signal when both subcells of the conversion cell are turned off.
  • the digital encoder is configured to turn on always one and only one subcell of a conversion cell when the first encoding scheme is selected.
  • each conversion cell is configured to adopt a differential output state comprising a high state and a low state when the first encoding scheme is selected, wherein the differential output state is based on a switching state of the switches of the conversion cell.
  • the DAC circuit can operate at high precision due to compensation of bias in the differential mode.
  • each conversion cell is configured to: generate a positive output signal when a first subcell of the conversion cell is turned on and a second subcell of the conversion cell is turned off, and generate a negative output signal when the first subcell is turned off and the second subcell is turned on.
  • a first subcell of the pair of subcells comprises a first current source configured to generate a first current; and a second subcell of the pair of subcells comprises a second current source configured to generate a second current, wherein a total output current at the DAC circuit is formed by adding contributions from all the first current sources of the first subcells and subtracting contributions from all the second current sources of the second subcells.
  • each subcell comprises a first transistor forming the switch and a second transistor forming the current source.
  • the DAC circuit comprises a controller configured to control the digital encoder selecting the first encoding scheme or the second encoding scheme.
  • the controller can be used to flexibly switch between the first and the second encoding schemes.
  • the controller can also be used to flexibly implement other encoding schemes.
  • the controller is configured to control the digital encoder based on linearity and/or power requirements.
  • DAC circuit can operate as high-precision converter or as power-saving converter depending on the specific requirements.
  • the controller can switch the different operation modes of the DAC circuit on-the-fly.
  • the controller is configured to set part of the conversion cells to zero, in particular during backoff. This provides the advantage that further power can be saved, for example in backoff situations, when some or all of the conversion cells are set to zero.
  • the digital encoder is configured to selectively generate the digitally encoded output signal according to a third encoding scheme in which each conversion cell is configured to simultaneously adopt a high state, a low state and a zero state.
  • the invention relates to a digital transmitter circuit, comprising: a modulator circuit, configured to modulate a radio signalto provide a digital input signal; and a DAC circuit according to the first aspect as such or according to any of the implementation forms of the first aspect, configured to convert the digital input signal to an analog output signal.
  • Such a digital transmitter utilizes a DAC, e.g. an RF-DAC, providing trade-off between high linearity and reduced power consumption.
  • the digital transmitter can flexibly transmit according to different different encoding schemes providing trade-off between linearity and power consumption.
  • the invention relates to a method for digital-to-analog conversion by a digital-to-analog converter (DAC) circuit comprising a digital encoder and a plurality of conversion cells, wherein each conversion cell comprises a pair of subcells and each subcell comprises a current source and a switch which is configured to switch the corresponding current source to an output of the subcell, the method comprising: generating, by the digital encoder, a digitally encoded output signal for controlling the switches of the pair of subcells of the conversion cells, wherein the digitally encoded output signal is selectively generated according to a first encoding scheme or according to a second encoding scheme.
  • DAC digital-to-analog converter
  • Such a method for digital-to-analog conversion can flexibly implement two different encoding schemes in one hardware implementation of a DAC.
  • a first encoding scheme may be applied to provide high linearity while a second encoding scheme may be applied to provide reduced power consumption.
  • Fig. 1 shows a block diagram illustrating the basic structure of a digital-to-analog converter (DAC) circuit 100 according to an implementation form;
  • DAC digital-to-analog converter
  • Figs. 2a, 2b, 2c show circuit diagrams illustrating a current cell 103 of the DAC circuit 100 of Fig. 1 in different output states;
  • Fig. 3 shows a non-linear output impedance model 300 for the entire DAC circuit 100 of Fig. 1 according to an implementation form
  • Figs. 4a and 4b show diagrams 400a, 400b illustrating integral non-linearity (INL) for a fully differential (Fig. 4a) and a pseudo-differential RF-DAC (Fig. 4b) implementation;
  • Fig. 5 shows output spectra 500 for a fully differential 502 and a pseudo-differential 501 RF-DAC implementation for a sine wave;
  • Fig. 6 shows output spectra 600 of a fully differential 602 and a pseudo-differential 601 RF- DAC implementation for a 20 MHz LTE signal.
  • Fig. 1 shows a block diagram illustrating the basic structure of a digital-to-analog converter (DAC) circuit 100 according to an implementation form.
  • DAC digital-to-analog converter
  • Fig. 1 a simplified internal structure of RF-DAC 100 along with a digital encoder 105 is shown.
  • the RF-DAC 100 is made of conversion cells 103 (one 103 of multiple conversion cells is exemplary highlighted in Fig. 1 ), where each cell 103 is divided into the p and n subcells 110, 120.
  • the general structure of the subcells 110, 120 is similar and although there can be mismatches among the subcells 110, 120, they can be ignored hereinafter.
  • the current source 111 , 121 is the basic conversion element here, implemented e.g. by using CMOS transistors, and can be connected or disconnected from output 113, 123 by means of switches 112, 122, which again can be implemented e.g. by using CMOS transistors.
  • the current I of the source 111 , 121 is proportional to the arbitrary weight assigned to the conversion cell 103 inside a given RF-DAC implementation.
  • the switches 112, 122 are turned on or off by the digital encoder's 105 output signal 106. Please note that the position of current source 111 , 121 and switch 112, 122 is not strictly limited to the schematic shown in Fig. 1 , but they can be swapped.
  • the output 113, 123, as shown in Fig. 1 is obtained by the differential combination of all the parallel p-subcells 110 and all the parallel n-subcells 120 with positive and negative terminals as indicated.
  • the RF-DAC 100 is implemented and used in both configurations (referred to as encoding schemes 101 , 102), e.g. as pseudo differential or as fully differential as described in the following.
  • the digital-to-analog converter (DAC) circuit 100 depicted in Fig. 1 includes a digital encoder 105 and a plurality of conversion cells 103. Each conversion cell 103 includes a pair of subcells 110, 120. Each subcell (e.g.
  • the subcell 110 includes a current source 111 and a switch 112 which is configured to switch the corresponding current source 111 to an output 113 of the subcell 110.
  • the digital encoder 105 is configured to generate a digitally encoded output signal 106 for controlling the switches 112, 122 of the pair of subcells 110, 120 of the conversion cells 103.
  • the digital encoder 105 is configured to selectively generate the digitally encoded output signal 106 according to a first encoding scheme
  • 102 e.g. a pseudo-differential encoding scheme.
  • Each conversion cell 103 may adopt a ternary output state including a high state, a low state and a zero state when the second encoding scheme 102 is selected.
  • the ternary output state is based on a switching state 201 , 202, 203, 204 of the switches 112, 122 of the conversion cell 103.
  • Each conversion cell 103 may be configured to adopt only two of the three output states at any given time.
  • Each conversion cell 103 may be configured to: generate a positive output signal 113, 123 when a first subcell 110 of the conversion cell 103 is turned on 204 and a second subcell 120 of the conversion cell 103 is turned off 201 , e.g. as shown below in Fig. 2a; to generate a negative output signal 113, 123 when the first subcell 110 is turned off 203 and the second subcell 120 is turned on 202, e.g. as shown below in Fig. 2c; and to generate a zero output signal 113, 123 when both subcells 110, 120 of the conversion cell 103 are turned off 203, 201 , e.g. as shown below in Fig. 2b.
  • the digital encoder 105 may be configured to turn on always one and only one subcell 110, 120 of a conversion cell 103 when the first encoding scheme 101 is selected.
  • Each conversion cell 103 may be configured to adopt a differential output state comprising a high state and a low state when the first encoding scheme 101 is selected, wherein the differential output state is based on a switching state 201 , 202, 203, 204 of the switches
  • Each conversion cell 103 may be configured to: generate a positive output signal 113, 123 when a first subcell 110 of the conversion cell 103 is turned on 204 and a second subcell 120 of the conversion cell 103 is turned off 201 , and generate a negative output signal
  • a first subcell 110 of the pair of subcells 110, 120 may include a first current source 111 configured to generate a first current.
  • a second subcell 120 of the pair of subcells 110, 120 may include a second current source 121 configured to generate a second current.
  • a total output current at the DAC circuit may be formed by adding contributions from all the first current sources 111 of the first subcells 110 and subtracting contributions from all the second current sources 121 of the second subcells 120.
  • Each subcell 110, 120 may include a first transistor forming the switch 112, 122 and a second transistor forming the current source 111 , 121 .
  • the DAC circuit 100 may include a controller configured to control the digital encoder 105 selecting the first encoding scheme 101 or the second encoding scheme 102.
  • the controller may be configured to control the digital encoder 105 based on linearity and/or power requirements.
  • the controller may be configured to set part of the conversion cells 103 to zero, in particular during backoff.
  • the digital encoder 105 may be configured to selectively generate the digitally encoded output signal 106 according to a third encoding scheme in which each conversion cell 103 is configured to simultaneously adopt a high state, a low state and a zero state.
  • Figs. 2a, 2b, 2c show circuit diagrams illustrating a current cell 103 of the DAC circuit 100 of Fig. 1 in different output states.
  • the depicted current cells 103 represent current cells 103 as depicted in Fig. 1 which are in different states.
  • Figs. 1 and 2 In order to better understand the difference between fully differential and pseudo differential RF-DACs consider the current cell 103 depicted in Figs. 1 and 2. For the fully differential case always one and only one of the conversion subcells 110, 120 will be turned on, as controlled by the digital encoder 105 output 106.
  • a low (or -1 ) output will be achieved if the n subcell 120 is turned on 202 and a high (or +1 ) output will be achieved if the p subcell 110 is turned on 204.
  • a pseudo differential RF-DACs conversion cell 103 has three output possibilities. These possibilities, as shown in Figure 2, are: low (or -1 ) output with n subcell 120 turned on 202, high (or +1 ) output with p subcell 110 turned on 204 and zero output with neither one of the subcells 110, 120 turned on, i.e. both subcells 110, 120 turned off 203, 201 . Again the switches 112, 122 are controlled by the digital encoder 105 output 106.
  • the pseudo differential encoding uses only two of the three allowed conversion cell 103 output states at any given time.
  • to represent positive RF-DAC output 113 123 only high and zero output states of conversion cells 103 are used, and to represent a negative RF-DAC output only low and zero output states of conversion cells 103 are used.
  • the high and low states are not simultaneously allowed at a given time. This way, the waste in power consumption of the RF-DAC can be minimized, since positive and negative conversion cell contributions will never cancel each other at the RF-DAC output 113, 123.
  • Fig. 3 shows a non-linear output impedance model 300 for the entire DAC circuit 100 of Fig. 1 according to an implementation form.
  • this impedance model 300 all the conversion cells are taken into account.
  • a contribution of the p subcells 110 can be modeled by a parallel circuit of a first impedance element 315 of (N- n P )G 0 ff, a current source 314 of n p LSB, a second impedance element 313 of n p G ON and a third impedance element 311 of RL/2.
  • a contribution of the n subcells 120 can be modeled by a parallel circuit of a first impedance element 325 of (N-n M )G 0 ff, a current source 324 of ⁇ I LSB, a second impedance element 323 of n M G ON and a third impedance element 321 of
  • n P Conversion cells switched to high output
  • n M Conversion cells switched to low output
  • Figs. 4a and 4b show diagrams 400a, 400b illustrating integral non-linearity (INL) for a fully differential (Fig. 4a) and a pseudo-differential RF-DAC (Fig. 4b) implementation.
  • FIG. 4a and 4b show the INL of fully differential (Fig. 4a) and pseudo differential (Fig. 4b) RF-DACs with finite output resistance and INLs normalized to LSB.
  • the simulations were carried out using a 10 bit RF-DAC, where the two encoding schemes were implemented according to the description above.
  • the non-linear model values used here are typical of CMOS implementations of the RF- DAC, and are given as:
  • Figure 5 shows the output for both the fully differential 502 and pseudo differential 501 RF-DACs.
  • Fig. 5 shows output spectra 500 for a fully differential 502 and a pseudo-differential 501 RF-DAC implementation for a sine wave.
  • FIG. 6 shows the output for both the fully differential 602 and pseudo differential 601 RF-DACs.
  • Fig. 6 shows output spectra 600 of a fully differential 602 and a pseudo- differential 601 RF-DAC implementation for a 20 MHz LTE signal.
  • pseudo differential RF-DAC 601 has worse ACLR (Adjacent Channel Leakage Ratio) value than the fully differential RF-DAC 602, therefore pointing towards a more non-linear behavior.
  • Figures 4 to 6 confirm the discussions above about the more non-linear behavior of pseudo differential RF-DAC when compared to the fully differential one.
  • the present disclosure also supports a method for digital-to-analog conversion by a digital-to-analog converter (DAC) circuit comprising a digital encoder and a plurality of conversion cells, wherein each conversion cell comprises a pair of subcells and each subcell comprises a current source and a switch which is configured to switch the corresponding current source to an output of the subcell.
  • DAC digital-to-analog converter
  • the method allows performing the functionality of the DAC circuits 100, 200 as described above.
  • the present disclosure also supports a computer program product including computer executable code or computer executable instructions that, when executed, causes at least one computer to execute the performing and computing steps described herein, in particular the steps of the method described above.
  • a computer program product may include a readable non-transitory storage medium storing program code thereon for use by a computer.
  • the program code may perform the method described above.

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Analogue/Digital Conversion (AREA)

Abstract

L'invention porte sur un circuit (100) de convertisseur numérique-analogique (CNA), comprenant : une pluralité de cellules de conversion (103), chaque cellule de conversion (103) comprenant une paire de sous-cellules (110, 120), chaque sous-cellule (110) comprenant une source de courant (111) et un commutateur (112) qui sert à commuter la source de courant (111) correspondante à une sortie (113) de la sous-cellule (110) ; et un codeur numérique (105), servant à générer un signal de sortie (106) à codage numérique pour la commande des commutateurs (112, 122) de la paire de sous-cellules (110, 120) des cellules de conversion (103), le codeur numérique (105) servant à générer sélectivement le signal de sortie (106) à codage numérique selon un premier principe de codage (101) ou selon un deuxième principe de codage (102).
PCT/EP2017/050944 2017-01-18 2017-01-18 Circuit de convertisseur numérique-analogique comportant deux principes de codage WO2018133927A1 (fr)

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PCT/EP2017/050944 WO2018133927A1 (fr) 2017-01-18 2017-01-18 Circuit de convertisseur numérique-analogique comportant deux principes de codage
CN201780083874.XA CN110192345B (zh) 2017-01-18 2017-01-18 具有两种编码方案的数模转换器电路

Applications Claiming Priority (1)

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PCT/EP2017/050944 WO2018133927A1 (fr) 2017-01-18 2017-01-18 Circuit de convertisseur numérique-analogique comportant deux principes de codage

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Citations (3)

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US20070252739A1 (en) * 2006-04-28 2007-11-01 Artimi Inc. Digital-to-analogue converters
US20110273317A1 (en) * 2009-01-29 2011-11-10 Munehiko Nagatani Current-switching cell and digital-to-analog converter
US20140253357A1 (en) * 2013-03-08 2014-09-11 Qualcomm Incorporated Low glitch-noise dac

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GB2390945B (en) * 2001-08-24 2004-03-10 Fujitsu Ltd Switching circuitry
US20030201924A1 (en) * 2002-04-27 2003-10-30 Lakshmikumar Kadaba R. Digital-to-analog converter
KR100454129B1 (ko) * 2002-05-06 2004-10-26 삼성전자주식회사 코드 변환 장치, 디지털-아날로그 변환 장치, 그리고 지연동기 루프회로
CN1855727B (zh) * 2005-04-28 2010-06-16 瑞昱半导体股份有限公司 具噪声整形功能的电路

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070252739A1 (en) * 2006-04-28 2007-11-01 Artimi Inc. Digital-to-analogue converters
US20110273317A1 (en) * 2009-01-29 2011-11-10 Munehiko Nagatani Current-switching cell and digital-to-analog converter
US20140253357A1 (en) * 2013-03-08 2014-09-11 Qualcomm Incorporated Low glitch-noise dac

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CN110192345A (zh) 2019-08-30

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