[go: up one dir, main page]

WO2018137560A1 - Module de puissance et son procédé de fabrication - Google Patents

Module de puissance et son procédé de fabrication Download PDF

Info

Publication number
WO2018137560A1
WO2018137560A1 PCT/CN2018/073368 CN2018073368W WO2018137560A1 WO 2018137560 A1 WO2018137560 A1 WO 2018137560A1 CN 2018073368 W CN2018073368 W CN 2018073368W WO 2018137560 A1 WO2018137560 A1 WO 2018137560A1
Authority
WO
WIPO (PCT)
Prior art keywords
conductive layer
chip
power module
terminal
electrically connected
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2018/073368
Other languages
English (en)
Chinese (zh)
Inventor
李慧
杨胜松
廖雯祺
杨钦耀
李艳
张建利
曾秋莲
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BYD Co Ltd
Original Assignee
BYD Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by BYD Co Ltd filed Critical BYD Co Ltd
Publication of WO2018137560A1 publication Critical patent/WO2018137560A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5387—Flexible insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/24137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors

Definitions

  • the present application relates to the field of hybrid integrated circuits, and in particular to a power module and a method of fabricating the same.
  • a power semiconductor module is a device that packages a plurality of semiconductor chips together in a certain circuit structure.
  • IGBT Insulated Gate Bipolar Transistor
  • the IGBT chip and the diode chip are integrated on a common substrate, and the power device of the power semiconductor module is insulated from the mounting surface thereof (ie, the heat sink) .
  • the power semiconductor module includes a supporting electrical adapter block, which makes the module larger in size and less integrated.
  • the object of the present invention is to provide a power module and a manufacturing method thereof, which are intended to solve the problem that a conventional power semiconductor module needs to be opened and includes a supporting electrical switch block, and the module has a large volume.
  • the invention provides a power module comprising:
  • An insulating dielectric substrate having a patterned first conductive layer on an upper surface thereof;
  • At least one switch tube chip and at least one diode chip, the switch tube chip and the diode chip are attached on an upper surface of the insulating dielectric substrate to form an electrical connection with the first conductive layer;
  • a patterned second conductive layer disposed on the insulating layer, wherein the second conductive layer is electrically connected to the first conductive layer through the conductive material, and the switch chip is formed by the conductive material Connected to the diode chip circuit.
  • the invention also provides a method for manufacturing a power module, comprising the following steps:
  • An insulating layer is disposed on the first insulating dielectric substrate to encapsulate the switch chip and the diode chip;
  • the conductive material inside is electrically connected to the first conductive layer, and the switch transistor chip and the diode chip are electrically connected.
  • the present invention has at least the following advantages:
  • the above power module and its manufacturing method module package do not need to be opened and sealed, which saves production cost; in addition, the power semiconductor chip is electrically connected by opening a through hole in the insulating layer and filling the conductive material with the upper conductive layer, thereby reducing the module.
  • the volume is conducive to the miniaturization of the module.
  • FIG. 1 is a schematic structural view of a power module according to a first embodiment of the present invention
  • FIG. 2 is a schematic structural diagram of a power module according to a second embodiment of the present invention.
  • FIG. 3 is a schematic structural diagram of an embodiment of a power module overall layout according to the present invention.
  • FIG. 4 is a schematic structural view of a heat dissipation flat plate according to an embodiment of the present invention.
  • FIG. 5 is a flow chart of a method of fabricating a power module in accordance with a preferred embodiment of the present invention.
  • the power module in the preferred embodiment of the present invention includes an insulating dielectric substrate 10 , at least one switch chip 20 , at least one diode chip 30 , an insulating layer 40 , and a second conductive layer 50 .
  • the insulating dielectric substrate 10 has oppositely disposed upper and lower surfaces, at least one of which is coated with a metal, and the intermediate layer is a ceramic layer 11.
  • the upper surface of the insulating dielectric substrate 10 is covered with a metal to form a patterned first conductive layer 12, and the lower surface may be covered with a metal to form another patterned conductive layer 13.
  • the heat dissipating fins 14 may be directly disposed (see figure 2).
  • the switch tube chip 20 in this embodiment is an IGBT, and the diode chip 30 is an FRD (Fast Recovery Diode).
  • the power module has one or more IGBTs and one or more FRDs to constitute a drive circuit.
  • the upper and lower surfaces of the switch tube chip 20 have polarity pins.
  • the upper surface of the switch tube chip 20 has two polarity pins, which are a gate and an emitter, respectively, and a lower surface has a collector.
  • the upper surface of the diode chip 30 has an anode, and the lower surface has a cathode, or vice versa.
  • the switch tube chip 20 and the diode chip 30 are attached to the upper surface of the insulating dielectric substrate 10 to form an electrical connection with the first conductive layer 12. Specifically, when a circuit pattern is formed on the first conductive layer 12, and the switch chip 20 and the diode chip 30 are attached to the circuit pattern by soldering or crimping, the polarity pins of the lower surface and the corresponding circuit patterns are formed. A circuit connection is formed to lead.
  • An insulating layer 40 covers the insulating dielectric substrate 10, and the switching transistor chip 20, the diode chip 30, and the first conductive layer 12 are covered, and the insulating layer 40 is covered on the insulating dielectric substrate by lamination. 10 on.
  • the lower surface of the insulating layer 40 is provided with a recess for accommodating the switch tube chip 20 and the diode chip 30.
  • the predetermined position of the insulating layer 40 defines a plurality of through holes 42 extending through the upper and lower surfaces thereof. As shown in FIG. 1 and FIG.
  • the plurality of through holes 42 extend through the insulating layer 40 to the switch tube chip 20 , the diode chip 30 , the first conductive layer 12 and the second conductive layer 50 , respectively, and the through holes 42 .
  • a conductive material electrically connected to the switch chip 20, the diode chip 30, the first conductive layer 12, and the second conductive layer 50 is filled therein.
  • the plurality of through holes 42 extend through the second conductive layer 50 and the insulating layer 40 to the switch chip chip 20, the diode chip 30, and the first conductive layer 12, respectively, and the through holes 42 are filled with A conductive material electrically connected to the switch chip 20, the diode chip 30, the first conductive layer 12, and the second conductive layer 50.
  • the through holes 42 of the same circuit connection path are disposed as much as possible to ensure the overcurrent capability of the circuit and improve the heat dissipation capability of the upper portion of the chip.
  • the insulating layer 40 is formed by pre-pregnant heating and curing, and at the same time, the conductive material in the through hole 42 is simultaneously metalized; wherein the prepreg is mainly composed of a resin and a reinforcing material.
  • the reinforcing material may be a fiberglass cloth, a paper base, a composite material or the like, and the coefficient of thermal expansion of the prepreg is matched with the thermal expansion coefficient of the switch tube chip 20 and the diode chip 30 to prevent the power device from being mismatched with the thermal expansion coefficient of the packaging material. The failure of the device is subject to excessive stress.
  • the second conductive layer 50 is disposed on the insulating layer 40, specifically, laminated on the insulating layer 40 by lamination.
  • the second conductive layer 50 is electrically connected to the switch chip 20, the diode chip 30, and the first conductive layer 12 through the conductive material, and the switch chip 20 and the diode chip 30 are electrically connected by the conductive material.
  • a circuit pattern is formed on the second conductive layer 50, and the polarity pins on the upper surface of the switch tube chip 20 are electrically connected to the corresponding circuit patterns for extraction.
  • the switch chip 20 is electrically connected to the second conductive layer 50 through the through hole 42 which is formed on the insulating layer 40, thereby replacing the electrical transfer block to achieve electrical connection, thereby reducing the volume of the module and facilitating the module. miniaturization.
  • the insulating dielectric substrate 10 in the listed embodiment is not limited to a DBC (Direct Bond Copper) substrate, and may be a DBA (Direct Bond Aluminum) substrate, or any other surface-covered metal insulating medium. Substrate, refer to Figure 1. In another embodiment, the insulating dielectric substrate 10 may be a copper-clad ceramic substrate having a surface coated with copper and the other surface provided with heat dissipating fins 14, as shown in FIG.
  • the second conductive layer 50 is a conductive metal sheet, and may be made of a copper sheet, an aluminum sheet or other conductive metal material.
  • the second conductive layer 50 may be made of a metal coated with a lower surface of another insulating dielectric substrate.
  • Another insulating dielectric substrate has opposite upper and lower surfaces, at least one of which is coated with a metal to form a second conductive layer 50, and the intermediate layer is a ceramic layer.
  • the upper surface may be coated with metal to form another conductive layer, and heat dissipating fins may also be provided.
  • the power module further includes a lead terminal 60 (ie, a power module pin), and one end of the lead terminal 60 is fixedly electrically connected to the first conductive layer 12 or the second conductive layer 50, and the through hole 42 is matched.
  • the conductive material inside is electrically connected to the corresponding polarity pins of the switch tube chip 20 and the diode chip 30, and the other end of the lead terminal 60 is outwardly extended.
  • the lead terminal 60 is for taking the switch tube chip 20 and the diode chip 30 out of the terminals of the circuit in a preset circuit for connection with an external circuit.
  • the lead terminal 60 may be fixed to the first conductive layer 12 or may be fixed to the second conductive layer 50.
  • the first terminal 12 is fixed to the first conductive layer 12 as an example.
  • the lead terminal 60 includes a control terminal 62 including an emitter power terminal 61A and a collector power terminal 61B, and a collector power terminal 61B, the first conductive layer 12 including a first circuit pattern 121 and a first portion on opposite sides of the power module
  • the two circuit patterns 122 include a emitter pad 121A and a collector pad 121B which are disposed side by side on the same side of the power module.
  • the switch pin chip 20 and the polarity pin on the lower surface of the diode chip 30 are electrically connected to the collector pad 121B of the first circuit pattern 121, and the collector power terminal 61B is electrically connected to the collector pad 121B;
  • the polarity pins of the upper surface of the chip 20 and the diode chip 30 are electrically connected to the emitter pads of the first circuit pattern 121 through the conductive materials in the corresponding through holes 42 and the second conductive layer 50, respectively.
  • 121A and the second circuit pattern 122, the control terminal 62 and the second circuit pattern 122 are soldered, and the emitter power terminal 61A and the emitter pad 121A of the first circuit pattern 121 are soldered.
  • the second circuit pattern 122 is also a pin pad.
  • the second conductive layer 50 includes a third circuit pattern 51 and a fourth circuit pattern 52.
  • the first circuit pattern 121 is connected to the switch chip through the conductive material in the corresponding through hole 42 and the third circuit pattern 51. 20 and a polarity pin on the upper surface of the diode chip 30.
  • the second circuit pattern 122 is connected to the polarity pin of the upper surface of the switch tube chip 20 through the conductive material in the corresponding through hole 42 and the fourth circuit pattern 52.
  • the switch tube chip 20 is electrically connected to the emitter pad 121A of the first circuit pattern 121, and is electrically connected to the second circuit pattern 122, and is connected to the collector of the first circuit pattern 12.
  • the pad 121B is electrically connected to a collector.
  • Figure 3 is a schematic diagram of the overall layout of the power module.
  • the filled area in the figure is substantially graphically patterned for the first conductive layer 12, and the blackened area of the wire frame is substantially graphically patterned for the second conductive layer 50.
  • the switch tube chip 20 and the diode chip 30 are soldered to the corresponding positions of the first conductive layer 12, and the control terminal 62 and the power terminal 61 are also soldered to the corresponding positions of the first conductive layer 12, and the chip polarity and the corresponding terminal are made via the metalized through holes 42.
  • the control terminal 62 and the power terminal 61 are respectively located on both sides of the module, and the low voltage control end is away from the high voltage power end, which reduces the electrical interference of the high voltage end to the low voltage end, and improves the reliability of the control end.
  • the power module further includes a heat sink 70 that is disposed on a lower surface of the insulating dielectric substrate 10 and/or an upper surface of the second conductive layer 50 .
  • the heat sink 70 may be directly formed of a metal-clad insulating dielectric substrate 10 (e.g., heat dissipating fins 14), or may be separately provided externally.
  • the heat sink 70 can be separately disposed on the lower surface of the power module, or can be disposed on the upper and lower surfaces of the power module to achieve double-sided heat dissipation.
  • the heat sink 70 is a heat dissipating fin or a flat heat pipe.
  • Figure 4 is a schematic view of a flat heat pipe. The heat generated by the switch tube chip 20 and the diode chip 30 is conducted to the heat pipe evaporation surface 71, and the working fluid 72 in the capillary absorbs heat and vaporizes and fills the steam chamber. The condensing surface 73 of the flat heat pipe 70 is cooled by circulating cooling liquid. The steam 90 is recondensed into a liquid on the condensation surface 73. Under the action of the capillary suction force of the capillary core 74, the liquid re-flows back to the evaporation surface 71, and the above steps are repeated to achieve circulating heat dissipation.
  • a manufacturing method capable of manufacturing the above power module including the following steps:
  • an insulating dielectric substrate 10 having a first conductive layer 12 on its upper surface is disposed.
  • the insulating dielectric substrate 10 is provided to have oppositely disposed upper and lower surfaces, at least one of which is metal-coated.
  • the upper surface of the insulating dielectric substrate 10 is covered with a metal to form a patterned first conductive layer 12, and the lower surface may be covered with a metal to form another conductive layer, and the heat dissipating fins 14 may be disposed (see FIG. 3); A corresponding circuit pattern should be preset on the first conductive layer 12.
  • At least one switch chip 20 and at least one diode chip 30 are disposed on the first conductive layer 12 to form an electrical connection with the first conductive layer 12.
  • the switch transistor chip 20 is an IGBT
  • the diode chip 30 is an FRD.
  • the upper and lower surfaces of the chip have polar pins, and the switch chip 20 is attached to the upper surface of the insulating dielectric substrate 10 to form an electrical connection with the first conductive layer 12.
  • the switch chip 20 and the diode chip 30 are attached to the circuit pattern of the first conductive layer 12 by soldering or crimping, the polarity pins of the lower surface are connected to the corresponding circuit pattern forming circuit to be led out. .
  • an insulating layer 40 is disposed on the first insulating dielectric substrate 10, and the switch tube chip 20 and the diode chip 30 are covered.
  • the insulating layer 40 is a prepreg, and the prepreg is insulated, and its thermal expansion coefficient needs to be matched with the thermal expansion coefficient of the switch chip 20 as much as possible.
  • a second conductive layer 50 is disposed on the insulating layer 40.
  • the second conductive layer 50 is preferably a conductive metal sheet.
  • the second conductive layer 50 (conductive metal sheet or second insulating dielectric substrate), the prepreg, and the insulating dielectric substrate 10 provided with the switch tube chip 20 and the diode chip 30 are sequentially laminated and pressed, and the prepreg is filled with glue.
  • the switch tube chip 20 and the diode chip 30 are covered.
  • the first conductive layer 12 is electrically connected, and the switch transistor chip 20 and the diode chip 30 are electrically connected.
  • a polarity pin reaching the switch transistor chip 20 and the diode chip 30 and a via hole 42 reaching the first conductive layer 12 are formed on the second conductive layer 50 and the insulating layer 40 by laser technology, and the through hole is formed in the through hole
  • the conductive material is filled in 42 to metalize the via hole 42.
  • the second conductive layer 50 needs to be formed with a circuit pattern before or after lamination, and the polarity pins of the switch tube chip 20 and the upper surface of the diode chip 30 are connected to the corresponding circuit pattern forming circuits through the metalized via holes 42.
  • the step S120 further includes: further providing a lead-out terminal 60, wherein the one end of the lead-out terminal 60 is fixedly electrically connected to the first conductive layer 12, and the other end is outwardly extended.
  • the lead-out terminal is provided, and one end of the lead-out terminal 60 is fixedly electrically connected to the second conductive layer 50, and the other end is outwardly extended.
  • the lead terminal includes a control terminal 62 and a power terminal 61, and the control terminal 62 and the power terminal 61 are respectively located on opposite sides of the power module.
  • the low voltage control terminal is away from the high voltage power terminal, which reduces the electrical interference of the high voltage terminal to the low voltage terminal and improves the reliability of the control terminal.
  • the method further includes the step of heating to cure the prepreg by heating to achieve insulation.
  • the method further includes the step of disposing a heat sink disposed on a lower surface of the insulating dielectric substrate and/or an upper surface of the second conductive layer.
  • the above manufacturing method is that the power module is manufactured without encapsulation, and the production cost is saved; the chip is electrically connected through the metalized through hole 42 to reduce the volume of the module and facilitate the miniaturization of the module.
  • the power module is manufactured by soldering the switch chip 20 and the diode chip 30, the control terminal 62, and the power terminal 61 to the first conductive layer 12 patterned on the insulating dielectric substrate 10 to form a prepreg of a corresponding thickness.
  • (Insulating layer) 40 the second conductive layer 50 is laminated with the chip-attached insulating dielectric substrate 10, and the flow of the prepreg 40 is filled and covers the chip.
  • the prepreg 40 is insulated, and the coefficient of thermal expansion needs to be as large as possible.
  • the thermal expansion coefficient of the power device is matched. Matching means that the values of the two coefficients of thermal expansion are as close as possible or equal.
  • the second conductive layer 50 of the laminated module is patterned, and the via hole 42 is formed by laser technology and metallized, so that the chip polarity pin and the corresponding lead terminal 60 are electrically connected.
  • the via hole 42 is disposed as much as possible in order to ensure the reliability of the bonding between the metallized via 42 and the chip, so as to ensure the overcurrent capability of the circuit and improve the heat dissipation capability of the upper portion of the chip.
  • the lower surface of the module (insulating dielectric substrate 10) is dissipated by the heat sink 70, and the upper surface of the module (second conductive layer 50) is coated with an insulating thermal conductive adhesive 80, and then connected to the other heat sink 70 to dissipate heat, thereby achieving double-sided heat dissipation and improving Cooling capacity.
  • the two heat sinks 70 do not necessarily need to be disposed at the same time, and in the case where the heat dissipation condition can be satisfied, the heat sink 70 on the lower surface alone may constitute a single-sided heat dissipation.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Structure Of Printed Boards (AREA)

Abstract

L'invention concerne un module de puissance et son procédé de fabrication, le module de puissance comprenant : un substrat diélectrique isolant (10) ayant une première couche conductrice (12) sur une surface supérieure de celui-ci; une puce de tube de commutation (20) et une puce de diode (30), les puces (20, 30) étant collées sur la surface supérieure du substrat diélectrique isolant (10); une couche d'isolation (40) recouvrant le substrat diélectrique isolant (10) et le gainage des puces (20, 30) à l'intérieur, la couche d'isolation (40) comprenant un trou traversant (42) situé au-dessus des puces (20, 30), et le trou traversant (42) est rempli d'une substance conductrice; et une seconde couche conductrice (50) disposée sur la couche d'isolation (40), la seconde couche conductrice (50) étant électriquement connectée aux puces (20, 30) à travers la substance conductrice. L'emballage ne nécessite pas l'ouverture d'un moule d'emballage en plastique, ce qui permet d'économiser des coûts de production. De plus, une puce semiconductrice de puissance est électriquement connectée à une couche conductrice supérieure en fournissant le trou traversant (42) sur la couche d'isolation (40) et en remplissant la substance conductrice, ce qui réduit la taille du module en étant avantageuse pour miniaturiser le module.
PCT/CN2018/073368 2017-01-24 2018-01-19 Module de puissance et son procédé de fabrication Ceased WO2018137560A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201710063330.9A CN108346645A (zh) 2017-01-24 2017-01-24 一种功率模块及其制造方法
CN201710063330.9 2017-01-24

Publications (1)

Publication Number Publication Date
WO2018137560A1 true WO2018137560A1 (fr) 2018-08-02

Family

ID=62963243

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2018/073368 Ceased WO2018137560A1 (fr) 2017-01-24 2018-01-19 Module de puissance et son procédé de fabrication

Country Status (2)

Country Link
CN (1) CN108346645A (fr)
WO (1) WO2018137560A1 (fr)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110120354A (zh) * 2019-05-06 2019-08-13 珠海格力电器股份有限公司 智能功率模块的封装方法及智能功率模块
CN113345852A (zh) * 2021-05-26 2021-09-03 全球能源互联网研究院有限公司 一种压接型功率芯片封装结构

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111244080B (zh) * 2020-03-15 2025-02-18 无锡先瞳半导体科技有限公司 功率模块结构、功率模块封装体及封装体的制作方法
CN113782498B (zh) * 2021-07-27 2024-05-17 华为数字能源技术有限公司 电源模块及功率器件
CN114203643B (zh) * 2021-12-14 2024-12-06 南瑞联研半导体有限责任公司 一种弹性压接式半导体模块封装结构

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7829386B2 (en) * 2005-08-17 2010-11-09 General Electric Company Power semiconductor packaging method and structure
CN102460693A (zh) * 2009-06-19 2012-05-16 株式会社安川电机 电力变换装置
CN104900609A (zh) * 2014-03-05 2015-09-09 台达电子国际（新加坡）私人有限公司 封装结构
CN105006453A (zh) * 2014-04-17 2015-10-28 台达电子国际（新加坡）私人有限公司 封装结构
CN106206483A (zh) * 2015-05-29 2016-12-07 台达电子国际（新加坡）私人有限公司 电源模块

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8455987B1 (en) * 2009-06-16 2013-06-04 Ixys Corporation Electrically isolated power semiconductor package with optimized layout
CN102800636B (zh) * 2012-08-28 2015-02-18 中国科学院微电子研究所 电子元件封装体及其制造方法
SG10201400396WA (en) * 2014-03-05 2015-10-29 Delta Electronics Int’L Singapore Pte Ltd Package structure and stacked package module with the same
KR20160049786A (ko) * 2014-10-28 2016-05-10 현대모비스 주식회사 파워 모듈 및 그의 패키징 방법
CN105161467B (zh) * 2015-08-14 2019-06-28 株洲南车时代电气股份有限公司 一种用于电动汽车的功率模块
CN205069617U (zh) * 2015-09-29 2016-03-02 比亚迪股份有限公司 功率模块和具有其的车辆

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7829386B2 (en) * 2005-08-17 2010-11-09 General Electric Company Power semiconductor packaging method and structure
CN102460693A (zh) * 2009-06-19 2012-05-16 株式会社安川电机 电力变换装置
CN104900609A (zh) * 2014-03-05 2015-09-09 台达电子国际（新加坡）私人有限公司 封装结构
CN105006453A (zh) * 2014-04-17 2015-10-28 台达电子国际（新加坡）私人有限公司 封装结构
CN106206483A (zh) * 2015-05-29 2016-12-07 台达电子国际（新加坡）私人有限公司 电源模块

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110120354A (zh) * 2019-05-06 2019-08-13 珠海格力电器股份有限公司 智能功率模块的封装方法及智能功率模块
CN110120354B (zh) * 2019-05-06 2024-05-28 珠海零边界集成电路有限公司 智能功率模块的封装方法及智能功率模块
CN113345852A (zh) * 2021-05-26 2021-09-03 全球能源互联网研究院有限公司 一种压接型功率芯片封装结构

Also Published As

Publication number Publication date
CN108346645A (zh) 2018-07-31

Similar Documents

Publication Publication Date Title
US10002821B1 (en) Semiconductor chip package comprising semiconductor chip and leadframe disposed between two substrates
CN108346628B (zh) 一种功率模块及其制造方法
WO2018137560A1 (fr) Module de puissance et son procédé de fabrication
CN108346637B (zh) 一种功率模块及其制造方法
US10818574B2 (en) Plug-in type power module and subsystem thereof
CN108321134A (zh) 高功率密度塑封式ipm模块的封装结构及加工工艺
KR102163662B1 (ko) 양면 냉각 파워 모듈 및 이의 제조방법
CN111584448A (zh) 一种芯片埋入式微流道模组封装结构及制作方法
US20150270201A1 (en) Semiconductor module package and method of manufacturing the same
CN206595255U (zh) 一种功率模块
CN108346649B (zh) 一种半桥功率模块及其制造方法
US7309838B2 (en) Multi-layered circuit board assembly with improved thermal dissipation
CN206524327U (zh) 一种功率模块
CN106298724A (zh) 塑封型功率模块
CN111584441A (zh) 具有改善的散热的电子模块及其制造
CN105990275A (zh) 功率模块封装件及其制作方法
CN210467819U (zh) 一种芯片封装件
CN110676232B (zh) 一种半导体器件封装结构及其制作方法、一种电子设备
CN207977311U (zh) 高可靠性igbt模块的封装结构
CN115380373B (zh) 具有改进的热性能的功率模块装置
JP2012238737A (ja) 半導体モジュール及びその製造方法
CN112447650A (zh) 一种芯片封装件
CN222785284U (zh) 电子装置
US20250054831A1 (en) Method for fabricating topside cooled semiconductor packages by film assisted molding and a semiconductor package
US20240170364A1 (en) Semiconductor package structure

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 18744727

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 18744727

Country of ref document: EP

Kind code of ref document: A1