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WO2018139495A1 - Circuit de commutation - Google Patents

Circuit de commutation Download PDF

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Publication number
WO2018139495A1
WO2018139495A1 PCT/JP2018/002160 JP2018002160W WO2018139495A1 WO 2018139495 A1 WO2018139495 A1 WO 2018139495A1 JP 2018002160 W JP2018002160 W JP 2018002160W WO 2018139495 A1 WO2018139495 A1 WO 2018139495A1
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Prior art keywords
fet
switch circuit
fets
input terminal
source
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Application number
PCT/JP2018/002160
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English (en)
Japanese (ja)
Inventor
勝利 徳田
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株式会社村田製作所
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Publication of WO2018139495A1 publication Critical patent/WO2018139495A1/fr

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H7/00—Multiple-port networks comprising only passive electrical elements as network components
    • H03H7/48—Networks for connecting several sources or loads, working on the same frequency or frequency band, to a common load or source
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors

Definitions

  • the present invention relates to a switch circuit.
  • a field effect transistor is used for a switch circuit mounted on a mobile communication device such as a mobile phone.
  • a switch circuit constituted by such FETs a configuration is known in which the withstand voltage of the switch circuit is improved by connecting a plurality of FETs in multiple stages in order to satisfy the demand for an increase in input power.
  • a voltage divided by the number of stages of FETs connected in multiple stages is applied between the source and drain of each FET, an input allowable voltage according to the number of stages of FETs can be obtained.
  • Patent Document 1 includes a capacitive element between the gate and source of an FET closest to the input terminal and between the gates of adjacent FETs. Thus, a configuration for evenly distributing the source-drain voltage of each FET is disclosed.
  • the present invention has been made in view of such circumstances, and an object thereof is to provide a switch circuit that realizes an increase in input power while suppressing an increase in circuit area.
  • a switching circuit includes an input terminal to which a signal is input, an output terminal to which a signal is output, and a plurality of stages connected in multiple stages between the input terminal and the output terminal.
  • a plurality of FETs that are controlled to be turned on and off according to a control voltage supplied to each gate, and the plurality of FETs are located farther from the input terminal than the first FET.
  • a gate length of the first FET is longer than a gate length of the second FET.
  • FIG. 1 is a diagram illustrating a configuration example of a switch circuit 100A according to the first embodiment of the present invention.
  • An apparatus in which the switch circuit 100A is used is not particularly limited, but in the present specification, as an example, a description will be given assuming that the switch circuit 100A is used in a power amplification module mounted on a mobile communication device such as a mobile phone.
  • the switch circuit 100A may be applied to a switch that passes a radio frequency (RF) signal input from an input terminal to an output terminal.
  • RF radio frequency
  • the switch circuit 100A is a band switching switch provided between the power amplifier and the antenna (that is, the signal path after the RF signal is amplified by the power amplifier) in order to increase the input power as described later. And may be applied to antenna switches and the like.
  • the switch circuit 100A includes an input terminal 10, an output terminal 20, N FETs 30 (1) to 30 (N) (N is an integer of 2 or more), and N resistive elements 40 (1 ) To 40 (N).
  • N FETs 30 (1) to 30 (N) N is an integer of 2 or more
  • N resistive elements 40 (1 ) To 40 (N) N
  • the i-th FET (i is an integer not less than 1 and not more than N) counted from the input terminal 10 side is represented as “30 (i)”.
  • an N-channel MOSFET Metal-oxide-semiconductor Field Effect Transistor
  • N FETs 30 (1) to 30 (N) (hereinafter, when these N FETs are not distinguished, they are also simply referred to as “each FET 30”. The same applies to other elements).
  • 10 and the output terminal 20 are connected in multiple stages.
  • the FETs 30 (1) to 30 (N) are connected in series, that is, the drain and source of adjacent FETs are connected, and the gate is connected to one end of each resistance element 40.
  • a control voltage is supplied to the gate of each FET 30 via each resistance element 40.
  • the input signal RFin supplied to the source of the FET 30 (1) is output as the output signal RFout from the drain of the FET 30 (N).
  • the input signal RFin supplied to the source of the FET 30 (1) is output as the output signal RFout from the drain of the FET 30 (N).
  • the power of the signal supplied to the input terminal of the switch circuit is divided by the parasitic capacitance of each FET. Therefore, the source-drain voltage of each FET becomes non-uniform. Specifically, the source-drain voltage of each FET gradually increases from the output terminal 20 to the input terminal 10. Therefore, a voltage exceeding the withstand voltage can be applied between the source and drain of the FET close to the input terminal, particularly when the switch circuit is off. Therefore, the allowable input voltage of the switch circuit is limited by the withstand voltage of the FET close to the input terminal.
  • the gate length of each FET 30 by adjusting the gate length of each FET 30, the input allowable voltage can be increased beyond the limitation.
  • the adjustment of the gate length will be specifically described.
  • FIG. 2 is a graph showing the relationship between the FET gate length and the withstand voltage.
  • the graph shown in FIG. 2 shows the withstand voltage of the single-stage FET when the gate length of the FET is 0.24 ⁇ m, 0.28 ⁇ m, and 0.32 ⁇ m.
  • the vertical axis indicates the withstand voltage (V) between the source and drain of the FET, and the horizontal axis indicates the gate length ( ⁇ m) of the FET.
  • V the withstand voltage
  • ⁇ m gate length of the FET.
  • the withstand voltage of the FET improves as the gate length increases. Therefore, even in a multi-stage connected FET, the withstand voltage of the FET can be improved by adjusting the gate length of the FET according to the source-drain voltage.
  • the gate length of each FET 30 is adjusted to be intentionally nonuniform. Specifically, for example, the gate lengths of several stages of FETs counted from the input terminal 10 side in each FET 30 are adjusted to be longer than the gate lengths of the other FETs. As a result, the withstand voltage of the FET close to the input terminal 10 is improved, so that the FET is suppressed from being broken even when a higher voltage is applied between the source and drain than other FETs. On the other hand, the withstand voltage of the FET far from the input terminal 10 is not improved, but the FET has a low voltage applied between the source and the drain as compared with other FETs, so the possibility of destruction is low. In general, the shorter the gate length of the FET, the lower the resistance value of the on-resistance. Therefore, in the FET far from the input terminal, the insertion length of the switch circuit can be reduced by relatively shortening the gate length.
  • the switch circuit 100A is configured so that, among the FETs 30 connected in multiple stages, the gate length of the FETs close to the input terminal 10 is longer than the gate lengths of the other FETs. It is possible to increase the input allowable voltage. That is, the switch circuit 100A can realize an increase in input power while suppressing an increase in circuit area.
  • the gate length of the FET far from the input terminal 10 (that is, the FET having a relatively low source-drain voltage) is designed to be shorter than the gate length of the other FETs.
  • the resistance value of the on-resistance is lowered and the insertion loss of the switch circuit is reduced as compared with the configuration in which the gate lengths of all the FETs are increased.
  • the specific configuration of the gate length is not particularly limited, but an example will be described below.
  • the FET 30 (1) first FET
  • the FET 30 (2) second FET
  • Attention is paid to the FET 30 (3) (third FET) provided at a position farther from the input terminal 10 than the FET 30 (2).
  • the gate length of the FET 30 (1) is longer than the gate length of the FET 30 (2)
  • the gate length of the FET 30 (2) is longer than the gate length of the FET 30 (3)
  • the lengths may be substantially the same length.
  • the gate length of the i-th FET counted from the input terminal 10 in each FET 30 is L (i)
  • the gate length may be designed so that That is, the gate length may be adjusted so that the FET closer to the input terminal 10 has a longer gate length and the FET farther from the input terminal 10 has a shorter gate length.
  • the withstand voltage is increased in an FET having a relatively high voltage between the source and the drain, and the insertion loss is reduced in an FET having a relatively low voltage between the source and the drain.
  • the gate width of the FET connected in multiple stages may be adjusted in addition to the gate length.
  • the gate width of the FET 30 (1) may be wider than the gate width of the FET 30 (2).
  • the gate width may be adjusted so that the FET closer to the input terminal 10 has a wider gate width and the FET farther from the input terminal 10 has a smaller gate width.
  • the source-drain voltage of each FET 30 can be adjusted to be uniform.
  • the gate width according to the gate length of each FET 30 it is possible to adjust so that a voltage close to the withstand voltage of each FET 30 is applied between the source and drain. Therefore, the input allowable voltage can be further increased as compared with the configuration in which the gate width is uniform.
  • the FETs 30 (1) to 30 (N) are not limited to MOSFETs, and may be FETs such as JFETs (Junction Field Effect Transistors) and MESFETs (Metal-semiconductor Field Effect Transistors).
  • the number of FETs connected in multiple stages is not particularly limited as long as it is two or more. Further, the FETs connected in multiple stages may be configured by connecting individual FETs in series as shown in FIG. 1, or a multi-gate FET may be used. The same applies to the following embodiments.
  • FIG. 3 is a diagram illustrating a configuration example of the switch circuit 100B according to the second embodiment of the present invention.
  • the same elements as those of the switch circuit 100A are denoted by the same reference numerals and description thereof is omitted. Further, description of matters common to the first embodiment is omitted, and only different points will be described. In particular, the same operation effect by the same configuration will not be sequentially described for each embodiment.
  • a capacitive element is provided between the source and drain of each FET 30.
  • the capacitive elements 50 (1) to 50 (N) are connected between the sources and drains of the FETs 30 (1) to 30 (N), respectively.
  • the capacitance value of each capacitive element 50 the voltage applied between the source and drain of each FET 30 can be adjusted.
  • the capacitance value of the capacitive element connected to the FET close to the input terminal 10 of each FET 30 is relatively large, and the capacitance value of the capacitive element connected to the FET far from the input terminal 10 is relatively large. By making it smaller, it is possible to achieve an even distribution of the source-drain voltage of the FET.
  • the source-drain voltage of the FET may not be distributed completely evenly due to the restriction of the size of the capacitive element accompanying the reduction in the circuit scale of the switch circuit.
  • the configuration of the switch circuit 100A that is, by adjusting the length of the gate length of each FET 30, it is possible to improve the withstand voltage of some FETs and compensate for the nonuniformity of the source-drain voltage. it can.
  • the capacitance value of the capacitive element connected to the FET having a high withstand voltage is made relatively large, and the capacitance value of the capacitive element connected to the FET having a low withstand voltage is made relatively small.
  • a voltage close to the withstand voltage can be applied to all FETs. Therefore, the input allowable voltage of the switch circuit can be further increased as compared with the switch circuit 100A.
  • FIG. 4 is a diagram illustrating a configuration example of a switch circuit 100C according to a modification of the second embodiment of the present invention.
  • a capacitive element is provided between the source of the FET 30 (1) closest to the input terminal 10 among the FETs 30 and the drain of each FET 30.
  • each of the capacitive elements 51 (1) to 51 (N) is connected to the source of the FET 30 (1) closest to the input terminal 10 (that is, the electrode on the input terminal side), and the other end is connected to each FET 30 (1).
  • To 30 (N) drains (ie, electrodes on the output terminal side).
  • each capacitive element 51 is connected between a terminal (source of FET 30 (1)) to which a signal having the highest signal level is supplied and the drain of each FET 30, and the drain voltage of each FET 30 is raised.
  • the switch circuit 100C the drain voltage of each FET 30 can be raised by the capacitive element having a capacitance value smaller than that of each capacitive element 50 in the switch circuit 100B, and the source-drain voltage can be evenly distributed.
  • the switch circuit 100C can improve the withstand voltage by adjusting the length of the gate length of each FET 30 similarly to the switch circuit 100A. Further, since the required capacitance values of the capacitive elements 51 (1) to 51 (N) become smaller as the switch circuit 100C is farther from the input terminal 10, an increase in circuit area can be suppressed compared to the switch circuit 100B. .
  • capacitive elements are connected in all FETs 30 (1) to 30 (N). However, some FETs (for example, on the side closer to the input terminal 10 in each FET 30). Capacitance elements may be connected only to some FETs).
  • FIG. 5 is a diagram illustrating a configuration example of a switch circuit 100D according to another modification of the second embodiment of the present invention.
  • the switch circuit 100D differs from the switch circuit 100C in the connection configuration of the capacitive elements.
  • a plurality of FETs have one unit, and one end of each capacitive element 52 is connected to the source of the FET closest to the input terminal 10 in the unit.
  • FETs 30 (1) to 30 (3) form a first unit
  • FETs 30 (5) to FET 30 (7) form a second unit.
  • One end of each of the capacitive elements 52 (1) to 52 (3) is connected to the source of the FET 30 (1) (that is, the FET closest to the input terminal 10 in the first unit), and the other end is connected to each FET 30 (1 ) To 30 (3) drains.
  • each of the capacitive elements 52 (5) to 52 (7) is connected to the source of the FET 30 (5) (that is, the FET closest to the input terminal 10 in the second unit), and the other end is connected to each FET 30. (5) to 30 (7) connected to the drain.
  • the capacitive element 52 (4) corresponding to the FET 30 (4) located between the first and second units has one end connected to the source of the FET 30 (4) and the other end FET 30 (4). Connected to the drain.
  • the switch circuit 100D can improve the withstand voltage by adjusting the gate length of each FET 30 in the same manner as the switch circuit 100A. Further, since the switch circuit 100D does not need to use a very small capacity compared to the switch circuit 100C, the ratio of good products is improved.
  • FIG. 6 is a diagram illustrating a configuration example of the switch circuit 100E according to the third embodiment of the present invention.
  • a resistance element is provided between the source and drain of each FET 30.
  • the resistance elements 41 (1) to 41 (N) are connected between the sources and drains of the FETs 30 (1) to 30 (N), respectively.
  • the resistance element 41 may be used in combination with any other embodiment.
  • FIG. 7 is a diagram illustrating a configuration example of a switch circuit 100F according to the fourth embodiment of the present invention
  • FIG. 8 is a diagram illustrating a configuration example of a switch circuit 100G according to a modification of the fourth embodiment of the present invention. It is.
  • capacitive elements 53 (1) to 53 (N) are provided between the gate and source of each FET 30, and capacitive elements 54 (1) to 54 (N) are provided between the gate and drain.
  • capacitive elements 55 (1) to 55 (N) are provided between the bulk and the source of each FET 30, and capacitive elements 56 (1) to 56 (N) are provided between the bulk and the drain. Yes.
  • connection position of the elements provided in order to uniformly distribute the voltage between the source and drain of each FET 30 is not limited between the source and drain of each FET, but between the gate and source and between the gate and drain, or It may be between the bulk and the source and between the bulk and the drain.
  • the switch circuits 100F and 100G can improve the withstand voltage by adjusting the length of the gate length of each FET 30 similarly to the switch circuit 100A.
  • the switch circuits 100F and 100G can further increase the allowable input voltage as compared with the switch circuit 100A, similarly to the switch circuit 100B.
  • FIG. 9 is a diagram illustrating a configuration example of a switch circuit 100H according to the fifth embodiment of the present invention
  • FIG. 10 is a diagram illustrating a configuration example of a switch circuit 100I according to a modification of the fifth embodiment of the present invention
  • FIG. 11 is a diagram illustrating a configuration example of a switch circuit 100J according to another modification of the fifth embodiment of the present invention.
  • elements are provided between the gate and the source of the FET 30 (1) (that is, the FET closest to the input terminal 10) and between the gates of the adjacent FETs.
  • a capacitive element 57 (1) (first element) is provided between the gate and the source (that is, the electrode on the input terminal side) of the FET 30 (1), and adjacent FETs.
  • Capacitance elements 57 (2) to 57 (N) (second element) are provided between the gates.
  • the switch circuit 100I is provided with a capacitive element 58 and a resistive element 42 (1) (first element) connected in series between the gate and source of the FET 30 (1), and the gates of the FETs adjacent to each other. Resistance elements 42 (2) to 42 (N) (second element) are provided between the two.
  • the switch circuit 100J is provided with a capacitive element 59 (1) and a resistance element 43 (1) (first element) connected in series between the gate and source of the FET 30 (1), and adjacent FETs.
  • Capacitance elements 59 (2) to 59 (N) and resistance elements 43 (2) to 43 (N) (second element) connected in series with each other are provided between the gates.
  • connection position of the elements provided in order to uniformly distribute the voltage between the source and drain of each FET 30 may be between the gates of the adjacent FETs.
  • the switch circuits 100H to 100J can improve the withstand voltage by adjusting the gate length of each FET 30 in the same manner as the switch circuit 100A.
  • the switch circuits 100H to 100J can further increase the allowable input voltage as compared with the switch circuit 100A, similarly to the switch circuit 100B.
  • FIG. 12 is a diagram showing a configuration example of a switch circuit 100K according to the sixth embodiment of the present invention
  • FIG. 13 is a diagram showing a configuration example of a switch circuit 100L according to a modification of the sixth embodiment of the present invention
  • FIG. 14 is a diagram illustrating a configuration example of a switch circuit 100M according to another modification of the sixth embodiment of the present invention.
  • elements are provided between the bulk sources of the FET 30 (1) (that is, the FET closest to the input terminal 10) and between the bulks of the adjacent FETs.
  • a capacitive element 60 (1) (third element) is provided between the bulk of the FET 30 (1) and the source (that is, the electrode on the input terminal side), and adjacent FETs.
  • Capacitance elements 60 (2) to 60 (N) (fourth element) are provided between the bulks.
  • the switch circuit 100L includes a capacitive element 61 and a resistive element 44 (1) (third element) connected in series between the bulk and the source of the FET 30 (1), and the bulks of the FETs adjacent to each other. Resistance elements 44 (2) to 44 (N) (fourth element) are provided between the two.
  • the switch circuit 100M includes a capacitive element 62 (1) and a resistive element 45 (1) (third element) connected in series between the bulk and the source of the FET 30 (1), and adjacent FETs.
  • Capacitance elements 62 (2) to 62 (N) and resistance elements 45 (2) to 45 (N) (fourth element) connected in series with each other are provided between the bulks.
  • connection position of the elements provided in order to evenly distribute the source-drain voltage of each FET 30 may be between the bulks of the adjacent FETs. Even with such a configuration, the switch circuits 100K to 100M can improve the withstand voltage by adjusting the gate length of each FET 30 in the same manner as the switch circuit 100A. In addition, the switch circuits 100K to 100M can further increase the allowable input voltage as compared with the switch circuit 100A, similarly to the switch circuit 100B.
  • FIG. 15 is a diagram illustrating a configuration example of a switch circuit 100N according to the seventh embodiment of the present invention
  • FIG. 16 is a diagram illustrating a configuration example of a switch circuit 100P according to a modification of the seventh embodiment of the present invention. It is.
  • a bias voltage is supplied to the bulk of each FET 30.
  • diode elements 70 (1) to 70 (N) are provided between the gate and bulk of each FET 30.
  • Each diode element 70 has an anode connected to the bulk of each FET 30 and a cathode connected to the gate of each FET 30.
  • the switch circuit 100P is provided with resistance elements 46 (1) to 46 (N) connected in series to the bulk of each FET 30.
  • a bias voltage Vbias is supplied to the bulk of each FET 30 via each resistance element 46.
  • a bias voltage can be supplied to the bulk of each FET. Even with such a configuration, the switch circuits 100N and 100P can improve the withstand voltage by adjusting the length of the gate length of each FET 30 similarly to the switch circuit 100A. In the switch circuits 100A to 100M, a bias voltage can be supplied to the bulk of each FET 30 similarly to the switch circuits 100N and 100P, and the same effect can be obtained.
  • FIG. 17 is a graph showing an example of a simulation result of the source-drain voltage in the switch circuit and the comparative example according to the first and second embodiments of the present invention.
  • the drain-to-drain voltage is shown in each of the switch circuits in which 12 stages of FETs are connected in multiple stages.
  • reference numerals 1 to 12 are used in order from the FET closest to the input terminal.
  • the gate length of the FET 30 (1) is 0.32 ⁇ m
  • the gate length of the FET 30 (2) is 0.28 ⁇ m
  • the length is 0.24 ⁇ m.
  • the gate length is the same as that of the first embodiment.
  • the capacitive elements 50 (1) to 50 (1) to 50 (1) to 30 (4) are arranged between the sources and drains of the four-stage FETs. 50 (4) is provided.
  • the gate lengths of the FETs 30 (1) to 30 (12) are all 0.24 ⁇ m. In the graph shown in FIG.
  • the vertical axis indicates the source-drain voltage (V) in each FET
  • the horizontal axis indicates the sign of the FETs attached in order from the input terminal.
  • the three horizontal lines in the graph shown in FIG. 17 indicate the withstand voltage according to the gate length of each FET.
  • the maximum input power 40.3 dBm is supplied when the FET 30 (3) reaches the withstand voltage.
  • the second embodiment by adjusting the capacitance value of the capacitive element provided between the source and drain of the FETs 30 (1) to 30 (4), the voltage between the source and drain of each FET is set to a withstand voltage. You can get closer. Therefore, in the second embodiment, the maximum input power (42 dBm) is supplied when all of the FETs 30 (1) to 30 (4) reach the withstand voltage.
  • FIG. 18 is a graph showing an example of simulation results of withstand voltage and on-resistance in the switch circuit and the comparative example according to the first and second embodiments of the present invention.
  • the left side of the vertical axis represents the withstand voltage (V) of the switch circuit
  • the right side of the vertical axis represents the on-resistance ⁇ off-capacitance (fsec) of the switch circuit.
  • the conditions in the graph are the same as the conditions in FIG.
  • the withstand voltage of the first embodiment is improved by about 6V compared to the comparative example. Further, the withstand voltage of the second embodiment is improved by about 7V compared to the first embodiment.
  • the on-resistance ⁇ off-capacitance is deteriorated as compared with the comparative example, particularly in the second embodiment in which the capacitive element is provided. That is, the length of the gate, the presence / absence of addition of a capacitor element, the number of elements to be added, or the like may be adjusted according to the required specifications of the switch circuit.
  • the switch circuits 100A to 100P include a plurality of FETs connected in multiple stages, and an FET closer to the input terminal 10 has a longer gate length than an FET farther from the input terminal 10 than the FET.
  • the withstand voltage of the FET close to the input terminal 10 is improved as compared with the configuration having a uniform gate length, and the input allowable voltage can be increased. Therefore, the switch circuits 100A to 100P can realize an increase in input power while suppressing an increase in circuit area. Further, the resistance value of the on-resistance is lowered and the insertion loss of the switch circuit is reduced as compared with the configuration in which the gate lengths of all the FETs are increased.
  • the configuration of the length of the gate length of the FET is not particularly limited.
  • the gate length may be increased in order from the FET closer to the input terminal 10.
  • each capacitive element 50 is provided between the source and drain of each FET 30. Thereby, equal distribution of the source-drain voltage of each FET 30 can be achieved. Alternatively, a voltage close to the withstand voltage can be applied to all FETs. Therefore, the input allowable voltage of the switch circuit can be further increased as compared with the switch circuit 100A.
  • each capacitive element 51 is provided between the source of the FET 30 (1) closest to the input terminal 10 among the FETs 30 and the drain of each FET 30. Thereby, equal distribution of the source-drain voltage of each FET 30 can be achieved. Alternatively, a voltage close to the withstand voltage can be applied to all FETs. Therefore, the input allowable voltage of the switch circuit can be further increased as compared with the switch circuit 100A. Further, since the required capacitance value of each capacitive element 51 becomes smaller as the switch circuit 100C is farther from the input terminal 10, an increase in circuit area can be suppressed compared to the switch circuit 100B.
  • the capacitive elements 53 and 54 are provided between the gate and the source of each FET 30 and between the gate and the drain. Thereby, equal distribution of the source-drain voltage of each FET 30 can be achieved. Alternatively, a voltage close to the withstand voltage can be applied to all FETs. Therefore, the input allowable voltage of the switch circuit can be further increased as compared with the switch circuit 100A.
  • the capacitive elements 55 and 56 are provided between the bulk and the source of the FET 30 and between the bulk and the drain. Thereby, equal distribution of the source-drain voltage of each FET 30 can be achieved. Alternatively, a voltage close to the withstand voltage can be applied to all FETs. Therefore, the input allowable voltage of the switch circuit can be further increased as compared with the switch circuit 100A.
  • the switch circuits 100H to 100J include a capacitance element, a resistance element, or a series connection between the gate and the source of the FET 30 (1) closest to the input terminal 10 among the FETs 30 and between the gates of the adjacent FETs. Either a connected capacitive element or resistive element is provided. Thereby, equal distribution of the source-drain voltage of each FET 30 can be achieved. Alternatively, a voltage close to the withstand voltage can be applied to all FETs. Therefore, the input allowable voltage of the switch circuit can be further increased as compared with the switch circuit 100A.
  • the switch circuits 100K to 100P include a capacitance element, a resistance element, or a series connection between the bulk sources of the FET 30 (1) closest to the input terminal 10 among the FETs 30 and between the bulks of adjacent FETs. Either a connected capacitive element or resistive element is provided. Thereby, equal distribution of the source-drain voltage of each FET 30 can be achieved. Alternatively, a voltage close to the withstand voltage can be applied to all FETs. Therefore, the input allowable voltage of the switch circuit can be further increased as compared with the switch circuit 100A.
  • a diode element 70 may be provided between the gate and bulk of each FET 30, and a bias voltage may be supplied to the bulk of each FET 30.
  • a bias voltage may be supplied to the bulk of each FET 30 via each resistance element 46.
  • each resistance element 41 is provided between the source and drain of each FET 30. This stabilizes the DC voltage at the source and drain of each FET 30 when the switch circuit is off.
  • the FET closer to the input terminal 10 among the FETs 30 may have a wider gate width than the FET farther from the input terminal 10 than the FET.
  • equal distribution of the source-drain voltage of each FET 30 can be achieved.
  • a voltage close to the withstand voltage can be applied to all FETs. Therefore, the input allowable voltage of the switch circuit can be further increased as compared with the configuration in which the gate width is uniform.
  • each FET 30 in each FET 30, an example in which the electrode on the input terminal side is the source and the electrode on the output terminal side is the drain is shown, but instead of this, the electrode on the input terminal side is The drain and the electrode on the output terminal side may be the source.
  • each embodiment described above is for facilitating the understanding of the present invention, and is not intended to limit the present invention.
  • the present invention can be changed or improved without departing from the gist thereof, and the present invention includes equivalents thereof.
  • those obtained by appropriately modifying the design of each embodiment by those skilled in the art are also included in the scope of the present invention as long as they include the features of the present invention.
  • each element included in each embodiment and its arrangement, material, condition, shape, size, and the like are not limited to those illustrated, and can be changed as appropriate.
  • each element included in each embodiment can be combined as much as technically possible, and combinations thereof are included in the scope of the present invention as long as they include the features of the present invention.

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Abstract

L'invention concerne un circuit de commutation qui permet d'obtenir une augmentation de la puissance électrique d'entrée tout en limitant une augmentation de la zone de circuit. Le circuit de commutation est pourvu : d'une borne d'entrée à laquelle un signal est appliqué ; d'une borne de sortie par laquelle un signal est sorti ; d'une pluralité de TEC dans une connexion à plusieurs étages entre les bornes d'entrée et de sortie, la pluralité de TEC étant activés/désactivés en fonction d'une tension de commande fournie à la grille de chaque TEC. La pluralité de TEC comprend un premier TEC et un second TEC qui est disposé en une position plus éloignée de la borne d'entrée que le premier TEC et dont la longueur de grille est inférieure à celle du premier TEC.
PCT/JP2018/002160 2017-01-30 2018-01-24 Circuit de commutation WO2018139495A1 (fr)

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JP2017-014360 2017-01-30
JP2017014360 2017-01-30

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WO2021171901A1 (fr) * 2020-02-25 2021-09-02 ソニーセミコンダクタソリューションズ株式会社 Circuit de commutation et dispositif de communication
JP7193447B2 (ja) 2017-03-22 2022-12-20 ソニーセミコンダクタソリューションズ株式会社 半導体装置及びモジュール

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JP2011249466A (ja) * 2010-05-25 2011-12-08 Renesas Electronics Corp 半導体装置
US20140312958A1 (en) * 2008-02-28 2014-10-23 Peregrine Semiconductor Corporation Devices and Methods for Improving Voltage Handling and/or Bi-Directionality of Stacks of Elements When Connected Between Terminals
JP2015115884A (ja) * 2013-12-13 2015-06-22 ルネサスエレクトロニクス株式会社 半導体装置
JP2015523810A (ja) * 2012-07-07 2015-08-13 スカイワークス ソリューションズ, インコーポレイテッドSkyworks Solutions, Inc. シリコン・オン・インシュレータベースの高周波スイッチに関する回路、デバイス、方法および組合せ
JP2016171498A (ja) * 2015-03-13 2016-09-23 株式会社東芝 半導体スイッチ

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US20140312958A1 (en) * 2008-02-28 2014-10-23 Peregrine Semiconductor Corporation Devices and Methods for Improving Voltage Handling and/or Bi-Directionality of Stacks of Elements When Connected Between Terminals
JP2011249466A (ja) * 2010-05-25 2011-12-08 Renesas Electronics Corp 半導体装置
JP2015523810A (ja) * 2012-07-07 2015-08-13 スカイワークス ソリューションズ, インコーポレイテッドSkyworks Solutions, Inc. シリコン・オン・インシュレータベースの高周波スイッチに関する回路、デバイス、方法および組合せ
JP2015115884A (ja) * 2013-12-13 2015-06-22 ルネサスエレクトロニクス株式会社 半導体装置
JP2016171498A (ja) * 2015-03-13 2016-09-23 株式会社東芝 半導体スイッチ

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP7193447B2 (ja) 2017-03-22 2022-12-20 ソニーセミコンダクタソリューションズ株式会社 半導体装置及びモジュール
WO2021171901A1 (fr) * 2020-02-25 2021-09-02 ソニーセミコンダクタソリューションズ株式会社 Circuit de commutation et dispositif de communication
US12212311B2 (en) 2020-02-25 2025-01-28 Sony Semiconductor Solutions Corporation Switch circuit and communication apparatus

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