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WO2019003840A1 - Dispositif de circuit intégré à semi-conducteur - Google Patents

Dispositif de circuit intégré à semi-conducteur Download PDF

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Publication number
WO2019003840A1
WO2019003840A1 PCT/JP2018/021733 JP2018021733W WO2019003840A1 WO 2019003840 A1 WO2019003840 A1 WO 2019003840A1 JP 2018021733 W JP2018021733 W JP 2018021733W WO 2019003840 A1 WO2019003840 A1 WO 2019003840A1
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WO
WIPO (PCT)
Prior art keywords
pitch
cell
standard cells
semiconductor integrated
integrated circuit
Prior art date
Application number
PCT/JP2018/021733
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English (en)
Japanese (ja)
Inventor
淳司 岩堀
Original Assignee
株式会社ソシオネクスト
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 株式会社ソシオネクスト filed Critical 株式会社ソシオネクスト
Priority to JP2019526755A priority Critical patent/JP7054013B2/ja
Publication of WO2019003840A1 publication Critical patent/WO2019003840A1/fr
Priority to US16/711,018 priority patent/US11348925B2/en

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices
    • H10B10/12—Static random access memory [SRAM] devices comprising a MOSFET load element
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/201—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates the substrates comprising an insulating layer on a semiconductor body, e.g. SOI
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices
    • H10B10/18—Peripheral circuit regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/40—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels
    • H10D30/43—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having 1D charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/6735—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes having gates fully surrounding the channels, e.g. gate-all-around
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6741—Group IV materials, e.g. germanium or silicon carbide
    • H10D30/6743—Silicon
    • H10D30/6744—Monocrystalline silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6757—Thin-film transistors [TFT] characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/117—Shapes of semiconductor bodies
    • H10D62/118—Nanostructure semiconductor bodies
    • H10D62/119—Nanowire, nanosheet or nanotube semiconductor bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/117—Shapes of semiconductor bodies
    • H10D62/118—Nanostructure semiconductor bodies
    • H10D62/119—Nanowire, nanosheet or nanotube semiconductor bodies
    • H10D62/121—Nanowire, nanosheet or nanotube semiconductor bodies oriented parallel to substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/90—Masterslice integrated circuits
    • H10D84/903—Masterslice integrated circuits comprising field effect technology
    • H10D84/907—CMOS gate arrays
    • H10D84/909—Microarchitecture
    • H10D84/959—Connectability characteristics, i.e. diffusion and polysilicon geometries
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/90—Masterslice integrated circuits
    • H10D84/903—Masterslice integrated circuits comprising field effect technology
    • H10D84/907—CMOS gate arrays
    • H10D84/968—Macro-architecture
    • H10D84/974—Layout specifications, i.e. inner core regions

Definitions

  • the present disclosure relates to a semiconductor integrated circuit device provided with a standard cell using a nanowire FET (Field Effect Transistor).
  • a nanowire FET Field Effect Transistor
  • a standard cell method is known as a method of forming a semiconductor integrated circuit on a semiconductor substrate.
  • basic units for example, inverters, latches, flip flops, full adders, etc.
  • a specific logic function for example, inverters, latches, flip flops, full adders, etc.
  • a plurality of standard cells are arranged on a semiconductor substrate. It is a method of designing an LSI chip by connecting those standard cells by wiring.
  • the transistor which is a basic component of LSI, has achieved improvement in integration, reduction in operating voltage, and improvement in operating speed by reducing the gate length (scaling).
  • the off current due to excessive scaling and the significant increase in power consumption due to it have become problems.
  • a three-dimensional structure transistor in which the transistor structure is changed from the conventional flat type to a three-dimensional type is actively studied. As one of them, a nanowire FET is attracting attention.
  • Non-Patent Documents 1 and 2 disclose an example of a method of manufacturing a nanowire FET.
  • An object of the present disclosure is to increase the degree of freedom of the cell height of a standard cell in a semiconductor integrated circuit device using a nanowire FET without impairing the consistency with the arrangement of the nanowire and the metal wiring.
  • a circuit block in which a plurality of cell rows composed of a plurality of standard cells arranged in a first direction are arranged in a plurality in a second direction perpendicular to the first direction.
  • the plurality of standard cells include a plurality of nanowires extending in the first direction and arranged at a first pitch in the second direction, and the plurality of standard cells have a size in the second direction.
  • the cell height is M times (M is an odd number) half of the first pitch.
  • the plurality of standard cells have a cell height that is M times (M is an odd number) half of the arrangement pitch of the nanowires.
  • a circuit block in which a plurality of cell rows each including a plurality of standard cells arranged in a first direction are arranged in a plurality in a second direction perpendicular to the first direction.
  • a macro block and the plurality of standard cells include a plurality of nanowires extending in the first direction and arranged at a first pitch in the second direction, and the plurality of standard cells include the second A cell height which is a size in a direction is N times (N is an integer) a half of the first pitch, and the circuit block is formed in a first wiring layer on the plurality of nanowires, A plurality of metal wires extending in the first direction and arranged at a second pitch in the second direction, wherein the macro block is formed in the first wiring layer; Extending in the direction, comprising a plurality of metal wires arranged at a third pitch in the second direction, the second pitch is greater than the third pitch.
  • the cell height is N times (N is an integer) half the arrangement pitch of the nanowires.
  • the arrangement pitch in the circuit block is larger than the arrangement pitch in the macro block.
  • the degree of freedom of the cell height of the standard cell can be enhanced without impairing the matching property with the arrangement of the nanowire and the metal wiring.
  • the semiconductor integrated circuit device includes a plurality of standard cells, and at least a part of the plurality of standard cells includes a nanowire FET (Field Effect Transistor).
  • a nanowire FET Field Effect Transistor
  • FIG. 8 is a schematic view showing an example of the basic structure of a nanowire FET (also referred to as a gate all around (GAA) structure).
  • the nanowire FET is an FET using a thin wire (nanowire) through which current flows.
  • the nanowires are formed, for example, by silicon.
  • the nanowires are formed on the substrate so as to extend in the horizontal direction, that is, in parallel with the substrate, and both ends thereof are connected to structures serving as source and drain regions of the nanowire FET.
  • a structure connected to both ends of the nanowire and serving as a source region and a drain region of the nanowire FET is referred to as a pad.
  • FIG. 1 a structure connected to both ends of the nanowire and serving as a source region and a drain region of the nanowire FET is referred to as a pad.
  • STI Shallow Trench Isolation
  • the silicon substrate is exposed below the nanowires (a hatched portion).
  • the hatched portion may actually be covered with a thermal oxide film or the like, it is omitted in FIG. 8 for simplification.
  • the nanowires are surrounded by a gate electrode made of, for example, polysilicon through an insulating film such as a silicon oxide film.
  • the pad and the gate electrode are formed on the substrate surface.
  • the pad is at least the source / drain region where the nanowire is connected
  • the portion below the portion where the nanowire is connected may not necessarily be the source / drain region.
  • a part of the nanowire (a part not surrounded by the gate electrode) may be a source / drain region.
  • two nanowires are arranged in the longitudinal direction, that is, in the direction perpendicular to the substrate.
  • the number of nanowires arranged in the vertical direction is not limited to two, and may be one, or three or more may be arranged in the vertical direction.
  • the top ends of the uppermost nanowires and the top ends of the pads are aligned in height. However, these heights do not have to be the same, and the upper end of the pad may be higher than the upper end of the uppermost nanowire.
  • a BOX Buried Oxide
  • a nanowire FET may be formed on this BOX.
  • FIG. 1 is a plan view schematically showing the entire configuration of a semiconductor integrated circuit device (semiconductor chip) according to the embodiment.
  • a core logic region 10 is provided on a semiconductor substrate 2.
  • the core logic unit 10 is configured by a standard cell (hereinafter simply referred to as “cell” as appropriate) including the above-described nanowire FET.
  • SRAM Static Random Access Memory
  • macro block 23 including an analog circuit such as an A / D converter or PLL, and the semiconductor integrated circuit device 1 on the semiconductor substrate 2.
  • I / O units 31, 32, 33, 34, etc. are provided to exchange signals with the outside.
  • FIG. 2 is an enlarged view of a part of the circuit block in the core logic area 10.
  • NW is a nanowire
  • PD is a pad
  • GT is a gate
  • DG is a dummy gate. Illustration of other components such as wiring is omitted.
  • the nanowire NW is formed to extend in the X direction (corresponding to the horizontal direction in the drawing, corresponding to the first direction), and the gate GT and the dummy gate DG extend in the Y direction (corresponding to the vertical direction in the drawing, corresponding to the second direction). It is formed as.
  • the nanowire FET comprises a nanowire NW and a gate GT formed around the nanowire NW.
  • the core logic region 10 includes a standard cell C including a nanowire FET.
  • Each cell row CR1, CR2, CR3 includes a plurality of standard cells C aligned in the X direction, and is arranged in the Y direction.
  • the height (size in the Y direction) of the standard cell C is Hc.
  • the cell rows CR1, CR2 and CR3 are alternately arranged in one row and flipped in the Y direction.
  • Power supply wirings VDD and VSS are disposed between the respective cell columns.
  • the power supply lines VDD and VSS are shared by the cell columns on both sides in the Y direction.
  • the nanowires NW are arranged at a pitch Pn (corresponding to a first pitch) in the Y direction throughout the entire circuit block.
  • the metal wiring is formed over the entire circuit block. It is disposed to extend in the X direction and at a pitch Pm (corresponding to a second pitch) in the Y direction.
  • the metal interconnections formed in the M2 interconnection layer are used as intra-cell interconnections or inter-cell interconnections. Further, as shown in FIG.
  • the metal interconnections 7 are arranged at a pitch Pm SRAM (corresponding to a third pitch).
  • Pm SRAM is equal to the minimum wiring pitch Pmmin in the semiconductor integrated circuit device 1.
  • the lengths of Pn and Pmmin are not limited thereto.
  • FIG. 3 is a configuration example of a standard cell showing feature 1 in the present disclosure.
  • the standard cells C11 and C12 are arranged side by side in the Y direction, and the standard cell C12 is inverted in the Y direction.
  • an alternate long and short dash line GR1 extending in the X direction is a grid representing a position where the nanowires NW can be arranged.
  • the grid GR1 is arranged at a pitch Pn.
  • the nanowires NW are disposed on the grid GR1. However, there is also a grid GR1 in which the nanowires NW are not arranged.
  • the cell height Hc of the standard cells C11 and C12 is 11.5 times the pitch Pn of the nanowires NW, in other words, 23 times the half pitch Pn of the nanowires NW.
  • the grid GR1 is uniformly disposed in the Y direction in the entire standard cells C11 and C12. That is, when the cell height Hc is M times half of the arrangement pitch pn of the nanowires NW (M is an odd number), in two standard cells arranged in the Y direction, one of them being reversed and disposed, Uniformity of placement pitch is maintained as a whole.
  • the cell height Hc, Hc (Pn ⁇ 0.5) ⁇ M (M: odd number)
  • the freedom of selection of the cell height Hc can be enhanced while maintaining the uniformity of the arrangement pitch of the nanowires NW.
  • FIG. 4 is a view showing metal wiring formed in the M2 wiring layer in the configuration example of FIG.
  • a broken line GR ⁇ b> 2 extending in the X direction is a grid representing a position where metal interconnections can be arranged in the M ⁇ b> 2 interconnection layer.
  • the grids GR2 are arranged at a pitch Pm. However, in the configuration of FIG. 4, the pitch Pm is larger than the minimum wiring pitch Pmmin in the semiconductor integrated circuit device 1 (Pm> Pmmin).
  • Metal wires 5a to 5e are arranged on grid GR2. However, there is also a grid GR2 in which no metal wiring is arranged. Metal interconnections 5a to 5e may be interconnections in cells or interconnections between cells.
  • the cell height Hc of the standard cells C11 and C12 is 11.5 times the pitch Pn of the nanowires NW, in other words, 23 times the half pitch Pn.
  • Pn 48 nm
  • the pitch Pm of the metal interconnections is slightly larger than the minimum interconnection pitch Pmmin, and the cell height Hc is an integral multiple of the metal interconnection pitch Pm.
  • Pm 69 nm.
  • the metal wiring pitch Pm is larger than the wiring pitch PmSRAM in the M2 wiring layer in the SRAM block 22.
  • the pitch Pm of the metal wiring is set by the following equation.
  • the pitch Pm is set to 1 nm as the minimum unit from the condition of layout design.
  • Integer () is a function indicating the integer part of the number in parentheses.
  • k is a variable for adjusting the value of the pitch Pm to be in 1 nm units.
  • FIG. 5 is a view showing an example of the relationship between the cell height Hc and the pitch Pm of the metal wiring.
  • n is Hc / (0.5 ⁇ Pn), that is, a value indicating how many times the cell height Hc corresponds to half the pitch Pn of the nanowire NW.
  • FIG. 6 is a configuration example according to a comparative example
  • FIG. 7 is a diagram showing an example of cell height in the comparative example.
  • Pn 48 nm
  • Pmmin the minimum wiring pitch
  • the cell height Hc can only be set in units of 96 nm, which corresponds to the least common multiple of half of the arrangement pitch Pn of the nanowires NW and the minimum wiring pitch Pmmin of metal wiring. That is, the degree of freedom in selection of the cell height Hc is lower than that of the present embodiment.
  • the wiring pitch PmSRAM in the M2 wiring layer of the SRAM block 22 is not necessarily the same as the minimum wiring pitch Pmmin in the semiconductor integrated circuit device 1. Further, in the M2 wiring layer of the SRAM block 22, the wiring pitch of all the wirings is not limited to the Pm SRAM, and the wiring pitch of some of the wirings may be the Pm SRAM.
  • the SRAM block 22 is used as a macro block to be compared with the wiring pitch, but other macro blocks such as mask ROM, memory block such as DRAM, PLL, A / D converter, D / A converter And the like may be used as the comparison targets of the wiring pitch.
  • the degree of freedom of the cell height of the standard cell can be enhanced without impairing the consistency with the arrangement of the nanowires and the metal interconnections. It is useful for performance improvement.
  • SRAM block (macro block) C, C11, C12 Standard cells CR1, CR2, CR3 Cell row Hc Cell height NW Nanowire Pn Nanowire pitch (first pitch) Pm Metal wiring pitch (second pitch) Metal wiring pitch in Pm SRAM SRAM block (3rd pitch)

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  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Chemical & Material Sciences (AREA)
  • Engineering & Computer Science (AREA)
  • Materials Engineering (AREA)
  • Nanotechnology (AREA)

Abstract

L'invention concerne un dispositif de circuit intégré à semi-conducteur qui utilise un transistor FET à nanofils comprenant un bloc de circuit dans lequel une pluralité de rangées de cellules (CR1-CR3) comprenant une pluralité de cellules standards (C) alignées dans une direction X sont alignées côte à côte dans une direction Y. La pluralité de cellules standards (C) comprennent chacune une pluralité de nanofils (NW) s'étendant dans la direction X et disposés à un pas prédéterminé (Pn) dans la direction Y. Dans la pluralité de cellules standards (C), la hauteur de cellule (Hc), qui est la taille dans la direction Y, est M fois (où M est un nombre impair) la moitié du pas (Pn) des nanofils (NW).
PCT/JP2018/021733 2017-06-27 2018-06-06 Dispositif de circuit intégré à semi-conducteur WO2019003840A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2019526755A JP7054013B2 (ja) 2017-06-27 2018-06-06 半導体集積回路装置
US16/711,018 US11348925B2 (en) 2017-06-27 2019-12-11 Matching nanowire FET periodic structuire to standard cell periodic structure in integrated circuits

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2017-125077 2017-06-27
JP2017125077 2017-06-27

Related Child Applications (1)

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US16/711,018 Continuation US11348925B2 (en) 2017-06-27 2019-12-11 Matching nanowire FET periodic structuire to standard cell periodic structure in integrated circuits

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Publication number Priority date Publication date Assignee Title
US10402529B2 (en) * 2016-11-18 2019-09-03 Taiwan Semiconductor Manufacturing Company, Ltd. Method and layout of an integrated circuit
US12046653B2 (en) 2020-11-05 2024-07-23 Samsung Electronics Co., Ltd. Integrated circuit including gate-all-around transistor

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US20140097493A1 (en) * 2012-10-09 2014-04-10 Samsung Electronics Co., Ltd. Cells including at least one fin field effect transistor and semiconductor integrated circuits including the same
JP2015019067A (ja) * 2013-07-12 2015-01-29 三星電子株式会社Ｓａｍｓｕｎｇ Ｅｌｅｃｔｒｏｎｉｃｓ Ｃｏ．，Ｌｔｄ． 半導体装置及びその製造方法
US20150041924A1 (en) * 2012-06-13 2015-02-12 Synopsys, Inc. N-channel and p-channel end-to-end finfet cell architecture
US20160125116A1 (en) * 2014-10-31 2016-05-05 Synopsys, Inc. Methodology using fin-fet transistors

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CN107424999A (zh) 2012-01-13 2017-12-01 特拉创新公司 具有线形翅片场效应结构的电路
US9659129B2 (en) 2013-05-02 2017-05-23 Taiwan Semiconductor Manufacturing Company, Ltd. Standard cell having cell height being non-integral multiple of nominal minimum pitch
KR102314778B1 (ko) * 2015-08-21 2021-10-21 삼성전자주식회사 반도체 소자

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Publication number Priority date Publication date Assignee Title
JP2010141187A (ja) * 2008-12-12 2010-06-24 Renesas Technology Corp 半導体集積回路装置
US20150041924A1 (en) * 2012-06-13 2015-02-12 Synopsys, Inc. N-channel and p-channel end-to-end finfet cell architecture
US20140097493A1 (en) * 2012-10-09 2014-04-10 Samsung Electronics Co., Ltd. Cells including at least one fin field effect transistor and semiconductor integrated circuits including the same
JP2015019067A (ja) * 2013-07-12 2015-01-29 三星電子株式会社Ｓａｍｓｕｎｇ Ｅｌｅｃｔｒｏｎｉｃｓ Ｃｏ．，Ｌｔｄ． 半導体装置及びその製造方法
US20160125116A1 (en) * 2014-10-31 2016-05-05 Synopsys, Inc. Methodology using fin-fet transistors

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US11348925B2 (en) 2022-05-31
US20200119022A1 (en) 2020-04-16
JP7054013B2 (ja) 2022-04-13
JPWO2019003840A1 (ja) 2020-04-23

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