WO2020107316A1 - Image sensor, method for preparing image sensor, and pixel circuit - Google Patents

Abstract

An image sensor (200), a method for preparing the image sensor (200), and a pixel circuit. The image sensor (200) comprises multiple pixel units (210), a circuit of each pixel unit (210) is provided on multiple wafers (221, 222), and the circuit of each pixel unit (210) is electrically connected between the multiple wafers (221, 222).

Description

Image sensor, method for preparing image sensor and pixel circuit

Copyright statement

The content disclosed in this patent document contains material protected by copyright. The copyright is owned by the copyright owner. The copyright owner has no objection to anyone copying the patent document or the patent disclosure existing in the official records and archives of the Patent and Trademark Office.

Technical field

The present application relates to the field of image sensors, and more particularly, to an image sensor, a method of preparing an image sensor, and a pixel circuit.

Background technique

Complementary metal oxide semiconductor image sensor (CMOSImageSensor, CIS) is widely used in consumer electronics, security monitoring, industrial automation, artificial intelligence, Internet of Things and other fields, for image data information collection and collation, to provide information for subsequent processing and application source.

CIS can be divided into rolling shutter image sensor (rolling shutter CIS, RS-CIS) and global shutter image sensor (global shutter CIS, GS-CIS) according to exposure and corresponding readout method. In the design of CIS, voltage-led GS-CIS is a mainstream solution. However, the current GS-CIS has a complicated structure. On the one hand, the area of a unit pixel is large, and on the other hand, a large number of transistors/capacitors occupy more pixel area, which affects the fill factor, the photosensitive efficiency, and the number of full well electrons. Thus affecting the performance of the image sensor.

Therefore, how to improve the performance of the image sensor has become an urgent technical problem to be solved.

Summary of the invention

The embodiments of the present application provide an image sensor, a method for preparing an image sensor, and a pixel circuit, which can improve the performance of the image sensor.

In a first aspect, an image sensor is provided, including: a plurality of pixel units; wherein the circuit of each pixel unit is provided on a plurality of wafers, and the circuit of each pixel unit is electrically connected between the plurality of wafers connection.

In a second aspect, a method of preparing an image sensor is provided, including: preparing a first circuit of each pixel unit of a plurality of pixel units of an image sensor on a first wafer; preparing each pixel on a second wafer A second circuit of the unit; electrically connecting the first circuit and the second circuit between the first wafer and the second wafer.

In a third aspect, a pixel circuit of an image sensor is provided, including: a photodiode, a transmission tube, a reset tube, a first source follower, a bias tube, a first switching tube, a second switching tube, a third switching tube, A fourth switch tube, a signal capacitor, a reference capacitor, a second source follower, and a row gate; wherein, the gate of the first source follower is connected to the photodiode through the transmission tube, and through the The reset tube is connected to the power supply; the source of the first source follower is connected to the drain of the bias tube; the drain of the bias tube is connected to the reference capacitor through the first switch tube, and Connected to the signal capacitor through the third switch tube; the gate of the second source follower is connected to the reference capacitor through the second switch tube, and connected to the signal capacitor through the fourth switch tube Signal capacitor; the source of the second source follower is connected to the row gate.

In the technical solution of the embodiment of the present application, the circuit of the pixel unit is provided on multiple wafers, and the pixel circuit connection is achieved through the electrical connection between the multiple wafers. , Can make the photodiode occupy a larger proportion of the pixel area, improve the fill factor, light-sensitive efficiency and the number of full-hole electrons, which can improve the performance of the image sensor.

BRIEF DESCRIPTION

FIG. 1 is a schematic diagram of a pixel circuit of an image sensor according to an embodiment of the application.

2 is a schematic diagram of an image sensor according to an embodiment of the present application.

3 is a schematic diagram of a pixel circuit of an image sensor according to another embodiment of the present application.

FIG. 4 is a timing chart of the pixel circuit in FIG. 3.

5-8 are schematic diagrams of pixel circuits of an image sensor according to an embodiment of the present application.

9 is a schematic flowchart of a method of preparing an image sensor according to an embodiment of the present application.

10-13 are schematic diagrams of the preparation process of the image sensor according to the embodiment of the present application.

detailed description

The technical solutions in the embodiments of the present application will be described below with reference to the drawings.

It should be understood that the specific examples in this document are only to help those skilled in the art to better understand the embodiments of the present application, but not to limit the scope of the embodiments of the present application.

It should also be understood that in various embodiments of the present application, the size of the sequence number of each process does not mean the order of execution, and the execution order of each process should be determined by its function and internal logic, and should not be applied to the embodiments of this application The implementation process constitutes no limitation.

It should also be understood that the various embodiments described in this specification may be implemented alone or in combination, which is not limited in the embodiments of the present application.

The technical solutions of the embodiments of the present application may be applied to various image sensors, such as global shutter image sensors, but the embodiments of the present application are not limited thereto.

FIG. 1 shows a schematic diagram of a pixel circuit 100 of a global shutter image sensor. As shown in FIG. 1, the pixel circuit 100 includes eight transistors, a photodiode for receiving light, and two capacitors. Since more devices are included, the pixel area is larger, and a large number of transistors/capacitors occupy more pixel area, which affects the fill factor, the light-sensitivity, and the number of full-well electrons, thereby affecting the performance of the image sensor.

In view of this, the embodiments of the present application provide an improved image sensor design scheme to improve the performance of the image sensor.

FIG. 2 shows a schematic diagram of an image sensor 200 according to an embodiment of the present application.

As shown in FIG. 2, the image sensor 200 includes a plurality of pixel units 210 (two are shown in FIG. 2 ), wherein the circuit of each pixel unit 210 is provided on multiple wafers (two are shown in FIG. 2) On the wafers, that is, the first wafer 221 and the second wafer 222), the circuits of each pixel unit 210 are electrically connected between the plurality of wafers.

In the embodiment of the present application, the circuit of the pixel unit 210 is disposed on a plurality of wafers, and then a complete pixel circuit is realized through the electrical connection between the plurality of wafers. With this arrangement, the area of the pixel is reduced, and the photodiode can occupy a larger proportion of the pixel area, so that the performance of the image sensor can be improved.

Alternatively, the electrical connection may be an intermetallic bonding connection.

For example, as shown in FIG. 2, bonding electrodes 231 and 232 are used between the first wafer 221 and the second wafer 222 for intermetallic bonding, and the circuit of the pixel unit 210 is implemented in the first wafer 221 and the second The electrical connection between the wafers 222.

It should be understood that the electrical connection may also be other electrical connection methods, as long as the electrical connection between the wafers can be achieved, which is not limited in the embodiments of the present application.

The multiple wafers may be stacked, that is, multiple wafers are stacked vertically, as shown in the stacking manner shown in FIG. 2.

Optionally, as shown in FIG. 2, in the design of two wafers, the circuit of each pixel unit 210 includes a first circuit and a second circuit, and the first circuit is disposed on the first wafer 221 The second circuit is disposed on the second wafer 222, and the first circuit and the second circuit are electrically connected between the first wafer 221 and the second wafer 222.

Optionally, as shown in FIG. 2, the first circuit includes a photodiode 211. In the first circuit, in addition to the photodiode 211, fewer other devices may be provided so that the photodiode occupies a larger proportion of the pixel area.

In the embodiment of the present application, for the pixel unit 210, various pixel circuits may be used, which is not limited in the embodiment of the present application. The following uses the design of two wafers as an example to specifically describe the circuit arrangement of the pixel unit 210, but it should not be construed as a limitation to the embodiments of the present application.

FIG. 3 shows a schematic diagram of a pixel circuit 300 of an image sensor according to an embodiment of the application. The pixel circuit 300 may be a circuit of the pixel unit 210 in FIG. 2.

As shown in FIG. 3, the pixel circuit 300 may include: a photodiode 301, a transmission tube 302, a reset tube 303, a first source follower 304, a bias tube 305, a first switch tube 306, a second switch tube 307, a first The three switch 308, the fourth switch 309, the signal capacitor 310, the reference capacitor 311, the second source follower 312 and the row gate 313.

Transmission tube 302, reset tube 303, first source follower 304, bias tube 305, first switch tube 306, second switch tube 307, third switch tube 308, fourth switch tube 309, second source follower 312 The N-type semiconductor transmission tube (nMOS transistor) may be used for the row gate gating tube 313.

The gate of the first source follower 304 is connected to the photodiode 301 through the transmission tube 302, and is connected to the power supply VDD1 through the reset tube 303. The source of the first source follower 304 is connected to the drain of the bias tube 305. The drain of the first source follower 304 is connected to the power supply VDD1. The drain of the biasing tube 305 is connected to the reference capacitor 311 through the first switching tube 306 and connected to the signal capacitor 310 through the third switching tube 308. The gate of the second source follower 312 is connected to the reference capacitor 311 through the second switch 307 and connected to the signal capacitor 310 through the fourth switch 309. The source of the second source follower 312 is connected to the row gate 313. The drain of the second source follower 312 is connected to the power supply VDD2.

The timing chart of the pixel circuit 300 is shown in FIG. 4. The voltage in FIG. 4 is the control voltage applied to the gate of each transistor. When the exposure is about to end, the bias tube 305 opens and works in the saturation region, then the reset tube 303 closes, the first switch tube 306 opens, and the reference voltage Vref is stored in the reference capacitor 311; then the first switch tube 306 closes, and then transmits The tube 302 is opened, the photodiode 301 is electronically injected into the gate of the first source follower 304, and its voltage drops, and then the transmission tube 302 is closed, the third switch tube 308 is opened, the signal voltage Vsig is stored in the signal capacitor 310, and then closed Third switch 308. In this way, at this time, the reference voltage and signal voltage of each pixel have been stored in the respective reference capacitance and signal capacitance, and then the reference voltage and signal voltage of each row only need to be read out row by row. Specifically, first turn on the second switching transistor 307, output the reference voltage Vref through the source terminal of the second source follower 312, turn off the second switching transistor 307, and turn on the fourth switching transistor 309, at this time in the second source follower 312 The source end has a signal voltage Vsig, and Vref-Vsig is the signal corresponding to the incident light intensity.

The pixel circuit 300 may be disposed on multiple wafers, and electrically connected between the multiple wafers. The embodiment of the present application does not limit the device distribution of the pixel circuit 300 on multiple wafers.

Optionally, in an embodiment of the present application, as shown in FIG. 5, the pixel circuit 300 is disposed on two wafers, wherein the first circuit of the pixel circuit 300 includes a photodiode 301, a transmission tube 302, and a reset The tube 303 and the first source follower 304 are disposed on the first wafer; the second circuit of the pixel circuit 300 includes a bias tube 305, a first switch tube 306, a second switch tube 307, a third switch tube 308, The fourth switch tube 309, the signal capacitor 310, the reference capacitor 311, the second source follower 312 and the row gate 313 are disposed on the second wafer.

On the first wafer, the gate of the first source follower 304 is connected to the photodiode 301 through the transmission tube 302 and connected to the power supply VDD1 through the reset tube 303. The drain of the first source follower 304 is connected to the power supply VDD1.

On the second wafer, the drain of the bias tube 305 is connected to the reference capacitor 311 through the first switch tube 306 and connected to the signal capacitor 310 through the third switch tube 308. The gate of the second source follower 312 is connected to the reference capacitor 311 through the second switch 307 and connected to the signal capacitor 310 through the fourth switch 309. The source of the second source follower 312 is connected to the row gate 313. The drain of the second source follower 312 is connected to the power supply VDD2.

The source of the first source follower 304 and the drain of the bias tube 305 are electrically connected between the first wafer and the second wafer. For example, the source of the first source follower 304 and the drain of the bias tube 305 may be connected by intermetal bonding.

In the above embodiment, the first source follower 304 and the bias tube 305 are the locations where the first wafer and the second wafer are connected. The position where the first wafer and the second wafer are connected may also be selected in other positions in the pixel circuit 300.

Optionally, in another embodiment of the present application, as shown in FIG. 6, the first circuit of the pixel circuit 300 includes a photodiode 301, a transmission tube 302, a reset tube 303, a first source follower 304, and a bias tube 305 On the first wafer; the second circuit of the pixel circuit 300 includes a first switch 306, a second switch 307, a third switch 308, a fourth switch 309, a signal capacitor 310, a reference capacitor 311, The second source follower 312 and the row gate 313 are disposed on the second wafer.

On the first wafer, the gate of the first source follower 304 is connected to the photodiode 301 through the transmission tube 302 and connected to the power supply VDD1 through the reset tube 303. The drain of the first source follower 304 is connected to the power supply VDD1. The source of the first source follower 304 is connected to the drain of the bias tube 305.

On the second wafer, the first switch 306 is connected to the reference capacitor 311 and the third switch 308 is connected to the signal capacitor 310. The gate of the second source follower 312 is connected to the reference capacitor 311 through the second switch 307 and connected to the signal capacitor 310 through the fourth switch 309. The source of the second source follower 312 is connected to the row gate 313. The drain of the second source follower 312 is connected to the power supply VDD2.

The drain of the bias tube 305 and the first switch tube 306 and/or the third switch tube 308 are electrically connected between the first wafer and the second wafer, so that the The drain of the bias tube 305 is connected to the reference capacitor 311 through the first switch tube 306 and connected to the signal capacitor 310 through the third switch tube 308.

Alternatively, the circuit of the pixel unit 210 in FIG. 2 may also adopt the pixel circuit 100 shown in FIG. 1.

As shown in FIG. 1, the pixel circuit 100 includes a photodiode 101, a transmission tube 102, a reset tube 103, a first source follower 104, a bias tube 105, a first switching tube 106, a second switching tube 107, and a first capacitor 108, a second capacitor 109, a second source follower 110 and a row gate 111.

Similarly, for the transmission tube 102, the reset tube 103, the first source follower 104, the bias tube 105, the first switch tube 106, the second switch tube 107, the second source follower 110 and the row gate 111 Type semiconductor transmission tube.

The gate of the first source follower 104 is connected to the photodiode 101 through the transmission tube 102 and is connected to the power supply VDD1 through the reset tube 103. The source of the first source follower 104 is connected to the drain of the bias tube 105. The drain of the first source follower 104 is connected to the power supply VDD1. The drain of the bias tube 105 is connected to the first capacitor 108 through the first switch tube 106, and connected to the second capacitor through the first switch tube 106 and the second switch tube 107 109 and the gate of the second source follower 110. The source of the second source follower 110 is connected to the row gate 111. The drain of the second source follower 110 is connected to the power supply VDD2.

The working principle of the pixel circuit 100 is similar to that of the pixel circuit 300, except that the pixel circuit 100 only uses two switch tubes, and the first switch tube 106 and the second switch tube 107 are simultaneously turned on and stored in the second capacitor 109 for reference At the voltage Vref, the second switching transistor 107 is turned off, and the signal voltage Vsig is stored in the first capacitor 108; in the signal reading stage, Vref is first read, and then the second switching transistor 107 is turned on, and (Vref+Vsig)/2 is read.

Optionally, in an embodiment of the present application, as shown in FIG. 7, the pixel circuit 100 is disposed on two wafers, wherein the first circuit of the pixel circuit 100 includes a photodiode 101, a transmission tube 102, and a reset tube 103 And the first source follower 104, disposed on the first wafer; the second circuit of the pixel circuit 100 includes a bias tube 105, a first switch tube 106, a second switch tube 107, a first capacitor 108, a second capacitor 109 2. The second source follower 110 and the row gate 111 are disposed on the second wafer.

On the first wafer, the gate of the first source follower 104 is connected to the photodiode 101 through the transfer tube 102 and connected to the power supply VDD1 through the reset tube 103. The drain of the first source follower 104 is connected to the power supply VDD1.

On the second wafer, the drain of the bias tube 105 is connected to the first capacitor 108 through the first switch tube 106, and through the first switch tube 106 and the second switch tube 107 Connected to the second capacitor 109 and the gate of the second source follower 110. The source of the second source follower 110 is connected to the row gate 111. The drain of the second source follower 110 is connected to the power supply VDD2.

The source of the first source follower 104 and the drain of the bias tube 105 are electrically connected between the first wafer and the second wafer.

Optionally, in another embodiment of the present application, as shown in FIG. 8, the first circuit of the pixel circuit 100 includes a photodiode 101, a transmission tube 102, a reset tube 103, a first source follower 104, and a bias tube 105 On the first wafer; the second circuit of the pixel circuit 100 includes a first switch 106, a second switch 107, a first capacitor 108, a second capacitor 109, a second source follower 110 and a row gate 111, set on the second wafer.

On the first wafer, the gate of the first source follower 104 is connected to the photodiode 101 through the transfer tube 102 and connected to the power supply VDD1 through the reset tube 103. The source of the first source follower 104 is connected to the drain of the bias tube 105. The drain of the first source follower 104 is connected to the power supply VDD1.

On the second wafer, the first switch tube 106 is connected to the first capacitor 108 and is connected to the second capacitor 109 and the second source follower 110 through the second switch tube 107 Grid. The source of the second source follower 110 is connected to the row gate 111. The drain of the second source follower 110 is connected to the power supply VDD2.

The drain of the bias tube 105 and the first switch tube 107 are electrically connected between the first wafer and the second wafer, so that the drain of the bias tube 105 passes through the The first switch tube 106 is connected to the first capacitor 108 and is connected to the gate of the second capacitor 109 and the second source follower 110 through the first switch tube 106 and the second switch tube 107 pole.

It should be understood that, in addition to the above description, the circuit of the pixel unit 210 may also use other pixel circuits. In addition, the device distribution of the pixel circuit on multiple wafers may also use other divisions, which is not limited in the embodiments of the present application. .

In the technical solution of the embodiment of the present application, the circuit of the pixel unit is provided on multiple wafers, and the pixel circuit connection is achieved through the electrical connection between the multiple wafers. , Can make the photodiode occupy a larger proportion of the pixel area, improve the fill factor, light-sensitive efficiency and the number of full-hole electrons, which can improve the performance of the image sensor.

The image sensor and the pixel circuit of the embodiment of the present application are described above, and the preparation method is described below. It should be understood that, for the related description in the following method embodiments, reference may be made to the foregoing embodiments, and for the sake of brevity, they are not described in detail below.

FIG. 9 shows a schematic flowchart of a method 900 for preparing an image sensor according to an embodiment of the present application.

910. Prepare a first circuit of each pixel unit of the plurality of pixel units of the image sensor on the first wafer.

The first circuit includes a photodiode, and may include fewer other devices, so that the photodiode occupies a larger proportion of the pixel area.

As shown in FIG. 10, a photodiode 1001 and a small number of other devices can be prepared on the first wafer 1000, and bonding electrodes 1002 are provided.

920. Prepare a second circuit for each pixel unit on the second wafer.

The second circuit includes devices other than the first circuit.

As shown in FIG. 11, devices other than the first circuit may be prepared on the second wafer 1100, and bonding electrodes 1102 may be provided.

930. Electrically connect the first circuit and the second circuit between the first wafer and the second wafer.

Alternatively, the first circuit and the second circuit may be connected between the first wafer and the second wafer using intermetallic bonding.

As shown in FIG. 12, the first wafer 1000 and the second wafer 1100 are bonded, wherein, for each pixel circuit, the bonding electrodes 1002 and 1102 are used for inter-metal bonding to realize the circuit between the two wafers connection.

Optionally, in an embodiment of the present application, the first circuit includes a photodiode, a transmission tube, a reset tube, and a first source follower;

The second circuit includes a bias tube, a first switch tube, a second switch tube, a third switch tube, a fourth switch tube, a signal capacitor, a reference capacitor, a second source follower, and a row gate tube.

The gate of the first source follower is connected to the photodiode through the transmission tube, and is connected to the power supply through the reset tube;

The drain of the bias tube is connected to the reference capacitor through the first switch tube, and is connected to the signal capacitor through the third switch tube;

The gate of the second source follower is connected to the reference capacitor through the second switch tube, and is connected to the signal capacitor through the fourth switch tube;

The source of the second source follower is connected to the row gate;

Wherein, the source of the first source follower and the drain of the bias tube are electrically connected between the first wafer and the second wafer.

Optionally, in an embodiment of the present application, the first circuit includes a photodiode, a transmission tube, a reset tube, a first source follower, and a bias tube;

The second circuit includes a first switch tube, a second switch tube, a third switch tube, a fourth switch tube, a signal capacitor, a reference capacitor, a second source follower, and a row gate tube.

The gate of the first source follower is connected to the photodiode through the transmission tube, and is connected to the power supply through the reset tube;

The source of the first source follower is connected to the drain of the bias tube;

The first switch tube is connected to the reference capacitor, and the third switch tube is connected to the signal capacitor;

The gate of the second source follower is connected to the reference capacitor through the second switch tube, and is connected to the signal capacitor through the fourth switch tube;

The source of the second source follower is connected to the row gate;

Wherein, the drain of the bias tube and the first switch tube and/or the third switch tube are electrically connected between the first wafer and the second wafer, so that the bias The drain of the set tube is connected to the reference capacitor through the first switch tube, and is connected to the signal capacitor through the third switch tube.

Optionally, in an embodiment of the present application, the first circuit includes a photodiode, a transmission tube, a reset tube, and a first source follower;

The second circuit includes a bias tube, a first switch tube, a second switch tube, a first capacitor, a second capacitor, a second source follower, and a row gate.

The gate of the first source follower is connected to the photodiode through the transmission tube, and is connected to the power supply through the reset tube;

The drain of the bias tube is connected to the first capacitor through the first switch tube, and connected to the second capacitor and the second capacitor through the first switch tube and the second switch tube The gate of the source follower;

The source of the second source follower is connected to the row gate;

Wherein, the source of the first source follower and the drain of the bias tube are electrically connected between the first wafer and the second wafer.

Optionally, in an embodiment of the present application, the first circuit includes a photodiode, a transmission tube, a reset tube, a first source follower, and a bias tube;

The second circuit includes a first switch tube, a second switch tube, a first capacitor, a second capacitor, a second source follower, and a row gate.

The gate of the first source follower is connected to the photodiode through the transmission tube, and is connected to the power supply through the reset tube;

The source of the first source follower is connected to the drain of the bias tube;

The first switch tube is connected to the first capacitor, and is connected to the second capacitor and the gate of the second source follower through the second switch tube;

The source of the second source follower is connected to the row gate;

Wherein, the drain of the bias tube and the first switch tube are electrically connected between the first wafer and the second wafer, so that the drain of the bias tube passes through the first A switch tube is connected to the first capacitor, and is connected to the second capacitor and the gate of the second source follower through the first switch tube and the second switch tube.

Optionally, after 930, the first wafer may also be thinned so that the photodiode receives the optical signal.

As shown in FIG. 13, after the first wafer 1000 and the second wafer 1100 are bonded, the first wafer 1000 is thinned so that the photodiode 1001 is on the surface of the pixel, so that it can receive optical signals.

It should be understood that although the design of the two wafers has been described above as an example, the technical solutions of the embodiments of the present application are not limited to two wafers. For more than two wafers, the two-wafer design described above can be used between each two wafers.

It should also be understood that the technical solutions of the embodiments of the present application are not limited to global shutter image sensors, and other image sensors may also use the technical solutions of the embodiments of the present application to reduce the pixel area and improve the performance of the image sensor.

Those of ordinary skill in the art may realize that the units and algorithm steps of the examples described in conjunction with the embodiments disclosed herein can be implemented by electronic hardware, computer software, or a combination of the two, in order to clearly explain the hardware and software. Interchangeability, in the above description, the composition and steps of each example have been described generally in terms of function. Whether these functions are executed in hardware or software depends on the specific application of the technical solution and design constraints. Professional technicians can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

In the several embodiments provided in this application, it should be understood that the disclosed system, device, and method may be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the units is only a division of logical functions. In actual implementation, there may be other divisions, for example, multiple units or components may be combined or Can be integrated into another system, or some features can be ignored, or not implemented. In addition, the displayed or discussed mutual couplings or direct couplings or communication connections may be indirect couplings or communication connections through some interfaces, devices, or units, and may also be electrical, mechanical, or other forms of connection.

The units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or may be distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the objectives of the solutions of the embodiments of the present application.

In addition, the functional units in the embodiments of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The above integrated unit may be implemented in the form of hardware or software functional unit.

If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it may be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application essentially or part of the contribution to the existing technology, or all or part of the technical solution can be embodied in the form of a software product, the computer software product is stored in a storage medium In it, several instructions are included to enable a computer device (which may be a personal computer, server, or network device, etc.) to perform all or part of the steps of the methods described in the embodiments of the present application. The aforementioned storage media include: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), magnetic disk or optical disk and other media that can store program code .

The above is only the specific implementation of this application, but the scope of protection of this application is not limited to this, any person skilled in the art can easily think of various equivalents within the technical scope disclosed in this application Modifications or replacements, these modifications or replacements should be covered within the scope of protection of this application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims (30)

An image sensor, characterized in that it includes: Multiple pixel units; Wherein, the circuit of each pixel unit is provided on multiple wafers, and the circuit of each pixel unit is electrically connected between the multiple wafers. The image sensor according to claim 1, wherein the plurality of wafers are stacked. The image sensor according to claim 1 or 2, wherein the plurality of wafers includes a first wafer and a second wafer, and the circuit of each pixel unit includes a first circuit and a second circuit, the The first circuit is provided on the first wafer, the second circuit is provided on the second wafer, the first circuit and the second circuit are provided on the first wafer and the first The two wafers are electrically connected. The image sensor according to claim 3, wherein the first circuit includes a photodiode. The image sensor according to claim 3 or 4, wherein the first circuit includes a photodiode, a transmission tube, a reset tube, and a first source follower; The second circuit includes a bias tube, a first switch tube, a second switch tube, a third switch tube, a fourth switch tube, a signal capacitor, a reference capacitor, a second source follower, and a row gate tube. The image sensor according to claim 5, wherein the gate of the first source follower is connected to the photodiode through the transmission tube, and is connected to a power source through the reset tube; The source electrode of the first source follower and the drain electrode of the bias tube are electrically connected between the first wafer and the second wafer; The drain of the bias tube is connected to the reference capacitor through the first switch tube, and is connected to the signal capacitor through the third switch tube; The gate of the second source follower is connected to the reference capacitor through the second switch tube, and is connected to the signal capacitor through the fourth switch tube; The source of the second source follower is connected to the row gate. The image sensor according to claim 3 or 4, wherein the first circuit includes a photodiode, a transmission tube, a reset tube, a first source follower, and a bias tube; The second circuit includes a first switch tube, a second switch tube, a third switch tube, a fourth switch tube, a signal capacitor, a reference capacitor, a second source follower, and a row gate tube. The image sensor according to claim 7, wherein the gate of the first source follower is connected to the photodiode through the transmission tube, and is connected to a power source through the reset tube; The source of the first source follower is connected to the drain of the bias tube; The drain of the bias tube is connected to the reference capacitor through the first switch tube, and to the signal capacitor through the third switch tube, wherein the drain of the bias tube is connected to the The first switch tube and/or the third switch tube are electrically connected between the first wafer and the second wafer; The gate of the second source follower is connected to the reference capacitor through the second switch tube, and is connected to the signal capacitor through the fourth switch tube; The source of the second source follower is connected to the row gate. The image sensor according to claim 3 or 4, wherein the first circuit includes a photodiode, a transmission tube, a reset tube, and a first source follower; The second circuit includes a bias tube, a first switch tube, a second switch tube, a first capacitor, a second capacitor, a second source follower, and a row gate. The image sensor according to claim 9, wherein the gate of the first source follower is connected to the photodiode through the transmission tube, and is connected to a power source through the reset tube; The source electrode of the first source follower and the drain electrode of the bias tube are electrically connected between the first wafer and the second wafer; The drain of the bias tube is connected to the first capacitor through the first switch tube, and connected to the second capacitor and the second capacitor through the first switch tube and the second switch tube The gate of the source follower; The source of the second source follower is connected to the row gate. The image sensor according to claim 3 or 4, wherein the first circuit includes a photodiode, a transmission tube, a reset tube, a first source follower, and a bias tube; The second circuit includes a first switch tube, a second switch tube, a first capacitor, a second capacitor, a second source follower, and a row gate. The image sensor according to claim 11, wherein the gate of the first source follower is connected to the photodiode through the transmission tube, and is connected to a power source through the reset tube; The source of the first source follower is connected to the drain of the bias tube; The drain of the bias tube is connected to the first capacitor through the first switch tube, and connected to the second capacitor and the second capacitor through the first switch tube and the second switch tube A gate of the source follower, wherein the drain of the bias tube and the first switch tube are electrically connected between the first wafer and the second wafer; The source of the second source follower is connected to the row gate. The image sensor according to any one of claims 1 to 12, wherein the electrical connection includes an intermetallic bonding connection. A method for preparing an image sensor, characterized in that it includes: Preparing the first circuit of each pixel unit of the plurality of pixel units of the image sensor on the first wafer; Preparing a second circuit for each pixel unit on the second wafer; The first circuit and the second circuit are electrically connected between the first wafer and the second wafer. The method of claim 14, wherein the first circuit includes a photodiode. The method according to claim 14 or 15, wherein the first circuit includes a photodiode, a transmission tube, a reset tube, and a first source follower; The second circuit includes a bias tube, a first switch tube, a second switch tube, a third switch tube, a fourth switch tube, a signal capacitor, a reference capacitor, a second source follower, and a row gate tube. The method according to claim 16, wherein the gate of the first source follower is connected to the photodiode through the transmission tube, and is connected to a power source through the reset tube; The drain of the bias tube is connected to the reference capacitor through the first switch tube, and is connected to the signal capacitor through the third switch tube; The gate of the second source follower is connected to the reference capacitor through the second switch tube, and is connected to the signal capacitor through the fourth switch tube; The source of the second source follower is connected to the row gate; Wherein, the electrically connecting the first circuit and the second circuit between the first wafer and the second wafer includes: The source of the first source follower and the drain of the bias tube are electrically connected between the first wafer and the second wafer. The method according to claim 14 or 15, wherein the first circuit includes a photodiode, a transmission tube, a reset tube, a first source follower, and a bias tube; The second circuit includes a first switch tube, a second switch tube, a third switch tube, a fourth switch tube, a signal capacitor, a reference capacitor, a second source follower, and a row gate tube. The method of claim 18, wherein the gate of the first source follower is connected to the photodiode through the transmission tube, and is connected to a power source through the reset tube; The source of the first source follower is connected to the drain of the bias tube; The first switch tube is connected to the reference capacitor, and the third switch tube is connected to the signal capacitor; The gate of the second source follower is connected to the reference capacitor through the second switch tube, and is connected to the signal capacitor through the fourth switch tube; The source of the second source follower is connected to the row gate; Wherein, the electrically connecting the first circuit and the second circuit between the first wafer and the second wafer includes: Electrically connecting the drain of the bias tube and the first switch tube and/or the third switch tube between the first wafer and the second wafer to make the bias tube The drain of is connected to the reference capacitor through the first switch, and is connected to the signal capacitor through the third switch. The method according to claim 14 or 15, wherein the first circuit includes a photodiode, a transmission tube, a reset tube, and a first source follower; The second circuit includes a bias tube, a first switch tube, a second switch tube, a first capacitor, a second capacitor, a second source follower, and a row gate. The method of claim 20, wherein the gate of the first source follower is connected to the photodiode through the transmission tube, and is connected to a power source through the reset tube; The drain of the bias tube is connected to the first capacitor through the first switch tube, and connected to the second capacitor and the second capacitor through the first switch tube and the second switch tube The gate of the source follower; The source of the second source follower is connected to the row gate; Wherein, the electrically connecting the first circuit and the second circuit between the first wafer and the second wafer includes: The source of the first source follower and the drain of the bias tube are electrically connected between the first wafer and the second wafer. The method according to claim 14 or 15, wherein the first circuit includes a photodiode, a transmission tube, a reset tube, a first source follower, and a bias tube; The second circuit includes a first switch tube, a second switch tube, a first capacitor, a second capacitor, a second source follower, and a row gate. The method of claim 22, wherein the gate of the first source follower is connected to the photodiode through the transmission tube, and is connected to a power source through the reset tube; The source of the first source follower is connected to the drain of the bias tube; The first switch tube is connected to the first capacitor, and is connected to the second capacitor and the gate of the second source follower through the second switch tube; The source of the second source follower is connected to the row gate; Wherein, the electrically connecting the first circuit and the second circuit between the first wafer and the second wafer includes: Electrically connecting the drain of the bias tube and the first switch tube between the first wafer and the second wafer so that the drain of the bias tube passes through the first switch The tube is connected to the first capacitor, and is connected to the second capacitor and the gate of the second source follower through the first switch tube and the second switch tube. The method according to any one of claims 14 to 23, wherein the first circuit and the second circuit are electrically connected between the first wafer and the second wafer ,include: The first circuit and the second circuit are connected between the first wafer and the second wafer by using inter-metal bonding. The method according to any one of claims 15 to 24, wherein the method further comprises: The first wafer is thinned so that the photodiode receives the optical signal. A pixel circuit of an image sensor is characterized by comprising: Photodiode, transmission tube, reset tube, first source follower, bias tube, first switch tube, second switch tube, third switch tube, fourth switch tube, signal capacitor, reference capacitor, second source follower Hexing gating tube; Wherein, the gate of the first source follower is connected to the photodiode through the transmission tube, and is connected to the power supply through the reset tube; The source of the first source follower is connected to the drain of the bias tube; The drain of the bias tube is connected to the reference capacitor through the first switch tube, and is connected to the signal capacitor through the third switch tube; The gate of the second source follower is connected to the reference capacitor through the second switch tube, and is connected to the signal capacitor through the fourth switch tube; The source of the second source follower is connected to the row gate. The pixel circuit according to claim 26, wherein the pixel circuit is disposed on a plurality of wafers and electrically connected between the plurality of wafers. The pixel circuit according to claims 26 and 27, wherein the photodiode, the transmission tube, the reset tube, and the first source follower are disposed on a first wafer; The bias tube, the first switch tube, the second switch tube, the third switch tube, the fourth switch tube, the signal capacitor, the reference capacitor, the second source follow And the row gate tube are arranged on the second wafer; The source of the first source follower and the drain of the bias tube are electrically connected between the first wafer and the second wafer. The pixel circuit according to claims 26 and 27, wherein the photodiode, the transfer tube, the reset tube, the first source follower, and the bias tube are provided on the first wafer on; The first switch tube, the second switch tube, the third switch tube, the fourth switch tube, the signal capacitor, the reference capacitor, the second source follower and the row selection The through tube is arranged on the second wafer; The drain of the bias tube is electrically connected to the first switching tube and/or the third switching tube between the first wafer and the second wafer. The pixel circuit according to any one of claims 26 to 29, wherein the electrical connection includes an intermetallic bonding connection.

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