WO2024152473A1 - Cxl memory module and memory storage system - Google Patents

Abstract

A CXL memory module and a memory storage system. The CXL memory module is used for expanding the memory of a computer, and the CXL memory module may comprise a controller chip and at least one DRAM chip; the controller chip is connected to each DRAM chip by using a serial interface.

Description

A CXL memory module and memory storage system

CROSS-REFERENCE TO RELATED APPLICATIONS

This disclosure claims priority to the Chinese patent application filed with CNIPA on January 19, 2023, with application number 202310058375.2 and invention name “A CXL memory module and memory storage system”, the contents of which are hereby incorporated by reference.

Technical Field

The present disclosure relates to but is not limited to storage technology, and in particular to a CXL memory module and a memory storage system.

Background technique

CXL is a memory interface protocol based on the PCIe physical layer. The CXL protocol allows the computer's memory to be expanded using CXL memory modules.

The CXL memory module consists of a CXL controller chip and a group of DRAM chips or DIMMs connected using the DDR protocol. Currently, the interface between DRAM and CPU uses the DDR protocol. As the transmission speed requirements become higher and higher, the DDR protocol can no longer meet the requirements.

SUMMARY OF THE INVENTION

The following is a summary of the subject matter of the detailed description of the present disclosure. This summary is not intended to limit the scope of the claims.

The disclosed embodiment provides a CXL memory module for expanding the memory of a computer, including a controller chip and at least one set of DRAM chips;

The controller chip is connected to each group of DRAM chips using a serial interface.

The disclosed embodiment further provides a memory storage system, comprising a host and the CXL memory module described in any one of the embodiments; the host is connected to a CXL interface in the CXL memory module.

The CXL memory module and memory storage system provided by at least one embodiment of the present disclosure have the following beneficial effects compared with the prior art: Compared with the existing solution in which the controller chip and the DRAM chip are connected using the DDR protocol, a higher transmission speed can be provided.

Other aspects will be apparent upon reading and understanding the drawings and detailed description.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings are used to provide an understanding of the technical solution of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solution of the present disclosure and do not constitute a limitation on the technical solution of the present disclosure.

FIG1 is a structural block diagram of a CXL memory module provided by an exemplary embodiment of the present disclosure;

FIG2 is a structural block diagram of a CXL memory module provided by another exemplary embodiment of the present disclosure;

FIG. 3 is a structural block diagram of a memory storage system provided in an example embodiment of the present disclosure.

Details

The embodiments of the present disclosure will be described in detail below in conjunction with the accompanying drawings. In the absence of conflict, the embodiments and features in the embodiments of the present disclosure can be combined with each other arbitrarily.

The present disclosure describes multiple embodiments, but the description is exemplary rather than restrictive, and it will be apparent to those skilled in the art that there may be more embodiments and implementations within the scope of the embodiments described in the present disclosure. Although many possible combinations of features are shown in the drawings and discussed in the specific embodiments, many other combinations of the disclosed features are possible. Unless specifically limited, any feature or element of any embodiment may be used in combination with any other feature or element in any other embodiment, or may replace any other feature or element in any other embodiment.

The present disclosure includes and contemplates combinations of features and elements known to those of ordinary skill in the art. The embodiments, features, and elements disclosed in the present disclosure may also be combined with any conventional features or elements to form a scheme defined by the claims. Any features or elements of any embodiment may also be combined with features or elements from other schemes to form another scheme defined by the claims. Therefore, it should be understood that any feature shown and/or discussed in this disclosure may be implemented alone or in any appropriate combination. Therefore, except for the limitations made according to the attached claims and their equivalents, the implementation Furthermore, various modifications and changes may be made within the scope of protection of the appended claims.

In addition, when describing representative embodiments, the specification may have presented the method and process as a specific sequence of steps. However, to the extent that the method or process does not rely on the specific order of the steps described herein, the method or process should not be limited to the steps in the specific order described. As will be understood by those of ordinary skill in the art, other orders of steps are also possible. Therefore, the specific order of the steps set forth in the specification should not be interpreted as a limitation on the claims. In addition, the claims for the method and process should not be limited to the steps performed in the order written, and those skilled in the art can easily understand that these orders can be changed and still remain within the spirit and scope of the disclosed embodiments.

FIG. 1 is a structural block diagram of a CXL memory module provided in an exemplary embodiment of the present disclosure, and FIG. 2 is a structural block diagram of a CXL memory module provided in another exemplary embodiment of the present disclosure. As shown in FIG. 1 and FIG. 2 , the CXL memory module may include a controller chip 11 and at least one group of DRAM chips 12, and each group of DRAM chips may include one or more DRAM chips;

The controller chip is connected to each group of DRAM chips using a serial interface.

CXL is a memory interface protocol based on the PCIe physical layer. The CXL protocol enables the use of CXL memory modules to expand the memory of a host, which may include a CPU chip, a computer, or a computing node.

The host can be expanded in memory through at least one group of DRAM chips of the CXL memory module. The controller chip can include a CXL interface. The host can be connected to the CXL memory module through the CXL interface. The CXL memory module can expand the memory of the host connected to the CXL interface. When the host needs to increase the memory capacity, it can send instructions to the CXL memory module connected to the host through the cxl.io protocol to apply for memory space. The CXL memory module allocates part or all of the space in the DRAM chip as the host's memory expansion capacity.

The controller chip and the DRAM chip can be connected using a serial interface, which can provide a higher transmission speed compared to the existing solution in which the controller chip and the DRAM chip are connected using the DDR protocol.

The controller chip may include a serial interface that is connected to a DRAM chip of a serial port. The controller chip and the DRAM chip are connected using a serial interface. The serial port DRAM chip can be developed by modifying the external interface of the existing DRAM chip, and the external interface of the DRAM chip is changed to a serial interface.

In an exemplary embodiment of the present disclosure, the serial interface may include a high-speed Serdes serial interface.

The controller chip and the DRAM chip can be connected using a high-speed serial interface (Serdes), which can provide a higher transmission speed with the same number of pins.

In an exemplary embodiment of the present disclosure, a high-speed Serdes serial interface may perform communication transmission based on a PCIe protocol.

The high-speed serial interface can select the PCIe protocol for communication transmission. The controller chip and the DRAM chip can communicate and transmit based on the PCIe protocol to achieve data exchange or data reading and writing.

In an example embodiment of the present disclosure, as shown in FIG2 , the controller chip may include: a PCIe switch system configured to be turned on when the controller chip performs data exchange according to a memory read/write request sent by a host, to establish a connection between the host and a corresponding group of DRAM chips for data exchange.

In the case where the high-speed serial interface performs communication transmission based on the PCIe protocol, the controller chip may include a PCIe switch system. Since the host communicates with the CXL memory module based on the CXL protocol, and the controller chip communicates with the DRAM chip based on the PCIe protocol, when data is exchanged, the PCIe switch system is turned on, and the host and one or a group of DRAM chips can be connected through the CXL-PCIe line to perform data exchange.

The PCIe switch system may be arranged between the CXL interface and the DRAM chip. The PCIe switch system may include a multi-way switch. One end of each switch is respectively connected to one or a group of DRAM chips, and the other end may be connected to the CXL interface.

In an example embodiment of the present disclosure, as shown in FIG2 , the controller chip may include: a CXL interface, which may be configured to connect to a host; the host connected to the CXL interface can send a memory read/write request of a CXL instruction to the CXL memory module, that is, the host connected to the CXL interface can send a CXL instruction of a memory read/write request to the CXL memory module;

The controller chip is configured to select a group of DRAM chips to exchange data with the host according to the address carried in the memory read/write request when receiving the memory read/write request from the host, that is, select a group of DRAM chips to exchange data with the host according to the address.

The host can be connected to the CXL memory module through the CXL interface. The host can send memory read and write requests to the CXL memory module through the cxl.mem protocol. The CXL memory module can read corresponding data from the DRAM chip according to the received memory read and write requests, or the CXL memory module can write corresponding data to the DRAM chip according to the received memory read and write requests.

When the controller chip receives a memory read/write request from the host, the memory read/write request includes the target address of the data to be read or the target address of the data to be written. The controller chip controls the conduction route of the PCIe switch system according to the address carried in the memory read/write request, selects one or a group of DRAM chips for data exchange, and exchanges data with the host.

In an exemplary embodiment of the present disclosure, a group of DRAM chips may include multiple silicon chips packaged together, that is, the DRAM chips may be packaged together by multiple silicon chips, and the multiple silicon chips use the same group of high-speed serial port pins for communication.

DRAM chips can be packaged together from multiple silicon chips, and multiple silicon chips can use the same set of high-speed serial port pins to communicate, which can improve chip performance and reduce costs.

In an example embodiment of the present disclosure, the same set of high-speed serial port pins used by multiple silicon chips can be connected to a control end of a controller chip; when the controller chip receives a memory read or write request from the host, it selects a group of DRAM chips according to the address, sends corresponding chip select signals, and connects the corresponding silicon chips for data exchange.

When a DRAM chip is packaged together with multiple silicon chips, the selection of multiple silicon chips can be achieved through the chip select signal. The chip select signal connected to the CXL memory module controller chip can be selected by the controller chip.

When the controller chip receives a memory read or write request from the host, the controller chip selects one or a group of DRAM chips according to the address in the memory read or write request, and selects the corresponding chip select signal, connects the corresponding silicon chip for data exchange, and exchanges data with the host.

In an example embodiment of the present disclosure, as shown in FIG2 , the controller chip may further include: an embedded CPU core configured to select a group of DRAM chips to exchange data with the host according to an address when receiving a memory read or write request from the host.

The controller chip may include an embedded CPU core, and the embedded CPU core may be used to implement corresponding control or management. The embedded CPU core may implement at least one of the following control or management:

The embedded CPU core can be connected to the CXL interface and can communicate with the host connected to the CXL interface. When receiving a memory read/write request from the host, the embedded CPU core can select a group of DRAM chips according to the address to exchange data with the host.

The embedded CPU core can select one or a group of DRAM chips according to the address in the memory read and write request, and select (or send) the corresponding chip select signal, connect the corresponding silicon chip for data exchange, and exchange with the host.

A control terminal of the embedded CPU core can be connected to the PCIe switch system. The embedded CPU core can control the conduction of the corresponding switch of the PCIe switch system when exchanging data according to the memory read and write request sent by the host.

The embedded CPU core can allocate part or all of the space in the DRAM chip as memory expansion capacity for the host.

In an example embodiment of the present disclosure, as shown in FIG2 , the controller chip may further include: an error correction code (ECC) correction system configured to perform ECC error correction on data of the DRAM chip.

When receiving a memory read/write request from the host and reading a data packet from the DRAM chip, the ECC error correction system can determine whether the data packet read from the DRAM chip is a problem data packet through ECC error correction, thereby improving the reliability of the DRAM chip. The implementation principle of ECC error correction is the same as that of the existing solution, and this embodiment will not be limited or elaborated here.

FIG3 is a structural block diagram of a memory storage system provided in an exemplary embodiment of the present disclosure. As shown in FIG3 , the memory storage system may include a host 31 and a CXL memory module 32 shown in any embodiment; the host is connected to a CXL interface in the CXL memory module.

The host can be connected to the CXL memory module through the CXL interface, and the CXL memory module can expand the memory of the host connected to the CXL interface. When the host needs to increase the memory capacity, it can send instructions to the CXL memory module connected to the host to apply for memory space through the cxl.io protocol. The CXL memory module allocates part or all of the space in the DRAM chip as the host's memory expansion capacity.

The host can connect to the CXL memory module through the CXL interface. The host can send memory read and write requests to the CXL memory module through the cxl.mem protocol. The CXL memory module can read the corresponding data from the DRAM chip according to the received memory read and write requests, or the CXL memory module can read the corresponding data from the DRAM chip according to the received memory read and write requests. The storage read and write request writes the corresponding data into the DRAM chip.

The CXL memory module may include a controller chip and at least one group of DRAM chips. The controller chip and the DRAM chips are connected using a serial interface, which can provide a higher transmission speed.

It will be appreciated by those skilled in the art that all or some of the steps, systems, and functional modules/units in the methods disclosed above may be implemented as software, firmware, hardware, and appropriate combinations thereof. In hardware implementations, the division between the functional modules/units mentioned in the above description does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be performed by several physical components in cooperation. Some or all components may be implemented as software executed by a processor, such as a digital signal processor or a microprocessor, or implemented as hardware, or implemented as an integrated circuit, such as an application-specific integrated circuit. Such software may be distributed on a computer-readable medium, which may include a computer storage medium (or non-transitory medium) and a communication medium (or temporary medium). As known to those skilled in the art, the term computer storage medium includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tapes, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to store the desired information and can be accessed by a computer. In addition, it is well known to those of ordinary skill in the art that communication media typically contain computer-readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transport mechanism, and may include any information delivery media.

Claims (10)

A CXL memory module is used for expanding the memory of a computer, comprising a controller chip and at least one set of DRAM chips; The controller chip is connected to each group of DRAM chips using a serial interface. The CXL memory module according to claim 1, wherein the serial interface comprises a high-speed SerDes serial interface. The CXL memory module according to claim 2, wherein the high-speed SerDes serial interface performs communication transmission based on the PCIe protocol. The CXL memory module according to claim 3, wherein the controller chip comprises: a PCIe switch system configured to be turned on when the controller chip performs data exchange according to a memory read/write request sent by the host, to establish a connection between the host and a corresponding group of DRAM chips for data exchange. The CXL memory module according to claim 1, wherein the controller chip comprises: a CXL interface, wherein the CXL interface is configured to connect to a host; The host connected to the CXL interface can send a memory read and write request in the form of a CXL instruction to the CXL memory module; The controller chip is configured to select a group of DRAM chips to exchange data with the host according to the address carried in the memory read/write request when receiving the memory read/write request from the host. The CXL memory module according to claim 5, wherein a group of the DRAM chips comprises a plurality of silicon chips packaged together, and the plurality of silicon chips communicate using the same set of high-speed serial port pins. The CXL memory module according to claim 6, wherein the same set of high-speed serial port pins used by the plurality of silicon chips are connected to a control terminal of the controller chip; When the controller chip receives a memory read/write request from the host, it selects a group of DRAM chips according to the address, sends a corresponding chip select signal, and connects to the corresponding silicon chips for data exchange. The CXL memory module according to claim 5, wherein the controller chip further comprises: an embedded CPU core configured to select a group of DRAM chips to exchange data with the host according to the address when receiving a memory read or write request from the host. The CXL memory module according to claim 1, wherein the controller chip further comprises: an ECC error correction system configured to perform ECC error correction on data of the DRAM chip. A memory storage system comprises a host and a CXL memory module as claimed in any one of claims 1 to 9; the host is connected to a CXL interface in the CXL memory module.