WO2025065635A1

WO2025065635A1 - Stacked structure, pixel driving circuit, control circuit, display module and electronic device

Info

Publication number: WO2025065635A1
Application number: PCT/CN2023/122931
Authority: WO
Inventors: Keitaro Yamashita; Kenji Sera; Masafumi Matsui; Kenichi Takatori; Yasuyuki Teranishi; Masahide Inoue
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2023-09-28
Filing date: 2023-09-28
Publication date: 2025-04-03
Anticipated expiration: 2026-03-28

Abstract

Embodiments of this application provide a stacked structure (300), a pixel driving circuit (111), a control circuit, a display module and an electronic device, the stacked structure (300) including: a first conductive layer (311), wherein the first conductive layer (311) comprises a first gate area (311-1); a first insulating layer (312) disposed on the first conductive layer (311); a first oxide layer (313) disposed on the first insulating layer (312), wherein the first oxide layer (313) comprises a first region of the first oxide layer (313-1) and the first region of the first oxide layer (313-1) comprises a first channel area (313-b), a first conductive source area (313-a) at one side of the first channel area (313-b) and a first conductive drain area (313-c) at the other side of the first channel area (313-b); a second insulating layer (314) disposed on the first oxide layer (313); a second conductive layer (315) disposed on the second insulating layer (314), wherein the second conductive layer (315) comprises a second gate area (315-1); a third insulating layer (316) disposed on the second conductive layer (315); a second oxide layer (317) disposed on the third insulating layer (316), wherein the second oxide layer (317) comprises a first region of the second oxide layer (317-1) and the first region of the second oxide layer (317-1) comprises a second channel area (317-b), a second conductive source area (317-a) at one side of the second channel area (317-b), and a second conductive drain area (317-c) at the other side of the second channel area (317-b), the second channel area (317-b) overlapping the first channel area (313-b); a fourth insulating layer (318) disposed on the second oxide layer (317); and a third conductive layer (319) disposed on the fourth insulating layer (318), wherein the third conductive layer (319) comprises a third gate area (319-1). According to the technical solution, the stacked structure (300), the pixel driving circuit (111), the control circuit, the display module and the electronic device involve simple structures and reduced layout areas.

Description

STACKED STRUCTURE, PIXEL DRIVING CIRCUIT, CONTROL CIRCUIT, DISPLAY MODULE AND ELECTRONIC DEVICE

TECHNICAL FIELD

Embodiments of the present application relate to the field of imaging technologies, and more specifically, to a stacked structure, a pixel driving circuit, a control circuit, a display module and an electronic device.

BACKGROUND

Display modules composed of only oxide TFTs (thin film transistor) are proposed to simplify the cross-section structure relative to a low temperature polycrystalline oxide (LTPO) , which combines both low temperature polycrystalline silicon (LTPS) TFTs and oxide TFTs (indium gallium zinc oxide, IGZO) to allow for more sufficient use of power by dynamically adjusting the refresh rate of the screen based on the content being displayed.

However, a protective layer is needed between two kinds of channel layers in the LTPO, which results in lower reliability and a bigger layout area.

SUMMARY

Embodiments of this application provide a stacked structure, a pixel driving circuit, a control circuit, a display module and an electronic device, which involve simple cross-section structure and small layout sizes.

According to a first aspect, a stacked structure is provided, including: a first conductive layer, wherein the first conductive layer comprises a first gate area; a first insulating layer disposed on the first conductive layer; a first oxide layer disposed on the first insulating layer, wherein the first oxide layer comprises a first region of the first oxide layer and the first region of the first oxide layer comprises a first channel area, a first conductive source area at one side of the first channel area and a first conductive drain area at the other side of the first channel area; a second insulating layer disposed on the first oxide layer; a second conductive layer disposed on the second insulating layer, wherein the second conductive layer comprises a second gate area; a third insulating layer disposed on the second conductive layer; a second oxide layer disposed on the third insulating layer, wherein the second oxide layer comprises a first region of the second oxide layer and the first region of the second oxide layer comprises a second channel area a second conductive source area at one side of the second channel area, and a second conductive drain area at the other side of the second channel area, the second channel area overlapping the first channel area; a fourth insulating layer disposed on the second oxide layer; and a third conductive layer disposed on the fourth insulating layer, wherein the third conductive layer comprises a third gate area.

In other word, the stacked structure includes: a first conductive layer, where the first conductive layer includes a first gate area; a first oxide layer with a first insulating layer disposed between the first oxide layer and the first conductive layer, where the first oxide layer includes a first channel area with a first conductive source area at one side of the first channel area and a first conductive drain area at the other side of the first channel area; a second conductive layer with a second insulating layer disposed between the second conductive layer and the first oxide layer, where the second conductive layer includes a second gate area; a second oxide layer with a third insulating layer between the second oxide layer and the second conductive layer, where the second oxide layer includes a second channel area with a second conductive source area at one side of the second channel area and a second conductive drain area at the other side of the second channel area, the second channel area overlapping the first channel area; and, a third conductive layer with a fourth insulating layer between the third conductive layer and the second oxide layer, where the third conductive layer includes a third gate area.

“Overlap” means that the two channel areas at least partly overlap in a layer thickness direction. For example, if the two channel areas completely overlap, a plane projection of one of the two channel areas falls into a range of that of the other of the two channel areas along the layer thickness direction; if the two channel areas partly overlap, the plane projection of any one of the two channel areas does not completely fall into a range of that of the other one of the two channel areas.

In this application, the two channel areas overlap each other to form a stacked structure which can provides high current density and a reduced layout area. In addition, with only oxide layers used as channel layers, extra protective layers are not needed and the display involves a simpler structure, resulting in a high reliability.

In one optional implementation, the first gate area, the first insulating layer, the first region of the first oxide layer, the second insulating layer, the second gate area, the third insulating layer, the first region of the second oxide layer, the fourth insulating layer and the third gate area form a first thin film transistor.

In one optional implementation, the first thin film transistor is used in a pixel driving circuit of a display module.

The first TFT can be used as a switching transistor in the pixel driving circuit. The stacked structure can provide a high driving ability and a reduced layout area.

In one optional implementation, at least three layers of the first conductive layer, the first oxide layer, the second conductive layer, the second oxide layer, the third conductive layer include at least three following corresponding regions, which are used as at least three terminals of a first capacitor: a third conductive region of the first conductive layer, a third conductive region of the first oxide layer, a third conductive region of the second conductive layer, a third conductive region of the second oxide layer and a third conductive region of the third conductive layer.

In this application, the at least three layers are used as terminals or plates of the first capacitor. At least two of the at least three layers are connected to function as a plate. For example, if five layers are used as part of the first capacity, four of these layers can be connected to function as one terminal and the last layer can function as the other terminal. Alternatively, three layers are connected to function as one terminal and the other two layers are connected to function as the other terminal.

The stacked structure of the first capacitor can save the layout area while changing the characteristic of the capacitor freely.

In one optional implementation, the second conductive source area contacts the first conductive source area to form a first contact pattern and the second conductive drain area contacts the first conductive drain area to form a second contact pattern by openings in the second insulating layer and the third insulating layer.

In this application, the source areas and the drain areas are connected so that the source areas can receive the same signal and the drain areas can receive the same signal.

In one optional implementation, the second oxide layer includes a second region of the second oxide layer and the second region of the second oxide layer includes a third channel area, a third conductive drain area at one side of the third channel area and a third conductive source area at the other side of the third channel area, the third conductive layer includes a fourth gate area, and the first oxide layer includes a second conductive region of the first oxide layer; the fourth gate area, the fourth insulating layer, the second region of the second oxide layer, the third insulating layer, the second insulating layer and the second conductive region of the first oxide layer form a second thin film transistor.

In this application, the second TFT is a driving TFT with a dual gate structure. The second oxide layer is used as a channel layer for the second TFT with the top gate formed by the third conductive layer and a bottom gate formed by the first oxide layer or the first conductive layer.

In one optional implementation, the second conductive region of the first oxide layer is connected with the second contact pattern by the first oxide layer.

In this application, the first TFT and the second TFT are connected via the first oxide layer rather than an extra metal layer to save the layout area.

In one optional implementation, the second oxide layer includes a second region of the second oxide layer and the second region of the second oxide layer includes a third channel area, a third conductive drain area at one side of the third channel area and a third conductive source area at the other side of the third channel area, the third conductive layer includes a fourth gate area, and the first conductive layer includes a second conductive region of the first conductive layer; the fourth gate area, the fourth insulating layer, the second region of the second oxide layer, the third insulating layer, the second insulating layer, the first insulating layer and the second conductive region of the first conductive layer form a second thin film transistor.

In one optional implementation, the second conductive region of the first conductive layer is connected with the second contact pattern by a third contact pattern, where the second oxide layer contact the second conductive region of the first conductive layer through openings in the first insulating layer, the second insulating layer and the third insulating layer to form the third contact pattern or the first oxide layer contacts the second conductive region of the first conductive layer through openings in the first insulating layer to form the third contact pattern..

In one optional implementation, the fourth gate area is connected with the third conductive source area.

The second TFT can be controlled via the bottom gate. The top gate is connected with the third conductive source area to avoid the dual gate function.

In one optional implementation, a sum of thicknesses of the second insulating layer and the third insulating layer is greater than a thickness of the fourth insulating layer or the first insulating layer.

When the second TFT is controlled from the bottom gate, a thickness of gate insulating layer is greater to provide a higher SS value for the second TFT. In addition, the gate insulating layer is thicker for the second TFT than the first TFT. When the second TFT is used as a driving transistor, the second TFT has a higher SS value than the first TFT.

In one optional implementation, the third conductive region of the first conductive layer overlaps the third channel area.

As the second TFT is controlled by the bottom gate, the bottom gate overlaps the third channel area to control the third channel area.

In one optional implementation, the first oxide layer includes a second region of the first oxide layer and the second region of the first oxide layer includes a fourth channel area, a fourth conductive drain area at one side of the fourth channel area and a fourth conductive source area at the other side of the fourth channel area, the first conductive layer includes a fifth gate area, and the second oxide layer includes a second conductive region of the second oxide layer; the fifth gate area, the first insulating layer, the second region of the first oxide layer, the second insulating layer, the third insulating layer and the second conductive region of the second oxide layer form a second thin film transistor.

In this application, the first oxide layer is used as a channel layer for the second TFT with the bottom gate formed by the first conductive layer and a top gate formed by the second oxide layer or the third conductive layer.

In one optional implementation, the second conductive region is connected with the second contact pattern by the second oxide layer.

The oxide pattern to connect the two TFTs can save the layout area.

In one optional implementation, the first oxide layer includes a second region of the first oxide layer and the second region of the first oxide layer includes a fourth channel area, a fourth conductive drain area at one side of the fourth channel area and a fourth conductive source area at the other side of the fourth channel area, the first conductive layer includes a fifth gate area, and the third conductive layer includes a second conductive region of the third conductive layer; the fifth gate area, the first insulating layer, the second region of the first oxide layer, the second insulating layer, the third insulating layer, the fourth insulating layer and the second conductive region of the third conductive layer form a second thin film transistor.

In one optional implementation, the second conductive region is connected with the second contact pattern.

In one optional implementation, the fifth gate area is connected with the fourth conductive source area.

The second TFT can be controlled via the top gate. The bottom gate is connected with the fourth conductive source area to avoid the dual gate function.

In one optional implementation, a sum of thicknesses of the second insulating layer and the third insulating layer is greater than a thickness of the first insulating layer or the fourth insulating layer.

When the second TFT is controlled from the top gate, a thickness of gate insulating layer is greater to provide a higher SS value for the second TFT. SS value is higher for the second TFT than the first TFT, providing a high driving performance in low grey scale when the second TFT is used as a driving TFT.

In one optional implementation, the first gate area, the first insulating layer, the first region of the first oxide layer, the second insulating layer and the second gate area form a third thin film transistor, and the second gate area, the third insulating layer, the first region of the second oxide layer, the fourth insulating layer and the third gate area form a fourth thin film transistor.

In this application, the stacked structure includes two TFTs and the source areas of the two TFTs are not connected to receive a different signal.

In one optional implementation, the second conductive source area contacts the first conductive source area to form a second contact pattern by openings in the second insulating layer and the third insulating layer.

In one optional implementation, the first thin film transistor is used in a control circuit of the display module.

According to a second aspect, a stacked structure is provided, including: a first conductive layer; a first insulating layer disposed on the first conductive layer; a first oxide layer disposed on the first insulating layer; a second insulating layer disposed on the first oxide layer; a second conductive layer disposed on the second insulating layer; a third insulating layer disposed on the second conductive layer; a second oxide layer disposed on the third insulating layer; a fourth insulating layer disposed on the second oxide layer; and a third conductive layer disposed on the fourth insulating layer; wherein at least three layers of the first conductive layer, the first oxide layer, the second conductive layer, the second oxide layer and the third conductive layer comprise at least three following corresponding regions, which are used as at least three terminals of a first capacitor of the stacked structure: a third conductive region of the first conductive layer, a third conductive region of the first oxide layer, a third conductive region of the second conductive layer, a third conductive region of the second oxide layer, and a third conductive region of the third conductive layer.

In other words, the stacked includes: a first conductive layer; a first oxide layer with a first insulating layer disposed between the first oxide layer and the first conductive layer; a second conductive layer with a second insulating layer disposed between the second conductive layer and the first oxide layer; a second oxide layer with a third insulating layer between the second oxide layer and the second conductive layer; a third conductive layer with a fourth insulating layer; where at least three layers of the first conductive layer, the first oxide layer, the second conductive layer, the second oxide layer, the third conductive layer include at least three following corresponding regions, which are used as at least three terminals of a first capacitor of the stacked structure: a third conductive region of the first conductive layer, a third conductive region of the first oxide layer, a third conductive region of the second conductive layer, a third conductive region of the second oxide layer, and a third conductive region of the third conductive layer.

According to a third aspect, a pixel driving circuit is provided, including the stacked structure in the first aspect or any optional implementation of the first aspect or in the second aspect.

According to a fourth aspect, a control circuit is provided, including: a first conductive layer, wherein the first conductive layer comprises a first gate area; a first insulating layer disposed on the first conductive layer; a first oxide layer disposed on the first insulating layer, wherein the first oxide layer comprises a first channel area, a first conductive source area at one side of the first channel area and a first conductive drain area at the other side of the first channel area; a second insulating layer disposed on the first oxide layer; a second conductive layer disposed on the second insulating layer, wherein the second conductive layer comprises a second gate area; a third insulating layer disposed on the second conductive layer; a second oxide layer disposed on the third insulating layer, wherein the second oxide layer comprises a second channel area a second conductive source area at one side of the second channel area, and a second conductive drain area at the other side of the second channel area, the second channel area overlapping the first channel area; a fourth insulating layer disposed on the second oxide layer; and a third conductive layer disposed on the fourth insulating layer, wherein the third conductive layer comprises a third gate area.

In one optional implementation, the first gate area, the first insulating layer, the first channel area, the first conductive source area, the first conductive drain area, the second insulating layer, the second gate area, the third insulating layer, the second channel area, the second conductive source area, the second conductive drain area, the fourth insulating layer and the third gate area form a thin film transistor.

In one optional implementation, the second conductive source area contacts the first conductive source area to form a first contact pattern, and the second conductive drain area contacts the first conductive drain area to form a second contact pattern by openings in the second insulating layer and the third insulating layer.

In one optional implementation, the control circuit is a GOA circuit.

According to a fifth aspect, a display module is provided, including: a substrate; the pixel driving circuit in the third aspect and/or the control circuit in the fourth aspect or any optional implementation of the fourth aspect, wherein the first conductive layer is disposed on the substrate.

According to a sixth aspect, an electronic device is provided, the electronic device includes the display module in the fifth aspect.

DESCRIPTION OF DRAWINGS

Fig. 1 is a schematic diagram of a display according to an embodiment of this application.

Fig. 2 is a schematic diagram of a stacked structure according to an embodiment of this application.

Fig. 3 is a schematic diagram of a pixel driving circuit according to an embodiment of this application.

Fig 4 is a cross-sectional side view of electronic components included in a dashed box 210 of Fig. 3 according to an embodiment of this application.

Fig. 5 is a voltage-current transform characteristic curve corresponding to different driving modes for a second TFT 330-1 according to an embodiment of this application.

Fig 6 is other cross-sectional side views of electronic components included in a dashed box 210 of Fig. 3 according to an embodiment of this application.

Fig. 7 is a schematic diagram of a pixel driving circuit according to an embodiment of this application.

Fig. 8 is a cross-sectional side view of electronic components included in a dashed box 610 of Fig. 6 according to an embodiment of this application.

Fig. 9 shows examples of possible structures according to an embodiment of this application.

Fig. 10 shows a method of manufacturing the structures shown in Fig. 2 and Fig. 6 according to an embodiment of this application.

Fig. 11 shows conceptual graphs of a control circuit in a display according to an embodiment of this application.

Fig. 12 shows an example of an output buffer circuit according to an embodiment of this application.

Fig. 13 shows a cross-section view of an output buffer circuit according to an embodiment of this application.

Fig. 14 shows a schematic diagram of a display module according to an embodiment of this application.

DESCRIPTION OF EMBODIMENTS

The following describes the technical solutions in this application with reference to the accompanying drawings.

Terms used in the following embodiments of this application are merely intended to describe specific embodiments, but are not intended to limit this application. Terms “one” , “a” , “the” , “the foregoing” , “this” , and “the one” of singular forms used in this specification and the appended claims of this application are also intended to include plural forms like “one or more” , unless otherwise specified in the context clearly. It should be further understood that, in the following embodiments of this application, “at least one” or “one or more” means one, two, or more. The term “and/or” describes an association relationship between associated objects and represents that three relationships may exist. For example, A and/or B may represent the following three cases: only A exists, both A and B exist, and only B exists. A and B may be in a singular or plural form. The character “/” generally indicates an “or” relationship between the associated objects.

Reference to “an embodiment” , “some embodiments” , or the like described in this specification indicates that one or more embodiments of this application include a specific feature, structure, or characteristic described with reference to the embodiments. Therefore, in this specification, statements, such as “in an embodiment” , “in some embodiments” , “in some other embodiments” , and “in other embodiments” , that appear at different places do not necessarily mean referring to the same embodiment, instead, but mean “one or more but not all of the embodiments” , unless otherwise specified. The terms “include” , “comprise” , “have” , and their variants all mean “include but are not limited to” , unless otherwise specified.

In the description of the present application, it should be noted that, unless otherwise stated, “multiple” means two or more. Further, the orientations or positional relationships indicated by the terms “upper” , “lower” , “left” , “right” , “inside” and/or “outside” are only used for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation or must be constructed and operated in a specific orientation, which therefore cannot be understood as a limitation of the present application. In addition, the terms “first” , “second” , “third” and the like are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance. “Vertical” is not strictly vertical, but within an allowable range of error. “Parallel” is not strictly parallel, but within an allowable range of error.

The orientation words appearing in the following description are all directions shown in the figures, and do not limit the specific structure of the present application. In the description of the present application, it should also be noted that, unless otherwise clearly defined and limited, the terms “installed” , “linked” , and “connected” should be understood in a broad sense. For example, it may be a fixed connection, a detachable connection, or an integral connection; it may be a direct connection, or an indirect connection through an intermediate medium. For those of ordinary skill in the art, the specific meaning of the above-mentioned terms in the present application can be understood according to specific circumstances.

The display module in the present application includes a display. The display includes but is not limited to a light-emitting diode (LED) display, an organic light-emitting diode (OLED) display, an active-matrix organic light-emitting diode (AMOLED) display, a nanorod LED (nano-LED or nanoLED) display or the like.

The display may be a flat panel display, a flexible display, or a micro-electromechanical system (MEMS) -based display, and the present application is not limited thereto.

Fig. 1 is a schematic diagram of a top view of a display 100 according to an embodiment of this application.

As shown in Fig. 1, the display 100 includes a display area 110 and a periphery area 120 arranged on a substrate.

The display area 110 includes a plurality of pixel driving circuits 111 arranged in a matrix. The periphery area 120 includes a control circuit and the control circuit includes a gate driver on array (GOA) circuit 121 and a data driver circuit 122 which provide a scan signal GN and a data signal DATA respectively. The pixel driving circuits 111 include a matrix in which M rows and N columns are arranged, and a pixel driving circuit 111 is provided at each of the cross points of rows and columns (N and M are integers) . The pixel driving circuits 111 are provided with N DATA lines (Y1 to Yn) and M GATE lines (X1 to Xm) and these DATA lines and GATE lines are orthogonally arranged with each other. Each pixel driving circuit 111 is controlled by the GOA circuit 121 and the data driver circuit 122. For example, the pixel driving circuit X1Y1, which is at the cross point of a DATA line Y1 and a GATA line X1, displays colors based on an electrical signal provided by X1 and an electrical signal provided by Y1.

Fig. 2 is a cross-sectional side view of a stacked structure 300 according to an embodiment of this application.

As shown in Fig. 2, the stacked structure 300 includes: a first conductive layer 311, wherein the first conductive layer 311 comprises a first gate area 311-1; a first insulating layer 312 disposed on the first conductive layer 311; a first oxide layer 313 disposed on the first insulating layer 312, wherein the first oxide layer 313 comprises a first region of the first oxide layer 313-1 and the first region of the first oxide layer 313-1 comprises a first channel area 313-b, a first conductive source area 313-a at one side of the first channel area 313-b and a first conductive drain area 313-c at the other side of the first channel area 313-b; a second insulating layer 314 disposed on the first oxide layer 313; a second conductive layer 315 disposed on the second insulating layer 314, wherein the second conductive layer 315 comprises a second gate area 315-1; a third insulating layer 316 disposed on the second conductive layer 315; a second oxide layer 317 disposed on the third insulating layer 316, wherein the second oxide layer 317 comprises a first region of the second oxide layer 317-1 and the first region of the second oxide layer 317-1 comprises a second channel area 317-b a second conductive source area 317-a at one side of the second channel area 317-b, and a second conductive drain area 317-c at the other side of the second channel area 317-b, the second channel area 317-b overlapping the first channel area 313-b; a fourth insulating layer 318 disposed on the second oxide layer 317; and a third conductive layer 319 disposed on the fourth insulating layer 318, wherein the third conductive layer 319 comprises a third gate area 319-1.

The stacked structure 300 in Fig. 2 has two channel areas overlapped. The first gate area 311-1, the first insulating layer 312, the first region of the first oxide layer 313-1 and the second gate area 315-1 form a first sub-TFT, and the second gate area 315-1, the third insulating layer 316, the first region of the second oxide layer 317-1, the fourth insulating layer 318 and the third gate area 319-1 form a second sub-TFT. The first sub-TFT and the second sub-TFT are dual gate TFTs with two of the first gate area-311-1, the second gate area 315-1 and the third gate area 319-1 being the gates of the two sub-TFTs respectively.

As the two channel areas overlap, current density and carrier mobility from the cross-section view increases and a reduced layout area is obtained. In addition, channel layers are all oxide layers and no protective layer is needed, and a further reduced layout area compared with LTPO is possible.

Understandably, with different driven modes (top gate driven, bottom gate driven and dual gate driven) , the gate insulating layer can be different, and the stacked TFT will have different electrical properties or characteristics.

The stacked structure 300 shown in Fig. 2 can be used in the pixel driving circuit 111 and/or the control circuit (for example, the GOA circuit 121) . Several examples of pixel driving circuits 111 or a GOA circuit 121 in a display module including the stacked structure 300 in Fig. 2 will be introduced in the following embodiments.

Fig. 3 shows a schematic diagram of a pixel driving circuit 111 in the display 100 according to an embodiment of this application. The pixel driving circuit 111 includes two transistors (M1, M2) and one capacity (C1) , where the transistor M1 works as a switching transistor the transistor M2 works as a driving transistor and the capacitor C1 is a storage capacitor. The two transistors are thin film transistors (TFTs) . Gate electrodes of the switching transistor M1 are connected with the GATE line to receive the scan signal GN. The scan signal GN is a pulse signal that controls the on/off state of the switching transistor M1 periodically. A source electrode of the switching transistor M1 is connected with the DATA line to receive the data signal DATA and a drain electrode of the switching transistor M1 is connected with a first gate electrode of the driving transistor M2. A drain electrode of the driving transistor M2 is connected with a first power source PVDD to receive a first voltage VDD (ahigh voltage) and a source electrode of the driving transistor M2 is connected with an anode of an emitting element E1 such as an OLED. A first terminal T1 of the capacitor C1 is connected with the drain electrode of the switching transistor M1 and the first gate electrode of the driving transistor M2, and a second terminal T2 of the storage capacitor C1 is connected with the source electrode of the driving transistor M2. The second gate of the driving transistor and the source electrode are short circuited by n2 so that the transistor functioning on the second gate electrode side can be turned off (Vgs = 0) , avoiding the unintended dual gate operation. A cathode of the emitting element E1 is connected with a second power source PVSS to receive a second voltage VSS (alow voltage, a grounded voltage for example) .

A driving manner of the pixel driving circuit 111 is to control bright and dark (agreyscale) of a pixel by the two TFTs and the storage capacitor C1. When the scan signal GN is applied by the GATE line to turn on the switching TFT M1, the data signal DATA inputted through the DATA line by the data driver circuit 122 charges the storage capacitor C1 through the switching TFT M1, so as to store the data signal in the storage capacitor C1. The data signal that is stored controls a conduction degree of the driving TFT M2, so as to control a value of a current that runs through the driving TFT M2 and drives the emitting element E1 to emit light.

A first TFT 310, a second TFT 330-1 and a capacity 350 correspond to the switching transistor M1, driving transistor M2 and storage capacity C1 in Fig. 3 respectively. The first TFT 310 has a stacked structure as shown in Fig. 2.

Different layers of the first TFT 310 can refer to Fig. 2. For the first sub-TFT or the lower sub-TFT, the first gate area 311-1 functions as a bottom gate and the second gate area 315-1 functions as a top gate. For the second sub-TFT or the upper sub-TFT, the second gate area 315-1 functions as a bottom gate and the third gate area 319-1 functions as a top gate.

Each of the two sub-TFTs of the first TFT 310 can be dual gate driven or top gate driven. For the dual gate driven mode, control terminals for controlling switching of the first TFT 310 are the first gate area 311-1, the second gate area 315-1 and the third gate area 319-1. The fourth insulating layer 318 functions as a gate insulating layer to the third gate area 319-1, the first insulating layer 312 functions as a gate insulating layer to the first gate area 311-1, and the second insulating layer 314 and the third insulating layer 316 function as gate insulating layers to the second gate area 315-1. For the top gate driven mode, the control terminals for controlling switching of the first TFT 310 are the second gate area 315-1 and the third gate area 319-1, with the fourth insulating layer 318 and the second insulating layer 314 being gate insulating layers respectively.

Thus, the first channel area 313-b overlaps the second gate area 315-1 and the second channel area 317-b overlaps the third gate area 319-1. In this application, the wording “overlap” means that a gate area faces a corresponding channel area in the layer thickness direction, for example, when projected onto a plane along the layer thickness direction (the plane is perpendicular to the layer thickness direction) , a projection of the gate area and a projection of the corresponding channel area have an overlap area. In one example, the projection of the gate area falls into a range of the projection of the corresponding channel area. In another example, the projection of the channel area falls into a range of the projection of the corresponding gate area. In another example, the projection of the gate area and the projection of the corresponding channel area are partly overlapped.

The conductive source area or conductive drain area of the first oxide layer 313 or the second oxide layer 317 may be doped with high concentration impurity to be conductive.

The conductive source areas 313-a and 317-a and the conductive drain areas 313-c and 317-c of the two oxide layers 313 and 317 are connected by a first contact pattern 317-4 and a second contact pattern 317-5 respectively. Thus, the two sub-TTFs can be seen as one stacked TFT.

When the structure in Fig. 4 is used in a display module, the display module also includes a fourth conductive layer 321 with a fifth insulating layer 320 disposed between the fourth conductive layer 321 and the third conductive layer 319. The fourth conductive layer 321 is used to set the source/drain electrode and can also be called as a S/D metal layer.

A source electrode is arranged on the fifth insulating layer 320 to receive the data signal DATA from the DATA line for the first TFT 310 as shown in Fig. 3. The source electrode is connected with the first contact pattern 317-4 by openings in the insulating layers 314, 316, 318 and 320, which is not shown in Fig. 4. The first gate area 311-1, the second gate area 315-1 and the third gate area 319-1 are connected to the GN line to receive the GN signal, which is used to periodically turn on the first TFT 310.

The first TFT 310 has two oxide layers forming two channels, which increases current density and corresponds to an increase in carrier mobility from the cross-section view. The first TFT 310 as the switching transistor has a high driving capability owing to the stacked structure shown above. In addition, the connection of the two stacked sub-TFTs by the contact patterns 317-4 and 317-5 can save the layout area compared with traditional connecting methods such as connecting by an additional metal layer.

The second TFT 330-1 functioning as the driving transistor is also a dual gate TFT. A fourth gate area 319-21 of the third conductive layer 319, the fourth insulating layer 318, a second region of the second oxide layer 317-21, the third insulating layer 316, the second insulating layer 314 and a second conductive region of the first oxide layer 313-21 form the second TFT 330-1, where the fourth gate area 319-21 is part of the third conductive layer 319, the second region of the second oxide layer 317-21 is part of the second oxide layer 317 and the second region of the second oxide layer 317-21 includes a third channel area 317-e1, a third conductive drain area 317-d1 at one side of the third channel area 317-e1 and a third conductive source area 317-f1 at the other side of the third channel area 317-e1. The second conductive region of the first oxide layer 313-21, the third conductive drain area 317-d1 and the third conductive source area 317-f1 are processed by means of doping to be conductive.

The second conductive region of the first oxide layer 313-21 functions as a bottom gate and the fourth gate area 319-21 functions as a top gate of the second TFT 330-1. The control terminal of the second TFT 330-1 is the bottom gate 313-21, where the insulating layers 314 and 316 are used as gate insulating layers. The third conductive source area 317-f1 is connected with the fourth gate area 319-21 by part of the fifth conductive layer 321 between contact patterns 321-1 and 321-2 (corresponding to n2 in Fig. 3) . The connection is meant to the turn off TFT function on the top gate side and avoid the unintended dual gate operation.

A drain electrode disposed on the fifth insulating layer 320 is connected with the third conductive drain area 317-d1 through openings in the insulating layers 318 and 320 to receive the voltage VDD and the emitting element is connected with the third conductive source area 317-f1, which is not shown in Fig. 4. The second conductive region of the first oxide layer 313-21 (bottom gate of the second TFT 330-1) is connected with the second contact pattern 317-5 of the first TFT 310 by the first oxide layer 313, so that the first TFT 310 can control the on/off state of the second TFT 330-1.

A capacitor 350 is formed by a third conductive region of the first conductive layer 311-3, a third conductive region of the first oxide layer 313-3 and a third conductive region of the second oxide layer 317-3, the first insulating layer 312, the second insulating layer 314 and the third insulating layer 316. The third conductive regions 311-3, 313-3 and 317-3 are part of the first conductive layer 311, the first oxide layer 313 and the second oxide layer 317, respectively. The third conductive regions are used as terminals or plates of the capacitor 350 to form a stacked capacitor. The third conductive region of the second oxide layer 317-3 is connected with the third conductive region of the first conductive layer 311-3 by part of the fourth conductive layer between contact patterns 321-2 and 321-3 to be used as the second terminal T2 as shown in Fig. 3. The second terminal T2 is connected with the top gate 319-21 and the third source area 317-f1 of the second TFT 330-1. The third conductive region of the first oxide layer 313-3 is connected with the second contact pattern 317-5 (drain) of the first TFT 310 and the bottom gate 313-21 of the second TFT 330-1 to be used as the first terminal T1 as shown in Fig. 3.

The third conductive region of the first conductive layer 311-3 is prolonged to overlap the third channel area 317-e1 of the second TFT 330-1, thus part of the capacitor 350 is imposed beside the second TFT 330-1. The stacked structure and the prolonging of terminals of the capacitor 350 can change the capacitance value of the capacitor 350 and save the layout area, so that the property of the pixel driving circuit 111 shown in Fig. 4 can be finely adjusted to meet certain demands.

When the second TFT 330-1 is driven by the top gate (319-21) , the insulating layer 318 functions as a gate insulating layer. When the second TFT 330-1 is driven by the bottom gate (313-21) , the insulating layers 314 and 316 function as a gate insulating layer. The thickness of the insulating layer is larger in the bottom gate driven mode than in the top gate driven mode, and a higher subthreshold swing (SS) value is expected. In this application, the second TFT 330-1 can be driven by the bottom gate 313-21 to give the driving transistor a higher SS value. Fig. 5 shows a voltage-current transform characteristic curve corresponding to different driving modes for the second TFT 330-1. It is obvious that the bottom gate driven mode shows a higher SS value.

The gate insulating layer of the first TFT 310 is the fourth insulating layer 318, the second insulating layer 314, the first insulating layer 312 or the third insulating layer 316 and the gate insulating layer of the TFT 330-1 is the second insulating layer 314 and the third insulating layer 316. In this application, the thickness of the fourth insulating layer 318 or the second insulating layer 314 or the first insulating layer 312 or the third insulating layer 316 is thinner than a sum of thicknesses of the second insulating layer 314 and the third insulating layer 316.

Since the gate insulating layer of the switching TFT 310 is thinner than the gate insulating layer of the driving TFT 330-1, an electric field is easily applied to the channel areas in the first oxide layer 313 or the second oxide layer 317, the on current can be increased and the switching characteristics of the switching TFT 310 can be improved. In addition, the stacked structure of the first TFT 310 by two oxide layers improves the carrier mobility and results in a reduction in the layout area.

In other aspects, the gate insulating layer of the driving TFT 330-1 is thicker than the gate insulating layer of the switching TFT 310, an electric field is less likely applied to the channel area in the second oxide layer 317, and the on current can be reduced. In addition, with the high SS value, the current change in low grey scale can be reduced, improving the display uniformity of the display module. In addition, a large amount of current can be suppressed from flowing through the driving TFT 330-1, it is possible to suppress a decrease in liability due to thermal degradation.

Fig 6 shows other three cross-sectional side views of electronic components included in a dashed box 210 of Fig. 3 according to an embodiment of this application.

As shown in Fig. 6 (a) , different layers of the switching TFT 310 are the same as that in Fig. 2, details can refer to Fig. 2. For the driving TFT 330-2, it differs from the driving TFT 330-1 in Fig. 4 in that instead of using the second conductive region of the first oxide layer 313-21, and it uses a second conductive region of the first conductive layer 311-21 as the bottom gate. The second TFT 330-2 includes: a fourth gate area 319-21, the fourth insulating layer 318, a second region of the second oxide layer 317-21, the third insulating layer 316, the second insulating layer 314, the first insulating layer 312 and the second conductive region of the first conductive layer 311-21, where the second region of the second oxide layer 317-21 includes a third channel area 317-e1, a third conductive source area 317-f1 and a third conductive drain area 317-d1. The third channel area 317-e1 is disposed between the third conductive source area 317-f1 and the third conductive drain area 317-d1.

The connection of the two TFTs, the second TFT 330-2 and the capacitor 350, structure of capacitor 350 also changes accordingly. The second contact pattern 317-5 is connected with the bottom gate 311-21 of the second TFT 330-2 by a third contact pattern 317-6 and the second oxide layer 317 contacts the bottom gate 311-21 through openings in the third insulating layer 316, the second insulating layer 314 and the first insulating layer 312. Although not shown in Fig. 6 (a) , the second contact pattern 317-6 can contact the bottom gate 311-21 of the second TFT 330-2 by a contact pattern formed by the first oxide layer 313 and the first oxide layer 313 contact the bottom gate 311-21 through openings in the first insulating layer 312 to form the second contact pattern.

The control terminal of the second TFT 330-2 is the bottom gate 311-21 and the first insulating layer 312, the second insulating layer 314 and the third insulating layer 316 as a whole function as a gate insulating layer. The top gate 319-21 is also connected with the third conductive source area 317-f1 of the second TFT 330-2 by part of the fourth conductive layer between contact patterns 321-4 and 321-5 (corresponding to n2 in Fig. 3) . As the gate insulating layer of the second TFT 330-2 is even thicker than that shown in Fig. 4, an even higher SS value is expected for this structure.

The capacitor 350 is a stacked capacitor formed by a third conductive region of the first conductive layer 311-3, a third conductive region of the first oxide layer 313-3, a third conductive region of the second conductive layer 315-3 and a third conductive region of the second oxide layer 317-3, the first insulating layer 312, the second insulating layer 314 and the third insulating layer 316. The third conductive region of the first oxide layer 313-3 is connected with the third conductive region of the second oxide layer 317-3 by a contact pattern 317-7 to serve as the second terminal T2 shown in Fig. 3. The second terminal T2 is connected with the third conductive source area 317-f1 of the second TFT 330-2. The third conductive region of the second conductive layer 315-3 is connected with the third conductive region of the first conductive layer 311-3 by part of the fourth conductive layer 321 between contact patterns 321-6 and 321-7 to serve as the first terminal T1 shown in Fig. 3. The first terminal T1 is connected with the second contact pattern 317-5.

For the electrode connection to different signals, the description can be referred to and this content are omitted for brevity.

As shown in Fig. 6 (b) , layers of the switching TFT 310 are the same as that in Fig. 2. For the driving TFT 330-3, it differs from the driving TFT 330-1 in Fig. 4 or the driving TFT 330-2 in Fig. 6 (a) in that a fourth source area 313-f2, a fourth drain area 313-d2 and a fourth channel area 313-e2 are disposed on the first oxide layer 313 instead of the second oxide layer 317. In addition, the control terminal of the second TFT 330-3 is the top gate 317-22 rather than the bottom gate 311-22. Accordingly, the first TFT 310 is connected with the top gate 317-22 to control the on/off of the second TFT 330-3 and the bottom gate 311-22 is connected with the fourth source area 313-f2 to avoid the dual gate operation.

The second TFT 330-3 includes: a fifth gate area 311-22 of the first conductive layer 311, the first insulating layer 312, a second region of the first oxide layer 313-22, the second insulating layer 314, the third insulating layer 316 and a second conductive region of the second oxide layer 317-22 and the second region of the first oxide layer 313-22 includes a fourth channel area 313-e2, a fourth conductive drain area 313-d2 and a fourth conductive source area 313-f2, where the fourth conductive drain area 313-d2 and the fourth conductive source area 313-f2 are disposed at two sides of the fourth channel area 313-e2. The second conductive region of the second oxide layer 317-22 is used as the top gate and the fifth gate area 311-22 is used as the bottom gate.

The capacitor 350 is a stacked capacitor formed by a third conductive region of the first conductive layer 311-3, a third conductive region of the first oxide layer 313-3, a third conductive region of the second conductive layer 315-3, a third conductive region of the second oxide layer 317-3 and a third conductive region of the third conductive layer 319-3, the first insulating layer 312, the second insulating layer 314, the third insulating layer 316 and the fourth insulating layer 318. The third conductive region of the third conductive layer 319-3 is connected with the third conductive region of the first oxide layer 313-3 and the third conductive region of the first conductive layer 311-3 to be used as the second terminal T2 shown in Fig. 3. The connection of these conductive layers is achieved by part of the fourth conductive layer 321 between contact patterns 321-8, 321-9, 321-10. The third conductive region of the second conductive layer 315-3 is connected with the third conductive region of the second oxide layer 317-3 to serve as the first terminal T1 shown in Fig. 3.

The control terminal of the second TFT 330-3 is the top gate 317-22 and the insulating layer 314 and insulating layer 316 as a whole are used as gate insulating layers. The bottom gate 311-22 and the fourth source area 313-f2 are connected by part of the fourth conductive layer 321 between contact patterns 321-9 and 321-10 to avoid the dual gate operation.

In this application, a thickness of the fourth insulating layer 318 or the first insulating layer 312 is smaller than a sum of a thicknesses of the second insulating layer 314 and the third insulating layer 316. As a result, the gate insulating layer of the first TFT 310 is thinner than that of the second TFT 330-3. The pixel driving circuit can show high electrical properties.

As shown in Fig. 6 (c) , layers of the switching TFT 310 are the same as that in Fig. 2. For the driving TFT 330-4, it differs from the driving TFT 330-3 in Fig. 6 (b) in that instead of using the second conductive region of the second oxide layer 317-22, and it uses a second conductive region 319-22 of the third conductive layer 319-22 as a top gate.

The second TFT 330-4 includes: a fifth gate area 311-22, the first insulating layer 312, a second region of the first oxide layer 313-22, the second insulating layer 314, the third insulating layer 316, the fourth insulating layer 318 and the second conductive region of the third conductive layer 319-22, where the second region of the first oxide layer 313-22 includes a fourth channel area 313-e2, a fourth conductive source area 313-f2 at one side of the fourth channel area 313-e2 and a fourth conductive drain area 313-d2 at the other side of the fourth channel area 313-e2, and the second region of the first oxide layer 313-22 is part of the first oxide layer 313.

The capacitor 350 is a stacked capacitor formed by a third conductive region of the first conductive layer 311-3, a third conductive region of the first oxide layer 313-3, a third conductive region of the second conductive layer 315-3, a third conductive region of the second oxide layer 317-3 and a third conductive region of the third conductive layer 319-3, the first insulating layer 312, the second insulating layer 314, the third insulating layer 316 and the fourth insulating layer 318. The third conductive region of the first conductive layer 311-3, the third conductive region of the first oxide layer 313-3 and the third conductive region of the second oxide layer 317-3 are connected to be used as a second terminal T2 as shown in Fig. 3. The third conductive region of the second conductive layer 315-3 and the third conductive region of the third conductive layer 319-3 are connected to be used as a first terminal T1 as shown Fig. 3.

The first TFT 310 is connected with the top gate 319-22 of the second TFT 330-4 by part of the fourth conductive layer 321 between contact patterns 321-11 and 321-12. The control terminal of the second TFT 330-4 is the top gate 319-22 and the second insulating layer 314, the third insulating layer 316 and the fourth insulating layer 318 as a whole are used as the gate insulating layer of the second TFT 330-4. The bottom gate 311-22 is connected with the fourth drain area 313-f2 by part of the fourth conductive layer 321 between contact patterns 321-14 and 321-15 to avoid the dual gate operation.

Fig. 7 shows another pixel driving circuit 111 according to an embodiment of this application. As shown in Fig. 7, the pixel driving circuit 111 includes three transistors (M1, M2, M3) and one capacity (C1) , where the transistors M1 and M3 work as switching transistors, the transistor M2 works as a driving transistor, and the capacitor C1 is a storage capacitor. The three transistors are dual gate thin film transistors (TFTs) . A first gate electrode of the switching TFT M1 is connected with the gate line to receive the scan signal GN. A second gate electrode of the switching TFT M1 is connected with the VBSM line to receive a reference signal VBSM. A source electrode of the switching transistor M1 is connected with the DATA line to receive the data signal DATA and the drain electrode of the switching TFT M1 is connected with a first gate electrode of the driving TFT M2. A gate of the TFT M3 is connected with the REF line to receive the signal REF. A source electrode of the TFT M3 is connected with the VREF line to receive a reference signal VREF and a drain electrode of the TFT M3 is connected with the first gate of the transistor M2. A drain electrode of the driving transistor M2 is connected with a first power source PVDD to receive a first voltage VDD (ahigh voltage) and the source electrode of the driving TFT M2 is connected with the anode of the emitting element E1 such as an OLED. One terminal of the capacitor C1 is connected with the drain electrode of the switching TFT M1 and a first gate electrode of the driving TFT M2, and the other terminal of the storage capacitor C1 is connected with the source electrode of the driving TFT M2. The second gate of the driving transistor M2 and the source electrode are short circuited by n2 so that the transistor functioning on the second gate electrode side can be turned off (gate bias voltage Vgs = 0) , avoiding the unintended dual gate operation. A cathode of the emitting element E1 is connected with a second power source PVSS to receive a second voltage VSS (alow voltage, a grounded voltage for example) .

Fig. 8 is a cross-sectional side view of electronic components included in a dashed box 710 of Fig. 7 according to an embodiment of this application.

The cross-section view in Fig. 8 is similar to the cross-section view shown in Fig. 4, but the conductive source areas 313-a and 317-a of the third TFT 301 and the fourth TFT 303 are not connected with each other by a contact pattern. The gate areas 311-1, 315-1 and 319-1 do not receive the same signal but the gate area 315-1 is connected with the VBSM line to receive a VBSM signal. The source area 313-a is connected with the DATA line to receive a signal DATA and the source area 317-a is connected with the VREF line to receive a signal VREF.

The third TFT 301 includes: a first gate area 311-1, the first insulating layer 312, a first region of the first oxide layer 313-1, the second insulating layer 314, and the second gate area 315-1, where the first region of the first oxide layer 313-1 is part of the first oxide layer 313 and includes: a source area 313-a, a channel area 313-b and a drain area 313-c. The fourth TFT 303 includes: the second gate area 315-1, the third insulating layer 316, a first region of the second oxide layer 317-1, the fourth insulating layer 318, and the third gate area 319-1, where the first region of the second oxide layer 317-1 is part of the second oxide layer 317 and the first region of the second oxide layer 317-1 includes: a source area 317-a, a channel area 317-b and a drain area 317-c. Structure of the driving transistor 330 and capacitor 350 are the same as those shown in Fig. 4 (330-1) .

Optionally, the structures of the driving TFT 330 and the capacitor 350 may be changed like those shown in Fig. 6 (a) to Fig. 6 (c) , details can refer to Fig. 6 (a) to Fig. 6 (c) .

In this application, the cross-section view of part of the pixel driving circuit 111 and the pixel driving circuit 111 itself can have adaptations to different conditions or cases, for example, the numbers of transistors and/or capacitors used in the pixel driving circuit 111, the driven mode of different transistors. In addition, the switching transistor, the driving transistor and/or capacitors can have other structures or be combined in a different way using only conductive layers, oxide layers and insulating layers. Fig. 9 shows examples of possible structure according to an embodiment of this application.

Fig. 9 (a) shows a transistor with at least one conductive layer used as gate area. The transistor includes: a first conductive layer 311, a first insulating layer 312, a second insulating layer 314, a third insulating layer 316, a second oxide layer 317, a fourth insulating layer 318, and a third conductive layer 319. The transistor can be top gate driven, bottom gate driven or dual gate driven in different cases. When this transistor is bottom gate driven, the insulating layers 314, 316 and 318 function as the gate insulating layer, which may provide a high SS and improved display quality when used as driving transistors owing to the thickness of these three layers.

Optionally, the second oxide layer 317 can be replaced with the first oxide layer 313 to set the channel area, the conductive source area or the conductive drain area. The first oxide layer 313 is disposed between the first insulating layer 312 and the second insulating layer 314.

Fig. 9 (b) shows a transistor stacked with a capacitor. The transistor includes: a second oxide layer 317 with a channel area, a conductive source area and a conductive drain area disposed at two sides of the channel area, a fourth insulating layer 318, and a third conductive layer 319. The capacity includes: a first conductive layer 311, a first insulating layer 312, and a first oxide layer 313, where the first oxide layer 313 is processed to be conductive to be used as a plate of the capacity. Insulating layers 314 and 316 are used to insulate the transistor from the capacitor.

Optionally, the transistor further includes: the first oxide layer 313, the second insulating layer 314 and the third insulating layer 316, where the first oxide layer 313 functions as a bottom gate for the dual gate transistor. In this case, one plate of the capacitor is connected with the bottom gate of the transistor.

Optionally, the second oxide layer 317 can be processed to be conductive to be used as a plate for a capacitor and the other plate of the capacitor is the conductive layer 319. The first oxide layer 313, the second oxide layer 317, the first conductive layer 311, the first insulating layer 312, the second insulating layer 314 and the third insulating layer 316 form the transistor, where the second oxide layer 317 includes a conductive source area, a channel area and a conductive drain area.

Fig. 9 (c) shows a transistor and a stacked capacitor. The transistor includes: a conductive layer 311, a first insulating layer 312, a first oxide layer 313, a second insulating layer 314, a second conductive layer 315, and a third insulating layer 316. The first conductive layer 311 and/or the second conductive layer 315 is used as a gate of the transistor. The first oxide layer 313 is partly processed to be conductive to form a stacked capacitor with the conductive layer 311 and the conductive layer 315. The stacked capacitor includes two sub-capacitors, sub-capacitor 1 includes: the first conductive layer 311, the first insulating layer 312 and the first oxide layer 313, and sub-capacitor 2 includes: the first oxide layer 313, the second insulating layer 314 and the second conductive layer 315.

Fig. 9 (d) shows a stacked capacitor including three sub-capacitors. Oxide layers 313 and 317 are processed to be conductive to form stacked capacitors. Sub-capacitor 1 includes: a first conductive layer 311, a first insulating layer 312 and a first oxide layer 313. Sub-capacitor 2 includes: the first oxide layer 313, a second insulating layer 314 and a second conductive layer 315. Sub-capacitor 3 includes: a second conductive layer 315, a third insulating layer 316 and a second oxide layer 317.

In addition, with the area of the oxide layers processed to be conductive, the contact between two oxide layers (which can be seen in Fig. 4) , the contact between oxide layers and conductive layers can possibly to replace an additional metal layer, which can reduce the layout area of the display. Fig. 9 (e) and Fig. 9 (f) show two structures to achieve contact between an oxide layer and a conductive layer.

Fig. 9 (e) shows a transistor with a second oxide layer 317 processed to be conductive to be used as the top gate and the first conductive 311 used as the bottom gate. The first oxide layer includes a conductive source area, a conductive drain area and a channel area.

In Fig. 9 (f) , contact between the second oxide layer 317 and first conductive layer 311 is achieved by openings in the insulating layers 312, 314 and 316. In Fig. 9 (g) , contact between the second oxide layer 317 and second conductive layer 315 is achieved by an opening in the third insulating layer 316.

Fig. 9 only shows several possible structures provided by this application, there may be other possible structures with patterned conductive layers and oxide layers. In addition, there may be more or less conductive layers and/or oxide layers and/or insulating layers than those have been shown in Fig. 2, Fig. 4, Fig. 6 and Fig. 8 and details in those cases are similar, which will be omitted for brevity.

Fig. 10 shows a method of manufacturing the structures shown in Fig. 2, Fig. 4, Fig. 6 and Fig. 8 according to an embodiment of this application.

S1, form the patterned first conductive layer 311.

For the first conductive layers, aluminum (Al) , titanium (Ti) , chromium (Cr) , cobalt (Co) , nickel (Ni) , zinc (Zn) , molybdenum (Mo) , copper (Cu) , indium (In) , tin (Sn) , hafnium (Hf) , tantalum (Ta) , tungsten (W) , platinum (Pt) , bismuth (Bi) , gold (Au) silver (Ag) or the like can be used. In addition, alloys of these metals may also be used.

S2, form the first insulating layer 312 over the patterned first conductive layer 311.

S3, form the patterned first oxide layer 313.

For the first oxide layer 313, InOx, znOx, snOx, in-Ga-O, in-Zn-O, in-Al-O, in-Sn-O, in-Hf-O, in-Zr-O, in-W-O, in-Y-O, in-Ga-Zn-O, in-Al-Zn-O, in-Sn-Zn-O, in-Hf-Zn-O, in-Ga-Sn-O, in-Al-Sn-O, in-Hf-Sn-O, in-Ga-Al-Zn-O, in-Ga-Hf-Zn-O, in-Sn-Ga-Zn-O or the like can be used.

Part of the first oxide layer 313 is processed to be conductive by means of for example ion implantation, etc.

S4, form the second insulating layer 314 over the patterned first oxide layer 313 with part processed to be conductive.

The second insulating layer 314 includes openings to expose the first oxide layer 313.

S5, form the patterned second conductive layer 315.

S6, form the third insulating layer 316 over the patterned second conductive layer 315.

S7, form the patterned second oxide layer 317 with part processed to be conductive.

The contact patterns are formed using part of the second oxide layer 317 through openings in the insulating layers.

S8, form the fourth insulating layer 318 over the patterned second oxide layer 317.

S9, form the patterned third conductive layer 319.

Optionally, when the structures are used in the display module, the following steps are also included.

S10, form the fourth insulating layer 320 over the patterned third conductive layer 319.

S11, form the patterned fourth conductive layer 321 including contact patterns.

In this application, the first conductive layer 311, the second conductive layer 315, the third conductive layer 319 and the fourth conductive layer 321 can be made of the same material or different materials. And the insulating layers 312, 314, 316 and 318 can also be made of the same or different materials and the first oxide layer 313 and the second oxide layer 317 can be made of the same or different materials.

From Fig. 4 to Fig. 10, embodiments about the stacked structure of Fig. 2 used in the pixel driving circuit 111 have been introduced. Fig. 11 to Fig. 13 introduce embodiments of the staked structure used in the GOA circuit 121.

Fig. 11 shows conceptual graphs of the GOA circuit in the display 100 and Fig. 12 shows an example of an output buffer. In a display, there are several shift resister circuits formed by several transistors. A first clock line to a nth clock line are used to supply a first clock signal (CLK_1) to an nth clock signal (CLK_n) to each of the shift register circuits. The VGL line and the VGH line are used to provide a first control signal and a second control signal to each of the shift register circuits. The first control signal is at a constant high level and the second control signal is at a constant low level. Each shift resister circuit includes a PD control circuit and a PU control circuit and an output buffer, where the PD, PU are gate terminals of the transistor M3 and the transistor M4. The output of the output buffer is connected with the gate electrode of the switching transistor of in pixel driving circuits.

Fig. 13 shows a cross-section view of an output buffer according to an embodiment of this application.

Layers of the transistor 410 and the transistor 430 are the same structure as the stacked structure 300 as shown in the Fig. 2. The transistor 410 and the transistor 430 correspond to the transistor M3 and M4 in Fig. 12 respectively. Structures of the two transistors are omitted for brevity.

The two oxide layers contact each other through openings in the insulating layers 314 and 316. Contact between the source/drain terminal in the second oxide layer 317 and the conductive layer 321 is achieved through openings in the insulating layers 318 and 320 (321-16, 321-17, 321-18) . The two transistors are connected with each other by the oxide layers 313 and 317. These contact structures will save the layout area.

Further, the transistors 410 and 430 are both dual gate transistors and have two channel areas, which will improve the circuit density from the cross-section view and corresponds to higher carrier density.

Understandably, the output buffer is not limited to the structures shown in Fig. 12 and Fig. 13, for example, in certain circumstances, structures shown in Fig. 9 may be applied to the output buffer, which will not be detailed in this application. A manufacturing method of the structures shown in Fig. 13 can refer to the method shown in Fig. 10.

It is to be noted that embodiments of this application show structures with two oxide layers (313 and 317) , four conductive layers (311, 315, 319, 321) and five insulating layers (312, 314, 316, 318, 320) , and more or less these layers are also possible in other cases.

Further, cross-section views of the pixel driving circuit 111, the output buffer can change under certain conditions.

It is to be noted that for any one of the TFTs shown in the preceding embodiments, the source area can also be defined as the drain area and the drain area can be defined as the source area.

An embodiment of the present application provides a stacked structure including structures shown in Fig. 4, Fig. 6, Fig. 8, Fig. 9 and Fig. 13. Optionally, the stacked structure may include one or more components in Fig. 4, Fig. 6, Fig. 8, Fig. 9 and Fig. 13, for example, the stacked structure may include one or more of the first TFT 310, the second TFT 330-1～330-4 and the capacitor 350.

An embodiment of the present application provides a pixel driving circuit including structures shown in Fig. 2, Fig. 4, Fig. 6, Fig. 8 and Fig. 9.

An embodiment of the present application provides a control circuit including structures shown in Fig. 2, Fig. 9 and Fig. 13.

Optionally, the control circuit is the GOA circuit.

An embodiment of the present application provides a display module including the stacked structure according to the above-mentioned embodiments.

Fig. 14 shows a schematic diagram of the display module according to an embodiment of this application. The display module includes: a substrate 309; the pixel driving circuit and/or the control circuit, the pixel driving circuit may include structures shown in Fig. 2, Fig. 4, Fig. 6, Fig. 8 and Fig. 9 and the control circuit including structures shown in Fig. 2, Fig. 9 and Fig. 13.

The pixel driving circuit and/or the control circuit are labeled as 30 in Fig. 14, which may include the stacked structure 300 according to the above-mentioned embodiments.

An embodiment of the present application provides an electronic device, the electronic device includes a display module according to above-mentioned embodiments.

An embodiment of the present application provides a device for manufacturing the stacked structure, the pixel driving circuit, the control circuit, the display module according to the above-mentioned embodiments. The device may include a manufacturing component, a power component, a processor, and a memory. The memory may be configured to store code, instructions, and the like executed by the processor. When the instructions are executed by the processor, the manufacturing component and the power component perform operations performed by the device in the methods in the foregoing embodiments. The foregoing descriptions are merely specific implementations of the present application, but are not intended to limit the protection scope of the present application. Any variation or replacement readily figured out by a person skilled in the art within the technical scope disclosed in the present application shall fall within the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

A stacked structure, comprising:

a first conductive layer (311) , wherein the first conductive layer (311) comprises a first gate area (311-1) ;

a first insulating layer (312) disposed on the first conductive layer (311) ;

a first oxide layer (313) disposed on the first insulating layer (312) , wherein the first oxide layer (313) comprises a first region of the first oxide layer (313-1) and the first region of the first oxide layer (313-1) comprises a first channel area (313-b) , a first conductive source area (313-a) at one side of the first channel area (313-b) and a first conductive drain area (313-c) at the other side of the first channel area (313-b) ;

a second insulating layer (314) disposed on the first oxide layer (313) ;

a second conductive layer (315) disposed on the second insulating layer (314) , wherein the second conductive layer (315) comprises a second gate area (315-1) ;

a third insulating layer (316) disposed on the second conductive layer (315) ;

a second oxide layer (317) disposed on the third insulating layer (316) , wherein the second oxide layer (317) comprises a first region of the second oxide layer (317-1) and the first region of the second oxide layer (317-1) comprises a second channel area (317-b) a second conductive source area (317-a) at one side of the second channel area (317-b) , and a second conductive drain area (317-c) at the other side of the second channel area (317-b) , the second channel area (317-b) overlapping the first channel area (313-b) ;

a fourth insulating layer (318) disposed on the second oxide layer (317) ; and,

a third conductive layer (319) disposed on the fourth insulating layer (318) , wherein the third conductive layer (319) comprises a third gate area (319-1) .
The stacked structure according to claim 1, the first gate area (311-1) , the first insulating layer (312) , the first region of the first oxide layer (313-1) , the second insulating layer (314) , the second gate area (315-1) , the third insulating layer (316) , the first region of the second oxide layer (317-1) , the fourth insulating layer (318) and the third gate area (319-1) form a first thin film transistor (310) .
The stacked structure according to claim 2, wherein the first thin film transistor (310) is used in a pixel driving circuit (111) of a display module.
The stacked structure according to any one of claims 1 to 3, wherein at least three layers of the first conductive layer (311) , the first oxide layer (313) , the second conductive layer (315) , the second oxide layer (317) and the third conductive layer (319) comprise at least three following corresponding regions, which are used as at least three terminals of a first capacitor (350) : a third conductive region of the first conductive layer (311-3) , a third conductive region of the first oxide layer (313-3) , a third conductive region of the second conductive layer (315-3) , a third conductive region of the second oxide layer (317-3) and a third conductive region of the third conductive layer (319-3) .
The stacked structure according to claim 4, wherein the second conductive source area (317-a) contacts the first conductive source area (313-a) to form a first contact pattern (317-4) and the second conductive drain area (317-c) contacts the first conductive drain area (313-c) to form a second contact pattern (317-5) by openings in the second insulating layer (314) and the third insulating layer (316) .
The stacked structure according to claim 5, wherein the second oxide layer (317) comprises a second region of the second oxide layer (317-21) and the second region of the second oxide layer (317-21) comprises a third channel area (317-e1) , a third conductive drain area (317-d1) at one side of the third channel area (317-e1) and a third conductive source area (317-f1) at the other side of the third channel area (317-e1) , the third conductive layer (319) comprises a fourth gate area (319-21) , and the first oxide layer (313) comprises a second conductive region of the first oxide layer (313-21) ;

the fourth gate area (319-21) , the fourth insulating layer (318) , the second region of the second oxide layer (317-21) , the third insulating layer (316) , the second insulating layer (314) and the second conductive region of the first oxide layer (313-21) form a second thin film transistor (330-1) .
The stacked structure according to claim 6, wherein the second conductive region of the first oxide layer (313-21) is connected with the second contact pattern (317-5) by the first oxide layer (313) .
The stacked structure according to claim 5, wherein the second oxide layer (317) comprises a second region of the second oxide layer (317-21) and the second region of the second oxide layer (317-21) comprises a third channel area (317-e1) , a third conductive drain area (317-d1) at one side of the third channel area (317-e1) and a third conductive source area (317-f1) at the other side of the third channel area (317-e1) , the third conductive layer (319) comprises a fourth gate area (319-21) , and the first conductive layer (311) comprises a second conductive region of the first conductive layer (311-21) ;

the fourth gate area (319-21) , the fourth insulating layer (318) , the second region of the second oxide layer (317-21) , the third insulating layer (316) , the second insulating layer (314) , the first insulating layer (312) and the second conductive region of the first conductive layer (311-21) form a second thin film transistor (330-2) .
The stacked structure according to claim 8, wherein the second conductive region of the first conductive layer (311-21) is connected with the second contact pattern (317-5) by a third contact pattern (317-6) , wherein the second oxide layer (317) contacts the second conductive region of the first conductive layer (311-21) through openings in the first insulating layer (312) , the second insulating layer (314) and the third insulating layer (316) to form the third contact pattern (317-6) .
The stacked structure according to one of claims 6 to 9, wherein the fourth gate area (319-21) is connected with the third conductive source area (317-f1) .
The stacked structure according to any one of claims 6 to 10, wherein a sum of thicknesses of the second insulating layer (314) and the third insulating layer (316) is greater than a thickness of the fourth insulating layer (318) or the first insulating layer (312) .
The stacked structure according to claim 6 or 7, wherein the third conductive region of the first conductive layer (311-3) overlaps the third channel area (317-e1) .
The stacked structure according to claim 5, wherein the first oxide layer (313) comprises a second region of the first oxide layer (313-22) and the second region of the first oxide layer (313-22) comprises a fourth channel area (313-e2) , a fourth conductive drain area (313-d2) at one side of the fourth channel area (313-e2) and a fourth conductive source area (313-f2) at the other side of the fourth channel area (313-e2) , the first conductive layer (311) comprises a fifth gate area (311-22) , and the second oxide layer (317) comprises a second conductive region of the second oxide layer (317-22) ;

the fifth gate area (311-22) , the first insulating layer (312) , the second region of the first oxide layer (313-22) , the second insulating layer (314) , the third insulating layer (316) and the second conductive region of the second oxide layer (317-22) form a second thin film transistor (330-3) .
The stacked structure according to claim 13, wherein the second conductive region of the second oxide layer (317-22) is connected with the second contact pattern (317-5) by the second oxide layer (317) .
The stacked structure according to claim 5, wherein the first oxide layer (313) comprises a second region of the first oxide layer (313-22) and the second region of the first oxide layer (313-22) comprises a fourth channel area (313-e2) , a fourth conductive drain area (313-d2) at one side of the fourth channel area (313-e2) and a fourth conductive source area (313-f2) at the other side of the fourth channel area (313-e2) , the first conductive layer (311) comprises a fifth gate area (311-22) , and the third conductive layer (319) comprises a second conductive region of the third conductive layer (319-22) ;

the fifth gate area (311-22) , the first insulating layer (312) , the second region of the first oxide layer (313-22) , the second insulating layer (314) , the third insulating layer (316) , the fourth insulating layer (318) and the second conductive region of the third conductive layer (319-22) form a second thin film transistor (330-4) .
The stacked structure according to claim 15, wherein the second conductive region of the third conductive layer (319-22) is connected with the second contact pattern (317-5) .
The stacked structure according to any one of claims 13 to 16, wherein the fifth gate area (311-22) is connected with the fourth conductive source area (313-f2) .
The stacked structure according to any one of claims 13 to 17, wherein a sum of thicknesses of the second insulating layer (314) and the third insulating layer (316) is greater than the thickness of the first insulating layer (312) or the fourth insulating layer (318) .
The stacked structure according to claim 1, wherein the first gate area (311-1) , the first insulating layer (312) , the first region of the first oxide layer (313-1) , the second insulating layer (314) and the second gate area (315-1) form a third thin film transistor (301) , and the second gate area (315-1) , the third insulating layer (316) , the first region of the second oxide layer (317-1) , the fourth insulating layer (318) and the third gate area (319-1) form a fourth thin film transistor (303) .
The stacked structure according to claim 19, wherein the second conductive source area (317-c) contacts the first conductive source area (313-c) to form a second contact pattern (317-5) by openings in the second insulating layer (314) and the third insulating layer (316) .
The stacked structure according to any one of claims 2 to 18, wherein the first thin film transistor (310) is used in a control circuit of the display module.
A stacked structure, comprising:

a first conductive layer (311) ;

a first insulating layer (312) disposed on the first conductive layer (311) ;

a first oxide layer (313) disposed on the first insulating layer (312) ;

a second insulating layer (314) disposed on the first oxide layer (313) ;

a second conductive layer (315) disposed on the second insulating layer (314) ;

a third insulating layer (316) disposed on the second conductive layer (315) ;

a second oxide layer (317) disposed on the third insulating layer (316) ;

a fourth insulating layer (318) disposed on the second oxide layer (317) ; and

a third conductive layer (319) disposed on the fourth insulating layer (318) ;

wherein at least three layers of the first conductive layer (311) , the first oxide layer (313) , the second conductive layer (315) , the second oxide layer (317) and the third conductive layer (319) comprise at least three following corresponding regions, which are used as at least three terminals of a first capacitor (350) of the stacked structure: a third conductive region of the first conductive layer (311-3) , a third conductive region of the first oxide layer (313-3) , a third conductive region of the second conductive layer (315-3) , a third conductive region of the second oxide layer (317-3) , and a third conductive region of the third conductive layer (319-3) .
A pixel driving circuit, comprising the stacked structure according to any one of claims 1 to 20 or 22.
A control circuit, comprising:

a first conductive layer (311) , wherein the first conductive layer (311) comprises a first gate area (311-1) ;

a first insulating layer (312) disposed on the first conductive layer (311) ;

a first oxide layer (313) disposed on the first insulating layer (312) , wherein the first oxide layer (313) comprises a first channel area (313-b) , a first conductive source area (313-a) at one side of the first channel area (313-b) and a first conductive drain area (313-c) at the other side of the first channel area (313-b) ;

a second insulating layer (314) disposed on the first oxide layer (313) ;

a second conductive layer (315) disposed on the second insulating layer (314) , wherein the second conductive layer (315) comprises a second gate area (315-1) ;

a third insulating layer (316) disposed on the second conductive layer (315) ;

a second oxide layer (317) disposed on the third insulating layer (316) , wherein the second oxide layer (317) comprises a second channel area (317-b) a second conductive source area (317-a) at one side of the second channel area (317-b) , and a second conductive drain area (317-c) at the other side of the second channel area (317-b) , the second channel area (317-b) overlapping the first channel area (313-b) ;

a fourth insulating layer (318) disposed on the second oxide layer (317) ; and,

a third conductive layer (319) disposed on the fourth insulating layer (318) , wherein the third conductive layer (319) comprises a third gate area (319-1) .
The control circuit, according to claim 24, wherein the first gate area (311-1) , the first insulating layer (312) , the first channel area (313-b) , the first conductive source area (313-a) , the first conductive drain area (313-c) , the second insulating layer (314) , the second gate area (315-1) , the third insulating layer (316) , the second channel area (317-b) , the second conductive source area (317-a) , the second conductive drain area (317-c) , the fourth insulating layer (318) and the third gate area (319-1) form a thin film transistor (410) .
The control circuit according to claim 24 or 25, wherein the second conductive source area (317-a) contacts the first conductive source area (313-a) to form a first contact pattern (317-4) , and the second conductive drain area (317-c) contacts the first conductive drain area (313-c) to form a second contact pattern (317-5) by openings in the second insulating layer (314) and the third insulating layer (316) .
The control circuit according to any one of claims 24 to 26, wherein the control circuit is a GOA circuit.
A display module, comprising:

a substrate (309) ;

the pixel driving circuit according to claim 23 and/or the control circuit according to any one of claims 24 to 27, wherein the first conductive layer (311) is disposed on the substrate (309) .
An electronic device comprising the display module according to claim 28.