WO2025032961A1 - Light detection device and electronic apparatus - Google Patents

Abstract

Provided is a light detection device capable of improving quantum efficiency Qe while suppressing the generation of dark current. Specifically, the light detection device comprises: a semiconductor substrate having a first surface on which light strikes, and a second surface which is positioned on the reverse side from the first surface; a plurality of photoelectric conversion parts formed in a two-dimensional array on the semiconductor substrate; a pixel separation structure formed between the photoelectric conversion parts of the semiconductor substrate; and an on-chip lens disposed on the first-surface side of the semiconductor substrate and shared by two or more photoelectric conversion parts. The pixel separation structure includes an inter-pixel separation part surrounding the peripheries of two or more photoelectric conversion parts, and an intra-pixel separation part positioned between the photoelectric conversion parts in a region surrounded by the inter-pixel separation part. An electrical conductor is disposed in the inter-pixel separation part. In the intra-pixel separation part, only a low-absorptance member which has a lower light absorptance than the electrical conductor is disposed.

Description

Photodetection device and electronic device

This technology (the technology disclosed herein) relates to a light detection device and electronic equipment.

　Conventionally, a photodetector has been proposed that includes, for example, a semiconductor substrate having two adjacent photoelectric conversion units, an inter-pixel separation unit surrounding a block consisting of the two photoelectric conversion units, an intra-pixel separation unit formed between the photoelectric conversion units that make up the block, and an on-chip lens that is disposed on the light receiving surface side of the semiconductor substrate and shared by the two photoelectric conversion units (see, for example, Patent Document 1). The photodetector described in Patent Document 1 detects a phase difference from the output of the two photoelectric conversion units, and performs autofocus using the detected phase difference. In addition, by applying a negative bias voltage to each of the inter-pixel separation unit and the intra-pixel separation unit, the peripheral areas of the inter-pixel separation unit and the intra-pixel separation unit are brought into a high hole concentration state, suppressing the generation of dark current.

JP 2022-148841 A

However, in the photodetector described in Patent Document 1, the on-chip lens focuses light on the central area of a block consisting of two photoelectric conversion units. Therefore, the focused light is irradiated onto the in-pixel separation unit, and there is a possibility that the light is absorbed by the in-pixel separation unit. This reduces the amount of light that reaches the photoelectric conversion unit, and there is a possibility that the quantum efficiency Qe decreases.

The present disclosure aims to provide a photodetector and electronic device that can improve quantum efficiency Qe while suppressing the generation of dark current.

The photodetector disclosed herein comprises (a) a semiconductor substrate having a first surface on which light is incident and a second surface located opposite the first surface, (b) a plurality of photoelectric conversion units formed in a two-dimensional array on the semiconductor substrate, (c) a pixel separation structure formed between the photoelectric conversion units of the semiconductor substrate, and (d) an on-chip lens arranged on the first surface side of the semiconductor substrate and shared by two or more photoelectric conversion units, (e) the pixel separation structure has an inter-pixel separation unit surrounding the periphery of the two or more photoelectric conversion units and an intra-pixel separation unit located between the photoelectric conversion units in the area surrounded by the inter-pixel separation unit, (f) a conductor is arranged within the inter-pixel separation unit, and (g) only a low-absorption material having a lower light absorption rate than the conductor is arranged within the intra-pixel separation unit.

The electronic device disclosed herein includes (a) a semiconductor substrate having a first surface on which light is incident and a second surface located opposite to the first surface, (b) a plurality of photoelectric conversion units formed in a two-dimensional array on the semiconductor substrate, (c) a pixel separation structure formed between the photoelectric conversion units of the semiconductor substrate, (d) and an on-chip lens arranged on the first surface side of the semiconductor substrate and shared by two or more photoelectric conversion units, (e) the pixel separation structure includes an inter-pixel separation unit surrounding the periphery of the two or more photoelectric conversion units and an intra-pixel separation unit located between the photoelectric conversion units in the area surrounded by the inter-pixel separation unit, (f) a conductor is arranged within the inter-pixel separation unit, and (g) a light detection device in which only a low absorptivity material having a lower light absorptivity than the conductor is arranged within the intra-pixel separation unit.

1 is a diagram showing an overall configuration of a solid-state imaging device according to a first embodiment. 2 is a diagram showing a cross-sectional configuration of the solid-state imaging device taken along line AA in FIG. 1. 3 is a diagram showing a cross-sectional configuration of the solid-state imaging device taken along line BB in FIG. 2. FIG. 1 is a diagram showing a cross-sectional configuration of a solid-state imaging device according to a comparative example. 5 is a diagram showing a cross-sectional configuration of the solid-state imaging device taken along line DD in FIG. 4. 1A to 1C are diagrams illustrating a method for manufacturing a solid-state imaging device. 7 is a diagram showing a cross-sectional configuration of the semiconductor substrate when broken along line FF in FIG. 6. 1A to 1C are diagrams illustrating a method for manufacturing a solid-state imaging device. 9 is a diagram showing a cross-sectional configuration of the semiconductor substrate when broken along line HH in FIG. 8. 9 is a diagram showing a cross-sectional configuration of a semiconductor substrate taken along line II in FIG. 8. 1A to 1C are diagrams illustrating a method for manufacturing a solid-state imaging device. 12 is a diagram showing a cross-sectional configuration of a semiconductor substrate taken along line K-K in FIG. 11. 12 is a diagram showing a cross-sectional configuration of a semiconductor substrate taken along line LL in FIG. 11. 1A to 1C are diagrams illustrating a method for manufacturing a solid-state imaging device. 15 is a diagram showing a cross-sectional configuration of a semiconductor substrate taken along line N-N in FIG. 14. 15 is a diagram showing a cross-sectional configuration of a semiconductor substrate taken along line OO in FIG. 14. FIG. 13 is a diagram showing a cross-sectional configuration of a solid-state imaging device according to a modified example. 1A to 1C are diagrams illustrating a method for manufacturing a solid-state imaging device. 19 is a diagram showing a cross-sectional configuration of a semiconductor substrate taken along line QQ in FIG. 18. 19 is a diagram showing a cross-sectional configuration of a semiconductor substrate taken along line R--R in FIG. 18. 1A to 1C are diagrams illustrating a method for manufacturing a solid-state imaging device. 22 is a diagram showing a cross-sectional configuration of a semiconductor substrate taken along line T-T in FIG. 21. 22 is a diagram showing a cross-sectional configuration of a semiconductor substrate taken along line UU in FIG. 21. FIG. 13 is a diagram showing a cross-sectional configuration of a solid-state imaging device according to a second embodiment. 1A to 1C are diagrams illustrating a method for manufacturing a solid-state imaging device. 1A to 1C are diagrams illustrating a method for manufacturing a solid-state imaging device. 1A to 1C are diagrams illustrating a method for manufacturing a solid-state imaging device. FIG. 13 is a diagram showing a cross-sectional configuration of a solid-state imaging device according to a third embodiment. FIG. 13 is a diagram showing a cross-sectional configuration of a solid-state imaging device according to a modified example. FIG. 13 is a diagram showing a cross-sectional configuration of a solid-state imaging device according to a fourth embodiment. FIG. 13 is a diagram showing a cross-sectional configuration of a solid-state imaging device according to a modified example. FIG. 13 is a diagram showing a schematic configuration of an electronic device according to a fifth embodiment.

Below, an example of a light detection device and electronic device according to an embodiment of the present disclosure will be described with reference to FIGS. 1 to 32. The embodiments of the present disclosure will be described in the following order. Note that the present disclosure is not limited to the following examples. In addition, the effects described in this specification are illustrative and not limiting, and other effects may also be present.

1. First embodiment: solid-state imaging device 1-1 Overall configuration of solid-state imaging device 1-2 Configuration of main parts 1-3 Manufacturing method of solid-state imaging device 1-4 Modification 2. Second embodiment: solid-state imaging device 2-1 Configuration of main parts 2-2 Manufacturing method of solid-state imaging device 2-3 Modification 3. Third embodiment: solid-state imaging device 3-1 Configuration of main parts 3-2 Modification 4. Fourth embodiment: solid-state imaging device 4-1 Configuration of main parts 4-2 Modification 5. Fifth embodiment: Application to electronic devices

1. First embodiment
[1-1 Overall configuration of solid-state imaging device]
A solid-state imaging device 1 (or, in a broader sense, a "photodetector") according to a first embodiment of the present disclosure will be described below. Fig. 1 is a diagram showing an overall configuration of the solid-state imaging device 1 according to the first embodiment.
The solid-state imaging device 1 in Fig. 1 is a back-illuminated CMOS (Complementary Metal Oxide Semiconductor) image sensor. As shown in Fig. 32, the solid-state imaging device 1 (1002) captures image light (incident light) from a subject via a lens group 1001, converts the amount of incident light focused on an imaging surface into an electrical signal on a pixel-by-pixel basis, and outputs the electrical signal.
As shown in FIG. 1, the solid-state imaging device 1 includes a pixel region 2, a vertical drive circuit 3, a column signal processing circuit 4, a horizontal drive circuit 5, an output circuit 6, and a control circuit .

The pixel region 2 has a plurality of pixels 8 arranged in a two-dimensional array. The pixel 8 has two photoelectric conversion units PD1 and PD2 (see FIG. 3) and a plurality of pixel transistors (e.g., a transfer transistor, a reset transistor, an amplification transistor, and a selection transistor). FIG. 3 illustrates a case in which the pixel 8 has two photoelectric conversion units PD1 and PD2 and is a square phase difference pixel with an aspect ratio of 1:1. In the first embodiment, as an example, a case in which all the pixels 8 are phase difference pixels is shown, but only some of the pixels 8 may be phase difference pixels and the remaining pixels 8 may be pixels having only one photoelectric conversion unit.
The vertical drive circuit 3 is configured, for example, by a shift register, and sequentially selects each pixel 8 in the pixel region 2 on a row-by-row basis by, for example, sequentially outputting selection pulses to pixel drive wiring 9, and outputs pixel signals of the selected pixels 8 to the column signal processing circuit 4 through vertical signal lines 10. The pixel signals are signals obtained from charges (for example, electrons) generated in the photoelectric conversion units PD1 and PD2.

The column signal processing circuit 4 is arranged, for example, for each column of pixels 8, and performs signal processing such as noise removal for each pixel column on signals output from one row of pixels 8. For example, correlated double sampling (CDS) for removing fixed pattern noise specific to each pixel and AD (Analog-Digital) conversion can be used as the signal processing.
The horizontal drive circuit 5 is, for example, composed of a shift register, and sequentially outputs horizontal scanning pulses to the column signal processing circuits 4, selects the column signal processing circuits 4 in order, and causes the selected column signal processing circuit 4 to output pixel signals that have been subjected to signal processing to the horizontal signal line 11.

The output circuit 6 performs various signal processing on each of the pixel signals sequentially output from the column signal processing circuit 4 through the horizontal signal line 11. As the signal processing, various types of digital signal processing such as buffering, black level adjustment, column variation correction, etc. can be used.
The control circuit 7 generates clock signals and control signals that serve as a reference for the operation of the vertical drive circuit 3, the column signal processing circuit 4, the horizontal drive circuit 5, etc., based on a vertical synchronization signal, a horizontal synchronization signal, and a master clock signal (not shown). Then, the control circuit 7 outputs the generated clock signals and control signals to the vertical drive circuit 3, the column signal processing circuit 4, the horizontal drive circuit 5, etc.

[1-2 Configuration of Main Parts]
Next, a detailed structure of the solid-state imaging device 1 will be described. Fig. 2 is a diagram showing a cross-sectional configuration of the solid-state imaging device 1 when cut along line A-A in Fig. 1. Fig. 2 is also a diagram showing a cross-sectional configuration of the solid-state imaging device 1 when cut along line CC in Fig. 3.
2, the solid-state imaging device 1 has a semiconductor substrate 12, and a fixed charge film 26, an insulator 27, a color filter 13, and an on-chip lens 14 are laminated in this order on a light incident surface (hereinafter also referred to as "rear surface S1") of the semiconductor substrate 12. In addition, a wiring layer 15 is disposed on a surface (hereinafter referred to as "front surface S2") of the semiconductor substrate 12 opposite to the rear surface S1.

The semiconductor substrate 12 is a substrate made of, for example, silicon (Si). In the semiconductor substrate 12, each region corresponding to each pixel 8 has a first region R1 and a second region R2. As shown in FIG. 3, the first region R1 and the second region R2 are arranged adjacent to each other in the row direction (left-right direction in FIG. 3) when viewed from the thickness direction of the semiconductor substrate 12, and each is formed in a rectangular shape extending in the column direction (up-down direction in FIG. 3). FIG. 3 is a diagram showing a cross-sectional configuration of the solid-state imaging device 1 when broken along line B-B in FIG. 2. In addition, a photoelectric conversion unit PD1 is formed in the first region R1, and a photoelectric conversion unit PD2 is formed in the second region R2. That is, in the semiconductor substrate 12, two photoelectric conversion units PD1 and PD2 are formed for one pixel 8, and a plurality of photoelectric conversion units PD1 and PD2 are arranged in a two-dimensional array.

Each of the photoelectric conversion units PD1 and PD2 constitutes a photodiode by a p-type semiconductor region and an n-type semiconductor region. The photoelectric conversion unit PD1 generates and accumulates electric charges according to the amount of light L1 incident from the back surface S1 side of the semiconductor substrate 12. Similarly, the photoelectric conversion unit PD2 generates and accumulates electric charges according to the amount of light L2 incident from the back surface S1 side of the semiconductor substrate 12. Here, the light L1 is the light that is incident on the first region R1 of the incident light L to the pixel 8. The light L2 is the light that is incident on the second region R2 of the incident light L.

Furthermore, a pixel isolation structure 18 is formed between the photoelectric conversion units PD1 and PD2 on the semiconductor substrate 12. That is, the pixel isolation structure 18 is formed in a lattice shape on the semiconductor substrate 12 so as to surround each of the multiple photoelectric conversion units PD1 and PD2. Furthermore, the pixel isolation structure 18 has a portion (hereinafter also referred to as an "inter-pixel isolation portion 19") that surrounds the periphery of the photoelectric conversion units PD1 and PD2 (also referred to as "two or more photoelectric conversion units" in a broad sense) in the same pixel 8, and a portion (hereinafter also referred to as an "intra-pixel isolation portion 20") located between the photoelectric conversion units PD1 and PD2 in the region surrounded by the inter-pixel isolation portion 19.
The pixel isolation portion 19 is formed from the back surface S1 of the semiconductor substrate 12 to the vicinity of the front surface S2. Specifically, the pixel isolation portion 19 has a trench portion 21, and an insulator 22 and a conductor 23 arranged in the trench portion 21. The trench portion 21 penetrates the semiconductor substrate 12 from the back surface S1 to the front surface S2 of the semiconductor substrate 12, and the side wall surface forms the outer shape of the pixel isolation portion 19. The insulator 22 and the conductor 23 are arranged in a space from the back surface S1 to an end position of the front surface S2 side of the pixel isolation portion 19 in the trench portion 21. Note that a silicon oxide (SiO) or other isolation portion 50 is arranged in the space from the end position of the front surface S2 side of the pixel isolation portion 19 of the trench portion 21 to the front surface S2. The insulator 22 covers the side wall surface of the trench portion 21. For example, silicon oxide (SiO ₂ ) can be used as the material of the insulator 22.

The conductor 23 is disposed in the space within the trench portion 21, that is, in the space between the sidewall surfaces covered with the insulator 22. The conductor 23 is disposed from the rear surface S1 of the semiconductor substrate 12 to the bottom surface of the space between the sidewall surfaces. Each part of the conductor 23 within the trench portion 21 is electrically integrated. For example, polysilicon doped with impurities such as boron (B) (B-doped polysilicon, hereinafter also referred to as "doped polysilicon") can be used as the material for the conductor 23. The conductor 23 is electrically connected to a negative bias voltage supply source, and a negative bias voltage is applied to the conductor 23. By applying a negative bias voltage, the peripheral portion of the pixel separation portion 19 can be brought into a high hole concentration state, and the generation of dark current is suppressed.

Further, the intra-pixel isolation portion 20 protrudes from the inter-pixel isolation portion 19 into a region between the photoelectric conversion portions PD1 and PD2 in the same pixel 8. FIG. 3 illustrates a case in which the intra-pixel isolation portion 20 is formed as a pair of strips extending in the column direction (up-down direction in FIG. 3) toward the center of the pixel 8 from each of a pair of linear portions extending along the row direction (left-right direction in FIG. 3) of the inter-pixel isolation portion 19 when viewed from the thickness direction of the semiconductor substrate 12. The tips of the pair of intra-pixel isolation portions 20 are spaced apart from each other in the column direction (up-down direction in FIG. 3) at the center of the pixel 8, forming a gap 24. As a result, the gap 24 functions as an overflow path that allows charge to pass from one side to the other side between the adjacent photoelectric conversion portions PD1 and PD2. Therefore, for example, during normal shooting, when the charge of one of the photoelectric conversion units PD1 and PD2 approaches saturation, the charge can be moved to the other photoelectric conversion unit via the overflow path, and saturation of the charge of the photoelectric conversion units PD1 and PD2 can be avoided. As a result, the linearity of the pixel signal output from the pixel 8 can be ensured, and degradation of the captured image can be suppressed.
When viewed in the thickness direction of the semiconductor substrate 12, the line width Wa of the intra-pixel separation portion 20 is constant from the portion (root portion) located on the inter-pixel separation portion 19 side to the tip portion. The line width Wa of the intra-pixel separation portion 20 is the same as the line width Wb of the inter-pixel separation portion 19.

The intra-pixel isolation portion 20 is formed from the back surface S1 of the semiconductor substrate 12 to near the front surface S2 (to the same depth as the inter-pixel isolation portion 19). Specifically, the intra-pixel isolation portion 20 has a trench portion 25, and a negatively charged fixed charge film 26 and an insulator 27 arranged in the trench portion 25. The trench portion 25 penetrates the semiconductor substrate 12 from the back surface S1 to the front surface S2 of the semiconductor substrate 12, and the sidewall surface forms the outer shape of the intra-pixel isolation portion 20. The fixed charge film 26 and the insulator 27 are arranged in the space from the back surface S1 to the end position on the front surface S2 side of the intra-pixel isolation portion 20 in the trench portion 25. The isolation portion 50 is arranged in the space from the end position on the front surface S2 side of the intra-pixel isolation portion 20 of the trench portion 25 to the front surface S2. The fixed charge film 26 continuously covers the sidewall surface of the trench portion 25 and the back surface S1 of the semiconductor substrate 12. That is, the fixed charge film 26 constitutes the sidewall of the pixel isolation section 20. The fixed charge film 26 induces holes (positive holes) on the pixel isolation section 20 side of the semiconductor substrate 12 to form a portion in a high hole concentration state, realizing pinning of the sidewall surface of the trench section 25 and suppressing the generation of dark current. The insulator 27 is disposed in the space within the trench section 25, that is, in the space between the sidewall surfaces covered with the fixed charge film 26. In addition to the space within the trench section 25, the insulator 27 also covers the light receiving surface (hereinafter also referred to as "back surface S3") of the fixed charge film 26 located on the back surface S1 of the semiconductor substrate 12. That is, the insulator 27 is disposed continuously within the pixel isolation section 20 and on the back surface S1 of the semiconductor substrate 12.

The fixed charge film 26 and the insulator 27 are made of a low absorptivity material having a lower light absorptivity than the conductor 23. That is, only low absorptivity materials having a lower light absorptivity than the conductor 23 are disposed in the pixel separation section 20. The fixed charge film 26 is made of a material (low absorptivity material) that can be formed on the semiconductor substrate 12 to generate fixed charges and strengthen pinning. Examples of the material include oxides or nitrides containing at least one element of hafnium (Hf), aluminum (Al), zirconium (Zr), tantalum (Ta), and titanium (Ti). In particular, hafnium oxide (HfO ₂ ) is preferable because it is difficult to peel off from the semiconductor substrate 12. The insulator 27 is made of a material (low absorptivity material) that can be formed on the semiconductor substrate ₁₂ to generate fixed charges and strengthen pinning.

In addition, in the semiconductor substrate 12, a p-type semiconductor region 16 is formed on the sidewall surface (sidewall surface of the pixel isolation structure 18) of each of the inter-pixel isolation portion 19 and the intra-pixel isolation portion 20. That is, the p-type semiconductor region 16 is formed on the side surface of the photoelectric conversion units PD1 and PD2 so as to cover the sidewall surface of the pixel isolation structure 18. The p-type semiconductor region 16 induces holes (positive holes) on the pixel isolation structure 18 side of the semiconductor substrate 12 to form a portion with a high hole concentration, realizing pinning of the sidewall surface of the trench portions 21 and 25, and more appropriately suppressing the generation of dark current. In addition, the p-type semiconductor region 16 can increase the potential depth of the photoelectric conversion units PD1 and PD2, and can increase the amount of charge (saturation charge amount Qs) that can be accumulated by the photoelectric conversion units PD1 and PD2.

The color filters 13 are arranged in a two-dimensional array on the back surface S1 side of the semiconductor substrate 12 so that one color filter 13 is arranged for one pixel 8. That is, a shared color filter 13 is arranged for the photoelectric conversion units PD1 and PD2 in the same pixel 8. As the color filters 13, for example, multiple types of color filters (that is, multiple types of color filters with different transmission characteristics) that transmit only light of different predetermined wavelengths are used. For example, an R filter that transmits red light, a G filter that transmits green light, and a B filter that transmits blue light are included. As a result, the color filters 13 transmit light of a predetermined wavelength (red light, green light, blue light, etc.) according to the transmission characteristics, and allow the transmitted light to enter the photoelectric conversion units PD1 and PD2. At that time, the light transmitted through the color filters 13 is also incident on the pixel separation unit 20 (fixed charge film 26, insulator 27) between the photoelectric conversion units PD1 and PD2.

The on-chip lenses 14 are arranged in a two-dimensional array on the light incident surface (hereinafter also referred to as "rear surface S4") side of the color filter 13 so that one on-chip lens 14 is arranged for one pixel 8. That is, the on-chip lens 14 is arranged on the rear surface S1 side of the semiconductor substrate 12, and is shared by the photoelectric conversion units PD1 and PD2 (also referred to as "two or more photoelectric conversion units" in a broad sense) in the same pixel 8. The on-chip lens 14 collects image light (incident light L) from a subject at the center of the pixel 8 (the region where the gap 24 in FIG. 3 is located), and causes the collected incident light L (light L1, L2) to be incident on each of the photoelectric conversion units PD1 and PD2.
The wiring layer 15 is disposed on the surface S2 side of the semiconductor substrate 12. The wiring layer 15 has an interlayer insulating film and wirings stacked in multiple layers with the interlayer insulating film interposed therebetween. The wiring layer 15 drives pixel transistors (not shown) of each pixel 8 via the multiple layers of wiring.

In the solid-state imaging device 1 having the above configuration, light is irradiated from the rear surface S1 side of the semiconductor substrate 12, the irradiated light is transmitted through the on-chip lens 14 and the color filter 13, and the transmitted light is photoelectrically converted by the photoelectric conversion units PD1 and PD2 to generate electric charges. The generated electric charges are then output as pixel signals from the vertical signal lines 10 formed by the wiring of the wiring layer 15.
Furthermore, when detecting a phase difference, the solid-state imaging device 1 detects the phase difference by detecting the difference between pixel signals based on the charges generated by the photoelectric conversion units PD1 and PD2. During normal shooting, the photoelectric conversion units PD1 and PD2 in the same pixel 8 are made to function as one photoelectric conversion unit, and the sum of the pixel signals based on the charges generated by the photoelectric conversion units PD1 and PD2 is detected. At that time, the gap 24 between the pair of intra-pixel isolation units 20 functions as an overflow path that allows the passage of charges from one of the photoelectric conversion units PD1 and PD2 to the other photoelectric conversion unit.

4 and 5, a comparative example is considered in which the side walls of the inter-pixel isolation portion 19 and the intra-pixel isolation portion 20 are continuously covered with an insulator 22, and a conductor 23 is continuously embedded in the space surrounded by the insulator 22 (the space in the inter-pixel isolation portion 19 and the space in the intra-pixel isolation portion 20). That is, a case is considered in which silicon oxide (SiO ₂ ) and doped polysilicon are also used as the material for the intra-pixel isolation portion 20. In this case, by applying a negative bias voltage to the conductor 23 in the inter-pixel isolation portion 19, a negative bias voltage is also applied to the conductor 23 in the intra-pixel isolation portion 20, so that both the peripheral portion of the inter-pixel isolation portion 19 and the peripheral portion of the intra-pixel isolation portion 20 are brought into a high hole concentration state, and the generation of dark current is suppressed.
However, polysilicon has a property of absorbing light. Therefore, incident light is absorbed by the intra-pixel isolation section 20, and the amount of light reaching the photoelectric conversion sections PD1 and PD2 is reduced, and the quantum efficiency Qe may decrease. In particular, the presence of the intra-pixel isolation section 20 including doped polysilicon near the central region (light-focused spot) of the pixel 8 where the light is focused by the on-chip lens 14 may increase the amount of decrease in the quantum efficiency Qe. FIG. 4 is also a diagram showing the cross-sectional configuration of the solid-state imaging device 1 when cut along the line E-E in FIG. 5. FIG. 5 is also a diagram showing the cross-sectional configuration of the solid-state imaging device 1 when cut along the line D-D in FIG. 4.

In contrast, in the solid-state imaging device 1 according to the first embodiment, the conductor 23 (doped polysilicon) is arranged in the inter-pixel isolation section 19. Therefore, by applying a negative bias voltage to the conductor 23 in the inter-pixel isolation section 19, the peripheral portion of the inter-pixel isolation section 19 is brought into a high hole concentration state, and the generation of dark current is suppressed. In addition, only low-absorption members (fixed charge film 26, insulator 27) having a lower light absorption rate than the conductor 23 are arranged in the intra-pixel isolation section 20. In other words, polysilicon (doped polysilicon) is not arranged near the light-focusing spot. Therefore, the absorption of incident light by the intra-pixel isolation section 20 can be suppressed, the amount of light reaching the photoelectric conversion sections PD1 and PD2 can be increased, and the decrease in quantum efficiency Qe can be suppressed. Therefore, the quantum efficiency Qe can be improved while suppressing the generation of dark current.

[1-3 Manufacturing method of solid-state imaging device]
Next, a method for manufacturing the solid-state imaging device 1 according to the first embodiment will be described.
First, as shown in FIG. 6 and FIG. 7, a trench portion 21 of the pixel isolation portion 19 is formed on the surface S2 of the semiconductor substrate 12 by using lithography and dry etching. Then, a conformal doping technique is used to dope the sidewall surface of the trench portion 21 with boron (B) to form a part of the p-type semiconductor region 16 in the semiconductor substrate 12. Then, an insulator 22 is formed so as to continuously cover the sidewall surface and the bottom surface of the trench portion 21. For example, a chemical vapor deposition (CVD) method or thermal oxidation can be used as a method for forming the insulator 22. Then, a conductor 23 is buried in the space between the sidewall surfaces covered with the insulator 22. The trench portion 21, the insulator 22, and the conductor 23 form the pixel isolation portion 19. For example, doped polysilicon is used as the material of the conductor 23. Moreover, silicon oxide (SiO) is embedded on the surface S2 side of the trench portion 21 to form an isolation portion 50. Fig. 6 is a diagram showing the semiconductor substrate 12 when cut along line G-G in Fig. 7. Fig. 7 is a diagram showing the semiconductor substrate 12 when cut along line F-F in Fig. 6.

Subsequently, as shown in Figs. 8, 9, and 10, a trench portion 25 of the intra-pixel isolation portion 20 is formed on the surface S2 of the semiconductor substrate 12 on which the inter-pixel isolation portion 19 is formed, using lithography and dry etching. Next, boron (B) is doped into the sidewall surface of the trench portion 25 using conformal doping technology to form the remaining portion of the p-type semiconductor region 16 in the semiconductor substrate 12. Next, an oxide film 31 is formed so as to continuously cover the sidewall surface and bottom surface of the trench portion 25 thus formed. For example, silicon oxide (SiO) can be used as the material for the oxide film 31. For example, chemical vapor deposition and thermal oxidation can be used as the method for forming the oxide film 31. Next, a filling material 32 is filled into the space between the sidewall surfaces covered with the oxide film 31. For example, polysilicon (Pure-Poly Si) that is not doped with impurities is used as the material for the filling material 32. By using pure polysilicon, the embedding material 32 can be removed with an alkaline chemical solution, and the process of removing the embedding material 32 can be performed relatively easily. Note that doped polysilicon doped with boron (B) is not suitable for the embedding material 32 because it cannot be removed with an alkaline chemical solution. The embedding material 32 is arranged so as not to come into direct contact with the conductor 23 of the inter-pixel isolation portion 19. In addition, silicon oxide (SiO) is embedded on the surface S2 side of the trench portion 25 to form an isolation portion 50. FIG. 8 is a diagram showing the semiconductor substrate 12 when broken along the line J-J in FIG. 9. FIG. 9 is a diagram showing the semiconductor substrate 12 when broken along the line H-H in FIG. 9. FIG. 10 is a diagram showing the semiconductor substrate 12 when broken along the line I-I in FIG. 10.

Next, the semiconductor substrate 12 is turned upside down, and then the back surface S1 side of the semiconductor substrate 12 is polished by CMP (Chemical Mechanical Polishing) or the like. Next, the filling material 32 is selectively removed from within the trench portion 25 using an alkaline chemical solution or the like, as shown in Figs. 11, 12, and 13. Fig. 11 is a diagram showing the semiconductor substrate 12 when broken along the line M-M in Fig. 12. Fig. 12 is a diagram showing the semiconductor substrate 12 when broken along the line K-K in Fig. 11. Fig. 13 is a diagram showing the semiconductor substrate 12 when broken along the line L-L in Fig. 11. Next, the oxide film 31 is removed from within the trench portion 25 using hydrofluoric acid (HF) or the like.
14, 15, and 16, a fixed charge film 26 is continuously formed in the trench portion 25 and on the back surface S1 of the semiconductor substrate 12. Then, an insulator 27 is continuously formed in the space between the sidewall surfaces covered with the fixed charge film 26 and on the back surface S1 of the semiconductor substrate 12. The trench portion 25, the fixed charge film 26, and the insulator 27 form the intra-pixel separation portion 20. For example, a material having a lower light absorption rate than the conductor 23 (doped polysilicon) can be used as the material of the fixed charge film 26 and the material of the insulator 27. For example, a high refractive index material film or a high dielectric film having a negative charge is used as the material of the fixed charge film 26. For example, silicon oxide (SiO ₂ ) is used as the material of the insulator 27. After that, a color filter 13 (see FIG. 2), an on-chip lens 14 (see FIG. 2), and the like are formed on the insulator 27.
Through these steps, the solid-state imaging device 1 shown in FIG. 2 is manufactured.

[1-4 Modifications]
(1) In the first embodiment, the trench portion 25 of the intra-pixel isolation portion 20 is formed from the back surface S1 to the front surface S2 of the semiconductor substrate 12, but other configurations may be adopted. For example, as shown in Fig. 17, the trench portion 25 of the intra-pixel isolation portion 20 may be formed from the back surface S1 of the semiconductor substrate 12 to a position midway between the back surface S1 and the front surface S2.
A process for forming the intra-pixel isolation portion 20 in the case where such a configuration is adopted will be described.
First, after forming the inter-pixel isolation portion 19 shown in FIG. 6 and polishing the back surface S1 side of the semiconductor substrate 12, the trench portion 25 of the intra-pixel isolation portion 20 is formed from the back surface S1 side of the semiconductor substrate 12 as shown in FIG. 18, FIG. 19, and FIG. 20. The trench portion 25 is formed from the back surface S1 to a position halfway between the back surface S1 and the front surface S2, and the side wall surface and the bottom surface form the outline of the intra-pixel isolation portion 20. Next, boron (B) is doped into the side wall surface of the trench portion 25 using a conformal doping technique, and a p-type semiconductor region 16 is formed in the semiconductor substrate 12. FIG. 18 is a diagram showing the semiconductor substrate 12 when broken along the line S-S in FIG. 19. FIG. 19 is a diagram showing the semiconductor substrate 12 when broken along the line Q-Q in FIG. 18. FIG. 20 is a diagram showing the semiconductor substrate 12 when broken along the line R-R in FIG. 18.

21, 22, and 23, a fixed charge film 26 having a negative charge is continuously formed in the trench portion 25 and on the back surface S1 of the semiconductor substrate 12. Then, an insulator 27 is continuously formed in the space between the sidewall surfaces covered with the fixed charge film 26 and on the back surface S1 of the semiconductor substrate 12. The trench portion 25, the fixed charge film 26, and the insulator 27 form the pixel separation portion 20. The material of the fixed charge film 26 and the material of the insulator 27 are materials having a lower light absorption rate than the conductor 23 (doped polysilicon). The material of the fixed charge film 26 is, for example, a high refractive index material film or a high dielectric film having a negative charge, such as hafnium oxide (HfO ₂ ). The material of the insulator 27 is, for example, silicon oxide (SiO ₂ ).

2. Second embodiment
[2-1 Configuration of Main Parts]
Next, a solid-state imaging device 1 according to a second embodiment of the present disclosure will be described. The overall configuration of the solid-state imaging device 1 of the second embodiment is the same as that of Fig. 1, and is therefore omitted from the illustration. Fig. 24 is a diagram corresponding to Fig. 3 of the first embodiment, and is a diagram showing a cross-sectional configuration of the solid-state imaging device 1 of the second embodiment. In Fig. 24, parts corresponding to Fig. 3 are given the same reference numerals, and duplicated explanations will be omitted.
The solid-state imaging device 1 according to the second embodiment differs from the solid-state imaging device 1 according to the first embodiment in the configuration of the intra-pixel isolation section 20. Specifically, the intra-pixel isolation section 20 according to the second embodiment protrudes from the inter-pixel isolation section 19 into a region between the photoelectric conversion sections PD1 and PD2 (also referred to as "two or more photoelectric conversion sections" in a broad sense) in the same pixel 8, and when viewed in the thickness direction of the semiconductor substrate 12, the tip section 35 of the intra-pixel isolation section 20 has a larger line width than the portion between the tip section 35 and the inter-pixel isolation section 19 (hereinafter also referred to as "connection section 36"). That is, the line width Wc of the connection section 36 is smaller than the line width Wd of the tip section 35 (the diameter of the circular section in FIG. 24).

The tip portion 35 has a circular shape when viewed from the thickness direction of the semiconductor substrate 12. In addition, it is formed from the back surface S1 of the semiconductor substrate 12 to the vicinity of the front surface S2 (to the same depth as the inter-pixel separation portion 19). Specifically, the tip portion 35 has a trench portion 37, and a fixed charge film 38 having a negative charge and an insulator 39 arranged in the trench portion 37. The trench portion 37 penetrates the semiconductor substrate 12 from the back surface S1 to the front surface S2 of the semiconductor substrate 12, and the side wall surface forms the outline of the intra-pixel separation portion 20. In addition, the fixed charge film 38 and the insulator 39 are arranged in the space from the back surface S1 to the end position of the tip portion 35 on the front surface S2 side in the trench portion 37. Note that a separation portion 50 (see FIG. 2) is arranged in the space from the end position on the front surface S2 side of the tip portion 35 of the trench portion 37 to the front surface S2. The fixed charge film 38 continuously covers the sidewall surface of the trench portion 37 and the back surface S1 of the semiconductor substrate 12. The fixed charge film 38 can make the periphery of the intra-pixel separation portion 20 into a high hole concentration state, and can suppress the generation of dark current. As the material of the fixed charge film 38, for example, a high refractive index material film or a high dielectric film having a negative charge that can generate fixed charges and strengthen pinning by being formed on the semiconductor substrate 12, similar to the fixed charge film 26 of the first embodiment, can be adopted. For example, an oxide or nitride containing at least one element of hafnium (Hf), aluminum (Al), zirconium (Zr), tantalum (Ta), and titanium (Ti) can be mentioned. The insulator 39 is disposed in the space in the trench portion 37, that is, in the space between the sidewall surfaces covered with the fixed charge film 38. In addition to covering the space within the trench portion 37, the insulator 39 also covers the light receiving surface (rear surface S3; see FIG. 2) of the fixed charge film 38 located on the rear surface S1 of the semiconductor substrate 12. That is, the insulator 39 is continuously disposed within the intra-pixel isolation portion 20 and on the rear surface S1 of the semiconductor substrate 12. As a material for the insulator 39, for example, silicon oxide ( _SiO2 ) can be used.

The connecting portion 36 has a strip shape extending along the column direction (the vertical direction in FIG. 24) when viewed from the thickness direction of the semiconductor substrate 12. Also, it is formed from the back surface S1 of the semiconductor substrate 12 to the vicinity of the front surface S2 (to the same depth as the tip portion 35). Specifically, the connecting portion 36 has a trench portion 40 and an insulator 41 arranged in the trench portion 40. The trench portion 40 penetrates the semiconductor substrate 12 from the back surface S1 to the front surface S2 of the semiconductor substrate 12, and the side wall surface forms the outline of the intra-pixel separation portion 20. Also, the insulator 41 is arranged in the space from the back surface S1 to the end position of the connecting portion 36 on the front surface S2 side in the trench portion 40. That is, only the insulator 41 is arranged in the connecting portion 36. Also, the insulator 41 is integrated with the insulator 22 of the inter-pixel separation portion 19. The same material (SiO ₂ ) as the insulator 22 of the inter-pixel separation portion 19 is used as the material of the insulator 41. An isolation portion 50 (see FIG. 2) is disposed in the space between the end position of the trench portion 40 on the surface S2 side of the connection portion 36 and the surface S2.
When viewed in the thickness direction of the semiconductor substrate 12, the line width Wd of the tip 35 of the intra-pixel isolation portion 20 is larger than the line width Wc of the connection portion 36 located on the inter-pixel isolation portion 19 side (Wc<Wd). As the line width Wd of the tip 35, for example, the maximum value of the width of the tip 35 in the row direction (left-right direction in FIG. 24) is used. The line width Wc of the connection portion 36 (trench portion 40) is constant at each point in the column direction and is equal to or less than twice the film thickness We of the insulator 22.

[2-2 Manufacturing method of solid-state imaging device]
Next, a method for manufacturing the solid-state imaging device 1 according to the second embodiment will be described.
First, as shown in FIG. 25, the trench portion 21 of the inter-pixel isolation portion 19 and the trench portion of the intra-pixel isolation portion 20 (the trench portion 37 of the tip portion 35 and the trench portion 40 of the connection portion 36) are formed on the surface S2 of the semiconductor substrate 12 using lithography and dry etching. The line width Wc of the trench portion 40 of the connection portion 36 is set to be equal to or less than twice the film thickness We of the insulator 22 (see FIG. 24) (Wc≦We×2). The line width Wc of the trench portion 40 may be formed to be wider than We×2, and then the sidewall surface of the trench portion 40 may be epitaxially grown to be equal to or less than We×2. Next, as shown in FIG. 26, the sidewall surfaces of the trench portions 21, 37, and 40 are doped with boron (B) using a conformal doping technique to form a p-type semiconductor region 16 in the semiconductor substrate 12. Next, by using a chemical vapor deposition method, the insulators 22, 41, 42 are continuously formed on the sidewall and bottom surfaces of the trench portions 21, 37, 40 so that the trench portion 40 of the connection portion 36 is closed. Specifically, a silicon oxide (SiO ₂ ) film is formed on the inner wall surfaces of the trench portions 21, 37, 40, and layers of the insulators 22, 41, 42 are formed in the trench portions 21, 37, 40 so as to cover the inner wall and bottom surfaces of the trench portions 21, 37, 40. The layers of the insulators 22, 41, 42 grow from the inner wall and bottom surfaces of the trench portions 21, 37, 40, and when the thickness of the layers of the insulators 22, 41, 42 reaches 1/2 the width of the trench portion 40 of the connection portion 36, the trench portion 40 is closed with the insulator 41. Next, conductors 23, 43 are embedded in the space of trench portion 21 covered with insulator 22 and in the space within trench portion 37 covered with insulator 42. The conductor 23 in trench portion 21 and the conductor 43 within trench portion 37 are separated by trench portion 40 blocked with insulator 41. The conductors 23, 43 are made of, for example, doped polysilicon. The trench portion 21, insulator 22, and conductor 23 form inter-pixel isolation portion 19. Silicon oxide (SiO) is embedded on the surface S2 side of trench portions 21, 37, 40 to form isolation portion 50 (see FIG. 2).

Next, after the semiconductor substrate 12 is turned upside down, a polishing process such as CMP (Chemical Mechanical Polishing) is performed on the back surface S1 side of the semiconductor substrate 12. Next, as shown in FIG. 27, the conductor 43 is selectively removed from the trench portion 37 of the tip portion 35 using a mixed solution of fluoronitric acid and acetic acid, etc. Next, the insulator 42 is removed from the trench portion 37 using hydrofluoric acid (HF), etc. Next, as shown in FIG. 24, a fixed charge film 38 is continuously formed in the trench portion 37 of the tip portion 35 and on the back surface S1 of the semiconductor substrate 12. Next, an insulator 39 is continuously formed in the space in the trench portion 37 covered with the fixed charge film 38 and on the back surface S1 of the semiconductor substrate 12. The trench portion 37, the fixed charge film 38, and the insulator 39 form the intra-pixel separation portion 20. The fixed charge film 38 and the insulator 39 are made of a material having a lower light absorption rate than the conductor 23 (polysilicon doped with boron), for example. The fixed charge film 38 is made of a negatively charged high refractive index material film or a high dielectric film, for example. The insulator 39 is made of silicon oxide (SiO ₂ ), for example. After that, the color filter 13, the on-chip lens 14, etc. are formed on the insulator 39.
Through these steps, the solid-state imaging device 1 shown in FIG. 2 is manufactured.

[2-3 Modifications]
(1) In the second embodiment, the trench portions 37, 40 of the intra-pixel isolation portion 20 are formed so as to penetrate the semiconductor substrate 12 from the rear surface S1 to the front surface S2 of the semiconductor substrate 12, but other configurations may be adopted. For example, similar to the modification (1) of the first embodiment shown in FIG. 17, the trench portions 37, 40 of the intra-pixel isolation portion 20 may be formed from the rear surface S1 of the semiconductor substrate 12 to a position midway between the rear surface S1 and the front surface S2.

3. Third embodiment
[3-1 Configuration of Main Parts]
Next, a solid-state imaging device 1 according to a third embodiment of the present disclosure will be described. The overall configuration of the solid-state imaging device 1 of the third embodiment is the same as that of Fig. 1, and is therefore omitted from the illustration. Fig. 28 is a diagram corresponding to Fig. 3 of the first embodiment, and is a diagram showing a cross-sectional configuration of the solid-state imaging device 1 of the third embodiment. In Fig. 28, parts corresponding to Fig. 3 are given the same reference numerals, and duplicated explanations will be omitted.
The solid-state imaging device 1 according to the third embodiment is different from the solid-state imaging devices 1 according to the first and second embodiments in the configuration of the intra-pixel isolation portion 20. Specifically, the intra-pixel isolation portion 20 of the third embodiment is disposed at a position away from the inter-pixel isolation portion 19 within a region surrounded by the inter-pixel isolation portion 19 when viewed in the thickness direction of the semiconductor substrate 12.

When viewed from the thickness direction of the semiconductor substrate 12, the intra-pixel isolation section 20 is formed in a band shape extending along the column direction (up-down direction in FIG. 28) passing through the center of the pixel 8 in the region between the photoelectric conversion units PD1 and PD2 in the same pixel 8. Each of the column direction ends (upper end and lower end in FIG. 28) of the intra-pixel isolation section 20 is separated from the linear portion of the inter-pixel isolation section 19 extending along the row direction (left-right direction in FIG. 28) so as to have gaps 45 and 46 between the intra-pixel isolation section 20 and the linear portion. As a result, when viewed from the thickness direction of the semiconductor substrate 12, the intra-pixel isolation section 20 is disposed at a position away from the inter-pixel isolation section 19 within the region surrounded by the inter-pixel isolation section 19. The gaps 45 and 46 function as an overflow path that allows the passage of electric charge from one side to the other side between the adjacent photoelectric conversion units PD1 and PD2. In addition, the trench portion 25 of the intra-pixel isolation portion 20 is formed to penetrate the semiconductor substrate 12 from the rear surface S1 to the front surface S2 of the semiconductor substrate 12, similar to the first embodiment shown in FIG. 2.

[3-2 Modifications]
(1) In the third embodiment, the gaps 45 and 46 are formed between the column-side ends (the upper end and the lower end in FIG. 28 ) of the intra-pixel separation unit 20 and the linear portion of the inter-pixel separation unit 19 extending along the row direction (the left-right direction in FIG. 28 ), respectively. However, other configurations may be adopted. For example, as shown in FIG. 29 , a configuration may be adopted in which a gap is formed only at one of the column-side ends (the upper end and the lower end in FIG. 29 ) of the intra-pixel separation unit 20. FIG. 29 illustrates a configuration having only the gap 45 of the gaps 45 and 46 shown in FIG. 28 . Specifically, the intra-pixel separation unit 20 is formed in a strip shape extending along the column direction (the up-down direction in FIG. 29 ) from one of a pair of linear portions extending along the row direction (the left-right direction in FIG. 29 ) of the inter-pixel separation unit 19, passing through the center of the pixel 8, when viewed from the thickness direction of the semiconductor substrate 12. The tip end (the end on the upper side in FIG. 29) of intra-pixel separation portion 20 is separated from the linear portion of inter-pixel separation portion 19 that extends along the row direction, forming a gap 45 .

(2) In the third embodiment, the trench portion 25 of the intra-pixel isolation portion 20 is formed so as to penetrate the semiconductor substrate 12 from the back surface S1 to the front surface S2 of the semiconductor substrate 12, but other configurations can also be adopted. For example, similar to the modified example (1) of the first embodiment shown in FIG. 17, the trench portion 25 of the intra-pixel isolation portion 20 may be formed from the back surface S1 of the semiconductor substrate 12 to a position halfway between the back surface S1 and the front surface S2.

4. Fourth embodiment
[4-1 Configuration of Main Parts]
Next, a solid-state imaging device 1 according to a fourth embodiment of the present disclosure will be described. The overall configuration of the solid-state imaging device 1 of the fourth embodiment is the same as that of Fig. 1, and therefore is not illustrated. Fig. 30 is a diagram corresponding to Fig. 3 of the first embodiment, and is a diagram showing a cross-sectional configuration of the solid-state imaging device 1 of the fourth embodiment. In Fig. 30, parts corresponding to Fig. 3 are given the same reference numerals, and duplicated explanations are omitted.
The solid-state imaging device 1 according to the fourth embodiment differs from the solid-state imaging device 1 according to the first embodiment in the configuration of the on-chip lens 14 and the configuration of the intra-pixel separation section 20. Specifically, as shown in Fig. 30, the on-chip lens 14 of the fourth embodiment is shared by 2 x 2 photoelectric conversion units PD1, PD2, PD3, and PD4. That is, 2 x 2 photoelectric conversion units PD1, PD2, PD3, and PD4 are used as "two or more photoelectric conversion units". Moreover, the intra-pixel separation section 20 is formed in a cross shape that divides the area surrounded by the inter-pixel separation section 19 into each of the photoelectric conversion units PD1, PD2, PD3, and PD4 when viewed from the thickness direction of the semiconductor substrate 12.

The semiconductor substrate 12 has a first region R1, a second region R2, a third region R3, and a fourth region R4, each of which corresponds to one of the pixels 8. When viewed from the thickness direction of the semiconductor substrate 12, the first region R1, the second region R2, the third region R3, and the fourth region R4 are arranged in a 2x2 two-dimensional array adjacent to each other in the row direction (left-right direction in FIG. 30) and the column direction (up-down direction in FIG. 30), and each is formed in a square shape. A photoelectric conversion unit PD1 is formed in the first region R1, and similarly, a photoelectric conversion unit PD2 is formed in the second region R2, a photoelectric conversion unit PD3 is formed in the third region R3, and a photoelectric conversion unit PD4 is formed in the fourth region R4. That is, four photoelectric conversion units PD1, PD2, PD3, and PD4 (broadly speaking, also called "two or more photoelectric conversion units") are formed for each pixel 8 on the semiconductor substrate 12, and the multiple photoelectric conversion units PD1, PD2, PD3, and PD4 are arranged in a two-dimensional array.

When viewed from the thickness direction of the semiconductor substrate 12, the intra-pixel separation portion 20 is formed in a cross shape extending from the center of the pixel 8 along both the row direction (left-right direction in FIG. 30) and the column direction (up-down direction in FIG. 30) to the inter-pixel separation portion 19. The intra-pixel separation portion 20 is formed from the rear surface S1 of the semiconductor substrate 12 to near the front surface S2 (to the same depth as the inter-pixel separation portion 19).
The color filters 13 and on-chip lenses 14 are arranged in a two-dimensional array on the rear surface S1 side of the semiconductor substrate 12 so that one color filter 13 and one on-chip lens 14 are arranged for one pixel 8. That is, a shared color filter 13 is arranged for the photoelectric conversion units PD1 to PD4 (also referred to as "two or more photoelectric conversion units" in a broad sense) in the same pixel 8. Also, a shared on-chip lens 14 is arranged for the photoelectric conversion units PD1 to PD4 (also referred to as "two or more photoelectric conversion units" in a broad sense) in the same pixel 8.

[4-2 Modifications]
(1) In the fourth embodiment, the intra-pixel separation section 20 is formed in a cross shape in the region surrounded by the inter-pixel separation section 19, but other configurations can also be adopted. For example, as shown in FIG. 31, a configuration in which a region overlapping with a region located at the center of the pixel 8 is omitted from the intra-pixel separation section 20 shown in FIG. 30 may be used. That is, when viewed from the thickness direction of the semiconductor substrate 12, the intra-pixel separation section 20 is formed in a cross shape in which a portion overlapping with a region located at the center of the block of 2×2 photoelectric conversion units PD1 to PD4 (hereinafter also referred to as a "center region 44") is omitted so that the region surrounded by the inter-pixel separation section 19 is divided into each of the photoelectric conversion units PD1, PD2, PD3, and PD4. With this configuration, for example, a floating diffusion (not shown) that is shared by the photoelectric conversion units PD1 to PD4 and to which the signal charges of the photoelectric conversion units PD1 to PD4 are transferred can be arranged on the surface S2 side of the center region 44 of the semiconductor substrate 12.

(2) In the fourth embodiment, the trench portion 25 of the intra-pixel isolation portion 20 is formed so as to penetrate the semiconductor substrate 12 from the back surface S1 to the front surface S2 of the semiconductor substrate 12, but other configurations can also be adopted. For example, similar to the modified example (1) of the first embodiment shown in FIG. 17, the trench portion 25 of the intra-pixel isolation portion 20 may be formed from the back surface S1 of the semiconductor substrate 12 to a position midway between the back surface S1 and the front surface S2.

(3) Furthermore, this technology can be applied to light detection devices in general, including distance measuring sensors that measure distance, also known as ToF (Time of Flight) sensors, in addition to the solid-state imaging device 1 as the image sensor described above. A distance measuring sensor is a sensor that emits light toward an object, detects the reflected light that is reflected back from the surface of the object, and calculates the distance to the object based on the flight time from when the light is emitted to when the reflected light is received. The structure of pixel 8 described above can be adopted as the light receiving pixel structure of this distance measuring sensor.

5. Fifth embodiment
The technology according to the present disclosure (the present technology) may be applied to various electronic devices.
FIG. 32 is a diagram showing an example of a schematic configuration of an imaging device (such as a video camera or a digital still camera) as an electronic device to which the present technology is applied.
32, the imaging device 1000 includes a lens group 1001, a solid-state imaging device 1002 (solid-state imaging device 1 according to the first embodiment), a DSP (Digital Signal Processor) circuit 1003, a frame memory 1004, a monitor 1005, and a memory 1006. The DSP circuit 1003, the frame memory 1004, the monitor 1005, and the memory 1006 are connected to each other via a bus line 1007.

The lens group 1001 guides incident light (image light) from a subject to the solid-state imaging device 1002 , and forms an image on the light receiving surface (pixel region) of the solid-state imaging device 1002 .
The solid-state imaging device 1002 is made up of the CMOS image sensor according to the first embodiment described above. The solid-state imaging device 1002 converts the amount of incident light focused on the light receiving surface by the lens group 1001 into an electrical signal on a pixel-by-pixel basis and supplies the signal to the DSP circuit 1003 as a pixel signal.
The DSP circuit 1003 performs predetermined image processing on the pixel signals supplied from the solid-state imaging device 1002. Then, the DSP circuit 1003 supplies the image signals after the image processing to a frame memory 1004 on a frame-by-frame basis, and causes the image signals to be temporarily stored in the frame memory 1004.
The monitor 1005 is formed of a panel-type display device such as a liquid crystal panel, an organic EL (Electro Luminescence) panel, etc. The monitor 1005 displays an image (moving image) of a subject based on pixel signals in frame units temporarily stored in the frame memory 1004.
The memory 1006 is composed of a DVD, a flash memory, etc. The memory 1006 reads out and records the pixel signals temporarily stored in the frame memory 1004 on a frame-by-frame basis.

The electronic device to which the solid-state imaging device 1 can be applied is not limited to the imaging device 1000, but can also be applied to other electronic devices. In addition, although the solid-state imaging device 1 according to the first embodiment is used as the solid-state imaging device 1002, other configurations can also be adopted. For example, the solid-state imaging device 1 according to the second to fourth embodiments, the solid-state imaging device 1 according to the modified examples, or other light detection devices to which the present technology is applied can also be used.

The present technology can also be configured as follows.
(1)
a semiconductor substrate having a first surface onto which light is incident and a second surface located on the opposite side to the first surface;
A plurality of photoelectric conversion units formed in a two-dimensional array on the semiconductor substrate;
a pixel isolation structure formed between the photoelectric conversion units of the semiconductor substrate;
an on-chip lens disposed on the first surface side of the semiconductor substrate and shared by two or more of the photoelectric conversion units;
the pixel isolation structure includes an inter-pixel isolation portion surrounding the two or more photoelectric conversion portions, and an intra-pixel isolation portion located between the photoelectric conversion portions within a region surrounded by the inter-pixel isolation portion,
a conductor is disposed within the inter-pixel isolation portion,
a low absorptivity member having a lower light absorptivity than the conductor is disposed within the pixel isolation portion.
(2)
the inter-pixel isolation portion has a trench portion formed so as to penetrate the semiconductor substrate from the first surface to the second surface, and the conductor disposed in the trench portion;
The photodetector according to any one of claims 1 to 4, wherein the semiconductor substrate includes a p-type semiconductor region formed on a side wall surface of the inter-pixel isolation portion.
(3)
The photodetector according to any one of (1) to (2), wherein the conductor is a conductor to which a negative bias voltage is applied.
(4)
the intra-pixel isolation portion includes a trench portion formed so as to penetrate the semiconductor substrate from the first surface to the second surface, and the low absorption rate member disposed in the trench portion;
The optical detection device according to any one of (1) to (3).
(5)
the intra-pixel isolation portion includes a trench portion formed from the first surface to a position midway between the first surface and the second surface, and the low absorption rate member disposed in the trench portion;
The optical detection device according to any one of (1) to (3).
(6)
The photodetector according to any one of (1) to (5), wherein the intra-pixel isolation portion has a fixed charge film having negative charges and constituting a side wall of the intra-pixel isolation portion.
(7)
The photodetector device described in (6), wherein the intra-pixel isolation portion protrudes from the inter-pixel isolation portion into a region between the two or more photoelectric conversion portions, and when viewed in the thickness direction of the semiconductor substrate, has a constant line width from a base portion located on the inter-pixel isolation portion side to a tip portion.
(8)
the intra-pixel isolation portion protrudes from the inter-pixel isolation portion into a region between the two or more photoelectric conversion portions, and when viewed in a thickness direction of the semiconductor substrate, a tip portion of the intra-pixel isolation portion has a line width larger than that of a connection portion which is a portion between the tip portion and the inter-pixel isolation portion,
The photodetector according to any one of (1) to (5), wherein only an insulator is disposed within the connection portion.
(9)
The photodetector device described in (6), wherein the intra-pixel isolation portion is disposed at a position away from the inter-pixel isolation portion within a region surrounded by the inter-pixel isolation portion when viewed in a thickness direction of the semiconductor substrate.
(10)
The two or more photoelectric conversion units are 2×2 photoelectric conversion units,
The photodetector device described in (6), wherein the intra-pixel isolation portion is formed in a cross shape that divides the area surrounded by the inter-pixel isolation portion into each of the photoelectric conversion portions when viewed in the thickness direction of the semiconductor substrate.
(11)
The two or more photoelectric conversion units are 2×2 photoelectric conversion units,
The photodetector device described in (6) above, in which the intra-pixel isolation portion is formed in a cross shape with the overlapping portion with the area located at the center of the 2 x 2 blocks of photoelectric conversion units omitted, so that the area surrounded by the inter-pixel isolation portion is divided for each photoelectric conversion unit when viewed in the thickness direction of the semiconductor substrate.
(12)
The photodetector according to any one of (1) to (11), wherein the conductor is doped polysilicon.
(13)
1. An electronic device comprising: a semiconductor substrate having a first surface through which light is incident and a second surface located opposite to the first surface; a plurality of photoelectric conversion units formed in a two-dimensional array on the semiconductor substrate; a pixel isolation structure formed between the photoelectric conversion units of the semiconductor substrate; and an on-chip lens located on the first surface side of the semiconductor substrate and shared by two or more of the photoelectric conversion units, the pixel isolation structure having an inter-pixel isolation unit surrounding the two or more photoelectric conversion units and an intra-pixel isolation unit located between the photoelectric conversion units in a region surrounded by the inter-pixel isolation unit, a conductor is arranged in the inter-pixel isolation unit, and only a low absorptance material having a lower light absorptance than the conductor is arranged in the intra-pixel isolation unit.

1...solid-state imaging device, 2...pixel region, 3...vertical drive circuit, 4...column signal processing circuit, 5...horizontal drive circuit, 6...output circuit, 7...control circuit, 8...pixel, 9...pixel drive wiring, 10...vertical signal line, 11...horizontal signal line, 12...semiconductor substrate, 13...color filter, 14...on-chip lens, 15...wiring layer, 16...semiconductor region, 18...pixel separation structure, 19...inter-pixel separation section, 20...inside pixel Isolation portion, 21...trench portion, 22...insulator, 23...conductor, 24...gap, 25...trench portion, 26...fixed charge film, 27...insulator, 31...oxide film, 32...filling material, 35...tip portion, 36...connection portion, 37...trench portion, 38...fixed charge film, 39...insulator, 40...trench portion, 41...insulator, 42...insulator, 43...conductor, 44...center region, 45...gap, 46...gap, 50...isolation portion

Claims (13)

a semiconductor substrate having a first surface onto which light is incident and a second surface located on the opposite side to the first surface;
A plurality of photoelectric conversion units formed in a two-dimensional array on the semiconductor substrate;
a pixel isolation structure formed between the photoelectric conversion units of the semiconductor substrate;
an on-chip lens disposed on the first surface side of the semiconductor substrate and shared by two or more of the photoelectric conversion units;
the pixel isolation structure includes an inter-pixel isolation portion surrounding the two or more photoelectric conversion portions, and an intra-pixel isolation portion located between the photoelectric conversion portions within a region surrounded by the inter-pixel isolation portion,
a conductor is disposed within the inter-pixel isolation portion,
a low absorptivity member having a lower light absorptivity than the conductor is disposed within the pixel isolation portion. the inter-pixel isolation portion has a trench portion formed so as to penetrate the semiconductor substrate from the first surface to the second surface, and the conductor disposed in the trench portion;
The photodetector according to claim 1 , wherein the semiconductor substrate includes a p-type semiconductor region formed on a side wall surface of the inter-pixel isolation portion. The photodetector according to claim 1 , wherein the conductor is a conductor to which a negative bias voltage is applied. the intra-pixel isolation portion includes a trench portion formed so as to penetrate the semiconductor substrate from the first surface to the second surface, and the low absorption rate member disposed in the trench portion;
2. The optical detection device according to claim 1. the intra-pixel isolation portion includes a trench portion formed from the first surface to a position midway between the first surface and the second surface, and the low absorption rate member disposed in the trench portion;
2. The optical detection device according to claim 1. The photodetector according to claim 1 , wherein the intra-pixel isolation portion has a fixed charge film having negative charges and constituting a side wall of the intra-pixel isolation portion. The photodetection device of claim 6, wherein the intra-pixel separation portion protrudes from the inter-pixel separation portion into a region between the two or more photoelectric conversion portions, and when viewed in the thickness direction of the semiconductor substrate, the intra-pixel separation portion has a constant line width from a base portion located on the inter-pixel separation portion side to a tip portion. the intra-pixel isolation portion protrudes from the inter-pixel isolation portion into a region between the two or more photoelectric conversion portions, and when viewed in a thickness direction of the semiconductor substrate, a tip portion of the intra-pixel isolation portion has a line width larger than that of a connection portion which is a portion between the tip portion and the inter-pixel isolation portion,
The photodetector according to claim 1 , wherein only an insulator is disposed within the connection portion. The photodetector according to claim 6 , wherein the intra-pixel isolation portion is disposed at a position away from the inter-pixel isolation portion within a region surrounded by the inter-pixel isolation portion when viewed in a thickness direction of the semiconductor substrate. The two or more photoelectric conversion units are 2×2 photoelectric conversion units,
The photodetector according to claim 6 , wherein the intra-pixel isolation portion is formed in a cross shape that divides an area surrounded by the inter-pixel isolation portion into each of the photoelectric conversion portions when viewed in a thickness direction of the semiconductor substrate. The two or more photoelectric conversion units are 2×2 photoelectric conversion units,
The photodetector device of claim 6, wherein the intra-pixel isolation portion is formed in a cross shape with the overlapping portion with the area located at the center of the 2 x 2 blocks of photoelectric conversion units omitted, so that, when viewed in the thickness direction of the semiconductor substrate, the area surrounded by the inter-pixel isolation portion is divided into each of the photoelectric conversion units. The photodetector of claim 1 , wherein the conductor is doped polysilicon. 1. An electronic device comprising: a semiconductor substrate having a first surface through which light is incident and a second surface located opposite to the first surface; a plurality of photoelectric conversion units formed in a two-dimensional array on the semiconductor substrate; a pixel isolation structure formed between the photoelectric conversion units of the semiconductor substrate; and an on-chip lens located on the first surface side of the semiconductor substrate and shared by two or more of the photoelectric conversion units, the pixel isolation structure having an inter-pixel isolation unit surrounding the two or more photoelectric conversion units and an intra-pixel isolation unit located between the photoelectric conversion units in a region surrounded by the inter-pixel isolation unit, a conductor is arranged in the inter-pixel isolation unit, and only a low absorptance material having a lower light absorptance than the conductor is arranged in the intra-pixel isolation unit.

Images