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WO2025170367A1 - Procédé mis en œuvre par un dispositif, dispositif et support de stockage - Google Patents

Procédé mis en œuvre par un dispositif, dispositif et support de stockage

Info

Publication number
WO2025170367A1
WO2025170367A1 PCT/KR2025/001847 KR2025001847W WO2025170367A1 WO 2025170367 A1 WO2025170367 A1 WO 2025170367A1 KR 2025001847 W KR2025001847 W KR 2025001847W WO 2025170367 A1 WO2025170367 A1 WO 2025170367A1
Authority
WO
WIPO (PCT)
Prior art keywords
matrix
codeword
size
global
processor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
PCT/KR2025/001847
Other languages
English (en)
Korean (ko)
Inventor
김봉회
하정석
아사드메리엄
손지현
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
LG Electronics Inc
Korea Advanced Institute of Science and Technology KAIST
Original Assignee
LG Electronics Inc
Korea Advanced Institute of Science and Technology KAIST
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by LG Electronics Inc, Korea Advanced Institute of Science and Technology KAIST filed Critical LG Electronics Inc
Publication of WO2025170367A1 publication Critical patent/WO2025170367A1/fr
Pending legal-status Critical Current
Anticipated expiration legal-status Critical

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received

Definitions

  • This specification relates to wireless communication systems.
  • M2M machine-to-machine
  • MTC machine-type communication
  • tablet PCs personal computers
  • eMBB enhanced mobile broadband
  • RAT legacy radio access technology
  • massive machine type communication which connects multiple devices and objects to provide diverse services anytime, anywhere, is a key issue to be considered in next-generation communications.
  • the predetermined column index sequence may be based on the number of decoding iterations required to determine bit values for each of the bits corresponding to the N columns of B G .
  • the predetermined column index sequence may be identical to a sequence obtained by sorting the N column indices of B G in ascending or descending order of the number of iterations, starting from the column index of the column with the fewest number of decoding iterations required to determine the corresponding bit value.
  • wireless communication signals can be transmitted and received efficiently. Consequently, the overall throughput of a wireless communication system can be increased.
  • Some implementations of this specification can reduce the probability of errors occurring during the transmission of transport blocks.
  • the receiver can efficiently recover the portion in which the error occurred.
  • the design complexity of GC LDPC codes for different transport block sizes or different numbers of code blocks can be reduced.
  • a GC LDPC code with excellent error correction performance can be obtained.
  • FIG. 2 is a block diagram illustrating examples of communication devices capable of performing a method according to the present specification
  • Fig. 7 illustrates the parity check matrix H of an LDPC code and the corresponding Tanner graph
  • Figure 21 illustrates the structure of a codeword obtained by concatenating local codewords
  • Figure 27 is an example of a base matrix for local codewords that may be used in some implementations of the present specification.
  • Figure 28 illustrates a 3-by-3 elementary matrix represented as an integer grid
  • FIG. 29 is an example of a basic matrix of a global part according to some implementations of this specification.
  • FIG 30 illustrates the amount of mutual information (MI) per variable node obtained according to the P-EXIT chart analysis for the variable nodes of the basic matrix illustrated in Figure 27;
  • FIG. 31 is another example of a basic matrix of a global part according to some implementations of the present specification.
  • FIG. 32 is another example of a basic matrix of a global part according to some implementations of this specification.
  • Figure 33 is an example of a matrix obtained by expanding the basic matrix of the global family part
  • Figures 34 to 36 illustrate parity check matrices obtained by extending the basic matrices of Figures 29, 31 and 32 for the global part, respectively;
  • Figure 37 illustrates the performance evaluation results of GC LDPC codes according to some implementations of the present specification
  • FIG. 38 illustrates a channel encoding process according to some implementations of the present specification
  • Figure 39 illustrates a channel decoding process according to some implementations of the present specification.
  • CDMA code division multiple access
  • FDMA frequency division multiple access
  • TDMA time division multiple access
  • OFDMA orthogonal frequency division multiple access
  • SC-FDMA single carrier frequency division multiple access
  • MC-FDMA multi-carrier frequency division multiple access
  • CDMA can be implemented in wireless technologies such as Universal Terrestrial Radio Access (UTRA) or CDMA2000.
  • TDMA can be implemented in wireless technologies such as Global System for Mobile communication (GSM), General Packet Radio Service (GPRS), and Enhanced Data Rates for GSM Evolution (EDGE) (i.e., GERAN).
  • GSM Global System for Mobile communication
  • GPRS General Packet Radio Service
  • EDGE Enhanced Data Rates for GSM Evolution
  • OFDMA can be implemented in wireless technologies such as IEEE (Institute of Electrical and Electronics Engineers) 802.11 (WiFi), IEEE 802.16 (WiMAX), IEEE802-20, and E-UTRA (evolved-UTRA).
  • UTRA is part of UMTS (Universal Mobile Telecommunication System)
  • 3GPP (3rd Generation Partnership Project) LTE (Long Term Evolution) is a part of E-UMTS that uses E-UTRA.
  • 3GPP LTE adopts OFDMA in the downlink (DL) and SC-FDMA in the uplink (UL).
  • LTE-A LTE-advanced
  • LTE-A LTE-advanced
  • 3GPP-based communication systems such as LTE and NR.
  • LTE and NR 3GPP-based communication systems
  • the technical features of this specification are not limited to this.
  • the detailed description below is based on a mobile communication system corresponding to a 3GPP LTE/NR system, it can also be applied to any other mobile communication system, except for features specific to 3GPP LTE/NR.
  • 3GPP-based standard documents such as 3GPP TS 36.211, 3GPP TS 36.212, 3GPP TS 36.213, 3GPP TS 36.321, 3GPP TS 36.300 and 3GPP TS 36.331, 3GPP TS 37.213, 3GPP TS 38.211, 3GPP TS 38.212, 3GPP TS 38.213, 3GPP TS 38.214, 3GPP TS 38.300, 3GPP TS 38.331, etc.
  • UE may be fixed or mobile, and includes various devices that communicate with a BS (base station) to transmit and/or receive user data and/or various control information.
  • UE may be called (Terminal Equipment), MS (Mobile Station), MT (Mobile Terminal), UT (User Terminal), SS (Subscribe Station), wireless device, PDA (Personal Digital Assistant), wireless modem, handheld device, etc.
  • BS generally refers to a fixed station that communicates with UE and/or other BS, and exchanges various data and control information with UE and other BS.
  • a node refers to a fixed point that can transmit/receive radio signals by communicating with a UE.
  • Various types of BSs can be used as nodes regardless of their names.
  • BSs, NBs, eNBs, pico-cell eNBs (PeNBs), home eNBs (HeNBs), relays, and repeaters can be nodes.
  • a node may not be a BS.
  • it can be a radio remote head (RRH) or a radio remote unit (RRU).
  • RRHs, RRUs, etc. generally have a lower power level than the BS.
  • RRH/RRU Since an RRH or RRU (hereinafter referred to as RRH/RRU) is generally connected to a BS via a dedicated line such as an optical cable, cooperative communication between an RRH/RRU and a BS can be performed more smoothly than cooperative communication between BSs that are generally connected via a wireless line.
  • Each node is equipped with at least one antenna.
  • the antenna may be a physical antenna, an antenna port, a virtual antenna, or an antenna group.
  • a node is also called a point.
  • a cell refers to a certain geographical area where one or more nodes provide communication services. Therefore, in this specification, communicating with a specific cell may mean communicating with a BS or node that provides communication services to the specific cell.
  • the downlink/uplink signal of a specific cell refers to a downlink/uplink signal from/to a BS or node that provides communication services to the specific cell.
  • a cell that provides uplink/downlink communication services to a UE is specifically referred to as a serving cell.
  • the channel state/quality of a specific cell refers to the channel state/quality of a channel or communication link formed between a BS or node that provides communication services to the specific cell and the UE.
  • a UE can measure a downlink channel state from a specific node using CRS (Cell-specific Reference Signal) resources transmitted by antenna port(s) of the specific node on CRS resources allocated to the specific node and/or CSI-RS (Channel State Information Reference Signal) resources transmitted.
  • CRS Cell-specific Reference Signal
  • CSI-RS Channel State Information Reference Signal
  • 3GPP-based communication systems use the concept of cells to manage radio resources, and cells associated with radio resources are distinguished from cells in geographical areas.
  • a "cell” in a geographical area can be understood as the coverage over which a node can provide a service using a carrier, and a "cell” in a radio resource is associated with a bandwidth (BW), which is a frequency range configured by the carrier. Since downlink coverage, which is the range over which a node can transmit a valid signal, and uplink coverage, which is the range over which a node can receive a valid signal from a UE, depend on the carrier carrying the signal, the coverage of a node is also associated with the coverage of the "cell" of the radio resource used by the node. Therefore, the term "cell” can sometimes be used to mean the coverage of a service provided by a node, sometimes a radio resource, and sometimes the range over which a signal using the radio resource can reach with a valid intensity.
  • BW bandwidth
  • a "cell” associated with radio resources is defined as a combination of downlink resources (DL resources) and uplink resources (UL resources), i.e., a combination of a DL component carrier (CC) and an UL CC.
  • DL resources downlink resources
  • UL resources uplink resources
  • a cell can be configured with DL resources alone or a combination of DL resources and UL resources.
  • the linkage between the carrier frequency of the DL resources (or DL CC) and the carrier frequency of the UL resources (or UL CC) can be indicated by system information.
  • SIB2 System Information Block Type 2
  • the carrier frequency can be the same as or different from the center frequency of each cell or CC.
  • CA carrier aggregation
  • the UE has only one radio resource control (RRC) connection with the network.
  • RRC radio resource control
  • One serving cell provides non-access stratum (NAS) mobility information during RRC connection establishment/re-establishment/handover, and one serving cell provides security input during RRC connection re-establishment/handover.
  • NAS non-access stratum
  • Pcell primary cell
  • a Pcell is a cell operating on the primary frequency where the UE performs the initial connection establishment procedure or initiates the connection re-establishment procedure.
  • Scells secondary cells
  • a Scell can be established after an RRC (Radio Resource Control) connection is established, and is a cell that provides additional radio resources beyond the resources of a special cell (SpCell).
  • the carrier corresponding to a Pcell in downlink is called a downlink primary CC (DL PCC)
  • the carrier corresponding to a Pcell in uplink is called an UL primary CC (DL PCC)
  • the carrier corresponding to an Scell in downlink is called a DL secondary CC (DL SCC)
  • UL SCC UL secondary CC
  • SpCell refers to a Pcell of a master cell group (MCG) or a Pcell of a secondary cell group (SCG).
  • MCG master cell group
  • SCG secondary cell group
  • An MCG is a group of serving cells associated with a master node (e.g., BS) and consists of a SpCell (Pcell) and optionally one or more Scells.
  • a master node e.g., BS
  • Pcell SpCell
  • SCG is a subset of serving cells associated with a secondary node and consists of a PSCell and zero or more Scells.
  • a PSCell is the primary Scell of an SCG.
  • An Scell indicated as a PUCCH Scell belongs to an Scell PUCCH group, and PUCCH transmission of the relevant UCI is performed on the PUCCH Scell, and an Scell where a PUCCH Scell is not indicated or is a Pcell indicated as a cell for PUCCH transmission, belongs to a Pcell PUCCH group, and PUCCH transmission of the relevant UCI is performed on the Pcell.
  • 3GPP-based communication standards define downlink physical channels corresponding to resource elements that carry information originating from higher layers, and downlink physical signals corresponding to resource elements that are used by the physical layer but do not carry information originating from higher layers.
  • the physical downlink shared channel (PDSCH), physical broadcast channel (PBCH), and physical downlink control channel (PDCCH) are defined as downlink physical channels
  • reference signals and synchronization signals are defined as downlink physical signals.
  • a reference signal (RS) also referred to as a pilot, refers to a signal with a predefined special waveform that is known to the BS and UE.
  • DMRS demodulation reference signal
  • CSI-RS channel state information RS
  • next-generation RATs that take advanced mobile broadband communication, massive MTC, and URLLC (Ultra-Reliable and Low Latency Communication) into account is currently under discussion.
  • 3GPP is currently conducting studies on next-generation mobile communication systems beyond EPC. For convenience, this technology is referred to as new RAT (NR) or 5G RAT, and a system that uses or supports NR is referred to as an NR system.
  • NR new RAT
  • 5G RAT 5G RAT
  • FIG. 1 illustrates an example of a communication system 1 to which implementations of the present specification are applied.
  • the communication system (1) applied to the present specification includes a wireless device, a BS, and a network.
  • the wireless device refers to a device that performs communication using a wireless access technology (e.g., 5G NR (New RAT), LTE (e.g., E-UTRA)) and may be referred to as a communication/wireless/5G device.
  • 5G NR New RAT
  • LTE e.g., E-UTRA
  • the wireless device may include a robot (100a), a vehicle (100b-1, 100b-2), an XR (eXtended Reality) device (100c), a hand-held device (100d), a home appliance (100e), an IoT (Internet of Things) device (100f), and an AI device/server (400).
  • the vehicle may include a vehicle equipped with a wireless communication function, an autonomous vehicle, a vehicle capable of performing vehicle-to-vehicle communication, etc.
  • the vehicle may include an Unmanned Aerial Vehicle (UAV) (e.g., a drone).
  • UAV Unmanned Aerial Vehicle
  • Wireless devices (100a to 100f) can be connected to a network (300) via a BS (200). Artificial Intelligence (AI) technology can be applied to the wireless devices (100a to 100f), and the wireless devices (100a to 100f) can be connected to an AI server (400) via the network (300).
  • the network (300) can be configured using a 3G network, a 4G (e.g., LTE) network, a 5G (e.g., NR) network, etc.
  • the wireless devices (100a to 100f) can communicate with each other via the BS (200)/network (300), but can also communicate directly (e.g., sidelink communication) without going through the BS/network.
  • vehicles can communicate directly (e.g., V2V (Vehicle to Vehicle)/V2X (Vehicle to everything) communication).
  • IoT devices e.g., sensors
  • IoT devices can communicate directly with other IoT devices (e.g., sensors) or other wireless devices (100a to 100f).
  • various configuration information setting processes for transmitting/receiving wireless signals various signal processing processes (e.g., channel encoding/decoding, modulation/demodulation, resource mapping/demapping, etc.), and resource allocation processes can be performed based on various proposals of this specification.
  • various signal processing processes e.g., channel encoding/decoding, modulation/demodulation, resource mapping/demapping, etc.
  • resource allocation processes can be performed based on various proposals of this specification.
  • FIG. 2 is a block diagram illustrating examples of communication devices capable of performing a method according to the present specification.
  • a first wireless device (100) and a second wireless device (200) can transmit and/or receive wireless signals via various wireless access technologies (e.g., LTE, NR).
  • ⁇ the first wireless device (100), the second wireless device (200) ⁇ can correspond to ⁇ the wireless device (100x), the BS (200) ⁇ and/or ⁇ the wireless device (100x), the wireless device (100x) ⁇ of FIG. 1.
  • a first wireless device (100) includes one or more processors (102) and one or more memories (104), and may further include one or more transceivers (106) and/or one or more antennas (108).
  • the processor (102) controls the memories (104) and/or the transceivers (106), and may be configured to implement functions, procedures, and/or methods described/suggested below.
  • the processor (102) may process information in the memory (104) to generate first information/signals, and then transmit a wireless signal including the first information/signals via the transceivers (106).
  • the processor (102) may receive a wireless signal including second information/signals via the transceivers (106), and then store information obtained from signal processing of the second information/signals in the memory (104).
  • the memory (104) may be connected to the processor (102) and may store various information related to the operation of the processor (102). For example, the memory (104) may perform some or all of the processes controlled by the processor (102), or may store software code including commands for performing the procedures and/or methods described/proposed below.
  • the processor (102) and the memory (104) may be part of a communication modem/circuit/chip designed to implement wireless communication technology (e.g., LTE, NR).
  • the transceiver (106) may be connected to the processor (102) and may transmit and/or receive wireless signals via one or more antennas (108).
  • the transceiver (106) may include a transmitter and/or a receiver.
  • the transceiver (106) may be used interchangeably with an RF (Radio Frequency) unit.
  • a wireless device may also mean a communication modem/circuit/chip.
  • the second wireless device (200) includes one or more processors (202), one or more memories (204), and may further include one or more transceivers (206) and/or one or more antennas (208).
  • the processor (202) controls the memories (204) and/or the transceivers (206), and may be configured to implement the functions, procedures, and/or methods described/suggested below.
  • the processor (202) may process information in the memory (204) to generate third information/signals, and then transmit a wireless signal including the third information/signals via the transceivers (206).
  • the processor (202) may receive a wireless signal including fourth information/signals via the transceivers (206), and then store information obtained from signal processing of the fourth information/signals in the memory (204).
  • the memory (204) may be connected to the processor (202) and may store various information related to the operation of the processor (202). For example, the memory (204) may perform some or all of the processes controlled by the processor (202), or may store software code including commands for performing the procedures and/or methods described/proposed below.
  • the processor (202) and the memory (204) may be part of a communication modem/circuit/chip designed to implement wireless communication technology (e.g., LTE, NR).
  • the transceiver (206) may be connected to the processor (202) and may transmit and/or receive wireless signals via one or more antennas (208).
  • the transceiver (206) may include a transmitter and/or a receiver.
  • the transceiver (206) may be used interchangeably with an RF unit.
  • a wireless device may also mean a communication modem/circuit/chip.
  • the wireless communication technology implemented in the wireless device (100, 200) of the present specification may include not only LTE, NR, and 6G, but also Narrowband Internet of Things for low-power communication.
  • NB-IoT technology may be an example of LPWAN (Low Power Wide Area Network) technology, and may be implemented with standards such as LTE Cat NB1 and/or LTE Cat NB2, and is not limited to the above-described names.
  • the wireless communication technology implemented in the wireless device (XXX, YYY) of the present specification may perform communication based on LTE-M technology.
  • LTE-M technology may be an example of LPWAN technology, and may be called by various names such as eMTC (enhanced Machine Type Communication).
  • LTE-M technology can be implemented by at least one of various standards such as 1) LTE CAT 0, 2) LTE Cat M1, 3) LTE Cat M2, 4) LTE non-BL (non-Bandwidth Limited), 5) LTE-MTC, 6) LTE Machine Type Communication, and/or 7) LTE M, and is not limited to the above-described names.
  • the wireless communication technology implemented in the wireless device (XXX, YYY) of the present specification can include at least one of ZigBee, Bluetooth, and Low Power Wide Area Network (LPWAN) considering low-power communication, and is not limited to the above-described names.
  • ZigBee technology can create PAN (personal area networks) related to small/low-power digital communication based on various standards such as IEEE 802.15.4, and can be called by various names.
  • one or more protocol layers may be implemented by one or more processors (102, 202).
  • one or more processors (102, 202) may implement one or more layers (e.g., functional layers such as a physical (PHY) layer, a medium access control (MAC) layer, a radio link control (RLC) layer, a packet data convergence protocol (PDCP) layer, a radio resource control (RRC) layer, and a service data adaptation protocol (SDAP) layer).
  • layers e.g., functional layers such as a physical (PHY) layer, a medium access control (MAC) layer, a radio link control (RLC) layer, a packet data convergence protocol (PDCP) layer, a radio resource control (RRC) layer, and a service data adaptation protocol (SDAP) layer).
  • PHY physical
  • MAC medium access control
  • RLC radio link control
  • PDCP packet data convergence protocol
  • RRC radio resource control
  • SDAP service data adaptation protocol
  • One or more processors (102, 202) may generate one or more protocol data units (PDUs) and/or one or more service data units (SDUs) according to the functions, procedures, proposals, and/or methods disclosed in this specification.
  • One or more processors (102, 202) may generate messages, control information, data or information according to the functions, procedures, proposals and/or methods disclosed in this specification.
  • One or more processors (102, 202) may generate signals (e.g., baseband signals) including PDUs, SDUs, messages, control information, data or information according to the functions, procedures, proposals and/or methods disclosed in this specification, and provide the signals to one or more transceivers (106, 206).
  • One or more processors (102, 202) may receive signals (e.g., baseband signals) from one or more transceivers (106, 206) and obtain PDUs, SDUs, messages, control information, data or information according to the functions, procedures, proposals and/or methods disclosed in this specification.
  • signals e.g., baseband signals
  • transceivers e.g., baseband signals
  • One or more processors (102, 202) may be referred to as a controller, a microcontroller, a microprocessor, or a microcomputer.
  • One or more processors (102, 202) may be implemented by hardware, firmware, software, or a combination thereof.
  • ASICs Application Specific Integrated Circuits
  • DSPs Digital Signal Processors
  • DSPDs Digital Signal Processing Devices
  • PLDs Programmable Logic Devices
  • FPGAs Field Programmable Gate Arrays
  • the functions, procedures, proposals, and/or methods disclosed in this specification may be implemented using firmware or software, and the firmware or software may be implemented to include modules, procedures, functions, etc.
  • Firmware or software configured to perform the functions, procedures, suggestions and/or methods disclosed in this specification may be included in one or more processors (102, 202) or stored in one or more memories (104, 204) and executed by one or more processors (102, 202).
  • the functions, procedures, suggestions and/or methods disclosed in this specification may be implemented using firmware or software in the form of codes, instructions and/or sets of instructions.
  • One or more memories (104, 204) may be coupled to one or more processors (102, 202) and may store various forms of data, signals, messages, information, programs, codes, instructions, and/or commands.
  • the one or more memories (104, 204) may be configured as ROM, RAM, EPROM, flash memory, hard drives, registers, cache memory, computer-readable storage media, and/or combinations thereof.
  • the one or more memories (104, 204) may be located internally and/or externally to the one or more processors (102, 202). Additionally, the one or more memories (104, 204) may be coupled to the one or more processors (102, 202) via various technologies, such as wired or wireless connections.
  • One or more transceivers (106, 206) may transmit user data, control information, wireless signals/channels, etc., as described in the methods and/or flowcharts of this specification, to one or more other devices.
  • One or more transceivers (106, 206) may receive user data, control information, wireless signals/channels, etc., as described in the functions, procedures, proposals, methods and/or flowcharts of this specification, from one or more other devices.
  • one or more transceivers (106, 206) may be coupled to one or more processors (102, 202) and may transmit and/or receive wireless signals.
  • one or more processors (102, 202) may control one or more transceivers (106, 206) to transmit user data, control information, or wireless signals to one or more other devices. Additionally, one or more processors (102, 202) may control one or more transceivers (106, 206) to receive user data, control information, or wireless signals from one or more other devices.
  • one or more transceivers (106, 206) may be coupled to one or more antennas (108, 208), and one or more transceivers (106, 206) may be configured to transmit and/or receive user data, control information, wireless signals/channels, or the like, as referred to in the functions, procedures, proposals, methods, and/or operational flowcharts disclosed in this specification, via one or more antennas (108, 208).
  • one or more antennas may be multiple physical antennas or multiple logical antennas (e.g., antenna ports).
  • One or more transceivers (106, 206) may convert received user data, control information, wireless signals/channels, etc.
  • One or more transceivers (106, 206) may convert processed user data, control information, wireless signals/channels, etc. from baseband signals to RF band signals using one or more processors (102, 202).
  • one or more transceivers (106, 206) may include an (analog) oscillator and/or a filter.
  • At least one memory can store instructions or programs that, when executed, cause at least one processor operably connected to the at least one memory to perform operations according to some embodiments or implementations of the present specification.
  • a computer-readable (non-transitory) storage medium can store at least one instruction or computer program, which when executed by at least one processor causes the at least one processor to perform operations according to some embodiments or implementations of this specification.
  • a processing device or apparatus may include at least one processor and at least one computer memory operatively connected to the at least one processor.
  • the at least one computer memory may store instructions or programs, which, when executed, cause at least one processor operatively connected to the at least one memory to perform operations according to some embodiments or implementations of the present specification.
  • a computer program may be stored in at least one computer-readable (non-transitory) storage medium and may include program code that, when executed, performs operations according to some implementations of the present specification or causes at least one processor to perform operations according to some implementations of the present specification.
  • the computer program may be provided in the form of a computer program product.
  • the computer program product may include at least one computer-readable (non-transitory) storage medium.
  • a communications device of the present specification comprises at least one processor; and at least one computer memory operably connected to said at least one processor and storing instructions that, when executed, cause said at least one processor to perform operations according to the example(s) of the present specification described below.
  • Figure 3 illustrates an example of a frame structure available in a 3GPP-based wireless communication system.
  • the structure of the frame in Fig. 3 is only an example, and the number of subframes, the number of slots, and the number of symbols in the frame can be changed in various ways.
  • OFDM numerology e.g., subcarrier spacing (SCS)
  • SCS subcarrier spacing
  • TTI transmission time interval
  • the symbol may include an OFDM symbol (or a cyclic prefix - orthogonal frequency division multiplexing (CP-OFDM) symbol), an SC-FDMA symbol (or a discrete Fourier transform-spread-OFDM (DFT-s-OFDM) symbol).
  • OFDM symbol or a cyclic prefix - orthogonal frequency division multiplexing (CP-OFDM) symbol
  • SC-FDMA symbol or a discrete Fourier transform-spread-OFDM (DFT-s-OFDM) symbol.
  • DFT-s-OFDM discrete Fourier transform-spread-OFDM
  • uplink and downlink transmissions are organized into frames.
  • Each half-frame consists of five subframes, and the duration T sf of a single subframe (SF) is 1 ms.
  • the subframes are further divided into slots, and the number of slots within a subframe depends on the subcarrier spacing.
  • Each slot consists of 14 or 12 OFDM symbols based on the cyclic prefix. For a normal cyclic prefix (CP), each slot consists of 14 OFDM symbols, and for an extended CP, each slot consists of 12 OFDM symbols.
  • slots are numbered in increasing order within a subframe as n u s ⁇ ⁇ 0, ..., n subframe,u slot - 1 ⁇ and in increasing order within a frame as n u s,f ⁇ ⁇ 0, ..., n frame,u slot - 1 ⁇ .
  • a slot contains multiple (e.g., 14 or 12) symbols in the time domain.
  • a resource grid of N size,u grid,x * N RB sc subcarriers and N subframe,u symb OFDM symbols is defined, starting from a common resource block ( CRB ) N start,u grid indicated by higher - layer signaling (e.g., radio resource control (RRC) signaling).
  • CRB common resource block
  • RRC radio resource control
  • N size ,u grid,x is the number of resource blocks (RBs) in the resource grid
  • the subscript x is DL for downlink and UL for uplink.
  • N RB sc is the number of subcarriers per RB, and in 3GPP-based wireless communication systems, N RB sc is typically 12.
  • the carrier bandwidth N size,u grid for the subcarrier spacing configuration u is given to the UE by higher layer parameters (e.g., RRC parameters) from the network.
  • Each element in the resource grid for antenna port p and subcarrier spacing configuration u is called a resource element (RE), and one complex symbol can be mapped to each RE.
  • Each RE in the resource grid is uniquely identified by an index k in the frequency domain and an index l indicating the symbol position relative to a reference point in the time domain.
  • an RB is defined by 12 consecutive subcarriers in the frequency domain.
  • RBs can be classified into common resource blocks (CRBs) and physical resource blocks (PRBs).
  • CRBs are numbered upwards from 0 in the frequency domain for a subcarrier spacing setting u .
  • the center of subcarrier 0 of CRB 0 for a subcarrier spacing setting u coincides with 'point A', which is a common reference point for resource block grids.
  • PRBs for a subcarrier spacing setting u are defined within a bandwidth part (BWP) and are numbered from 0 to N size,u BWP,i -1, where i is the number of the bandwidth part.
  • BWP bandwidth part
  • n u PRB n u CRB + N start,u BWP,i , where N start,u BWP,i is the common resource block where the bandwidth part starts relative to CRB 0.
  • a BWP includes a plurality of contiguous RBs in the frequency domain.
  • a BWP is a subset of contiguous CRBs defined for a given numerology u i within a BWP i on a given carrier.
  • a carrier may include at most N (e.g., 5) BWPs.
  • a UE may be configured to have one or more BWPs on a given component carrier. Data communication is performed through the activated BWPs, and only a predetermined number (e.g., 1) of BWPs configured for the UE can be activated on the corresponding carrier.
  • a UE configured with carrier aggregation may be configured to use one or more cells. If the UE is configured to have multiple serving cells, the UE may be configured to have one or more cell groups. The UE may be configured to have multiple cell groups associated with different BSs. Alternatively, the UE may be configured to have multiple cell groups associated with a single BS. Each cell group of the UE consists of one or more serving cells, and each cell group includes a single PUCCH cell configured with PUCCH resources.
  • the PUCCH cell may be a Pcell or an Scell configured as a PUCCH cell among the Scells of the corresponding cell group. Each serving cell of the UE belongs to one of the cell groups of the UE and does not belong to multiple cell groups.
  • NR frequency bands are defined by two types of frequency ranges, FR1 and FR2, with FR2 also referred to as millimeter wave (mmW).
  • FR1 and FR2 also referred to as millimeter wave (mmW).
  • mmW millimeter wave
  • Figure 4 illustrates a processing process on the transmission side for a transport block (TB).
  • the transmitter encodes the information it sends using a forward error correction code before transmitting it.
  • the receiver demodulates the received signal and then decodes the error correction code to restore the transmitted information. This decoding process corrects errors in the received signal caused by the wireless channel.
  • Data arrives at the coding block in the form of up to two transport blocks per TTI per DL/UL cell.
  • the following coding steps can be applied to each transport block in a DL/UL cell:
  • transport blocks larger than a certain size are divided into multiple smaller data blocks for encoding. These smaller data blocks are called code blocks.
  • Figure 5 illustrates an example of a transport block encoding process according to several scenarios.
  • a TB CRC may be attached to a TB.
  • the TB CRC may be used to confirm the TB during the decoding process. If the TB CRC attached TB is not larger than a predetermined size, the TB CRC attached TB is encoded by a (channel) encoder. If the TB CRC attached TB is larger than the predetermined size, the TB CRC attached TB may be divided into multiple code blocks (CBs). If the TB CRC attached TB is divided into multiple CBs, in some scenarios, CB CRCs may be attached to each CB. This may result in multiple CB CRC attached CBs.
  • CBs code blocks
  • the CB CRCs may be used to confirm the CBs during the decoding process by the receiver.
  • Each of the above multiple CB CRC attached CBs can be encoded via a (channel) encoder.
  • the CBs will generally have the same size, but due to the size limitation of the internal interleaver of the channel encoder, one of the multiple CBs may have a different size.
  • the above multiple CB CRC attached CBs may be encoded in parallel via respective (channel) encoders, or may be encoded one by one via a single (channel) encoder.
  • interleaving may be performed to reduce the impact of burst errors that occur when transmitting over a wireless channel after an error correction coding process is performed on a CB unit of a fixed interleaver size. Then, they are mapped to actual wireless resources and transmitted. Since the amount of wireless resources used in actual transmission is constant, rate matching must be performed on the encoded code blocks to match this. Rate matching is typically performed by puncturing or repetition.
  • the amount of wireless resources e.g., the number of transmission bits that can be transmitted by the wireless resources
  • the number of coded bit sequences i.e., the number of output bits of an encoder
  • rate matching is performed to adjust the length of the coded bit sequence to match M. If M>N, all or part of the bits of the coded bit sequence are repeated so that the length of the rate-matched sequence becomes equal to M. If M ⁇ N, part of the bits of the coded bit sequence are punctured so that the length of the rate-matched sequence becomes equal to M, and the punctured bits are excluded from transmission.
  • a transmitter encodes data to be transmitted using channel coding having a specific code rate, and then adjusts the code rate of the data to be transmitted through a rate matching process consisting of puncturing and repetition.
  • the output bit sequence after rate matching and code block concatenation is modulated into modulation symbols through a modulator according to a modulation scheme.
  • the modulation symbols are mapped to radio resources allocated by the base station and transmitted to the receiver through the radio resources.
  • the decoding process of the channel code is the reverse process of the encoding process, and a decoder corresponding to each encoder of the transmitter is used in the decoding process performed at the receiver.
  • the receiver performs decoding for each code block (CB), then forms a TB, and finally checks whether the TB CRC passes or fails.
  • the CB CRC is used for fast decoding termination. For example, if the CB CRC fails, the receiver can generate a NACK without decoding other CBs.
  • Figure 6 is a diagram illustrating the concept of the rate matching process.
  • rate matching may be performed after channel coding.
  • rate matching for coded bits may be defined per code block and may consist of sub-block interleaving, bit selection, and bit interleaving. For example, if the input bit sequence to rate matching is denoted as d 0 ,d 1 ,d 2 ,d 3 ,...,d N-1 , and the output bit sequence after rate matching is denoted as f 0 ,f 1 ,f 2 ,f 3 ,...,f E-1 , and the bits input to the sub-block interleavers are denoted as coded bits d 0 ,d 1 ,d 2 ,d 3 ,...,d N-1 , then the coded bits d 0 ,d 1 ,d 2 ,d 3 ,...,d N-1 may be divided into multiple sub-blocks.
  • E may be a value determined based on the size of the radio resources scheduled for the corresponding transport block. It may be a predetermined or predefined length for the corresponding code block. If the bits output from the sub-block interleavers are denoted as y 0 , y 1 , y 2 , y 3 ,..., y N-1 , the bit sequence y 0 , y 1 , y 2 , y 3 ,..., y N-1 after sub-block interleaving is written to a circular buffer of length N.
  • the coded bits d 0 , d 1 , d 2 , d 3 ,..., d N-1 are written to a circular buffer of length N.
  • Bits of the rate-matching output sequence length E from the circular buffer are output as transmission bits.
  • rate-matched outputs for different code blocks can be sequentially concatenated.
  • Hybrid automatic request is a technology that combines forward error correction (FEC) and automatic repeat request (ARQ).
  • FEC forward error correction
  • ARQ automatic repeat request
  • a transmitter transmits all or part of the encoded coded bits using FEC, and a receiver detects whether there are errors in the received data and transmits a HARQ-ACK signal indicating an acknowledgment (ACK) or negative ACK (NACK) of the received data to the transmitter. If the receiver determines that the received data is error-free or below a certain threshold, the transmitter transmits new data. On the other hand, if the receiver determines that the received data contains errors or exceeds a certain threshold, the transmitter retransmits the corresponding data block.
  • FEC forward error correction
  • ARQ automatic repeat request
  • the receiver combines the retransmitted data block with a previously transmitted data block and decodes it again to detect errors. This operation can be repeated until no errors are detected or until a predetermined number of errors are detected.
  • the combining methods for decoding retransmitted data blocks can be divided into the following two types.
  • Chase combining For combining at the receiver, the transmitter retransmits coded bits identical to the initially transmitted coded bits. Chase combining can reduce the error probability through power gain during decoding of retransmitted data blocks.
  • Incremental redundancy For combining at the receiver, the transmitter retransmits coded bits that are not identical to the coded bits that were initially transmitted. For example, the transmitter sends the redundancy that was not sent in the initial transmission to the receiver in the retransmission. Since the redundancy that was not sent in the previous transmission is sent in the retransmission, the redundancy of the previous transmission and the redundancy of the current transmission are combined to increase the redundancy, which has the effect of lowering the code rate. In other words, incremental redundancy can reduce the error probability through coding gain when decoding retransmitted data blocks. In general, since chase combining corresponds to the case where there is no incremental redundancy among incremental redundancies, chase combining can be interpreted as a special form of incremental redundancy.
  • the receiver In HARQ operation, the receiver generates an ACK or NACK for received or scheduled packets and provides them to the transmitter.
  • a transmitter that receives a NACK for a transmission can retransmit the requested packet.
  • the bits read from the circular buffer and sent in each retransmission may differ depending on the transmission start position determined by the redundancy version (RV). Referring to Figure 6, there are multiple (e.g., four) RVs that define the positions of the starting points from which bits are read from the circular buffer.
  • the circular buffer is a crucial component for rate matching and enables puncturing and/or repetition of coded bits.
  • the coded bits or the output bits after sub-block interleaving of the coded bits are sequentially written to the circular buffer for the mother code.
  • the number of coded bits is read sequentially from the starting point specified by the RV point within the circular buffer.
  • LDPC low-density parity check
  • MAC Wireless LAN Medium Access Control
  • PHY Physical Layer
  • 802.11ac Enhancements for Higher Throughput', March 2006.'
  • DVD digital video broadcasting
  • encoding is performed using a parity check matrix instead of a generator matrix.
  • the parity check matrix of an LDPC code has a very small number of 1s, decoding is possible through iterative decoding even in very large block sizes, and when the block size becomes very large, it shows performance approaching Shannon's channel capacity limit like a turbo code.
  • the number of 1s included in a row or column is called a weight.
  • the LDPC code can be described by an (nk)*n parity check matrix H.
  • the generator matrix G corresponding to the parity check matrix H can be obtained by the following mathematical formula.
  • c is a codeword
  • x are information bits.
  • Figure 7 illustrates the parity check matrix H of an LDPC code and its corresponding Tanner graph.
  • a parity check matrix is a binary matrix that defines the parity check equations of an LDPC code.
  • a parity check matrix defining an LDPC code can be represented by a Tanner graph.
  • the column vector of a parity check matrix is associated with a variable node, and the row vector of a parity check matrix is associated with a check node.
  • the presence of '1' in the i-th row and j-th column of a parity check matrix means that the i-th check node is connected to the j-th variable node. For example, suppose there is the following parity check matrix (PCM) H.
  • PCM parity check matrix
  • the first row of the PCM H i.e., the first check node (CN) is connected to the first, second, third, and fourth variable nodes (VNs), the second CN is connected to the third, fourth, and sixth VNs, and the third CN is connected to the first, fourth, and fifth VNs.
  • VNs variable nodes
  • the Tanner graph is composed of i) VNs representing coded bits, ii) CNs representing parity check equations that the coded bits must satisfy, and iii) edges connecting the VNs and CNs.
  • check nodes are conventionally expressed as rectangles, and variable nodes are expressed as circles.
  • Properties of the PCM H such as row and column weights, are converted into node degrees in the Tanner graph.
  • the sparsely distributed non-zero entries in the PCM H represent edges in the Tanner graph.
  • the sparsity of the non-zero entries allows for efficient decoding of these codes using an iterative decoding algorithm known as the belief propagation (BP) algorithm.
  • BP belief propagation
  • Figure 8 is an example of a systematic codeword structure generated by encoding.
  • the process of mapping message bits to valid codewords is called encoding.
  • the generated codeword x may have the form shown in Fig. 8.
  • Figures 9 and 10 illustrate the parity check matrix H of an LDPC code using a bipartite graph.
  • a '1' in a row represents an edge connected to a check node in the bipartite graph
  • a '1' in a column represents an edge connected to a variable node.
  • Fig. 9(b) illustrates a portion of a bipartite graph corresponding to the parity check matrix illustrated in Fig. 9(a). Referring to Fig. 9(b), the nodes on the left side of the reciprocal graph represent variable nodes, and the nodes on the right side represent check nodes.
  • Figure 10 illustrates another parity check matrix and the entire bipartite lines.
  • the LDPC code reflected in the NR standard can be classified as a quasi-cyclic LDPC (QC-LDPC) code.
  • the QC-LDPC code has a low encoding/decoding complexity and a structure that is advantageous for parallelization.
  • the parity check matrix of the QC-LDPC code can be expressed as an m-by-n array of Z c -by-Z c circulant permutation matrices (CPMs).
  • CPMs circulant permutation matrices
  • the parity check matrix can be obtained by replacing each element in the model matrix or base graph (BG) (also called the base matrix or base code) with a Z c -by-Z c CPM or a Z c -by-Z c zero matrix.
  • BG model matrix or base graph
  • Fig. 11 illustrates circulant permutation matrices (CPMs).
  • CPMs circulant permutation matrices
  • Fig. 11 illustrates a 4 ⁇ 4 CPM.
  • a is a circulant shift value, a non-negative integer, and is obtained by circulantly shifting an identity matrix I of size Z c ⁇ Z c to the right or left a times.
  • the zero matrix is expressed as P ⁇ , but may be expressed differently depending on the definition in the system or standard.
  • each element represents a cyclic shift value of the CPM or a zero matrix.
  • Each element of the LDPC BG is 0 or 1, and each element of value 0 in the LDPC BG is replaced by a zero matrix 0 of size Z c ⁇ Z c , and each element of value 1 in the LDPC BG is replaced by a CPM I (P i,j ), where i and j are the row and column indices of the element, and I (P i,j ) is obtained by cyclically shifting the identity matrix I of size Z c -by-Z c to the right or left P i,j times.
  • the value of V i,j can correspond to a cyclic shift value of the model matrix and may be predefined depending on the system in which the LDPC is used. For example, for 3GPP TS 38.212 Release 15, the values of V i,j are given by Table 5.3.2-2 and Table 5.3.2-3 of 3GPP TS 38.212 Release 15 according to the set index i LS and LDPC BG (see Section 5.3.2 of 3GPSS TS 38.212 Release 15).
  • the BG introduced in the NR standard has the feature of a single parity extension to support low code rates.
  • two BGs are defined, each having eight CPM values (i.e., cyclic shift values for the eight CPMs, respectively).
  • BG1 is advantageous in terms of performance for large data block sizes
  • BG2 is advantageous in terms of decoding latency for small data block sizes and low code rates.
  • FIG. 13 is a diagram illustrating a criterion for selecting an LDPC base graph.
  • a coding rate R i.e., code rate R
  • MCS modulation and coding scheme
  • LDPC BG2 is used; otherwise, LDPC BG1 is used, where A is the payload size, for example, the transport block size (TBS).
  • TBS transport block size
  • CPM sizes i.e., lifting sizes
  • i ⁇ Z ⁇ S j
  • the following table illustrates various sets of Z values obtained using this formula.
  • a transport block (TB), which is transmission data, is a MAC PDU, and the transmitter appends, for example, a 24-bit CRC sequence to the TB and performs LDPC encoding.
  • the TB with the CRC appended is segmented into multiple code blocks (CBs).
  • CBs code blocks
  • code block segmentation is performed if the size of the TB with the CRC appended exceeds 8448 bits
  • code block segmentation is performed if the size of the TB with the CRC appended exceeds 3840 bits.
  • B is the size of the TB with the CRC appended.
  • K cb is 8448 for BG1, 3840 for BG2, and L is 24. If the number of CBs C > 1, a 24-bit CRC is appended to each CB, and then LDPC encoding is performed.
  • bit sequence input for a given code block is denoted as c 0 ,c 1 ,c 2 ,c 3 ,...,c K-1
  • bits after encoding are denoted as d 0 ,d 1 ,d 2 ,d 3 ,...,d N-1
  • K is the number of bits to be encoded
  • N is the number of bits after encoding:
  • the parity check matrix H can be obtained by replacing each element of H BG with a Z c -by-Z c matrix as follows:
  • Each element of value 1 in H BG is replaced by a cyclic permutation matrix I (P i,j ) of size Z c *Z c , where i and j are the row and column indices of the element, and I (P i,j ) is obtained by cyclically shifting the identity matrix I of size Z c -by-Z c to the right or left P i,j times.
  • V i,j are given by Table 5.3.2-2 and Table 5.3.2-3 of 3GPP TS 38.212 Release 15 according to the set index i LS and LDPC BG (see Section 5.3.2 of 3GPSS TS 38.212 Release 15).
  • transmission data bits are transmitted in the form of transport blocks (TBs). If a TB exceeds a certain size, it is divided into multiple code blocks (CBs), and the transmitter encodes and transmits each CB. In this case, to support higher data rates, the TBS increases, which increases the number of transmitted CBs.
  • transmission parameters are set to satisfy a certain block error ratio (BLER) for TB transmission. As the number of CBs increases, the error requirements for each CB to satisfy the corresponding BLER also increase. Furthermore, because the entire TB must be retransmitted even if a specific CB fails, HARQ transmission efficiency decreases. To address this situation, the following transmission methods can be considered.
  • the transmitter can improve HARQ transmission efficiency by selectively retransmitting only CBs where errors occurred. In this case, the HARQ ACK feedback overhead and the number of control signaling bits increase.
  • CB BLER can be improved by having the transmitter perform inter-CB encoding and the receiver perform inter-CB decoding when a CB error occurs. This requires additional decoding, which increases complexity.
  • Method 1 has been adopted in the 5G standard. Considering signaling overhead, Method 1 can also be applied by defining multiple CBs as code block groups (CBGs), thereby reducing signaling overhead.
  • CBGs code block groups
  • Method 2 is considered in some implementations of this specification described below.
  • globally coupled LDPC codes may be used for inter-CB encoding.
  • Fig. 14 is an example of the structure of a globally coupled LDPC (GC LDPC) code.
  • Fig. 14 may be the structure of a base matrix or a parity check matrix of a GC LDPC code.
  • Fig. 14(a) illustrates the structure of a base matrix or a parity check matrix of a GC LDPC
  • Fig. 14(b) illustrates GC LDPC from the perspective of a Tanner graph representation.
  • the construction of GC LDPC codes typically goes through two steps. In the first step, a base matrix (i.e., a base graph) is designed, and then each element of the base matrix is replaced with a CPM of size Z-by-Z or a zero matrix of size Z-by-Z.
  • a base matrix i.e., a base graph
  • GC LDPC codes are designed based on multiple constituent block LDPC codes (see the paper "Li, S. Lin, K. Abdel-Ghaffar, W. E. Ryan, and D. J. Costello, "Globally coupled LDPC codes," in Information Theory and Applications Workshop (ITA), Jan. 2016.”).
  • GC LDPC codes are a novel extension of traditional LDPC codes by introducing global coupling between variable nodes to enhance error correction capability.
  • the base matrix or parity check matrix of a GC LDPC code includes disjoint copies of the block LDPC codes, called local codes, and a global part that concatenates the base matrices or parity check matrices of all local codes into a single large matrix.
  • the above local codes also called local LDPC codes, are connected only by global coupling check nodes, as illustrated in Fig. 14. These global check nodes provide diversity between codes during decoding, thereby improving the error correction performance of the constituent codes.
  • the check nodes connect all variable nodes, providing high connectivity for each coded bit, which provides faster convergence of iterative decoding and improves error correction performance.
  • the structure of GC LDPC codes provides high throughput transmission because disjoint local codes can facilitate parallel encoding and decoding.
  • a local codeword may mean a codeword generated by a local code
  • a global codeword may mean a codeword obtained by applying a global code according to some implementations of the present specification to a codeword obtained from local codewords (e.g., a codeword obtained by concatenating the local codewords).
  • Figures 15 and 16 illustrate the error correction performance of GC LDPC codes.
  • Figure 15 illustrates the performance as the number L of component codes (e.g., the number L of local codes) with a code rate of 0.5 varies
  • Figure 16 compares the error rate performance of decoding for a single GC LDPC code and two-step decoding according to the code rate.
  • the GC LDPC code can obtain an error rate performance gain as the number L of coupled constituent codes increases.
  • the receiver For GC LDPC codes, the receiver first performs decoding on local codes, and if decoding of some local codes fails, decoding is performed on the entire code using global coupling check nodes. This allows the receiver to minimize decoding delay by minimizing the number of times global check nodes are utilized. In other words, for GC LDPC codes, the receiver can minimize delay and decoding complexity by decoding global codewords only when decoding of individual local codewords fails through two-stage decoding. Referring to Fig.
  • Figure 17 illustrates the general structure of a parity check matrix of a GC LDPC code.
  • a global-coupled (GC) LDPC code is a type of LDPC code that connects multiple local LDPC codes via global check node(s).
  • global check node(s) are added, and the addition of global check node(s) can be considered equivalent to adding new row(s) from the perspective of a parity check matrix. Therefore, a general parity check matrix H GC of a GC LDPC code using n L local LDPC codes can have a structure illustrated in FIG. 17. Referring to FIG. 17, a matrix H local,i (where 1 ⁇ i ⁇ n L ) in H GC is a form that replicates the parity check matrix of a local LDPC code.
  • the parity check matrix of the local LDPC code is replicated a total of n L times, and the n L replicates can be used as n L parity check matrices of the diagonal of the GC LDPC code.
  • undefined parts e.g., parts indicated as blank
  • Fig. 18 is an example of a parity check matrix of a GC LDPC code.
  • the parity check matrix corresponding to H Global consists of one row. It is assumed that each element of the row generated for adding the global check node is randomly assigned a value of '0' or '1'. In the example of Fig.
  • each of H local,1 and H local,2 has the same form as the matrix of Equation 3, and the matrix of Equation 3 is replicated twice, and the two copies are used as a total of two local LDPC codes.
  • the last row used as the global parity check matrix is randomly generated.
  • Fig. 19 illustrates a Tanner graph corresponding to the GC LDPC code of Fig. 18.
  • the first, third, and fourth VNs are connected to a new CN (corresponding to the global parity check node of Fig. 19), and in the second local code, the second and third VNs are connected to the new VN.
  • CN(s) are added through additional row(s) in addition to the rows of the local LDPC codes, and the connection(s) between CN(s) and VN(s) are not limited to the VN(s) of one local code, and connectivity with VNs of multiple local codes can be established.
  • GC LDPC codes depend on the global coupling check part that connects the local codes, and the performance of GC LDPC codes depends on the optimization of the global coupling check part.
  • the design methods proposed so far for the global coupling check part for GC LDPC codes have focused on optimizing the global coupling check part for a fixed TBS or a fixed number of local codes.
  • the global coupling check part since the number of CBs and the number of local codes vary depending on the TBS, if the global coupling check part is defined for a fixed TBS or a fixed number of local codes, the global coupling check part must be defined or optimized for each TBS or number of local codes.
  • the global parity check matrix H Global is optimized for a fixed n L , the number of local codes (or the number of code blocks to be transmitted/received at a single transmission/reception time, or the number of code blocks within a code block group) is not easily used in a flexible communication technology. Taking this into consideration, some implementations of the present specification for the global coupling check part of the GC LDPC code are described below.
  • the global part of the global parity check matrix is designed to match the size of each local code. Therefore, some implementations of this specification can design or determine GC LDPC codes to accommodate a dynamic or diverse number of local codes. This can reduce the search space for connecting additional global check node(s) to variable node(s) of local codes as a block-level design.
  • Fig. 20 illustrates a schematic structure of a GC LDPC code according to some implementations of the present specification.
  • the part indicated as “Local Code” is the basic matrix or parity check matrix of the local codeword
  • the part indicated as “Global part” is the basic matrix or parity check matrix of the global part corresponding to each local codeword.
  • the part indicated as “Global parities” is a part that enables efficient encoding by the global parity check matrix as an additional parity variable node.
  • global parity part is composed of an identity matrix.
  • some implementations of this specification are not limited to the global parity matrix (e.g., the matrix in the part labeled "Global parities") being an identity matrix with each row or each column having weight 1, and some row(s) or column(s) may have weights greater than 1 (e.g., see the submatrix by the last 46 columns of Fig. 12(a) or the submatrix by the last 42 columns of Fig. 12(b)).
  • global parities are generated by global parts that have a connection relationship with a plurality of local codes.
  • the global parity part since the number of code blocks varies according to the TBS, it can be efficient to design the global parity part to be divided according to the length of the local code in terms of scalability of the number of code blocks. Referring to FIG. 20, for example, when the length of the local code is N and the length of the global parity is M G , the size of the matrix corresponding to the global part divided by the length of the local code is M G * N, and the size of the global parity matrix is M G * M G.
  • n L be the number of CBs associated with one TB or the number of CBs in a CBG to be transmitted at one transmission time
  • the number of local codes of the GC LDPC code used for channel encoding for each CB of the TB or CBG can be n L
  • the n L local codes can correspond to the n L CBs respectively (respectively) or to the n L CRC additional CBs respectively (respectively).
  • an input sequence of length n input to a channel encoder or an information sequence corresponding to a local PCM of length n is also referred to as an information block.
  • n L local codes e.g., n L code blocks
  • n GlobalPart global parts can be designed to have the same (parity) structure. In this case, since the number of global parts to be optimized is multiplied by 1/n GlobalPart , the global parity check matrix can be efficiently optimized and designed.
  • n GlobalPart n L.
  • all n L global parts can be designed to have the same (parity) structure. This design approach can reduce optimization complexity. Furthermore, this design approach can be applied to BG1 or BG2 according to the current NR standard, or to cases where the corresponding PCM is used as a local code.
  • the global part and global parity part can be designed with a quasi-cyclic (QC) structure, and the following lifting method can be considered for the global part and global parity part with a QC structure.
  • QC quasi-cyclic
  • the design complexity can be reduced by using the same lifting method as the local code.
  • the lifting method according to the current 5G standard e.g., lifting factor, number of cyclic shifts (e.g., cyclic shift values V i,j of CPM), etc.
  • the lifting method according to the current 5G standard can be applied to the global part and/or global parity part, thereby reducing the PCM design complexity of the global part and/or global parity part.
  • Performance can be improved by lifting methods that are not identical to the local code. For example, assuming that the PCM(s) of the local code are designed, if the PCM(s) of the global part and/or the global parity part are redesigned considering the PCM(s) of the local code, the performance of the GC LDPC code can be improved.
  • Some implementations of the present specification described below e.g., identity matrix-based global part, strong node to strong node-based global part, weak node to strong node-based global part, etc.
  • scaling factor e.g., 1, 0.8, 0.75, and 0.4
  • BLER TB and BLER CB are the required BLER for TB and the required BLER for CB, respectively (respectively), and C is the number of CBs obtained from one TB.
  • the transport block size can be determined based on the number of resource elements (REs) N RE within a physical resource block (PRB).
  • the number of REs allocated for PDSCH within a PRB N ' RE can be calculated as follows.
  • N PRB DMRS Number of REs for DM-RS per PRB in the scheduled duration
  • N RE min(156, N ' RE )n PRB , where n PRB is the total number of allocated PRBs for the UE.
  • a TB can be divided into C CB(s), and each of the multiple CRC-added CBs obtained by adding a CRC code to each CB can be encoded using an LDPC code according to the 5G standard.
  • a single local parity check matrix can be used repeatedly for multiple CBs.
  • Fig. 21 illustrates the structure of a codeword obtained by concatenating local codewords
  • Fig. 22 illustrates the structure of a codeword obtained by adding global parity bits to the codeword of Fig. 21.
  • n L C, which means the number of local codewords, and in Fig. 21, it is assumed that each block has a length equal to the length n of the (local) codeword (CW) after encoding.
  • encoding is performed on the codeword obtained by concatenating local codewords to obtain global parity(s).
  • m G global parity bit(s) are added, so that a codeword having the form of, for example, FIG. 22 can be obtained.
  • the matrix corresponding to the global parity part may be constructed by an identity matrix, in which case a valid codeword by a GC LDPC code must satisfy the following.
  • the additional parity check bit sequence is represented by p GC .
  • H Global is a parity check matrix, and the matrix consisting of global parts and the matrix of the global parity part, which is the identity matrix, can be expressed as [ A I ].
  • x can be a codeword obtained by concatenating local codewords (or codewords obtained by applying rate matching to local codewords).
  • Figure 23 illustrates the structure of a parity check matrix for a global code within the GC LDPC structure illustrated in Figure 20.
  • I may be an m G -by-m G identity matrix.
  • the value of the i-th global parity check node after encoding is the sum of the information bits corresponding to the columns whose element values of the parity check matrix are '1' in the i -th row of the matrix A.
  • h (0, 0, 1, 1, 1, 0, 0, 1, 1, 1, 1)
  • the first sub-row vector h 1 [0, 0, 1, 1, 1] consisting of the first five elements
  • the last element 1 is the global parity part.
  • FIG. 24 is an example of a parity check matrix of a GC LDPC code according to some implementations of the present specification. Referring to FIG. 24, according to the first step described above, if two codewords, which are the results of two code blocks independently encoded by the local codes illustrated in FIG.
  • p 2 (c 11 + c 13 + c 21 + c 23 ) mod 2
  • the column(s) containing 1 for each row of the matrix of the global part can be determined using a P-EXIT chart.
  • the elements containing 1 among the elements in the matrix of the global part can be determined using a P-EXIT chart.
  • the P-EXIT chart is a tool used to quantitatively evaluate the convergence of a decoding algorithm by visualizing the iterative message passing process of a decoder (also known as the iterative decoding process).
  • the P-EXIT chart can be used to track how the mutual information (MI) exchanged at each node (e.g., VN or CN) changes during iterative decoding in a protograph-based LDPC code.
  • MI mutual information
  • the conventional EXIT chart estimates the performance of an entire large ensemble of QC LDPC codes with specific column and row weights
  • the P-EXIT chart simulates the mutual information transfer characteristics of a type specified for each node in the base matrix.
  • the curve of the variable node (VN) side (VNP) and the curve of the check node (CN) side (CNP) are expressed as a function of I A and I E (I A , I E ) to check whether the decoding performance has converged.
  • I A is the mutual information between the VN associated with the VNP and the VNP input (e.g., a priori information)
  • I E is the mutual information between the VN associated with the VNP and the VNP output (extrinsic information).
  • I A can represent how much the a priori information input to the VN is related to the actual coded bits
  • I E can represent the quality of the information newly generated by the VN (e.g., how much more accurate information the VN provides after iterative decoding).
  • the two curves do not overlap and gradually connect, forming a tunnel. If this tunnel exists, it indicates that decoding can converge through iterative decoding.
  • SNR signal-to-noise ratio
  • a parity check matrix can be generated using a protograph LDPC code.
  • a protograph LDPC code is a design technique that generates a large LDPC code, such as a parity check matrix, by expanding (also called lifting) a relatively small "base graph” multiple times based on it.
  • the LDPC code currently used in 3GPP 5G NR also defines a "base graph (BG)" that matches the concept of a protograph, and lifts it to form a large matrix used in actual transmission.
  • BG base graph
  • a very small bipartite graph consisting of variable node(s) and check node(s) is first established. Next, the bipartite graph goes through a lifting or expansion process.
  • the size of the graph is increased by replicating one edge existing in the protograph by a lifting factor. This ultimately forms a graph that is larger than the protograph by a factor of expansion.
  • a lifting factor e.g., the shortest cycle in the Tanner graph of an LDPC code
  • various techniques such as cyclic shifts are used to optimize the structure of the graph and improve performance.
  • Each element of the protograph is replaced with a locally cyclically shifted form of the identity matrix through lifting.
  • the matrix indicating the number of cyclic shifts of the identity matrix corresponding to each element can be defined as an exponent matrix.
  • the final parity check matrix can be completed by rearranging the connectivity of this extended large-scale graph in matrix form.
  • the size of the basic graph is M ⁇ N and the lifting factor is Z
  • the size of the parity check matrix obtained through lifting is (Z*M) ⁇ (Z*N)
  • a codeword of length Z*N can be generated.
  • the 1 in the first row and first column of the above basic matrix B is replaced with a 3-by-3 matrix obtained by cyclically shifting the 3-by-3 identity matrix by 0, which is the value of the first row and first column of the above exponential matrix E.
  • Figures 25 and 26 illustrate the results of P-EXIT analysis for an example of a simple protograph LDPC code and the amount of mutual information for each variable node, respectively (respectively).
  • Eb means energy per bit
  • No means noise power.
  • the integer value in each element of the basic matrix represents the weight of each column or each row of the Z-by-Z matrix corresponding to the element (e.g., the number of 1s in each row or each row). For example, since the element value of the first row and the first column of the basic matrix B is 2, among the Z elements in each row or each column of the Z-by-Z matrix that replaces the first row and the first element, there are 2 elements with 1.
  • FIG. 27 is an example of a base matrix for a local codeword that may be used in some implementations of the present specification.
  • the base matrix of FIG. 27 may be used as a base matrix corresponding to one local code in the parity check matrix illustrated in FIG. 20.
  • some implementations of the present specification are described herein using a small-sized matrix as an example of the base matrix; however, LDPC base matrices or LDPC base graphs of different sizes and shapes may also be used for local codes.
  • the global parity part indicated as "Global parities" is configured by an identity matrix
  • the part to be designed in some implementations of the present specification may be one global part.
  • the size of the basic matrix is 9X13.
  • FIG. 29 is an example of a base matrix of a global part according to some implementations of the present specification.
  • FIG. 29 is an example of a base matrix of a global part that can be used when the base matrix of FIG. 27 is used as a base matrix for a local codeword.
  • the identity matrix-based fundamental matrix for the global part can be obtained by cyclically concatenating identity matrices of size M G -by-M G until the number of columns of the fundamental matrix becomes equal to the number of columns of the fundamental matrix of the local codeword.
  • M G 3
  • the identity matrix-based fundamental matrix for the global part can be, for example, as shown in FIG. 29 .
  • the fundamental matrix of FIG. 29 is a matrix of size 3X13, and is designed to have rows corresponding to three global check nodes and a row length that matches the column length 13 of the fundamental matrix for the local codeword (e.g., the fundamental matrix illustrated in FIG. 27 ).
  • Fig. 30 illustrates the amount of mutual information per variable node according to the P-EXIT chart analysis for the variable nodes of the basic matrix illustrated in Fig. 27.
  • Fig. 30 illustrates the extent to which the amount of mutual information per variable node of the basic matrix increases through the P-EXIT chart analysis of the variable nodes of the basic matrix for an example of the basic matrix illustrated in Fig. 27.
  • variable nodes of the basic matrix of the local code illustrated in Fig. 27 can be obtained.
  • the rank of the degree of decoding convergence for each variable node can be determined. If the variable nodes 1 to 13 of the basic matrix illustrated in Fig. 27 are sorted in descending order of the positive MI from the variable node with the highest MI in the special number of iterations, the following variable node sequence or column index sequence can be obtained: ⁇ 5, 3, 6, 1, 2, 4, 11, 13, 9, 10, 12, 8, 7 ⁇ . Referring to the above variable node sequence ⁇ 5, 3, 6, 1, 2, 4, 11, 13, 9, 10, 12, 8, 7 ⁇ , the basic matrix illustrated in FIG. 27 can determine the bit value of variable node 5 with fewer decoding iterations than the bit value of variable node 7.
  • variable node sequence or row index sequence used to determine the order of the strong variable nodes can be obtained by sorting the variable node indices or row indices in positive descending or ascending order of MI.
  • the variable node sequence or row index sequence used to determine the order of the strong variable nodes can be obtained by sorting the variable node indices or row indices in positive descending or ascending order of the number of decoding iterations required to determine the bit value corresponding to the corresponding variable node or row.
  • a GC LDPC structure that outperforms existing GC LDPC code structures that use a global parity check matrix composed of identity matrices can be obtained by connecting strong variable nodes to strong variable nodes to generate a base matrix or parity check matrix for the global part. Connecting strong variable nodes can perform better than connecting strong nodes to weak nodes.
  • the reason for this performance improvement is as follows. Once a bit (e.g., a VN) is successfully decoded, information exchange through edges connected to the bit that have already been recovered in the Tanner graph is not actually performed during the decoding iteration. Therefore, the edge connected to the recovered bit can be considered to be effectively removed from the Tanner graph, and the node connected to the recovered bit can be advantageous for decoding because it is no longer connected during the remaining decoding process.
  • variable nodes can be explained in terms of the base matrix.
  • the floor ⁇ N/ M G ⁇ strongest variable nodes can be connected to each other, and the floor ⁇ N/M G ⁇ next strongest variable nodes can be connected to each other.
  • Connecting the variable nodes can mean that the elements of the columns corresponding to the variable nodes in a row each have '1'. Since the parity check matrix is obtained by lifting the base matrix by the lifting factor, the variable nodes that are connected in the base matrix will also be connected in the parity check matrix.
  • N is not an integer multiple of M G
  • N - M G *floor ⁇ N/M G ⁇ > 0, and the problem is how to deal with the 'N - M G *floor ⁇ N/M G ⁇ ' weakest variable nodes. If N is not an integer multiple of M G , or if N - M G *floor ⁇ N/M G ⁇ > 0, then in some implementations, the 'N - M G *floor ⁇ N/M G ⁇ ' weakest variable nodes can remain unconnected to any other variable node.
  • N is not an integer multiple of M G , or if N - M G *floor ⁇ N/M G ⁇ > 0, then in some implementations, the 'floor ⁇ N/M G ⁇ + N - M G *floor ⁇ N/M G ⁇ ' weakest variable nodes can be connected to each other.
  • Figure 31 is another example of a basic matrix of a global part according to some implementations of this specification.
  • variable nodes when connecting strong nodes to strong nodes according to some implementations of the present specification, based on the variable node sequence ⁇ 5, 3, 6, 1, 2, 4, 11, 13, 9, 10, 12, 8, 7 ⁇ described above, variable nodes ⁇ 5, 3, 6, 1 ⁇ can be connected to each other, variable nodes ⁇ 2, 4, 11, 13 ⁇ can be connected to each other, and variable nodes ⁇ 9, 10, 12, 8 ⁇ can be connected to each other.
  • the weakest variable node 7 could remain unconnected to any other variable node.
  • the weakest variable node 7 could be interconnected with the weak variable nodes ⁇ 9, 10, 12, 8 ⁇ .
  • Figure 31 illustrates a case in which the strongest variable nodes ⁇ 5, 3, 6, 1 ⁇ are connected in the first row of the fundamental matrix of the global part, the next strongest variable nodes ⁇ 2, 4, 11, 13 ⁇ are connected in the second row of the fundamental matrix of the global part, and the weakest variable nodes ⁇ 9, 10, 12, 8 ⁇ are connected in the last row of the fundamental matrix of the global part.
  • Fig. 32 is another example of a basic matrix of a global part according to some implementations of the present specification.
  • Fig. 32 illustrates a basic matrix obtained by connecting weak variable nodes and strong variable nodes.
  • weak node-strong node connection for example, referring to Fig. 32, among the 13 variable nodes of the basic matrix, variable nodes ⁇ 5, 3, 7, 8 ⁇ may be connected to each other, variable nodes ⁇ 6, 1, 12, 10 ⁇ may be connected to each other, and variable nodes ⁇ 2, 4, 9, 13 ⁇ may be connected to each other.
  • the basic matrix of the global code can be converted to PCM through lifting, and global parity bits can be generated through encoding using the PCM for codewords obtained from local codewords corresponding to local codes (e.g., codewords obtained by concatenating local codewords).
  • Transmission bits can be determined (through rate matching) based on the codewords and the global parity bits, and the transmission bits can be transmitted to a receiver through a wireless channel.
  • Each element in the base matrix can be replaced by a Z-by-Z matrix through lifting.
  • the Z-by-Z matrix that replaces each element through lifting can be a Z-by-Z zero matrix or a Z-by-Z circulant permutation matrix (CPM).
  • CPM circulant permutation matrix
  • Simulated annealing can be used as a method for obtaining CPMs associated with cyclic shifts for the basic matrices designed according to some implementations of the present specification described above (the basic matrix of FIG. 29, the basic matrix of FIG. 31, and/or the basic matrix of FIG. 32). It is known that performance degradation occurs when the shortest cycle in the Tanner graph of an LDPC code is 4. In order to avoid performance degradation in all implementations, it may be desirable to design an LDPC code with a girth of 6.
  • the parity check matrix generated by the CPM value(s) determined through the SA technique has a girth (e.g., the shortest cycle in the Tanner graph of the LDPC code) of 6.
  • the number of global check nodes in the aforementioned basic matrix of the global part is 3
  • Figure 33 is an example of a matrix obtained by extending the basic matrix of the global parity part.
  • the parity check matrix of the global parity part becomes a 99-by-99 matrix.
  • FIGS. 34, 35, and 36 illustrate parity check matrices obtained by extending the basic matrices of FIGS. 29, 31, and 32 for the global part, respectively.
  • the parity check matrices of FIGS. 34, 35, and 36 for the global part, respectively can be obtained.
  • a parity check matrix of size 99-by-429 corresponding to the global part of the GC LDPC code can be obtained.
  • FIG. 34 illustrates an identity matrix-based parity check matrix for the global part
  • FIG. 35 illustrates a strong node-strong node connection-based parity check matrix for the global part according to some implementations of the present specification
  • FIG. 36 illustrates a weak node-weak node connection-based parity check matrix for the global part according to some implementations of the present specification.
  • Figure 37 illustrates the performance evaluation results of GC LDPC codes according to some implementations of the present specification.
  • “Baseline” represents the performance by the identity matrix-based parity check matrix
  • “StoS” represents the performance by the strong node-strong node connection-based parity check matrix
  • “WtoS” represents the performance by the weak node-strong node connection-based parity check matrix.
  • 10 codewords were used for one code block group, an additive white Gaussian noise (AWGN) channel, binary phase shift keying (BPSK) were assumed, and a two-stage decoder based on belief propagation (BP) decoder was used.
  • AWGN additive white Gaussian noise
  • BPSK binary phase shift keying
  • BP belief propagation
  • a CG LDPC code can be designed efficiently.
  • a GC LDPC code having a scalable structure depending on the number of TBSs or CBs to be transmitted/received in one transmission occasion can be provided.
  • a GC LDPC code capable of reducing a TB or CBG error rate can be provided.
  • even if an error occurs in a TB, CB, or CBG error correction can be enabled, reducing the number of retransmissions and thus improving system throughput.
  • Figure 38 illustrates a channel encoding process according to some implementations of this specification.
  • a communications device or encoder may perform operations according to some implementations of the present disclosure in connection with channel encoding.
  • the communications device may include at least one transceiver; at least one processor; and at least one computer memory operably connected to the at least one processor and storing instructions that, when executed, cause the at least one processor to perform operations according to some implementations of the present disclosure.
  • a processing device for the communications device or encoder may include at least one processor; and at least one computer memory operably connected to the at least one processor and storing instructions that, when executed, cause the at least one processor to perform operations according to some implementations of the present disclosure.
  • a computer-readable (non-transitory) storage medium may store at least one computer program comprising instructions that, when executed by at least one processor, cause the at least one processor to perform operations according to some implementations of the present disclosure.
  • a computer program or computer program product may be recorded on at least one computer-readable (non-transitory) storage medium and may contain instructions that, when executed, cause (at least one processor) to perform operations according to some implementations of the present specification.
  • the second matrix may have a structure according to some implementations of the present specification.
  • Figure 39 illustrates a channel decoding process according to some implementations of the present specification.
  • a communications device or decoder may perform operations according to some implementations of the present disclosure in connection with channel decoding.
  • the communications device may include at least one transceiver; at least one processor; and at least one computer memory operably connected to the at least one processor and storing instructions that, when executed, cause the at least one processor to perform operations according to some implementations of the present disclosure.
  • a processing device for the communications device or decoder may include at least one processor; and at least one computer memory operably connected to the at least one processor and storing instructions that, when executed, cause the at least one processor to perform operations according to some implementations of the present disclosure.
  • a computer-readable (non-transitory) storage medium may store at least one computer program comprising instructions that, when executed by at least one processor, cause the at least one processor to perform operations according to some implementations of the present disclosure.
  • a computer program or computer program product may be recorded on at least one computer-readable (non-transitory) storage medium and may contain instructions that, when executed, cause (at least one processor) to perform operations according to some implementations of the present specification.
  • a method performed by the communication device, or in the communication device, the decoder, the processing device, the computer-readable (non-transitory) storage medium, and/or the computer program product may include: receiving coded bits associated with a second codeword (S3901); and performing decoding on the coded bits based on a first matrix and a second matrix to determine n L information blocks (S3903).
  • the second codeword may be obtained through encoding based on the second matrix for the first codeword
  • the first codeword may be obtained based on n L local codewords, each having a length n
  • the n L local codewords may be obtained by encoding each of the n L information blocks based on the first matrix.
  • the second matrix may have a structure according to some implementations of the present specification.
  • P may be an identity matrix of size m G -by-m G.
  • the N columns of B G may each include M G column sets, each including floor(N/M G ) columns based on a predetermined column index sequence, and each of the M G rows of B G may include an integer representing a Z-by-Z matrix that is not a Z-by-Z zero matrix in each column of a different column set among the M G column sets.
  • each of the M G rows of B G may include an integer representing a Z-by-Z zero matrix in each of the remaining columns of the M G column sets excluding the corresponding column set.
  • the predetermined column index sequence may be based on the number of decoding iterations required to determine bit values for each of the bits corresponding to the N columns of B G .
  • the predetermined column index sequence may be identical to a sequence obtained by sorting the N column indices of B G in ascending or descending order of the number of iterations, starting from the column index of the column with the fewest number of decoding iterations required to determine the corresponding bit value.
  • the n L information blocks may be n L code blocks obtained from transport blocks.
  • the n L information blocks may be n L CRC additional code blocks obtained by adding a CRC code to each of the n L code blocks.
  • encoding each of the n L information blocks based on a first matrix to determine n L local codewords, each of which has a length n may include: lifting the first matrix by a lifting factor Z to obtain a first PCM; and encoding each of the n L information blocks with the first PCM.
  • Implementations of this specification may be used in wireless communication systems, base stations, user equipment, or other equipment.

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Abstract

La présente invention peut comprendre : le codage de chacun des nL blocs d'informations sur la base d'une première matrice de façon à déterminer nL mots de code locaux ; acquérir un premier mot de code de longueur n*nL sur la base des nL mots de code locaux ; et coder le premier mot de code sur la base d'une seconde matrice de manière à déterminer un second mot de code ayant une longueur de nG, où nG = n*nL + mG, la seconde matrice correspondant à HGlobal = [A P], P étant une matrice de mG-par-m G , A = [A_1 A_2... A_nL], A_1 = A_2 =... = A_nL = AG, et G est une matrice de mG-by-n.
PCT/KR2025/001847 2024-02-07 2025-02-07 Procédé mis en œuvre par un dispositif, dispositif et support de stockage Pending WO2025170367A1 (fr)

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