WO2025100106A1 - Signal processing device, display system, and electronic apparatus - Google Patents

Abstract

Provided is a signal processing device capable of acquiring data for calculating an APL, for example, while suppressing an increase in circuit scale and an increase in power consumption.　The signal processing device includes a memory unit in which image data is temporarily stored, and the memory unit includes a memory cell and an AD converter connected to a storage node of the memory cell.

Description

Signal processing device, display system, and electronic device

This technology relates to signal processing devices, display systems, and electronic devices.

Display devices that use self-luminous elements (light-emitting elements) are known. Such display devices have the advantages of high visibility compared to conventional display devices that use liquid crystal, and can be made lighter, thinner, and smaller with low power consumption (see, for example, Patent Documents 1 and 2). In such display devices, the average brightness level, APL (Average Picture Level), is calculated, and image processing is performed according to the calculated APL, thereby improving image quality and extending the lifespan of the display device.

JP 2020-144256 A JP 2008-233931 A

Generally, a logic circuit is used to calculate the APL. With this configuration, the circuit size of the logic circuit increases as the resolution of the display device increases, which causes a problem of increased power consumption.

One of the objectives of this technology is to provide a signal processing device that can acquire data for calculating APL while suppressing increases in circuit size and power consumption, a display system that has the signal processing device, and an electronic device that has the display system.

This technology is, for example,
A memory unit for temporarily storing image data;
The memory section is
A memory cell;
an AD converter connected to a storage node of the memory cell;
The signal processing device includes:
The present technology relates to the above-mentioned signal processing device,
a display device that displays image data read from the memory unit;
The display system may include:
The present technology may be an electronic device having the above-mentioned display system.

FIG. 1 is a diagram to which reference is made when explaining problems to be considered in the present technology. FIG. 1 is a diagram to which reference is made when explaining problems to be considered in the present technology. 1 is a block diagram showing an example of the configuration of a display system according to an embodiment. 2 is a diagram for explaining a configuration example of a pixel array unit according to the embodiment; FIG. 2 is a diagram for explaining a configuration example of a pixel circuit according to the embodiment; FIG. 2 is a diagram for explaining a schematic configuration example of a memory unit according to the first embodiment; FIG. 4 is a diagram for explaining a detailed configuration example of a memory unit according to the first embodiment; FIG. 4 is a diagram for explaining an example of a connection mode between a memory cell and a peripheral circuit according to the first embodiment; FIG. FIG. 2 is a diagram for explaining an example of the configuration of an image processing unit according to the embodiment; 1A and 1B are diagrams to be referred to when describing an example of processing performed in a memory unit according to the first embodiment. 3 is a diagram referred to when describing an example of processing performed in a memory unit according to the first embodiment. FIG. 3 is a diagram to be referred to when describing an example of processing performed by an image processing unit according to the embodiment. FIG. 4 is a diagram for explaining an example of the arrangement of components when a memory unit and an image processing unit according to the first embodiment are integrated into an IC; FIG. FIG. 13 is a diagram showing an image processing unit and the like according to a comparative example. FIG. 11 is a diagram for explaining a configuration example of a memory unit according to a second embodiment; FIG. 1 is a perspective view showing an example of the appearance of a head mounted display. 1 is a perspective view showing an example of the appearance of a see-through head mounted display. 1A is a front view showing an example of the external appearance of a digital still camera, and FIG. FIG. 1 is a perspective view showing an example of the appearance of a television device. FIG. 1 is a perspective view showing an example of the appearance of a smartphone. 1A is a diagram showing an example of the interior of a vehicle from the rear to the front of the vehicle, and FIG. 1B is a diagram showing an example of the interior of a vehicle from the diagonally rear to the diagonally front of the vehicle. FIG. 13 is a diagram showing another example of the configuration of a pixel circuit. FIG. 13 is a diagram showing another example of the configuration of a pixel circuit. FIG. 13 is a diagram showing another example of the configuration of a pixel circuit. FIG. 13 is a diagram showing another example of the configuration of a pixel circuit. FIG. 13 is a diagram showing another example of the configuration of a pixel circuit. FIG. 13 is a diagram showing another example of the configuration of a pixel circuit. FIG. 13 is a diagram showing another example of the configuration of a pixel circuit.

Hereinafter, embodiments of the present technology will be described with reference to the drawings. The description will be made in the following order.
<Issues to be considered with this technology>
First Embodiment
Second Embodiment
<Application Examples>
<Modification>
In this specification and the drawings, the same reference numerals are used to denote components having substantially the same functions or configurations, and redundant explanations will be omitted as appropriate. In addition, for the sake of simplicity of illustration, reference numerals may be omitted in the drawings, or reference numerals may be used only to some of the same components.

<Issues to be considered with this technology>
First, in order to facilitate understanding of the present technology, problems to be considered in the present technology will be described. In a self-luminous display such as an OLED (Organic Light Emitting Diode), as described above, an APL is calculated, and various processes based on the calculated APL are performed.

For example, power limit processing is performed to control the overall brightness according to the APL of the input image data. The horizontal axis of the graph shown in FIG. 1 indicates the APL, and the vertical axis indicates the gain for the input image data. As shown by line LN1 in FIG. 1, the gain is reduced when the APL is equal to or higher than a predetermined value. Even if the gain is reduced because the APL is equal to or higher than a predetermined value, there is little risk that the user will perceive a change in brightness. Furthermore, by performing such power limit processing, power consumption can be reduced.

As mentioned above, APL is generally calculated using a logic circuit. For example, as shown in FIG. 2, input image data is input to a logic circuit LC, which outputs output image data and the APL calculated by the logic circuit LC. The logic circuit LC is configured by appropriately combining an adder, a counter, a divider for averaging, and the like. When a logic circuit is used in this way, the APL is calculated for each pixel, so that the circuit scale of the logic circuit increases as the resolution of the display device increases, and power consumption also increases. In addition, one frame's worth of image data is required to calculate the APL, since the total luminance must be accumulated. Taking the above points into consideration, the details of this technology will be described with reference to the embodiment.

First Embodiment
[Display System Overview]
FIG. 3 is a block diagram showing a schematic configuration example of a display system 100 including a display device (display device 4) according to the first embodiment. The display device 4 according to the present technology is, for example, a device having a light-emitting element. The light-emitting element is, for example, an LED (Light Emitting Diode). The LED includes an LED used in a micro LED display and an OLED used in an organic EL (Electro-Luminescence) display. The organic EL display includes, for example, an OLED micro display (Organic Light-Emitting Diode Micro Display). The display device 4 is, for example, a display mounted on an electronic device such as an electronic viewfinder (EVF: Electronic View Finder) of a digital camera, an Augmented Reality (AR) glass, or a Virtual Reality (VR) glass. Note that the display device 4 is not limited to this, and may be, for example, a medium-sized or large-sized display such as a smartphone or a tablet.

The display system 100 has a data input/output I/F (Interface) unit 1, a timing controller 2, a display controller 3, and a display device 4. Note that in FIG. 3, the data input/output I/F unit 1, the timing controller 2, and the display controller 3 are separate from the display device 4, but the display controller 3 etc. may be integrated into the display device 4 to form a single display device.

The data input/output I/F unit 1 has a high-speed I/F unit 11, a data S/P unit 12, a clock control unit 13, and an H/V synchronization unit 14.

The timing controller 2 has a clock generator 23, a timing generator 24, a memory unit 25, and an image processing unit 26. The timing controller 2 corresponds to an example of a signal processing device of the present technology.

The display controller 3 has an HLOGIC section 31 as a horizontal logic circuit and a VLOGIC section 32 as a vertical logic circuit.

The display device 4 has a pixel array section 41, a VANALOG 42 as a vertical analog circuit, a HANALOG 43 as a horizontal analog circuit, and a signal processing section 44. Each component will be described in detail below.

(Data input I/F section)
The high-speed I/F unit 11 receives image data for display that has been serially transferred from the outside. The data S/P unit 12 converts the image data into parallel data. The image data converted into parallel data is sent to a memory unit 25 in the timing controller 2. The clock control unit 13 generates a clock that matches the display frequency of the display device 4. The H/V synchronization unit 14 generates a horizontal synchronization signal and a vertical synchronization signal based on the image data and sends them to the timing generator 24.

(Timing Controller)
The clock generator 23 generates a vertical synchronization clock signal and a horizontal synchronization clock signal for the display device 4 under the control of the clock control unit 13, and supplies them to the display controller 3. The timing generator 24 generates a timing signal that specifies the operation timing of the display controller 3 based on the horizontal synchronization signal and the vertical synchronization signal supplied from the H/V synchronization unit 14. The timing signal is supplied to the display controller 3. The memory unit 25 temporarily stores image data supplied from the data S/P 12 unit. Details of the memory unit 25 will be described later. The image processing unit 26 performs various image processes on the image data supplied from the memory unit 25. As the image processes, known image processes can be applied. For example, the image processing unit 26 performs gain adjustment, brightness adjustment, gamma adjustment, resolution conversion, color correction for each pixel, and the like. The image data output from the image processing unit 26 is supplied to the HLOGIC 31 via a source amplifier (not shown in FIG. 3).

(Display Controller)
The HLOGIC 31 supplies pixel data to the HANALOG 43 in synchronization with the timing oscillation. For example, the HLOGIC 31 distributes image data input from the timing controller 2 to each signal line. The VLOGIC 32 controls the VANALOG 42 in synchronization with the timing signal. For example, the VLOGIC 32 generates a shift signal from a start pulse.

(Display device)
"Example of the overall configuration of a display device"
The pixel array section 41 has, for example, a rectangular display area, and has a configuration in which a plurality of pixel circuits PIX having light-emitting elements such as organic EL elements that are driven for display are arranged in a matrix. In the pixel array section 41, control lines are provided in the horizontal direction (horizontal direction) for each row of the pixel circuits PIX arranged in the matrix, and further, signal lines are provided for each column so as to be perpendicular to the control lines. The pixel array section 41 is provided with pixels (also called sub-pixels) of three primary colors R (red), G (green), and B (blue). These three pixels represent one dot of a color image. Note that the combination of pixels that represent one dot is not limited to this, and may be configured by adding a W (white) pixel for improving brightness, or may be configured by adding a complementary color pixel for expanding the color reproduction range. In addition, the display device 4 may be configured to represent not only color images but also monochrome (black and white) images. In addition, the shape of the pixel array section 41 may be a shape other than a rectangle, such as a circle or an ellipse.

VANALOG 42 generates control signals (e.g., control signals WS, DS, AZ) using the shift signal generated by VLOGIC 32 and outputs them to the pixel array unit 41. HANALOG 43 outputs the pixel signal supplied from the signal processing unit 44 to the corresponding signal line of the pixel array unit 41.

The signal processing unit 44 performs signal processing on the image data to be displayed on the pixel array unit 41. The specific content of the signal processing is not important, but an example is gamma correction. For example, the signal processing unit 44 performs gamma correction on the image data allocated by the HLOGIC 31 to generate a gamma-corrected pixel signal. The pixel signal that has been signal-processed by the signal processing unit 44 is sent to the HANALOG unit 43. Note that the gradation voltage indicating the gradation generated when the signal processing unit 44 performs gamma correction is generated based on a setting value stored in a register (not shown). For example, the timing controller 2 has the above-mentioned register.

As a result, the display device 4 sequentially drives each pixel arranged in the pixel array section 41, causes each pixel to emit light according to the signal level of each signal line, and displays a desired image on the pixel array section 41. Note that the display device 4 is one example of a display device to which the present technology can be applied, and is also applicable to other configurations. For example, scanning is not limited to line sequential scanning, and may be point sequential scanning. Furthermore, the arrangement of pixels is not limited to a matrix arrangement, and may be arranged along an arc. The signal lines and control lines need only be formed accordingly.

"Example of pixel array configuration"
4 is a diagram for explaining a schematic configuration example of the pixel array section 41. In the pixel array section 41, a signal line SIG is wired for each pixel column along the column direction CD for the arrangement of pixel circuits PIX. In addition, control lines (control lines WSL, DSL, AZSL) are wired for each pixel row along the row direction RD for the arrangement of pixel circuits PIX. Note that the pixel arrangement shown in the figure is merely an example for the purpose of simplifying the illustration.

Each signal line SIG is connected to the output terminal of the corresponding column of HANALOG43. Each control line WSL, DSL, AZSL is connected to the output terminal of the corresponding row of VANALOG42.

HANALOG 43 supplies pixel signals corresponding to the display image to each signal line SIG based on image data supplied from the timing controller 2. HANALOG 43 selectively outputs, for example, as pixel signals, a signal voltage Vsig corresponding to the luminance of the display image and various reference voltages that serve as the basis for the signal voltage Vsig.

VANALOG42 supplies control signals (control signals WS, DS, AZ) that control driving based on pixel signals to each control line WSL, DSL, AZSL. The control signal WS is a control signal that scans each of the multiple pixels, the control signal DS is a control signal that controls light emission/extinction, and the control signal AZ is a control signal that controls so as not to emit light during the extinction period. Specifically, when writing pixel signals to each pixel circuit PIX of the pixel array section 41, VANALOG42 sequentially supplies control signals WS0, WS1, ... to each control line WSL to scan each pixel circuit PIX of the pixel array section 41 in sequence by row (line sequential scanning). In addition, VANALOG42 controls the light emission/extinction of the pixel circuits PIX by supplying control signals DS0, DS1, ... to the control line DSL in synchronization with the scanning. Furthermore, VANALOG42 controls the light-emitting element of pixel circuit PIX not to emit light during the extinction period by supplying control signals AZ0, AZ1, ... to control line AZSL in synchronization with the scanning.

"Configuration example of pixel circuit PIX"
5 shows an example of the configuration of the pixel circuit PIX. The pixel circuit PIX has a capacitor C01, transistors MN02 to MN03, and a light-emitting element EL. The transistors MN02 to MN03 are N-type MOSFETs (Metal Oxide Semiconductor Field Effect Transistors). The gate of the transistor MN02 is connected to a control line WSL, the drain is connected to a signal line SIG, and the source is connected to the gate of the transistor MN03 and the capacitor C01. One end of the capacitor C01 is connected to the source of the transistor MN02 and the gate of the transistor MN03, and the other end is connected to the source of the transistor MN03 and the anode of the light-emitting element EL. The gate of the transistor MN03 is connected to the source of the transistor MN02 and one end of the capacitor C01, the drain is connected to the power supply line VCCP, and the source is connected to the other end of the capacitor C01 and the anode of the light-emitting element EL. The anode of the light-emitting element EL is connected to the source of the transistor MN03 and the other end of the capacitor C01, and the cathode is connected to the power supply line Vcath. The voltage of the power supply line VCCP is appropriately switched between a first voltage and a second voltage lower than the first voltage.

With this configuration, in the pixel circuit PIX, when the transistor MN02 is turned on, the voltage across the capacitor C01 is set based on the pixel signal supplied from the signal line SIG. During the period when the voltage of the power supply line VCCP is the first voltage, the transistor MN03 passes a current corresponding to the voltage across the capacitor C01 through the light-emitting element EL. The light-emitting element EL emits light based on the current supplied from the transistor MN03. In this way, the pixel circuit PIX emits light with a brightness corresponding to the pixel signal. Note that during the period when the voltage of the power supply line VCCP is the second voltage, the light-emitting element EL is turned off.

[Example of memory configuration]
Next, a configuration example of the memory unit 25 according to the present embodiment will be described with reference to Fig. 6 to Fig. 8. Fig. 6 is a diagram for explaining a schematic configuration example of the memory unit 25 according to the present embodiment. Fig. 7 is a diagram for explaining a detailed configuration example of the memory unit 25 according to the present embodiment. Fig. 8 is a diagram for explaining an example of a connection mode between the memory cell and the peripheral circuit according to the present embodiment.

The memory unit 25 according to this embodiment is, for example, a frame memory that temporarily stores one frame's worth of image data. The memory unit 25 according to this embodiment is also a component that applies a technology known as in-memory computing (also called memory-in computing or near-memory computing), in which a storage circuit and an arithmetic circuit are integrated within a memory. By configuring the memory unit 25 as in-memory computing, there is no need to exchange data stored in the memory with processing elements such as arithmetic circuits outside the memory, and therefore data processing speed and power efficiency of calculations can be significantly improved.

As shown in FIG. 6, the memory unit 25 includes, for example, a memory circuit 51 and an arithmetic circuit 61.

The memory circuit 51 has a memory cell section MCX, a peripheral circuit section 52, a data write circuit 53, and a data read circuit 54.

The memory cell unit MCX is composed of multiple memory cells MC. In this embodiment, an example in which an SRAM (Static Random Access Memory) cell is used as the memory cell MC will be described. Specifically, an example in which a CMOS (Complementary Metal Oxide Semiconductor) type SRAM cell using six transistors will be described. However, the memory cell MC may not be an SRAM, but may be other memory elements such as a DRAM (Dynamic Random Access Memory). In addition, the SRAM cell is not limited to the CMOS type, and other types of SRAM cells can be used, such as a high resistance load type or an SRAM cell using a TFT (Thin Film Transistor).

The peripheral circuit section 52 is a general term for the peripheral circuits connected to the memory cell section MCX. The peripheral circuit section 52 includes, for example, an address decoder 52A that decodes an address to select a specific memory cell MC, and a precharge circuit 52B that precharges the bit lines. Note that the precharge circuit 52B refers to any precharge circuit among the precharge circuits 52B0, 52B1, ..., 52Bm described below. The peripheral circuit section 52 also includes a circuit that generates a precharge control signal PRE that operates the precharge circuit 52B, and a circuit that generates a sense amplifier enable signal SAE that operates the sense amplifier (sense amplifier 54A described below). Illustration of these circuits is omitted.

The data write circuit 53 is a circuit that writes a logical value of "1 (H (High) level)" or "0 (L (Low) level)" into each memory cell MC that constitutes the memory cell unit MCX.

The data read circuit 54 is a circuit that reads out the logical values stored in each memory cell MC. The data read circuit 54 includes, for example, a sense amplifier 54A. The sense amplifier 54A refers to any of the sense amplifiers 54A0, 54A1, ... 54Am described below.

The arithmetic circuit 61 has an AD converter 62 and an APL calculation circuit 63. The AD converter 62 converts information (e.g., potential) obtained based on the outputs of a plurality of memory cells MC from an analog signal to a digital signal. The AD converter 62 is connected to the memory node of each memory cell MC. Note that the AD converter 62 refers to any of the AD converters 620, 621, ... 62m described below. Each AD converter 62 is connected to the APL calculation circuit 63, and the output of each AD converter 62 is supplied to the APL calculation circuit 63.

The APL calculation circuit 63 calculates, for example, the APL of one frame of image data stored in the memory unit 25 based on the digital signal output from the AD converter 62. The APL calculation circuit 63 is configured, for example, by a product-sum calculation circuit.

Furthermore, a detailed configuration example of the memory unit 25 will be described with reference to FIG. 7. Note that in FIG. 7, the data write circuit 53 is omitted, and only the sense amplifier 54A of the data read circuit 54 is shown.

As shown in FIG. 7, the memory cell unit MCX has, for example, a plurality of memory cells MC-00 to MC-mn arranged in a matrix. Each word line WL0, WL1, ... WLn is connected to the address decoder 52A. Each word line WL0, WL1, ... WLn extends from the address decoder 52A to the arrangement area of the memory cells MC.

The multiple memory cells MC-00, MC-10, ..., MC-m0 arranged in the uppermost row direction are connected to the same word line WL0. The multiple memory cells MC-01, MC-11, ..., MC-m1 arranged in the next row direction are connected to the same word line WL1. And the multiple memory cells MC-0n, MC-1n, ..., MC-mn arranged in the lowermost row direction are connected to the same word line WLn. In the following explanation, when there is no need to distinguish between individual word lines, they will be referred to as word lines WL.

The multiple memory cells MC-00, MC-01, ..., MC-0n arranged in the leftmost column direction are connected to a pair of bit lines, bit lines BL0 (an example of a first bit line) and BLX0 (an example of a second bit line). Bit line BL0 has a parasitic capacitance C0. Bit line BLX0 has a parasitic capacitance CX0. The memory cells MC-00, MC-01, ..., MC-0n arranged in the same column direction form a memory cell group MCX0.

The next set of memory cells MC-10, MC-11, ..., MC-1n arranged in the column direction are connected to a pair of bit lines BL1 and BLX1. Bit line BL1 has a parasitic capacitance C1. Bit line BLX1 has a parasitic capacitance CX1. The memory cells MC-10, MC-11, ..., MC-1n arranged in the same column direction form a memory cell group MCX1.

The multiple memory cells MC-m0, MC-m1, ..., MC-mn arranged in the rightmost column direction are connected to a pair of bit lines BLm, BLXm. Bit line BLm has a parasitic capacitance Cm. Bit line BLXm has a parasitic capacitance CXm. The memory cells MC-m0, MC-m1, ..., MC-mn arranged in the same column direction form a memory cell group MCXm.

In this embodiment, a precharge circuit 52B, a sense amplifier 54A, and an AD converter 62 are provided for each memory cell group. For example, a precharge circuit 52B0, a sense amplifier 54A0, and an AD converter 620 are provided for memory cell group MCX0. Specifically, the precharge circuit 52B0, the sense amplifier 54A0, and the AD converter 620 are each connected to a pair of bit lines BL0, BLX0 to which each memory cell constituting memory cell group MCX0 is connected.

Furthermore, a precharge circuit 52B1, a sense amplifier 54A1, and an AD converter 621 are provided for the memory cell group MCX1. Specifically, the precharge circuit 52B1, the sense amplifier 54A1, and the AD converter 621 are each connected to a pair of bit lines BL1, BLX1 to which each memory cell constituting the memory cell group MCX1 is connected.

Furthermore, a precharge circuit 52Bm, a sense amplifier 54Am, and an AD converter 62m are provided for the memory cell group MCXm. Specifically, the precharge circuit 52Bm, the sense amplifier 54Am, and the AD converter 62m are connected to a pair of bit lines BLm, BLXm to which each memory cell constituting the memory cell group MCXm is connected.

With reference to FIG. 8, a specific configuration example of memory cell MC and a specific connection example between memory cell MC and precharge circuit 52B etc. will be described. For ease of explanation, FIG. 8 shows only memory cell MC-00 out of the multiple memories, only precharge circuit 52B0 out of the multiple precharge circuits 52B, only sense amplifier 54A0 out of the multiple sense amplifiers 54A, and only AD converter 620 out of the multiple AD converters 62. The other memory cells MC also have a circuit configuration similar to that of memory cell MC-00. Although only one bit of memory cell MC-00 is shown, the configuration can be made according to any number of bits.

Memory cell MC-00 has two load transistors P1 and P2 made of PMOS, and two driver transistors N1 and N2 made of N-channel MOS transistors (NMOS). Memory cell MC-00 also has two access transistors ST1 and ST2 made of NMOS.

Load transistor P1 and driver transistor N1 are connected in series (cascade connected) between the supply line of power supply voltage Vdd and the supply line of reference voltage Vss (e.g., ground voltage). Load transistor P2 and driver transistor N2 are connected in series (cascade connected) between the supply line of power supply voltage Vdd and the supply line of reference voltage Vss (e.g., ground voltage).

The gates of the load transistor P2 and the driver transistor N2 are both connected to the connection point between the load transistor P1 and the driver transistor N1. This connection point forms a first memory node ND1. Similarly, the gates of the load transistor P1 and the driver transistor N1 are both connected to the connection point between the load transistor P2 and the driver transistor N2. This connection point forms a second memory node ND2. The logical level of the first memory node ND1 and the logical level of the second memory node ND2 are complementary to each other.

One of the source and drain of the access transistor ST1 is connected to the first memory node ND1, the other is connected to the write bit line BL0, and the gate is connected to the word line WL0. One of the source and drain of the access transistor ST2 is connected to the second memory node ND2, the other is connected to the bit line BLX0, and the gate is connected to the word line WL0.

The precharge circuit 52B0 is connected to the memory node of the memory cell MC-00 via a specific bit line. For example, the precharge circuit 52B0 is connected to the first memory node ND1 of the memory cell MC-00 via the bit line BL0 and the access transistor ST1, and is connected to the second memory node ND2 of the memory cell MC-00 via the bit line BLX0 and the access transistor ST2. Although not shown in the figure, the precharge circuit 52B0 is also connected to the first memory node ND1 of the other memory cells MC-01...MC-0n via the bit line BL0, and is also connected to the second memory node ND2 via the bit line BLX0.

The sense amplifier 54A0 is connected to the memory node of the memory cell MC-00 via a specific bit line. For example, the sense amplifier 54A0 is connected to the first memory node ND1 of the memory cell MC-00 via the bit line BL0 and the access transistor ST1, and is connected to the second memory node ND2 of the memory cell MC-00 via the bit line BLX0 and the access transistor ST2. Although not shown in the figure, the sense amplifier 54A0 is also connected to the first memory node ND1 of the other memory cells MC-01...MC-0n via the bit line BL0, and is also connected to the second memory node ND2 via the bit line BLX0.

The AD converter 620 is connected to the memory node of the memory cell MC-00 via a specific bit line. For example, the AD converter 620 is connected to the first memory node ND1 of the memory cell MC-00 via the bit line BL0 and the access transistor ST1, and is connected to the second memory node ND2 of the memory cell MC-00 via the bit line BLX0 and the access transistor ST2. Although not shown in the figure, the AD converter 620 is also connected to the first memory node ND1 of the other memory cells MC-01...MC-0n via the bit line BL0, and is also connected to the second memory node ND2 via the bit line BLX0.

Although not shown, the precharge circuit 52B1, sense amplifier 54A1, and AD converter 621 are connected to the memory cells MC-10, MC-11, ... MC-1n via bit lines BL1, BLX1, etc. in the same manner as described above. The precharge circuit 52Bm, sense amplifier 54Am, and AD converter 62m are connected to the memory cells MC-m0, MC-m1, ... MC-mn via bit lines BLm, BLXm in the same manner as described above.

[Configuration example of image processing unit]
9 is a diagram for explaining an example of the configuration of the image processing unit 26. The image processing unit performs image processing according to the APL calculated by the APL calculation circuit 63. The image processing unit 26 has, as functional blocks, for example, a gain adjustment unit 26A, a brightness adjustment unit 26B, a gamma adjustment unit 26C, and a data latch unit 26D.

The gain adjustment unit 26A adjusts the gain of the image data input from the memory unit 25. The brightness adjustment unit 26B adjusts the brightness of the image data that has been subjected to gain adjustment processing by the gain adjustment unit 26A. The gamma adjustment unit 26C adjusts the gamma of the image data that has been subjected to brightness adjustment by the brightness adjustment unit 26B. The data latch unit 26D latches the image data that has been subjected to gamma adjustment, and outputs the latched image data in response to a predetermined clock signal. The image data output from the image processing unit 26 is supplied to the HLOGIC 31 via the source amplifier 27. Note that the image processing unit 26 may be configured to include the source amplifier 27.

[Processing example]
(Processing performed in the memory section)
Next, an example of processing performed in the display system 100 will be described. First, an example of processing performed in the memory unit 25 will be described with reference to the circuit example shown in Fig. 8 and Figs. 10A and 10B. Fig. 10A is the same circuit example as that shown in Fig. 8, and shows an example in which the logic level of the first storage node ND1 is H level and the logic level of the second storage node ND2 is L level. Fig. 10B is a timing chart to be referred to when describing data read processing, etc.

The precharge circuit 52B0 operates when the precharge control signal PRE is supplied. The same applies to the other precharge circuits 52B. The sense amplifier 54A0 operates when the sense amplifier enable signal SAE is supplied. The same applies to the other sense amplifiers 54A. The precharge control signal PRE and the sense amplifier enable signal SAE are generated by the peripheral circuit unit 52 based on, for example, the external clock signal ECK.

Data writing process
First, a data write process for writing data to each memory cell MC will be described. In this example, the memory cell MC to which data is to be written is assumed to be the memory cell MC-00.

The data write circuit 53 selects a pair of bit lines (bit lines BL0, BLX0 in this example) connected to the memory cell MC-00 into which data is to be written. The data write circuit 53 then writes a voltage corresponding to the input image data into the memory cell MC-00 via the selected bit lines BL0, BLX0. Data is written into the other memory cells MC in the same manner.

"Data reading process"
Next, a data read process will be described. When reading data from the memory cell MC-00, first, a precharge control signal PRE of L level is input to the precharge circuit 52B0, and the bit lines BL0 and BLX0 are precharged to H level by the precharge circuit 52B0 (until timing t10 in FIG. 10B).

After that, a word line selection signal (H level signal) which is a memory cell selection signal is applied to the word line WL0 (timing t10 in FIG. 10B), turning on the access transistors ST1 and ST2 of the memory cell MC-00, and the voltage latched in the memory cell MC-00 is output to the bit lines BL0 and BLX0. If the latched voltage is set to H level at the first memory node ND1 and L level at the second memory node ND2 as shown in FIG. 9A, a H level voltage is applied to the bit line BL0 via the access transistor ST1, and a L level voltage is applied to the bit line BLX0 via the access transistor ST2. Since the bit lines BL0 and BLX0 are charged to a H level voltage in advance by the precharge circuit 52B0, the bit line BL0 maintains a H level voltage state, while the bit line BLX0 is discharged via the access transistor ST2 by the latch section of the memory cell MC-00, and the voltage level transitions from H level to L level.

Then, after the voltage of bit line BLX0 has sufficiently approached the L level, the sense amplifier enable signal SAE is input to the sense amplifier 54A0 (see timing t11 in FIG. 10B). This causes the sense amplifier 54A0 to operate, and the voltages of bit lines BL0 and BLX0 are amplified by the sense amplifier 54A0, fixing the voltage of bit line BL0 to the H level and the voltage of bit line BLX0 to the L level. Then, an output signal (output signal VOUT in FIG. 10B) corresponding to the voltages of bit lines BL0 and BLX0 is output from the sense amplifier 54A0 via an output circuit (not shown) (see timing t11 in FIG. 10B). This causes the data stored in memory cell MC-00 to be read out.

(APL Calculation Process)
Next, the APL calculation process will be described with reference to the circuit example shown in FIG. 8. The APL calculation process can be performed at any timing in a series of image processing sequences. For example, after image data corresponding to a specific frame is written to the memory cell unit MCX, each AD converter 62 is operated by a specific control signal. The APL calculation circuit 63 calculates the APL of the frame according to the output of each AD converter 62, and outputs the APL to the image processing unit 26. At the next timing, the image data corresponding to the specific frame is written again to the memory cell unit MCX, and then, at the next specified timing, the sense amplifier 54A is operated instead of the AD converter 62 to read the image data corresponding to the specific frame from the memory unit 25. The read image data is supplied to the image processing unit 26. The image processing unit 26 executes various image processes based on the APL.

After image data corresponding to a specific frame is written to the memory cell unit MCX, each precharge circuit 52B precharges the pair of bit lines connected to it to the H level. Then, a specific control signal is supplied to each AD converter 62, causing each AD converter 62 to start operating. For example, after the precharge circuit 52B0 precharges the bit lines BL0 and BLX0 to the H level, a specific control signal is supplied, causing the AD converter 620 to start operating.

As described above, when the first memory node ND1 is at H level and the second memory node ND2 is at L level voltage, an H level voltage is applied to the bit line BL0 via the access transistor ST1, and an L level voltage is applied to the bit line BLX0 via the access transistor ST2. Since the bit lines BL0 and BLX0 have been charged to H level voltage in advance by the precharge circuit 52B0, the bit line BL0 maintains an H level voltage state. Meanwhile, the bit line BLX0 is discharged via the access transistor ST2, and the voltage level transitions from H level to L level.

Here, a number of memory cells MC-00, MC-01...MC-0n are connected to bit line BL0 and bit line BLX0. When the logical level of the first memory node ND1 of each memory cell MC is more often H level than L level, the amount of discharge is small and the amount of drop in the potential of the bit line BL0 from the potential after precharging is small. When the logical level of the first memory node ND1 of each memory cell MC is more often L level than H level, the amount of discharge is large and the amount of drop in the potential of the bit line BL0 from the potential after precharging is large. The same is true for bit line BLX0.

That is, as shown in FIG. 11, a predetermined detection period is set from the timing when the precharging of the bit lines BL0 and BLX0 is completed (timing t21 in FIG. 11). At the timing after the detection period (timing t22 in FIG. 11), the potential of at least one of the bit lines BL0 and BLX0 is detected. As described above, when the logic level of the first memory node ND1 of each memory cell MC is more H level than L level, the discharge amount is small, and the drop in the potential of the bit line BL0 is small, as shown by lines LNa and LNb in FIG. 11. When the logic level of the first memory node ND1 of each memory cell MC is more L level than H level, the discharge amount is large, and the drop in the potential of the bit line BL0 is large, as shown by lines LNc and LNd. By detecting the potential at timing t22, it is possible to detect the approximate number of H levels of the bit line BL0 (or bit line BLX0), in other words, the memory state of each memory cell MC. The AD converter 620 converts the potential at timing t22 into a digital signal and outputs it to the APL calculation circuit 63. Note that in FIG. 11, four patterns of potential changes are shown by lines LNa to LNd, but this is only an example and the patterns of potential changes are not limited to the examples shown.

When each AD converter 62 operates in the same manner as described above, the digital signal output from each AD converter is supplied to the APL calculation circuit 63. The APL calculation circuit 63 calculates the APL of one frame of image data stored in the memory cell unit MCX by performing a product-sum operation on the digital signal (digital signal corresponding to the potential after the detection period has elapsed) supplied from each AD converter 62. The APL calculation method may be other known methods other than the product-sum operation. The APL calculation circuit 63 outputs the calculated APL to the image processing unit 26.

(Image processing performed by the image processing unit)
Next, an example of image processing by the image processing unit 26 according to this embodiment will be described with reference to Fig. 12. As described above, the memory unit 25 is provided with an AD converter 62 and an APL calculation circuit 63 configured as in-memory computing. As indicated by the arrows in Fig. 12, the APL calculated by the APL calculation circuit 63 is supplied to, for example, each of the gain adjustment unit 26A, the brightness adjustment unit 26B, and the gamma adjustment unit 26C of the image processing unit 26.

The gain adjustment unit 26A multiplies the image data by a gain corresponding to the APL. For example, the gain decreases as the APL increases (see FIG. 1). For example, the gain adjustment unit 26A refers to a table that describes the relationship between the APL and the gain, reads out the gain corresponding to the APL, and multiplies the image data by the read out gain.

The brightness adjustment unit 26B adjusts the image data so that the brightness level corresponds to the APL. For example, the brightness adjustment unit 26B adjusts the brightness of the image data so that it is within a range of peak brightness corresponding to the APL. The peak brightness is set to increase as the APL increases. For example, the brightness adjustment unit 26B refers to a table that describes the relationship between the APL and peak brightness, reads out the peak brightness corresponding to the APL, and adjusts the brightness of the image data so that it is within the range of the read peak brightness. Note that the brightness adjustment unit 26B may adjust the brightness level of the image data so that it is a brightness level corresponding to the APL rather than the peak brightness.

The gamma adjustment unit 26C performs gamma correction on the image data using a gamma value corresponding to the APL. For example, the gamma adjustment unit 26C refers to a table that describes the relationship between the APL and the gamma value, reads out the gamma value corresponding to the APL, and performs gamma correction on the image data using the read out gamma value.

Note that the APL calculated by the APL calculation circuit 63 may be used to perform processing other than the above-mentioned processing. For example, the light emission time of the light-emitting element in each pixel circuit PIX may be adjusted so that the light emission time corresponds to the APL.

[Example of layout when configured as an IC (Integrated Circuit)]
13 shows an example of a layout in which the memory unit 25, image processing unit 26, and source amplifier 27 are configured as one IC. For example, the APL calculation circuit 63 and image processing unit 26 are placed in the center of the layout space of the IC. On either side of them, the memory cell unit MCX of the memory unit 25, the address decoder 52A, the data write circuit 53, the data read circuit 54, and the AD converter 62 are placed. The source amplifier 27 is then placed so that the output of the image processing unit 26 is supplied to it. By placing the APL calculation circuit 63 and the image processing unit 26 in the center of the layout space of the IC, it is possible to reduce the size of the entire IC.

Of the components shown in FIG. 13, those other than the AD converter 62 are often also provided in ICs used in general display devices. In this embodiment, the AD converter 62 is essentially the only component that needs to be added, so even if the IC is configured as an IC, it is possible to prevent the IC from becoming too large.

[Effects obtained by this embodiment]
According to this embodiment, for example, the following effects can be obtained.
According to this embodiment, for example, data for calculating the APL can be obtained by adding an AD converter to an existing circuit. Also, by using a precharge circuit, which is a commonly used component, when calculating the APL, the number of newly added components can be minimized.
By configuring the AD converter and APL calculation circuit as in-memory computing of a memory unit (e.g., a frame memory) used in general display devices, it is possible to suppress the increase in size of the IC, and further to significantly improve the data processing speed and the power efficiency of calculations.
Conventionally, as shown in FIG. 14, for example, the APL calculation circuit 63 is configured using a logic circuit included in the image processing unit 26 to calculate the APL. In this method, processing is required for each frame and each dot. Therefore, as the resolution of the display device increases, the circuit scale increases, and the power consumption increases due to the increased number of calculation processes. In contrast, in this embodiment, since it is sufficient to add only an AD converter, the circuit scale does not increase. In addition, this embodiment is advantageous in terms of power consumption compared to a logic circuit. For example, the power consumption can be reduced to about 1/4 compared to when the APL calculation circuit is configured with a logic circuit. In addition, according to this embodiment, even if there is not necessarily one frame of image data, the APL can be calculated for each block of image data, and it is also possible to calculate the APL while inputting the image data.
The accuracy of the APL calculated in this embodiment may be inferior to that of the APL calculated by the logic circuit, but in image processing using the APL, the accuracy of the APL does not need to be high, and there are many cases where an approximate accuracy does not cause any inconvenience, so the above-mentioned advantages are greater.

Second Embodiment
Next, a second embodiment will be described. In the description of the second embodiment, the same or similar components in the above description are given the same reference numerals, and duplicated descriptions will be omitted as appropriate. In addition, unless otherwise specified, the matters described in the first embodiment can be applied to the second embodiment.

In the first embodiment, the memory cell unit MCX of the memory unit 25 is configured as a frame memory capable of storing one frame's worth of image data. The memory cell unit MCX of the memory unit (memory unit 70) in this embodiment differs from the first embodiment in that it is configured as a line buffer (line memory) capable of storing one line's worth of image data.

(Example of memory configuration)
15 is a diagram showing an example of the configuration of a memory unit 70 according to the second embodiment. The memory unit 70 has an input terminal TI connected to the data S/P unit 12 and an output terminal TO connected to the image processing unit 26.

A number of memory cells are connected in a row between the input terminal TI and the output terminal TO. For example, memory cells MC-0, MC-1, ... MC-m are connected between the input terminal TI and the output terminal TO. In this embodiment, the memory cell unit MCX is composed of memory cells MC-0, MC-1, ... MC-m.

The memory unit 70 also has a precharge circuit 52B, an AD converter 62, and an APL calculation circuit 63. The precharge circuit 52B and the AD converter 62 are connected via a connection line LY. The AD converter 62 is connected to the APL calculation circuit 63, and a digital signal that is the result of conversion by the AD converter 62 is supplied to the APL calculation circuit 63.

Bit lines BLY0, BLY1, ... BLYm extend from the connection line LY. Each bit line BLY0, BLY1, ... BLYm is connected to a corresponding memory cell MC. The connection line LY has a parasitic capacitance CY.

A detailed description of an example of the configuration of the memory unit 70 will be given. Each memory cell has, for example, a loop circuit (latch circuit) using two inverters. Specifically, the memory cell MC-0 has an inverter 710 whose input is connected to the input terminal TI, and an inverter 720 whose input terminal is connected to the output terminal of the inverter 710. A switching element SWA-0 is provided between the input terminal of the inverter 710 and the output terminal of the inverter 720 in the loop. The memory cell MC-1 has an inverter 711 whose input terminal is connected to the output terminal of the inverter 710, and an inverter 721 whose input terminal is connected to the output terminal of the inverter 711. A switching element SWA-1 is provided between the input terminal of the inverter 711 and the output terminal of the inverter 721 in the loop. The memory cell MC-m has an inverter 71m whose input terminal is connected to the output terminal side of the inverter 711, and an inverter 72m whose input terminal is connected to the output terminal of the inverter 71m. A switching element SWA-m is provided between the input terminal of the inverter 71m and the output terminal of the inverter 72m in the loop.

A switching element is provided at the input stage of each memory cell MC. Specifically, switching element SWB-0 is provided between the input terminal of inverter 710 and input terminal TI. Switching element SWB-1 is provided between the input terminal of inverter 711 and the output terminal of inverter 710. Switching element SWB-m is provided between the input terminal of inverter 71m and the output terminal side of inverter 711.

Each bit line is connected to a memory cell MC via a switching element. Specifically, the bit line BLY0 is connected to the memory cell MC-0 via the switching element SWC-0. More specifically, the bit line BLY0 is connected to a connection point CP0 between the output terminal of the inverter 720 in the loop circuit of the memory cell MC-0 and the switching element SWA-0 via the switching element SWC-0. The bit line BLY1 is connected to the memory cell MC-1 via the switching element SWC-1. More specifically, the bit line BLY1 is connected to a connection point CP1 between the output terminal of the inverter 721 in the loop circuit of the memory cell MC-1 and the switching element SWA-1 via the switching element SWC-1. The bit line BLYm is connected to the memory cell MC-m via the switching element SWC-m. More specifically, the bit line BLYm is connected to a connection point CPm between the output terminal of the inverter 72m in the loop circuit of the memory cell MC-m and the switching element SWA-m via the switching element SWC-m. In this embodiment, each connection point CP0, CP1, ... CPm forms a storage node of each memory cell.

The precharge circuit 52B is connected to each memory cell MC via a predetermined bit line and a switching element provided for each memory cell MC. Specifically, the precharge circuit 52B is connected to memory cell MC-0 via bit line BLY0 and switching element SWC-0. The precharge circuit 52B is also connected to memory cell MC-1 via bit line BLY1 and switching element SWC-1. The precharge circuit 52B is also connected to memory cell MC-m via bit line BLYm and switching element SWC-m.

The AD converter 62 is connected to each memory cell MC via a predetermined bit line and a switching element provided for each memory cell MC. Specifically, the AD converter 62 is connected to memory cell MC-0 via bit line BLY0 and switching element SWC-0. The AD converter 62 is also connected to memory cell MC-1 via bit line BLY1 and switching element SWC-1. The AD converter 62 is also connected to memory cell MC-m via bit line BLYm and switching element SWC-m.

(Example of processing performed in the memory unit)
Next, an example of processing performed in the memory unit 70 will be described. First, a data write process and a data read process for the memory unit 70 will be described. Note that, during the data write process and the data read process, all of the switching elements SWC-0, SWC-1, ..., SWC-m are turned off.

When data is written to memory cell MC-0, switching element SWB-0 is turned on, switching element SWB-1 is turned off, and switching element SWA-0 is turned off. As a result, H-level or L-level data input via input terminal TI is written and held in memory cell MC-0. The data written to memory cell MC-0 is transferred to the next-stage memory cell MC-1 in response to a predetermined clock signal. For example, switching element SWB-0 is turned off, switching element SWB-1 is turned on, switching element SWA-0 is turned on, and switching element SWA-1 is turned off. As a result, the data held in memory cell MC-0 is transferred to memory cell MC-1. By repeating the above process, image data input via input terminal TI is transferred sequentially, and one line's worth of image data is stored in memory unit 70. By sequentially transferring image data stored in each memory cell MC in response to a predetermined clock signal, the image data is read out and output from output terminal TO.

Next, the APL calculation process performed in the memory unit 70 will be described. The method of calculating the APL is basically the same as in the first embodiment. That is, the precharge circuit 52B precharges each bit line to the H level, the AD converter 62 detects the potential after a predetermined detection period, and outputs the value obtained by converting the detected potential into a digital signal to the APL calculation circuit 63. The APL calculation circuit 63 then calculates the APL according to the digital signal.

The APL calculation process is performed, for example, after one line of image data is stored in the memory unit 70. The APL calculation process can be performed at an appropriate timing within a series of sequences for processing image data.

After image data is written to each memory cell MC, the switching elements SWA-0, SWA-1...SWA-m and SWB-0, SWB-1...SWB-m are turned off. At this stage, each switching element SWC-0, SWC-1...SWC-m is also turned off. After each switching element SWC-0, SWC-1...SWC-m is turned on, the precharge circuit 52B operates to precharge each bit line BLY0, BLY1...BLYm to the H level.

As described above, when the logical levels of the connection points CP0, CP1, ... CPm, which are the storage nodes of each memory cell MC, are more H-level than L-level, the discharge amount is small and the drop in potential after precharge is small. When the logical levels of the connection points CP0, CP1, ... CPm, which are the storage nodes of each memory cell MC, are more L-level than H-level, the discharge amount is large and the drop in potential after precharge is large. By detecting the potential at a predetermined timing after the detection period, it is possible to detect the approximate number of H-levels of each connection point CP0, CP1, ... CPm, in other words, the memory state of each memory cell MC. The AD converter 62 converts the potential at the timing after the detection period into a digital signal and outputs it to the APL calculation circuit 63. The APL calculation circuit 63 calculates the APL according to the value of the digital signal and outputs the calculated APL to the image processing unit 26 at the subsequent stage. The processing using the APL in the image processing unit 26 is the same as in the first embodiment, so a duplicated description will be omitted.

As explained above, this technology can also be applied to memory units configured as line buffers.

<Application Examples>
(electronic equipment)
The display device according to the above embodiment to which the present technology is applied may be provided in various electronic devices. Application examples of the electronic device include the following.

(Application Example 1)
16 shows an example of the appearance of a head mounted display 110. The head mounted display 110 has, for example, ear hooks 112 for wearing on the user's head on both sides of a glasses-shaped display unit 111. The display system according to the above-described embodiment and the like can be applied to such a head mounted display 110.

(Application Example 2)
FIG. 17 shows an example of the appearance of another head mounted display 120. The head mounted display 120 is a see-through head mounted display having a main body 121, an arm 122, and a lens barrel 123. This head mounted display 120 is attached to glasses 128. The main body 121 has a control board and a display unit for controlling the operation of the head mounted display 120. This display unit emits image light of a display image. The arm 122 connects the main body 121 and the lens barrel 123, and supports the lens barrel 123. The lens barrel 123 projects the image light supplied from the main body 121 through the arm 122 toward the user's eyes through the lens 129 of the glasses 128. The display system according to the above embodiment can be applied to such a head mounted display 120.

Note that the head mounted display 120 is a so-called light guide plate type head mounted display, but is not limited to this and may be, for example, a so-called birdbath type head mounted display. The birdbath type head mounted display includes, for example, a beam splitter and a partially transparent mirror. The beam splitter outputs light encoded with image information toward the mirror, and the mirror reflects the light toward the user's eyes. Both the beam splitter and the partially transparent mirror are partially transparent. This allows light from the surrounding environment to reach the user's eyes.

(Application Example 3)
18A and 18B show an example of the appearance of a digital still camera 138, with FIG. 18A showing a front view and FIG. 18B showing a rear view. This digital still camera 138 is a lens-interchangeable single-lens reflex type camera, and has a camera main body (camera body) 131, a photographing lens unit 132, a grip unit 133, a monitor 134, and an electronic viewfinder 135. The photographing lens unit 132 is an interchangeable lens unit, and is provided near the approximate center of the front of the camera main body 311. The grip unit 133 is provided on the left side of the front of the camera main body 311, and the photographer holds the grip unit 133. The monitor 134 is provided on the left side of the approximate center of the rear of the camera main body 131. The electronic viewfinder 135 is provided above the monitor 134 on the rear of the camera main body 131. A photographer can visually confirm the optical image of the subject guided through the photographing lens unit 132 and determine the composition by looking through the electronic viewfinder 135. The display system according to the above-described embodiment and the like can be applied to the electronic viewfinder 135.

(Application Example 4)
19 shows an example of the appearance of a television device 140. The television device 140 has an image display screen unit 141 including a front panel 142 and a filter glass 143. The display system according to the above-described embodiment and the like can be applied to this image display screen unit 141.

(Application Example 5)
20 shows an example of the appearance of a smartphone 150. The smartphone 150 has a display unit 151 that displays various information, and an operation unit 152 that includes buttons and the like that accept operation inputs by a user. The display system according to the above-described embodiment and the like can be applied to this display unit 151.

(Application Example 6)
The display device according to the above-described embodiment may be provided in various displays provided in vehicles.

21A and 21B are diagrams showing an example of the internal configuration of a vehicle 200 equipped with various displays. Specifically, FIG. 21A is a diagram showing an example of the interior of the vehicle 200 from the rear to the front, and FIG. 21B is a diagram showing an example of the interior of the vehicle 200 from diagonally rear to diagonally front.

The vehicle 200 includes a center display 201, a console display 202, a head-up display 203, a digital rear mirror 204, a steering wheel display 205, and a rear entertainment display 206. At least one of these displays includes a display system according to an embodiment. For example, all of these displays may include a display system according to an embodiment.

The center display 201 is disposed in a portion of the dashboard facing the driver's seat 208 and the passenger seat 209. Although Figs. 21A and 21B show an example of a horizontally elongated center display 201 extending from the driver's seat 208 side to the passenger seat 209 side, the screen size and location of the center display 201 are arbitrary. The center display 201 can display information detected by various sensors. As a specific example, the center display 201 can display an image captured by an image sensor, an image of the distance to an obstacle in front of or to the side of the vehicle 200 measured by a ToF sensor, and the body temperature of a passenger detected by an infrared sensor. The center display 201 can be used to display, for example, at least one of safety-related information, operation-related information, a life log, health-related information, authentication/identification-related information, and entertainment-related information.

The safety-related information includes information such as detection of drowsiness, detection of distraction, detection of tampering by children in the vehicle, whether or not a seat belt is fastened, and detection of an occupant being left behind, and is information detected, for example, by a sensor arranged on the back side of the center display 201. The operation-related information is obtained by detecting gestures related to the operation of the occupant using a sensor. The detected gestures may include operations of various facilities in the vehicle 200. For example, operations of air conditioning equipment, navigation equipment, AV equipment, lighting equipment, etc. are detected. The life log includes the life log of all occupants. For example, the life log includes a record of the actions of each occupant while on board. By acquiring and saving the life log, it is possible to confirm the condition of the occupant at the time of the accident. The health-related information is obtained by detecting the body temperature of the occupant using a sensor such as a temperature sensor, and inferring the health condition of the occupant based on the detected body temperature. Alternatively, the face of the occupant may be captured using an image sensor, and the health condition of the occupant may be inferred from the facial expression captured in the image. Furthermore, the occupant may be spoken to by an automated voice and the occupant's health condition may be inferred based on the occupant's responses. Authentication/identification related information includes a keyless entry function that uses a sensor to perform face authentication, and a function for automatically adjusting seat height and position using face recognition. Entertainment related information includes a function for detecting operation information of an AV device by an occupant using a sensor, and a function for recognizing the occupant's face using a sensor and providing content suitable for the occupant via the AV device.

The console display 202 can be used, for example, to display life log information. The console display 202 is disposed near the shift lever 211 on the center console 210 between the driver's seat 208 and the passenger seat 209. Information detected by various sensors can also be displayed on the console display 202. In addition, the console display 202 may display an image of the surroundings of the vehicle captured by an image sensor, or may display an image showing the distance to obstacles around the vehicle.

The head-up display 203 is virtually displayed behind the windshield 212 in front of the driver's seat 208. The head-up display 203 can be used to display, for example, at least one of safety-related information, operation-related information, a life log, health-related information, authentication/identification-related information, and entertainment-related information. Since the head-up display 203 is often virtually positioned in front of the driver's seat 208, it is suitable for displaying information directly related to the operation of the vehicle 200, such as the speed of the vehicle 200 and the remaining fuel (battery) level.

The digital rear-view mirror 204 can not only display the rear of the vehicle 200, but also display the state of passengers in the back seats. Therefore, by placing a sensor on the back side of the digital rear-view mirror 204, it can be used to display life log information, for example.

The steering wheel display 205 is disposed near the center of the steering wheel 213 of the vehicle 200. The steering wheel display 205 can be used to display, for example, at least one of safety-related information, operation-related information, life log, health-related information, authentication/identification-related information, and entertainment-related information. In particular, since the steering wheel display 205 is located near the driver's hands, it is suitable for displaying life log information such as the driver's body temperature, and for displaying information related to the operation of AV equipment, air conditioning equipment, etc.

The rear entertainment display 206 is attached to the back side of the driver's seat 208 and passenger seat 209, and is intended for viewing by rear seat passengers. The rear entertainment display 206 can be used to display at least one of safety-related information, operation-related information, life log, health-related information, authentication/identification-related information, and entertainment-related information, for example. In particular, since the rear entertainment display 206 is located in front of the rear seat passengers, information related to the rear seat passengers is displayed on the rear entertainment display 206. For example, the rear entertainment display 206 may display information related to the operation of AV equipment or air conditioning equipment, or may display the results of measuring the body temperature of the rear seat passengers using a temperature sensor.

A sensor may be placed on the back side of the display device to measure the distance to surrounding objects. Optical distance measurement methods are broadly divided into passive and active types. Passive types measure distance by receiving light from an object without projecting light from the sensor onto the object. Passive types include the lens focusing method, stereo method, and monocular vision method. Active types measure distance by projecting light onto an object and receiving the light reflected from the object with a sensor. Active types include the optical radar method, active stereo method, photometric stereo method, moire topography method, and interference method. The above display device can be applied to any of these distance measurement methods. By using a sensor placed on the back side of the above display device, the above passive or active distance measurement can be performed.

<Modification>
Although the embodiments and application examples of the present technology have been specifically described above, the content of the present technology is not limited to the above-described embodiments and application examples, and various modifications based on the technical ideas of the present technology are possible.

[Modification of pixel circuit]
First, a modified example of the pixel circuit will be described. Fig. 22 shows another example of the configuration of the pixel circuit (pixel) PIX. This pixel circuit PIX has capacitors C11 and C12, transistors MP12 to MP15, and a light-emitting element EL. The transistors MP12 to MP15 are P-type MOSFETs. The gate of the transistor MP12 is connected to a control line WSL, the source is connected to a signal line SIG, and the drain is connected to the gate of the transistor MP14 and the capacitor C12. One end of the capacitor C11 is connected to a power supply line VCCP, and the other end is connected to the capacitor C12, the drain of the transistor MP13, and the source of the transistor MP14. One end of the capacitor C12 is connected to the other end of the capacitor C11, the drain of the transistor MP13, and the source of the transistor MP14, and the other end is connected to the drain of the transistor MP12 and the gate of the transistor MP14. The gate of the transistor MP13 is connected to the control line DSL, the source is connected to the power supply line VCCP, and the drain is connected to the source of the transistor MP14, the other end of the capacitor C11, and one end of the capacitor C12. The gate of the transistor MP14 is connected to the drain of the transistor MP12 and the other end of the capacitor C12, the source is connected to the drain of the transistor MP13, the other end of the capacitor C11, and one end of the capacitor C12, and the drain is connected to the anode of the light-emitting element EL and the source of the transistor MP15. The gate of the transistor MP15 is connected to the control line AZSL, the source is connected to the drain of the transistor MP14 and the anode of the light-emitting element EL, and the drain is connected to the power supply line VSS.

With this configuration, in the pixel circuit PIX, when the transistor MP12 is turned on, the voltage across the capacitor C12 is set based on the pixel signal supplied from the signal line SIG. The transistor MP13 is turned on and off based on the signal on the control line DSL. During the period when the transistor MP13 is on, the transistor MP14 passes a current corresponding to the voltage across the capacitor C12 through the light-emitting element EL. The light-emitting element EL emits light based on the current supplied from the transistor MP14. In this way, the pixel circuit PIX emits light at a brightness corresponding to the pixel signal. The transistor MP15 is turned on and off based on the signal on the control line AZSL. During the period when the transistor MP15 is on, the voltage of the anode of the light-emitting element EL is initialized by being set to the voltage of the power supply line VSS.

Note that the transistors MP12 to MP15 may be transistors using low temperature polycrystalline silicon (LTPS). In addition, at least one of the transistors MP12 and MP15 may be a transistor using an oxide semiconductor.

Figure 23 shows another example configuration of the pixel circuit PIX. This pixel circuit PIX has a capacitor C21, transistors MN22 to MN25, and a light-emitting element EL. Transistors MN22 to MN25 are N-type MOSFETs. The gate of transistor MN22 is connected to a control line WSL, the drain is connected to a signal line SIG, and the source is connected to the gate of transistor MN24 and capacitor C21. One end of capacitor C21 is connected to the source of transistor MN22 and the gate of transistor MN24, and the other end is connected to the source of transistor MN24, the drain of transistor MN25, and the anode of the light-emitting element EL. The gate of transistor MN23 is connected to a control line DSL, the drain is connected to a power supply line VCCP, and the source is connected to the drain of transistor MN24. The gate of transistor MN24 is connected to the source of transistor MN22 and one end of capacitor C21, the drain is connected to the source of transistor MN23, the source is connected to the other end of capacitor C21, the drain of transistor MN25, and the anode of the light-emitting element EL. The gate of transistor MN25 is connected to the control line AZSL, the drain is connected to the source of transistor MN24, the other end of capacitor C21, and the anode of the light-emitting element EL, and the source is connected to the power supply line VSS.

With this configuration, in the pixel circuit PIX, when the transistor MN22 is turned on, the voltage across the capacitor C21 is set based on the pixel signal supplied from the signal line SIG. The transistor MN23 is turned on and off based on the signal on the control line DSL. During the period when the transistor MN23 is on, the transistor MN24 passes a current corresponding to the voltage across the capacitor C21 through the light-emitting element EL. The light-emitting element EL emits light based on the current supplied from the transistor MN24. In this way, the pixel circuit PIX emits light with a brightness corresponding to the pixel signal. The transistor MN25 is turned on and off based on the signal on the control line AZSL. During the period when the transistor MN25 is on, the voltage of the anode of the light-emitting element EL is initialized by being set to the voltage of the power supply line VSS.

Note that the transistors MN22 to MN25 may be transistors using low temperature polycrystalline silicon (LTPS). In addition, at least one of the transistors MN22 and MN25 may be a transistor using an oxide semiconductor.

Figure 24 shows another example configuration of the pixel circuit PIX. This pixel circuit PIX has a capacitor C31, transistors MP32 to MP36, and a light-emitting element EL. Transistors MP32 to MP36 are P-type MOSFETs. The gate of transistor MP32 is connected to a control line WSL, its source is connected to a signal line SIG, and its drain is connected to the gate of transistor MP33, the drain of transistor MP34, and capacitor C31. One end of capacitor C31 is connected to a power supply line VCCP, and the other end is connected to the drain of transistor MP32, the gate of transistor MP33, and the drain of transistor MP34. The gate of transistor MP34 is connected to a control line AZSL1, its source is connected to the drain of transistor MP33 and the source of transistor MP35, and its drain is connected to the drain of transistor MP32, the gate of transistor MP33, and the other end of capacitor C31. The gate of transistor MP35 is connected to the control line DSL, the source is connected to the drain of transistor MP33 and the source of transistor MP34, and the drain is connected to the source of transistor MP36 and the anode of the light-emitting element EL. The gate of transistor MP36 is connected to the control line AZSL2, the source is connected to the drain of transistor MP35 and the anode of the light-emitting element EL, and the drain is connected to the power supply line VSS.

With this configuration, in the pixel circuit PIX, when the transistor MP32 is turned on, the voltage across the capacitor C31 is set based on the pixel signal supplied from the signal line SIG. The transistor MP35 is turned on and off based on the signal on the control line DSL. During the period when the transistor MP35 is on, the transistor MP33 passes a current corresponding to the voltage across the capacitor C31 through the light-emitting element EL. The light-emitting element EL emits light based on the current supplied from the transistor MP33. In this way, the pixel circuit PIX emits light at a luminance corresponding to the pixel signal. The transistor MP34 is turned on and off based on the signal on the control line AZSL1. During the period when the transistor MP34 is on, the drain and gate of the transistor MP33 are connected to each other. The transistor MP36 is turned on and off based on the signal on the control line AZSL2. During the period when the transistor MP36 is on, the voltage of the anode of the light-emitting element EL is initialized by being set to the voltage of the power supply line VSS.

Note that transistors MP32 to MP36 may be transistors using low temperature polycrystalline silicon (LTPS). Also, at least one of transistors MP32, MP34, and MP36 may be a transistor using an oxide semiconductor.

FIG. 25 shows another example of the configuration of the pixel circuit PIX. One end of the capacitor C48 is connected to the signal line SIG1, and the other end is connected to the power supply line VSS. One end of the capacitor C49 is connected to the signal line SIG1, and the other end is connected to the signal line SIG2. The transistor MP49 is a P-type MOSFET, with its gate connected to the control line WSL2, its source connected to the signal line SIG1, and its drain connected to the signal line SIG2.

The pixel circuit PIX has a capacitor C41, transistors MP42 to MP46, and a light-emitting element EL. Transistors MP42 to MP46 are P-type MOSFETs. The gate of transistor MP42 is connected to control line WSL1, its source is connected to signal line SIG2, and its drain is connected to the gate of transistor MP43 and capacitor C41. One end of capacitor C41 is connected to power supply line VCCP, and the other end is connected to the drain of transistor MP42 and the gate of transistor MP43. The gate of transistor MP43 is connected to the drain of transistor MP42 and the other end of capacitor C41, its source is connected to power supply line VCCP, and its drain is connected to the sources of transistors MP44 and MP45. The gate of transistor MP44 is connected to control line AZSL1, its source is connected to the drain of transistor MP43 and the source of transistor MP45, and its drain is connected to signal line SIG2. The gate of transistor MP45 is connected to the control line DSL, the source is connected to the drain of transistor MP43 and the source of transistor MP44, and the drain is connected to the source of transistor MP46 and the anode of the light-emitting element EL. The gate of transistor MP46 is connected to the control line AZSL2, the source is connected to the drain of transistor MP45 and the anode of the light-emitting element EL, and the drain is connected to the power supply line VSS.

With this configuration, in the pixel circuit PIX, when the transistor MP42 is turned on, the voltage across the capacitor C41 is set based on the pixel signal supplied from the signal line SIG1 via the capacitor C49. The transistor MP45 is turned on and off based on the signal on the control line DSL. During the period when the transistor MP45 is on, the transistor MP43 passes a current corresponding to the voltage across the capacitor C41 through the light-emitting element EL. The light-emitting element EL emits light based on the current supplied from the transistor MP43. In this way, the pixel circuit PIX emits light at a luminance corresponding to the pixel signal. The transistor MP44 is turned on and off based on the signal on the control line AZSL1. During the period when the transistor MP44 is on, the drain of the transistor MP43 and the signal line SIG2 are connected to each other. The transistor MP46 is turned on and off based on the signal on the control line AZSL2. During the period when the transistor MP46 is on, the voltage of the anode of the light-emitting element EL is initialized by being set to the voltage of the power supply line VSS.

Note that transistors MP42 to MP46 and MP49 may be transistors using low temperature polycrystalline silicon (LTPS). Also, at least one of transistors MP42, MP46 and MP49 may be a transistor using an oxide semiconductor.

FIG. 26 shows another example of the configuration of the pixel circuit PIX. A plurality of pixel circuits PIX are arranged in a matrix in the display area 300, and the display area 300 is arranged between the first control unit 400 and the second control unit 80.

The first control unit 400 has transmission gates TG45 and TG46, transistors MP56 and MP57, and a capacitor C61. The transistors MP56 and MP57 are P-type MOSFETs. A pixel signal is supplied to the input terminal of the transmission gate TG45, and the output terminal of the transmission gate TG45 is connected to one end of the signal line 14a. The input terminal of the transmission gate TG46 is connected to the signal line 14b, and the output terminal of the transmission gate TG46 is connected to the power line Vorst. One end of the capacitor C61 is connected to the signal line 14a, and the other end is connected to the power line VSS1. The gate of the transistor MP56 is connected to the control line INIL, the source is connected to the power line Vini, and the drain is connected to the signal line 14b. The gate of the transistor MP57 is connected to the control line ELL, the source is connected to the power line Vel, and the drain is connected to the signal line 14b.

The second control unit 80 has a transmission gate TG72, a transistor MP73, and a capacitor C82. The transistor MP73 is a P-type MOSFET. The input end of the transmission gate TG72 is connected to the other end of the signal line 14a, and the output end is connected to the drain of the transistor MP73 and one end of the capacitor C82. The gate of the transistor MP73 is connected to the control line REFL, the source is connected to the power supply line Vref, and the drain is connected to the output end of the transmission gate TG72 and one end of the capacitor C82. One end of the capacitor C82 is connected to the output end of the transmission gate TG72 and the drain of the transistor MP73, and the other end is connected to one end of the signal line 14b.

The pixel circuit PIX has a capacitor C132, transistors MP121 to MP125, and a light-emitting element EL. Transistors MP121 to MP125 are P-type MOSFETs. The gate of transistor MP122 is connected to a control line WSL, its source is connected to signal line 14b, and its drain is connected to the gate of transistor MP121 and capacitor C132. One end of capacitor C132 is connected to a power supply line Vel, and the other end is connected to the drain of transistor MP122 and the gate of transistor MP121. The gate of transistor MP121 is connected to the drain of transistor MP122 and the other end of capacitor C132, its source is connected to the power supply line Vel, and its drain is connected to the sources of transistors MP123 and MP124. The gate of transistor MP123 is connected to a control line AZSL, its source is connected to the drain of transistor MP121 and the source of transistor MP124, and its drain is connected to signal line 14b. The gate of transistor MP124 is connected to the control line DSL, the source is connected to the drain of transistor MP121 and the source of transistor MP123, and the drain is connected to the drain of transistor MP125 and the anode of light-emitting element 130. The gate of transistor MP125 is connected to the control line AZSL, the source is connected to the power supply line Vorst, and the drain is connected to the drain of transistor MP124 and the anode of light-emitting element 130.

With this configuration, in the pixel circuit PIX, when the transistor MP122 is turned on, the voltage across the capacitor C132 is set based on the pixel signal supplied via the transmission gate TG45, the signal line 14a, the transmission gate TG72, the capacitor C82, and the signal line 14b. The transistor MP124 is turned on and off based on the signal on the control line DSL. During the period when the transistor MP124 is on, the transistor MP121 passes a current corresponding to the voltage across the capacitor C132 through the light-emitting element EL. The light-emitting element EL emits light based on the current supplied from the transistor MP121. In this way, the pixel circuit PIX emits light at a luminance corresponding to the pixel signal. The transistors MP123 and MP125 are turned on and off based on the signal on the control line AZSL. During the period when the transistor MP123 is on, the drain of the transistor MP121 and the source of the transistor MP124 are connected to the signal line 14b. During the period when transistor MP125 is in the ON state, the voltage of the anode of the light-emitting element EL is initialized by being set to the voltage of the power supply line Vorst. In addition, transistor MP56 is turned on and off based on the signal of the control line INIL, transistor MP57 is turned on and off based on the signal of the control line ELL, and transistor MP73 is turned on and off based on the signal of the control line REFL. When transistor MP56 is in the ON state, signal line 14b is set to the voltage of the power supply line Vini, and when transistor MP57 is in the ON state, signal line 14b is set to the voltage of the power supply line Vel. When transistor MP73 is in the ON state, one end of capacitor C82 is initialized by being set to the voltage of the power supply line Vref.

Note that transistors MP121 to MP125, MP56, and MP57 may be transistors using low temperature polycrystalline silicon (LTPS). Also, at least one of transistors MP122 and MP125 may be a transistor using an oxide semiconductor.

Figure 27 shows another example configuration of a pixel circuit PIX. This pixel circuit PIX has a capacitor C51, transistors MP52 to MP60, and a light-emitting element EL. Transistors MP52 to MP60 are P-type MOSFETs. The gate of transistor MP52 is connected to a control line WSL, its source is connected to a signal line SIG, and its drain is connected to the drain of transistor MP53 and the source of transistor MP54. The gate of transistor MP53 is connected to a control line DSL, its source is connected to a power supply line VCCP, and its drain is connected to the drain of transistor MP52 and the source of transistor MP54. The gate of transistor MP54 is connected to the source of transistor MP55, the drain of transistor MP57, and capacitor C51, its source is connected to the drains of transistors MP52 and MP53, and its drain is connected to the sources of transistors MP58 and MP59. One end of the capacitor C51 is connected to the power supply line VCCP, and the other end is connected to the gate of the transistor MP54, the source of the transistor MP55, and the drain of the transistor MP57. The capacitor C51 may include two capacitors connected in parallel to each other. The gate of the transistor MP55 is connected to the control line AZSL1, the source is connected to the gate of the transistor MP54, the drain of the transistor MP57, and the other end of the capacitor C51, and the drain is connected to the source of the transistor MP56. The gate of the transistor MP56 is connected to the control line AZSL1, the source is connected to the drain of the transistor MP55, and the drain is connected to the power supply line VSS. The gate of the transistor MP57 is connected to the control line WSL, the drain is connected to the gate of the transistor MP54, the source of the transistor MP55, and the other end of the capacitor C51, and the source is connected to the drain of the transistor MP58. The gate of transistor MP58 is connected to the control line WSL, the drain is connected to the source of transistor MP57, and the source is connected to the drain of transistor MP54 and the source of transistor MP59. The gate of transistor 59 is connected to the control line DSL, the source is connected to the drain of transistor MP54 and the source of transistor MP58, and the drain is connected to the source of transistor MP60 and the anode of the light-emitting element EL. The gate of transistor MP60 is connected to the control line AZSL2, the source is connected to the drain of transistor MP59 and the anode of the light-emitting element EL, and the drain is connected to the power supply line VSS.

With this configuration, in the pixel circuit PIX, the transistors MP52, MP54, MP58, and MP57 are turned on, and the voltage across the capacitor C51 is set based on the pixel signal supplied from the signal line SIG. The transistors MP53 and MP59 are turned on and off based on the signal on the control line DSL. During the period when the transistors MP53 and MP59 are on, the transistor MP54 passes a current corresponding to the voltage across the capacitor C51 through the light-emitting element EL. The light-emitting element EL emits light based on the current supplied from the transistor MP54. In this way, the pixel circuit PIX emits light with a luminance corresponding to the pixel signal. The transistors MP55 and MP56 are turned on and off based on the signal on the control line AZSL1. During the period when the transistors MP55 and MP56 are on, the voltage of the gate of the transistor MP54 is initialized by being set to the voltage of the power supply line VSS. The transistor MP60 is turned on and off based on the signal on the control line AZSL2. While the transistor MP60 is in the on state, the anode voltage of the light-emitting element EL is initialized by being set to the voltage of the power supply line VSS.

Note that transistors MP52 to MP60 may be transistors using low temperature polycrystalline silicon (LTPS). Also, at least one of transistors MP55 to MP58 and MP60 may be a transistor using an oxide semiconductor.

FIG. 28 shows another example of the configuration of the pixel circuit PIX. The signal on the control line WSNL and the signal on the control line WSPL are mutually inverted signals.

The pixel circuit PIX has capacitors C61 and C62, transistors MN63, MP64, MN65 to MN67, and a light-emitting element EL. Transistors MN63, MN65 to MN67 are N-type MOSFETs, and transistor MP64 is a P-type MOSFET. The gate of transistor MN63 is connected to a control line WSNL, the drain is connected to a signal line SIG and the source of transistor MP64, the source is connected to the drain of transistor MP64, capacitors C61 and C62, and the gate of transistor MN65. The gate of transistor MP64 is connected to a control line WSPL, the source is connected to a signal line SIG and the drain of transistor MN63, and the drain is connected to the source of transistor MN63, capacitors C61 and C62, and the gate of transistor MN65. The capacitor C61 is configured, for example, using a MOM (Metal Oxide Metal) capacitor, one end of which is connected to the source of the transistor MN63, the drain of the transistor MP64, the capacitor C62, and the gate of the transistor MN65, and the other end of which is connected to the power supply line VSS2. The capacitor C61 may be configured, for example, using a MOS capacitor or a MIM (Metal Insulator Metal) capacitor. The capacitor C62 is configured, for example, using a MOS capacitor, one end of which is connected to the source of the transistor MN63, the drain of the transistor MP64, one end of the capacitor C61, and the gate of the transistor MN65, and the other end of which is connected to the power supply line VSS2. The capacitor C62 may be configured, for example, using a MOM capacitor or a MIM capacitor. The other end of the capacitor C62 may be connected to the power supply line VSS3 (not shown). The gate of transistor MN65 is connected to the source of transistor MN63, the drain of transistor MP64, and one end of capacitors C61 and C62, the drain is connected to the power supply line VCCP, and the source is connected to the drains of transistors MN66 and MN67. The gate of transistor MN66 is connected to the control line AZL, the drain is connected to the source of transistor MN65 and the drain of transistor MN67, and the source is connected to the power supply line VSS1. The gate of transistor MN67 is connected to the control line DSL, the drain is connected to the source of transistor MN65 and the drain of transistor MN66, and the source is connected to the anode of the light-emitting element EL. Note that the transistor MN67 and the control line DSL may not be provided, and the source of transistor MN65 may be connected to the drain of transistor MN66 and the anode of the light-emitting element EL.

With this configuration, in the pixel circuit PIX, when at least one of the transistors MN63 and MP64 is turned on, the voltage between both ends of the capacitors C61 and C62 is set based on the pixel signal supplied from the signal line SIG. The transistor MN67 is turned on and off based on the signal on the control line DSL. During the period when the transistor MN67 is in the on state, the transistor MN65 passes a current corresponding to the voltage between both ends of the capacitors C61 and C62 through the light-emitting element EL. The light-emitting element EL emits light based on the current supplied from the transistor MP65. In this way, the pixel circuit PIX emits light with a luminance corresponding to the pixel signal. The transistor MN66 may be turned on and off based on the signal on the control line AZL. The transistor MN66 may also function as a resistive element having a resistance value corresponding to the signal on the control line AZL. In this case, the transistors MN65 and MN66 form a so-called source follower circuit.

Note that the transistors MN63, MP64, MN65 to MN67 may be transistors using low temperature polycrystalline silicon (LTPS: Low Temperature Polysilicon). Also, at least one of the transistors MN63, MP64, and MN66 may be a transistor using an oxide semiconductor.

[Other Modifications]
In the first embodiment described above, the APL of the entire frame is calculated, but the APL of a specific region in one frame may be calculated. For example, the address decoder selects memory cells included in the specific region, and the selected memory cells are subjected to the processing described in the embodiment to calculate the APL in the specific region. For example, in a display system using VR glasses, only a portion of image data (a portion of image data of one frame) may be displayed on a portion of the display device. In this case, if the APL is calculated using data for one frame, the difference with the APL corresponding to the portion of image data may become large, and the result of image processing using the APL may become inappropriate. However, such inconvenience can be avoided by selecting a portion of memory cells and calculating the APL of the portion of image data in which the memory cells are included, as in this modified example.

The memory cell unit MCX described above stores data corresponding to each of the colors RGB, for example. When calculating the APL, weighting according to each color may be applied. For example, the APL may be calculated by weighting the G component, which has high luminosity, more heavily than the R and B components. Also, in the case of 8-bit image data, for example, the APL may be calculated by weighting the MSB (Most Significant Bit) or a few bits from the MSB more heavily than the LSB (Least Significant Bit). For example, a large weight may be assigned to a memory cell MC corresponding to green or a memory cell MC corresponding to the MSB, and the APL may be calculated by applying the weighting to the data corresponding to the memory cell MC.

In the above-described embodiment, the circuit configuration of the memory unit 25 and the arrangement of each component are merely examples and are not limited to the illustrated circuit configurations, and other known circuit configurations can be applied. In addition, an APL configured with a logic circuit, i.e., a circuit capable of calculating the APL with high accuracy, may be provided, and two APL calculation circuits may be switched so that the APL calculation circuit described in the embodiment is used for normal processing, and the APL calculation circuit configured with a logic circuit is used for processing requiring a high accuracy APL. In addition, the memory unit described in the second embodiment may be a memory capable of storing image data for multiple lines. In addition, from the viewpoint of obtaining the effects described in the embodiment, it is preferable that the AD converter and the APL calculation circuit are configured as in-memory computing, but they may be separate from the memory unit.

For example, the configurations, methods, processes, shapes, materials, and numerical values of the above-mentioned embodiments and application examples can be combined or substituted with each other without departing from the spirit of the present technology. Also, one thing can be divided into two or more things, and some can be omitted. Also, as long as the present technology is applicable, each of the above-mentioned configurations can be added, deleted, or modified as appropriate.

The present technology can also be configured as follows.
(1)
A memory unit for temporarily storing image data;
The memory unit includes:
A memory cell;
an AD converter connected to a storage node of the memory cell;
A signal processing device comprising:
(2)
the memory unit has a precharge circuit,
the precharge circuit is connected to a storage node of the memory cell;
A signal processing device as described in (1).
(3)
the AD converter and the precharge circuit are connected to the storage node via a predetermined bit line;
A signal processing device as described in (2).
(4)
The precharge circuit precharges the bit line at a predetermined timing;
the AD converter converts the potential of the bit line after a predetermined period of time from an analog signal to a digital signal;
A signal processing device as described in (3).
(5)
The memory unit has an average luminance calculation unit,
The average luminance calculation unit calculates an average luminance of the image data based on the digital signal.
A signal processing device as described in (4).
(6)
The memory unit has an address decoder,
the average luminance calculation unit calculates an average luminance in a specific area of the image data specified by the address decoder;
A signal processing device as described in (5).
(7)
the average luminance calculation unit calculates an average luminance by using a weight associated with the memory cell;
A signal processing device according to (5) or (6).
(8)
an image processing unit that performs image processing according to the average luminance calculated by the average luminance calculation unit;
A signal processing device according to any one of (5) to (7).
(9)
A plurality of memory cell groups each including a plurality of the memory cells;
the AD converter and the precharge circuit are provided for each of the plurality of memory cell groups;
A signal processing device according to any one of (2) to (8).
(10)
the memory cell is an SRAM cell,
the SRAM cell having a first storage node and a second storage node;
a first bit line is connected to the first storage node, and a second bit line is connected to the second storage node;
the AD converter is connected to the first bit line and the second bit line;
the precharge circuit is connected to the first bit line and the second bit line;
A signal processing device according to any one of (3) to (8).
(11)
The memory unit has an address decoder,
The SRAM cells are connected to word lines extending from the address decoder.
A signal processing device as described in (10).
(12)
the memory unit has a memory cell unit configured of a plurality of the memory cells,
The memory cell unit is configured as a line buffer that stores the image data for one line or a predetermined number of lines.
A signal processing device according to any one of (2) to (8).
(13)
the AD converter and the precharge circuit are connected to a storage node of each memory cell constituting the line buffer via a switch provided for each of the memory cells;
A signal processing device as described in (12).
(14)
A signal processing device according to any one of (1) to (13) above;
a display device that displays the image data read from the memory unit;
A display system including:
(15)
(14) An electronic device having the display system according to (14).

2: Timing controller 4: Display device 25: Memory section 26: Image processing section 52A: Address decoder 62: Arithmetic circuit 63: APL calculation circuit 100: Display system MCX: Memory cell section MC-00 to MC-mn, MC-0 to MC-m: Memory cell

Claims (15)

A memory unit for temporarily storing image data;
The memory unit includes:
A memory cell;
an AD converter connected to a storage node of the memory cell;
A signal processing device comprising: the memory unit has a precharge circuit,
the precharge circuit is connected to a storage node of the memory cell;
The signal processing device according to claim 1 . the AD converter and the precharge circuit are connected to the storage node via a predetermined bit line;
The signal processing device according to claim 2 . The precharge circuit precharges the bit line at a predetermined timing;
The AD converter converts the potential of the bit line after a predetermined period of time from an analog signal to a digital signal.
The signal processing device according to claim 3 . The memory unit has an average luminance calculation unit,
The average luminance calculation unit calculates an average luminance of the image data based on the digital signal.
The signal processing device according to claim 4. The memory unit has an address decoder,
the average luminance calculation unit calculates an average luminance in a specific area of the image data selected by the address decoder;
The signal processing device according to claim 5 . the average luminance calculation unit calculates an average luminance by using a weight associated with the memory cell;
The signal processing device according to claim 5 . an image processing unit that performs image processing according to the average luminance calculated by the average luminance calculation unit;
The signal processing device according to claim 5 . A plurality of memory cell groups each including a plurality of the memory cells;
the AD converter and the precharge circuit are provided for each of the plurality of memory cell groups;
The signal processing device according to claim 2 . the memory cell is an SRAM cell,
the SRAM cell having a first storage node and a second storage node;
a first bit line is connected to the first storage node, and a second bit line is connected to the second storage node;
the AD converter is connected to the first bit line and the second bit line;
the precharge circuit is connected to the first bit line and the second bit line;
The signal processing device according to claim 3 . The memory unit has an address decoder,
The SRAM cells are connected to word lines extending from the address decoder.
The signal processing device according to claim 10. the memory unit has a memory cell unit configured of a plurality of the memory cells,
The memory cell unit is configured as a line buffer that stores the image data for one line or a predetermined number of lines.
The signal processing device according to claim 2 . the AD converter and the precharge circuit are connected to a storage node of each memory cell constituting the line buffer via a switch provided for each of the memory cells;
The signal processing device according to claim 12. A signal processing device according to claim 1 ;
a display device that displays the image data read from the memory unit;
A display system including: An electronic device having the display system according to claim 14.

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