Search Results for "fpga"
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Showing 165 open source projects for "fpga"
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AWS EC2 FPGA
AWS EC2 FPGA hardware and software development Kit
AWS EC2 FPGA Development Kit is a set of development and runtime tools to develop, simulate, debug, compile and run hardware-accelerated applications on Amazon EC2 F1 instances. It is distributed between this GitHub repository and FPGA Developer AMI - Centos/AL2 provided by AWS with no cost of development tools. After creating an FPGA design (also called CL - Custom logic), developers can create an Amazon FPGA Image (AFI) and easily deploy it to an F1 instance. AFIs are reusable, shareable... -
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Icestudio
Visual editor for open FPGA boards
Visual editor for open FPGA boards. Built on top of the Icestorm project using Apio. -
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dsp-fpga-dip-nn-pasa-itba
Archivos para TPs de materias de Ingeniería Electrónica - ITBA
Repositorio de archivos varios para TPs de materias de la carrera Ingeniería Electrónica del Instituto Tecnológico de Buenos Aires (ITBA). En general, son archivos .zip con imágenes o audios, para descargar en notebooks de Python (Jupyter) con wget o similares. 22.49 - Laboratorio de Dsp_fpga --->>> dsp-fpga 22.48 - Procesamiento de Imágenes --->>> dip 25.87 - Redes Neuronales II --->>> nn 22.46 - Procesamiento Adaptativo de Señales (Aleatorias) --->>> pasa -
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BSC
Bluespec Compiler (BSC)
BSC is the open source compiler toolchain for Bluespec SystemVerilog, a high-level, rule-based hardware design language. It translates Bluespec descriptions into synthesizable Verilog, letting developers bring typed, modular abstractions into mainstream FPGA/ASIC flows. The compiler performs scheduling of atomic rules, elaborates parameterized modules, and enforces interface contracts, producing predictable RTL that integrates with existing EDA tools. A companion simulator enables fast... -
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SWUpdate
Software Update for Embedded Systems
SWUpdate is a Linux Update agent with the goal to provide an efficient and safe way to update an embedded Linux system in the field. SWUpdate supports local and OTA updates and multiple update strategies and it is designed with security in mind. To start with SWUpdate, it is suggested you look at the documentation and build for one evaluation board (or you run SWUpdate on your host for a first overview). If you plan to update your device locally or remotely, SWUpdate is the right framework... -
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Openwifi
open-source IEEE 802.11 WiFi baseband FPGA (chip) design
Linux mac80211 compatible full-stack IEEE802.11/Wi-Fi design based on SDR (Software Defined Radio). -
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Chipyard
An Agile RISC-V SoC Design Framework with in-order cores
Chipyard is a framework and generator for constructing custom RISC‑V SoC hardware. Built at UC Berkeley, it leverages Chisel/FIRRTL to generate full-stack systems—from CPU cores to peripherals—and includes simulators, FPGA deployment tools, and integration with Rocket Chip and other RISC‑V ecosystems. -
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FuseSoC
Package manager and build abstraction tool for FPGA/ASIC development
FuseSoC is a package manager and build abstraction tool for hardware description language (HDL) code, aimed at simplifying the development and reuse of IP cores. It provides a standardized way to describe, manage, and build hardware projects, facilitating collaboration and reducing duplication of effort in FPGA and ASIC development. -
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XLS
XLS: Accelerated HW Synthesis
XLS is an open-source toolkit for building high-level hardware with a modern compiler stack that spans from a functional DSL to optimized IR and hardware generation. At the front end, DSLX lets you describe algorithms with strong typing and familiar control flow while remaining synthesis-friendly. The compiler lowers DSLX into a rich intermediate representation, applies aggressive optimization and scheduling passes, and can either JIT the design for software simulation or emit Verilog for FPGA... -
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DarFPGA
FPGA software and hardware
FPGA software and hardware, mainly recreation of old stuff (Arcade or 8bits computer) at low cost. -
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Dogecoin Mining - Software
This is a multi-threaded multi-pool FPGA and ASIC miner for DOGECOIN
Dogecoin Mining - Software is an open source miner for ASIC, GPU and FPGA. It works on Windows, Linux and macOS. This miner is extremely flexible in terms of platform and can work with a variety of hardware miners and GPUs including AMD, CUDA and NVIDIA platforms.">
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Infra-red Remote Sampler
Infra-red Remote Control Sampling using FPGA
Infra-red Remote Control Sampling using FPGA -
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Software interface and gateware for magnetic resonance experiments using the limesdr board, as detailed in https://doi.org/10.1063/1.5127746 December 2019: Initial release containing the software used in the publication. In particular, the FPGA gateware, Cpp interface routines and the limr python class. The Cpp interface routines require compilation and the compilation call is found in the files. The FPGA gateware needs to be downloaded to the FPGA using LimeSuiteGUI. At the time...
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V4SA Emutos
Emutos version version for v4sa Amiga card, based on Emutos 1.0
This is a version dedicated to Emutos for Apollo V4SA card able to run Atari on this standalone card with 68080 FPGA and SAGA. This version of Emutos is based on Emutos 1.0 version you can find Emutos official at https://github.com/emutos -
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QtPALS
Qt software for positron lifetime measurement
PALS software using DRS4 EVM board (http://www.psi.ch/drs/evaluation-board) to determine time between two pulses. Time distance is then send to histogram and evaluated in odher programs likes LT or PALSFit. 2, 3 or 4 detector PALS setup. DRS4 inputs: Ch1 - Start detector 1274keV, Ch2 - 511keV stop detector1, Ch3 511keV - stop detector 2, Ch4 - external trigger input - after FPGA firmware no external trigger needed. -
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ALCHA
A New Programming Language for FPGA Projects
ALCHA aims to reduce FPGA project develop time by means of automation and abstraction, but without loosing the low-level control that HDLs, such as Verilog, provides. It will support an object oriented programming model, abstract data and signal types, and compile-time scripting. -
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Gwyscope
Open hardware SPM controller with advanced sampling support.
... It is based on a low cost FPGA board Red Pitaya and additional high bit depth AD and DA converters. When put together with the AFM scanning hardware (sensor, scanner and their amplifiers) and user interface software it can serve as a standalone SPM system. Otherwise, it can serve as a sub-module for a custom built SPM system, e.g. providing the feedback loop mechanism only. Finally, it can be used as a board for developing advanced sampling techniques, which was the primary goal. -
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Iris
2-photon scanning software
Iris is a LabVIEW package, developed at the Keller Lab (Basel FMI), for running 2-photon microscopes. It is supplied with auxiliary software for recording additional experimental parameters, such as behavioral states. Iris is freely available. You may modify it as you wish and use it as you wish, so long as you comply with the licence terms (see below). However, please note that we are **unable to offer any guarantee of support**. There are two exceptions to this. 1) If you find a... -
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Rocket Chip
Rocket Chip Generator
Rocket Chip is a parameterized RISC-V SoC generator written in Chisel that produces synthesizable RTL for a wide range of cores and configurations. At its heart is the Rocket core, a simple, in-order, five-stage RISC-V implementation, but the generator composes much more: coherent caches, MMUs, interrupt controllers, and buses via the TileLink interconnect. A diplomacy framework (LazyModules) lets designers wire components with negotiated parameters, enabling reuse and rapid exploration of... -
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Computer From Scratch
Verilog source files for a basic computer
This project follows The Elements of Computing fundamentals book, except all the hardware is written in Verilog . This is currently a hobby project, eventually I plan on implementing this onto a FPGA and tinkering with it some more. -
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SYSU-OpenEdgeAI
A public account displaying works from SYSU-OpenEdgeAI Club
.... 3. rapidlayout.zip is an end-to-end hard block placement and routing flow for systolic accelerators on FPGA, RapidLayout. It is the sourcecode of our paper:https://ieeexplore.ieee.org/document/9221566 . If you have any question about our projects, please leave reviews and contact us! -
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UFBmod
#6 - Ultra-Fine-Business Modulation
#6 - Ultra-Fine-Business Modulation - Trying a new data modulation to compete with LoRa (R) -
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FUI Audio DAC
FPGA-Based USB-Input Audio Digital to Analogue Converter
An open-hardware and -firmware project that implements a USB-input fully-digital class-D audio amplifier. All processing is done on FPGA, including the USB-physical, USB-SIE, HID interface, clock-recovery, bus voltage regulation, noise-shaping and PWM output. A Microchip PIC based remote control is also included. The remote maps to the media buttons of the USB HID interface. The volume control, next track, previous track, stop and play/pause functions are supported. -
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pyrpl
PyRPL turns your Red Pitaya into a powerful analog feedback device.
The Red Pitaya is a commercial, affordable FPGA board with fast analog inputs and outputs. This makes it useful for quantum optics experiments, in particular as a digital feedback controller for analog systems. Based on the open source software provided by the board manufacturer, PyRPL (Python RedPitaya Lockbox) implements many devices that are needed for optics experiments with the Red Pitaya. PyRPL implements various digital signal processing (DSP) modules (see features below). It allows... -
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RISC-V BOOM
SonicBOOM: The Berkeley Out-of-Order Machine
The riscv-boom project (also called BOOM or SonicBOOM) implements a high-performance, synthesizable out-of-order RISC-V core written in the Chisel hardware construction language. It targets the RV64GC (i.e. 64-bit with general + compressed + floating point) instruction set and supports features such as virtual memory, caches, atomics, and IEEE-754 floating point. The design is parameterizable, meaning users can tune pipeline widths, buffer sizes, functional units, and other...