[go: up one dir, main page]

Werner, 2023 - Google Patents

Performance Evaluation of Interconnection Networks on Processors

Werner, 2023

View PDF
Document ID
10474270577952695363
Author
Werner L
Publication year

External Links

Snippet

With the number of processing cores per chip steadily growing, the on chip communication between processing cores and shared resources becomes an increasingly difficult task. In older processor architectures simple busses or controllers with direct connections to every …
Continue reading at es.cs.rptu.de (PDF) (other versions)

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a programme unit and a register, e.g. for a simultaneous processing of several programmes
    • G06F15/163—Interprocessor communication
    • G06F15/173—Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
    • G06F15/17356—Indirect interconnection networks
    • G06F15/17368—Indirect interconnection networks non hierarchical topologies
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50—Computer-aided design
    • G06F17/5009—Computer-aided design using simulation
    • G06F17/5022—Logic simulation, e.g. for logic circuit operation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50—Computer-aided design
    • G06F17/5045—Circuit design
    • G06F17/5054—Circuit design for user-programmable logic devices, e.g. field programmable gate arrays [FPGA]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored programme computers
    • G06F15/78—Architectures of general purpose stored programme computers comprising a single central processing unit
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems
    • H04L12/56—Packet switching systems
    • H04L12/5601—Transfer mode dependent, e.g. ATM
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/50—Overload detection; Overload protection
    • H04L49/505—Corrective Measures, e.g. backpressure
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/30—Peripheral units, e.g. input or output ports
    • H04L49/3009—Header conversion, routing tables or routing tags
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/25—Routing or path finding through a switch fabric
    • H04L49/253—Connections establishment or release between ports
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for programme control, e.g. control unit

Similar Documents

Publication Publication Date Title
Adriahantenaina et al. SPIN: a scalable, packet switched, on-chip micro-network
Yebenes et al. Towards modeling interconnection networks of exascale systems with omnet++
Kamali et al. AdapNoC: A fast and flexible FPGA-based NoC simulator
Jiang et al. An asynchronous NoC router in a 14nm FinFET library: comparison to an industrial synchronous counterpart
Abdelfattah et al. Design and applications for embedded networks-on-chip on FPGAs
Wehner et al. MPSoCSim: An extended OVP simulator for modeling and evaluation of network-on-chip based heterogeneous MPSoCs
Ehliar et al. An FPGA based open source network-on-chip architecture
Rane et al. Network on Chip (NoC) Mesh Topology FPGA Verification: Real Time Operating System Emulation Framework
Prasad et al. YaNoC: Yet another network-on-chip simulation acceleration engine using FPGAs
Werner Performance Evaluation of Interconnection Networks on Processors
Gharan et al. Flexible simulation and modeling for 2D topology NoC system design
Parane et al. FPGA based NoC simulation acceleration framework supporting adaptive routing
Attia et al. A modular router architecture desgin for Network on Chip
Tan et al. Generation of emulation platforms for NoC exploration on FPGA
Parane et al. YaNoC: Yet another network-on-chip simulation acceleration engine supporting congestion-aware adaptive routing using FPGAs
Luo-Feng et al. Design and performance evaluation of a 2D-mesh Network on Chip prototype using FPGA
Beldachi et al. Configurable router design for dynamically reconfigurable systems based on the SoCWire NoC
Pereira et al. MPI hardware framework for many-core based embedded systems
Ponnan et al. On chip network with increased performance for efficient wireless communication
Mahajan et al. Design Automation of Network-on-Chip Prototype on FPGA
Wang et al. System-level buffer allocation for application specific network-on-chip with wormhole routing
e Fizardo et al. State of art of network on chip
Kassam et al. Enhancing virtual switching system of on-chip networks
Hou et al. Design and performance evaluation of virtual-channel based NoC
Karnthak et al. A hardware implementation of PCA based-on the networks-on-chip paradigm