CN104638069A - Vertical LED (Light-Emitting Diode) chip structure and manufacturing method thereof - Google Patents

Abstract

The present invention provides a vertical LED chip structure and a manufacturing method thereof. The vertical LED chip structure comprises from bottom to top: a conductive substrate, a metal bonding layer, a reflective layer, a current blocking layer, a P-GaN layer, a multilayer Quantum well layer, N-GaN layer and N electrode. By preparing a current blocking layer with a shape different from that of the N electrode on the surface of the P-GaN layer, the longitudinal expansion current from the N electrode to the P-GaN layer region can be diffused, effectively blocking the current under the N electrode. The current crowding effect makes the vertical LED current spread more evenly, thereby improving the photoelectric performance of the LED chip.

Description

Vertical LED chip structure and manufacturing method thereof

technical field

The invention belongs to the field of LED chip manufacturing, and relates to a vertical LED chip structure and a manufacturing method thereof.

Background technique

Light Emitting Diode (Light Emitting Diode) is a semiconductor element that can emit light. LED has the characteristics of small size, low power consumption and long service life. Nowadays, LEDs are gradually replacing traditional light sources. In this era of environmental protection, LEDs play a very important role. The demand for high-brightness LEDs is becoming more and more urgent, and vertical structure LEDs can solve the shortcomings of traditional LEDs, such as current congestion and high local heat generation, which limit the driving current and ensure that a larger current can be used under the premise of a certain luminous efficiency. to drive. Therefore, the vertical structure LED will inevitably accelerate the process of LED application in the field of general lighting, which is the direction of the market and the inevitable trend of the development of semiconductor lighting. In order to continuously improve the brightness and lifespan, it is necessary to make the current distribution more uniform. Compared with the traditional method, the current blocking layer is added to alleviate the current crowding effect, so as to achieve the purpose of making the current spread more uniform and the light efficiency higher.

In conventional devices, there is a current distribution under the metal electrode, so a certain number of photons are generated in this area. The metal electrode is an opaque material, and this part of the light cannot be extracted normally, and will be absorbed in the form of heat, which has potential hazards to the luminous performance and reliability of the device. Adding a layer of current blocking layer under the electrode will prevent the current from flowing through the area under the electrode and hinder the generation of photons in this area, thereby reducing the waste of injected current and making the current mainly concentrated in the area that is not blocked by the metal electrode and can perform normal light extraction. The light emitting area will indirectly increase the current density of the light emitting area in the chip. In the case of a certain quantum efficiency in the epitaxial wafer, the increase of the current density increases the number of photons generated in the light-emitting area of the chip, which increases the extracted luminous flux, which has a significant positive impact on improving the photoelectric conversion efficiency.

In the vertical structure, because the current spreads directly from N-GaN to the whole P-GaN, and P-GaN is more prone to current crowding, under the N-PAD (N electrode), especially in the electrode interpolation overlapping area, the current crowding effect Obviously, the light extraction efficiency is seriously affected, and a certain shape of current blocking layer (current blocking layer CBL) is effectively added near the interpolation of the N electrode to alleviate the current crowding effect under the electrode, so that the current diffusion on the P surface is more uniform, thereby improving the photoelectric efficiency.

Contents of the invention

In view of the above-mentioned shortcomings of the prior art, the object of the present invention is to provide a vertical LED chip structure and its manufacturing method, which is used to solve the problem in the prior art that the current is directly distributed from N-GaN to the entire P-GaN , P-GaN is more prone to current crowding. Under the N-PAD (N electrode), especially in the electrode interpolation overlapping area, the current crowding effect is obvious, which seriously affects the light efficiency of the vertical LED chip structure.

In order to achieve the above purpose and other related purposes, the present invention provides a method for manufacturing a vertical LED chip structure, the vertical LED chip structure at least includes the following steps:

A growth substrate is provided, and an epitaxial layer is formed on the growth substrate, and the epitaxial layer includes an undoped GaN layer, an N-GaN layer, a multi-quantum well layer, and a P-GaN layer sequentially formed from bottom to top;

forming a contact layer on the P-GaN layer, and performing photolithography and etching on the contact layer to form a current blocking layer;

forming a reflective layer on the epitaxial layer and the current blocking layer;

forming a metal bonding layer on the epitaxial layer and the reflective layer;

bonding the substrate forming the metal bonding layer to a conductive substrate, and removing the growth substrate;

etching the undoped GaN layer to expose the N-GaN layer;

An N electrode is formed on the N-GaN layer.

Preferably, the substrate is a sapphire substrate, a silicon substrate, a silicon carbide substrate or a patterned substrate.

Preferably, the thickness of the current blocking layer is 200 angstroms to 6000 angstroms, and the material of the current blocking layer is ITO, ZnO or Ni/Ag.

Preferably, the current blocking layer includes at least one patterned structure consisting of a first current blocking layer structure and a plurality of second current blocking layer structures; the shape of the first current blocking layer structure is consistent with that of the N electrode The shape is the same, the center of the first current blocking layer structure corresponds up and down to the center of the N electrode, and the lateral dimension of the first current blocking layer is greater than or equal to the lateral dimension of the N electrode; the second current blocking layer The blocking layer structures are symmetrically distributed around the first current blocking layer structure.

Preferably, the first current blocking layer structure is a large circular structure, and the second current blocking layer structure is a small circular structure.

Preferably, the diameter of the large circular structure is 50 μm to 150 μm, and the diameter of the small circular structure is 5 μm to 50 μm.

Preferably, the lateral dimension of the reflective layer is smaller than that of the vertical LED chip; the material of the reflective layer is Ag, Al or Rh.

Preferably, the metal bonding layer is made of Au, Sn or AuSn alloy.

Preferably, after removing the growth substrate and before forming the N electrode, the undoped GaN layer is firstly etched using a wet or dry etching process until the N-GaN layer is exposed ; Secondly, the roughening treatment is performed on the N-GaN layer to form a rough surface, and the solution used in the roughening treatment is KOH or H ₂ SO ₄ .

Preferably, the material of the N electrode is Ni/Au, Al/Ti/Pt/Au, or Cr/Pt/Au.

The present invention also provides a vertical LED chip structure. The vertical LED chip structure at least includes: a conductive substrate, a metal bonding layer, a reflective layer, a current blocking layer, a P-GaN layer, and multiple quantum wells from bottom to top. layer, an N-GaN layer, and an N electrode; wherein, a rough surface is formed on the surface of the N-GaN layer close to the N electrode, and the rough surface exposes the N electrode.

Preferably, the current blocking layer includes at least one patterned structure consisting of a first current blocking layer structure and a plurality of second current blocking layer structures; the shape of the first current blocking layer structure is consistent with that of the N electrode The shape is the same, the center of the first current blocking layer structure corresponds up and down to the center of the N electrode, and the lateral dimension of the first current blocking layer is greater than or equal to the lateral dimension of the N electrode; the second current blocking layer The blocking layer structures are symmetrically distributed around the first current blocking layer structure.

Preferably, the first current blocking layer structure is a large circular structure, and the second current blocking layer structure is a small circular structure.

Preferably, the diameter of the large circular structure is 50 μm-150 μm, and the diameter of the small circular structure is 5 μm-50 μm; the total number of the small circular structures in one patterned structure is a multiple of 4.

As mentioned above, the vertical LED chip structure and its manufacturing method of the present invention have the following beneficial effects: by preparing a current blocking layer having a shape different from that of the N electrode on the surface of the P-GaN layer, that is, the current The blocking layer not only includes the first current blocking layer structure corresponding to the upper and lower sides of the N electrode, but also includes the second current blocking layer structure symmetrically distributed around the first current blocking layer structure, and the N-PAD ( N electrode) to the longitudinal expansion of the P-GaN layer region, effectively blocking the current crowding effect under the N electrode, making the vertical LED current diffusion more uniform, thereby improving the photoelectric performance of the LED chip structure.

Description of drawings

FIG. 1 is a flow chart showing a method for fabricating a vertical LED chip structure of the present invention.

FIG. 2 to FIG. 10 are schematic structural diagrams during the fabrication process of the vertical LED chip structure of the present invention.

Component designation description

20 growth substrate

21 epitaxial layer

211 undoped GaN layer

212 N-GaN layer

213 multiple quantum well layer

214 P-GaN layer

22 current blocking layer

221 Graphical structure

2211 The first current blocking layer structure

2212 Second current blocking layer structure

23 reflective layer

24 metal bonding layer

25 Conductive substrate

26 N electrode

27 rough surface

Detailed ways

Embodiments of the present invention are described below through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation modes, and various modifications or changes can be made to the details in this specification based on different viewpoints and applications without departing from the spirit of the present invention.

See Figures 1 through 10. It should be noted that the diagrams provided in this embodiment are only schematically illustrating the basic concept of the present invention, although only the components related to the present invention are shown in the diagrams rather than the number, shape and Dimensional drawing, the type, quantity and proportion of each component can be changed arbitrarily during actual implementation, and the component layout type may also be more complicated.

Embodiment one

Please refer to FIG. 1 to FIG. 10, the present invention provides a method for manufacturing a vertical LED chip structure, the method for manufacturing a vertical LED chip structure at least includes the following steps:

S1: Provide a growth substrate 20, and form an epitaxial layer 21 on the growth substrate 20, and the epitaxial layer 21 includes an undoped GaN layer 211, an N-GaN layer 212, and a multi-quantum well layer formed sequentially from bottom to top 213 and a P-GaN layer 214;

S2: forming a contact layer on the P-GaN layer 214, and performing photolithography and etching on the contact layer to form a current blocking layer 22;

S3: forming a reflective layer 23 on the epitaxial layer 21 and the current blocking layer 22;

S4: forming a metal bonding layer 24 on the epitaxial layer 21 and the reflective layer 23;

S5: bonding the substrate of the metal bonding layer 24 to the conductive substrate 25, and removing the growth substrate 20;

S6: Etching the undoped GaN layer 211 to expose the N-GaN layer 212;

S7: forming an N electrode 26 on the N—GaN layer 212 .

In step S1, referring to step S1 in FIG. 1 and FIG. 2, a growth substrate 20 is provided, and an epitaxial layer 21 is formed on the growth substrate 20, and the epitaxial layer 21 includes undoped GaN layer 211 , N-GaN layer 212 , multiple quantum well layer 213 and P-GaN layer 214 .

Specifically, the growth substrate 20 may be a sapphire substrate, a silicon substrate, a silicon carbide substrate or a patterned substrate.

Specifically, the epitaxial layer 21 can be formed by growth processes such as MOCVD (Metal Organic Chemical Vapor Deposition) and/or MBE (Molecular Beam Epitaxy).

In step S2, referring to step S2 in FIG. 1 and FIG. 3 to FIG. 4, a contact layer is formed on the P-GaN layer 214, and the contact layer is photolithographically and etched to form a current blocking layer 22. ; Wherein FIG. 3 is a schematic top view of forming a current blocking layer 22 on the P-GaN layer 214, and FIG. 4 is a schematic cross-sectional view of FIG. 3 along the direction AA'.

Specifically, the thickness of the current blocking layer 22 is 200 angstroms to 6000 angstroms, and the material of the current blocking layer 22 may be ITO, ZnO or Ni/Ag.

Specifically, a contact layer is first formed on the P-GaN layer 214 , and then the contact layer is etched using a wet etching process or a dry etching process to form the required current blocking layer 22 .

Specifically, as shown in FIG. 3, the current blocking layer 22 includes at least one patterned structure 221 composed of a first current blocking layer structure 2211 and a plurality of second current blocking layer structures 2212; The shape of the layer structure 2211 is the same as that of the N electrode 26, the center of the first current blocking layer structure 2211 corresponds up and down to the center of the N electrode 26, and the lateral dimension of the first current blocking layer 2211 is larger than Or equal to the lateral dimension of the N electrode 26 ; the second current blocking layer structure 2212 is symmetrically distributed around the first current blocking layer structure 2211 . Preferably, in this embodiment, the first current blocking layer structure 2211 is a large circular structure, and the second current blocking layer structure 2212 is a small circular structure.

Specifically, the diameter of the large circular structure is 50 μm˜150 μm, and the diameter of the small circular structure is 5 μm˜50 μm.

Specifically, the number of the second current blocking layer structures 2212 around the first current blocking layer structure 2211 can be set in the patterned structure 221 according to actual needs; preferably, in this embodiment, one of the The total number of the second current blocking layer structures 2212 in the patterned structure 221 is a multiple of 4, that is, the total number of the small circular structures around the large circular structure in one patterned structure 221 can be For 4, 8, 12 and so on.

Specifically, the current blocking layer 22 may include a plurality of patterned structures 221 , and the plurality of patterned structures 221 are distributed in an array.

By growing a current blocking layer 22 having a shape different from that of the N electrode 26 on the surface of the P-GaN layer 214, that is, the current blocking layer 22 not only includes the first current blocking layer corresponding to the top and bottom of the N electrode 26 The structure 2211 also includes the second current blocking layer structure 2212 symmetrically distributed around the first current blocking layer structure 2211, which can connect the N-PAD (N electrode) to the longitudinal direction of the P-GaN layer 214 region The extended current spreads out, effectively blocking the current crowding effect under the N electrode, making the vertical LED current spread more evenly, thereby improving the photoelectric performance of the LED chip structure.

In step S3 , referring to step S3 in FIG. 1 and FIG. 5 , a reflective layer 23 is formed on the epitaxial layer 21 and the current blocking layer 22 .

Specifically, the material of the reflective layer 23 can be Ag, Al or Rh; the thickness of the reflective layer 23 is greater than the thickness of the current blocking layer 22, so as to ensure that the reflective layer 23 completely wraps the current blocking layer 22 .

Specifically, the lateral dimension of the reflective layer 23 is determined according to the lateral dimension of the vertical LED chip. Preferably, in this embodiment, the reflective layer 23 is formed by vapor deposition in a fixed area using lift-off technology, so that the lateral dimension of the reflective layer 23 is smaller than the lateral dimension of the vertical LED chip , that is, the reflective layer 23 exposes the edge of the epitaxial layer 21 , which facilitates subsequent formation of a barrier layer to fully protect the reflective layer 23 .

In step S4 , referring to step S4 in FIG. 1 and FIG. 6 , a metal bonding layer 24 is formed on the epitaxial layer 21 and the reflective layer 23 .

Specifically, the material of the metal bonding layer 24 is Au, Sn or AuSn alloy, and the metal bonding layer 24 is used to bond with the subsequently formed conductive substrate; the thickness of the metal bonding layer 24 is greater than The thickness of the reflective layer 23 is to ensure that the metal bonding layer 24 completely covers the reflective layer 23 .

In step S5 , referring to step S5 of FIG. 1 and FIG. 7 , the substrate of the metal bonding layer 24 is bonded to the conductive substrate 25 , and the growth substrate 20 is removed.

Specifically, the conductive substrate 25 is made of Si, Cu or MoCu, which is conductive and has good heat dissipation.

Specifically, the growth substrate 20 may be removed by laser lift-off or chemical lift-off. Since the growth substrate is in contact with the undoped GaN layer, when the growth substrate 20 is removed by laser liftoff, the laser liftoff will cause a layer of metal Ga to be formed on the surface of the undoped GaN layer. Therefore, after removing the growth substrate 20 by laser lift-off, it is necessary to use acid solution or alkali solution to remove the metal Ga, and the solution used to remove the metal Ga may be HCl or KOH.

In step S6 , referring to step S6 of FIG. 1 and FIG. 8 , the undoped GaN layer 211 is etched to expose the N-GaN layer 212 .

Specifically, the undoped GaN layer 211 may be etched using a wet etching process or a dry etching process until the N-GaN layer 212 is exposed. During the etching process, the undoped GaN 211 may be etched entirely or patterned, that is, the undoped GaN layer 211 may be etched completely or only partially removed.

Specifically, after etching the undoped GaN layer 211 to expose the N-GaN layer 212 , a step of roughening the N-GaN layer 212 to form a rough surface 27 is also included. Roughening the N-GaN layer 212 and forming the rough surface 27 can increase the surface area of the N-GaN layer 212 , thereby increasing the light emitting area, thereby improving the light emitting efficiency of the vertical LED chip structure.

Specifically, the N-GaN layer 212 may be roughened by using a wet etching process, and the solution used in the wet etching process may be KOH or H ₂ SO ₄ .

In step S7, referring to step S7 of FIG. 1 and FIG. 9 and FIG. 10, an N electrode 26 is formed on the N-GaN layer 212; wherein, FIG. 9 is an N electrode formed on the N-GaN layer 212 26 is a schematic top view, and FIG. 10 is a schematic cross-sectional view along the direction BB' of FIG. 9 .

Specifically, an evaporation process is used to form the N-electrode 26 on the N-GaN layer 212, the upper surface of the N-electrode 26 is higher than the upper surface of the rough surface 27 to expose the N-electrode 26; The material of the N electrode 26 can be Ni/Au, Al/Ti/Pt/Au, or Cr/Pt/Au.

Specifically, the shape of the N electrode 26 can be designed according to actual needs. In this embodiment, on the premise that the first current blocking layer 2211 is a circular current blocking layer, the N electrode 26 is a circular electrode , the center of the N electrode corresponds up and down to the center of the first current blocking layer structure 2211; the radius of the N electrode 26 is less than or equal to the radius of the first current blocking layer structure 2211, and the first current The radius difference between the barrier layer structure 2211 and the N electrode 26 is less than or equal to 10 μm.

Specifically, after forming the N electrode 26 on the N-GaN layer 212 , a step of forming a passivation layer (not shown) on the rough surface 27 may also be included. The passivation layer is used to protect the entire chip structure, and the formed passivation layer exposes the N electrode 212 .

Embodiment two

Please continue to refer to FIG. 3 and FIG. 9 to FIG. 10, the present invention also provides a vertical LED chip structure, the vertical LED chip structure at least includes: a conductive substrate 25, a metal bonding layer 24, a reflective Layer 23, current blocking layer 22, P-GaN layer 214, multi-quantum well layer 213, N-GaN layer 212 and N electrode 26; wherein, the surface of the N-GaN layer 212 close to the N electrode 26 is formed with a rough The rough surface 27 exposes the N electrode 26 . Forming the rough surface 27 on the N-GaN layer 212 can increase the surface area of the N-GaN layer 212, thereby increasing the light emitting area, thereby improving the light emitting efficiency of the vertical LED chip structure.

Specifically, the thickness of the current blocking layer 22 is 200 angstroms to 6000 angstroms, and the material of the current blocking layer 22 may be ITO, ZnO or Ni/Ag.

Specifically, as shown in FIG. 3, the current blocking layer 22 includes at least one patterned structure 221 composed of a first current blocking layer structure 2211 and a plurality of second current blocking layer structures 2212; The shape of the layer structure 2211 is the same as that of the N electrode 26, the center of the first current blocking layer structure 2211 corresponds up and down to the center of the N electrode 26, and the lateral dimension of the first current blocking layer 2211 is larger than Or equal to the lateral dimension of the N electrode 26 ; the second current blocking layer structure 2212 is symmetrically distributed around the first current blocking layer structure 2211 . Preferably, in this embodiment, the first current blocking layer structure 2211 is a large circular structure, and the second current blocking layer structure 2212 is a small circular structure.

Specifically, the diameter of the large circular structure is 50 μm˜150 μm, and the diameter of the small circular structure is 5 μm˜50 μm.

Specifically, the number of the second current blocking layer structures 2212 around the first current blocking layer structure 2211 can be set in the patterned structure 221 according to actual needs; preferably, in this embodiment, one of the The total number of the second current blocking layer structures 2212 in the patterned structure 221 is a multiple of 4, that is, the total number of the small circular structures around the large circular structure in one patterned structure 221 can be For 4, 8, 12 and so on.

Specifically, the current blocking layer 22 may include a plurality of patterned structures 221 , and the plurality of patterned structures 221 are distributed in an array.

Specifically, the shape of the N electrode 26 can be designed according to actual needs. As shown in FIG. 9, in this embodiment, on the premise that the first current blocking layer 2211 is a circular current blocking layer, the N The electrode 26 is a circular electrode, and the center of the N electrode corresponds up and down to the center of the first current blocking layer structure 2211; the radius of the N electrode 26 is less than or equal to the radius of the first current blocking layer structure 2211, And the radius difference between the first current blocking layer structure 2211 and the N electrode 26 is less than or equal to 10 μm.

By preparing a current blocking layer 22 having a shape different from that of the N electrode 26 on the surface of the P-GaN layer 214, that is, the current blocking layer 22 not only includes the first current blocking layer corresponding to the top and bottom of the N electrode 26 The structure 2211 also includes the second current blocking layer structure 2212 symmetrically distributed around the first current blocking layer structure 2211, which can connect the N-PAD (N electrode) to the longitudinal direction of the P-GaN layer 214 region The extended current spreads out, effectively blocking the current crowding effect under the N electrode, making the vertical LED current spread more evenly, thereby improving the photoelectric performance of the LED chip structure.

To sum up, the present invention provides a vertical LED chip structure and its manufacturing method. The vertical LED chip structure at least includes: a conductive substrate 25, a metal bonding layer 24, a reflective layer 23, an ohmic The contact layer 23 , the current blocking layer 22 , the P-GaN layer 214 , the multi-quantum well layer 213 , the N-GaN layer 212 and the N electrode 26 . By preparing a current blocking layer 22 having a shape different from that of the N electrode 26 on the surface of the P-GaN layer 214, that is, the current blocking layer 22 not only includes the first current blocking layer corresponding to the top and bottom of the N electrode 26 The structure 2211 also includes the second current blocking layer structure 2212 symmetrically distributed around the first current blocking layer structure 2211, which can connect the N-PAD (N electrode) to the longitudinal direction of the P-GaN layer 214 region The extended current spreads out, effectively blocking the current crowding effect under the N electrode, making the vertical LED current spread more evenly, thereby improving the photoelectric performance of the LED chip structure.

The above-mentioned embodiments only illustrate the principles and effects of the present invention, but are not intended to limit the present invention. Anyone skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by those skilled in the art without departing from the spirit and technical ideas disclosed in the present invention should still be covered by the claims of the present invention.

Claims (14)

1. A method for making a vertical LED chip structure, characterized in that: comprising the following steps: A growth substrate is provided, and an epitaxial layer is formed on the growth substrate, and the epitaxial layer includes an undoped GaN layer, an N-GaN layer, a multi-quantum well layer, and a P-GaN layer sequentially formed from bottom to top; forming a contact layer on the P-GaN layer, and performing photolithography and etching on the contact layer to form a current blocking layer; forming a reflective layer on the epitaxial layer and the current blocking layer; forming a metal bonding layer on the epitaxial layer and the reflective layer; bonding the substrate forming the metal bonding layer to a conductive substrate, and removing the growth substrate; etching the undoped GaN layer to expose the N-GaN layer; An N electrode is formed on the N-GaN layer. 2. The method for manufacturing a vertical LED chip structure according to claim 1, wherein the substrate is a sapphire substrate, a silicon substrate, a silicon carbide substrate or a patterned substrate. 3. The manufacturing method of the vertical LED chip structure according to claim 1, characterized in that: the thickness of the current blocking layer is 200 angstroms to 6000 angstroms, and the material of the current blocking layer is ITO, ZnO or Ni/ Ag. 4. The method for manufacturing a vertical LED chip structure according to claim 1, wherein the current blocking layer comprises at least one pattern consisting of a first current blocking layer structure and a plurality of second current blocking layer structures structure; the shape of the first current blocking layer structure is the same as that of the N electrode, the center of the first current blocking layer structure corresponds up and down to the center of the N electrode, and the first current blocking layer The lateral dimension is greater than or equal to the lateral dimension of the N electrode; the second current blocking layer structure is symmetrically distributed around the first current blocking layer structure. 5. The method for manufacturing a vertical LED chip structure according to claim 4, wherein the first current blocking layer structure is a large circular structure, and the second current blocking layer structure is a small circular structure. 6 . The method for manufacturing a vertical LED chip structure according to claim 5 , wherein the diameter of the large circular structure is 50 μm˜150 μm, and the diameter of the small circular structure is 5 μm˜50 μm. 7. The manufacturing method of the vertical LED chip structure according to claim 1, characterized in that: the lateral dimension of the reflective layer is smaller than the lateral dimension of the vertical LED chip; the material of the reflective layer is Ag, Al or Rh. 8. The method for manufacturing a vertical LED chip structure according to claim 1, wherein the metal bonding layer is made of Au, Sn or AuSn alloy. 9. The method for manufacturing a vertical LED chip structure according to claim 1, characterized in that: after removing the growth substrate and before forming the N electrode, the wet or dry etching process is first used to etch the The undoped GaN layer is etched until the N-GaN layer is exposed; secondly, the N-GaN layer is roughened to form a rough surface, and the solution used for the roughening treatment is KOH or H ₂ SO ₄ . 10. The method for manufacturing a vertical LED chip structure according to claim 1, wherein the material of the N electrode is Ni/Au, Al/Ti/Pt/Au, or Cr/Pt/Au. 11. A vertical LED chip structure, characterized in that the vertical LED chip structure comprises from bottom to top: a conductive substrate, a metal bonding layer, a reflective layer, a current blocking layer, a P-GaN layer, a multi-quantum Well layer, N-GaN layer and N electrode; Wherein, a rough surface is formed on the surface of the N-GaN layer close to the N electrode, and the N electrode is exposed by the rough surface. 12. The vertical LED chip structure according to claim 11, wherein the current blocking layer comprises at least one patterned structure consisting of a first current blocking layer structure and a plurality of second current blocking layer structures; The shape of the first current blocking layer structure is the same as that of the N electrode, the center of the first current blocking layer structure corresponds up and down to the center of the N electrode, and the lateral dimension of the first current blocking layer greater than or equal to the lateral size of the N electrode; the second current blocking layer structure is symmetrically distributed around the first current blocking layer structure. 13. The vertical LED chip structure according to claim 12, wherein the first current blocking layer structure is a large circular structure, and the second current blocking layer structure is a small circular structure. 14. The vertical LED chip structure according to claim 13, wherein the diameter of the large circular structure is 50 μm˜150 μm, and the diameter of the small circular structure is 5 μm˜50 μm.