CN105097528A - FINFET manufacturing method - Google Patents

Abstract

The invention provides a FINFET manufacturing method, comprising: a. providing a semiconductor substrate, and forming a first fin on the substrate; b. covering the first fin with a mask layer; c. Form a pass-through barrier layer in the semiconductor substrate; d. use the first fin and the mask layer as a mask to etch the pass-through barrier layer and a part of the semiconductor substrate in sequence, and the first fin Expanding into a second fin, and removing the mask; e. forming a trench isolation structure on the semiconductor substrate, forming a source and drain region on the second fin, and forming a gate on the semiconductor substrate and the second fin Pole stack and interlayer dielectric layer The present invention adopts the method of side scattering to form the penetration barrier layer, and at the same time, the substrate material is used as the carrier of scattering impurities, and the isolation layer is formed after forming the penetration barrier layer, which effectively solves the problem of side scattering. The introduced impurities and damage greatly improve the device performance.

Description

A kind of FINFET manufacturing method

technical field

The invention relates to a method for manufacturing a semiconductor device, in particular to a method for manufacturing a FINFET.

technical background

As the size of the semiconductor device is scaled down, there arises a problem that the threshold voltage decreases with the decrease of the channel length, that is, a short channel effect is generated in the semiconductor device. To meet the challenges from semiconductor design and manufacturing, led to the development of Fin Field Effect Transistor, or FinFET.

Channel punch-through effect (Channelpunch-througheffect) is a phenomenon that the source junction and the depletion region of the drain junction of the field effect transistor are connected. When the channel is penetrated, the potential barrier between the source and the drain is significantly reduced, and a large number of carriers are injected from the source to the channel, and drift through the space charge region between the source and the drain to form a large current; The size of this current will be limited by the space charge, which is the so-called space charge limited current. This space charge limited current is in parallel with the channel current controlled by the gate voltage, so the channel penetration will greatly increase the total current through the device; and in the case of channel penetration, even if the gate voltage is lower than the threshold voltage, the source - There will also be current passing through the drain. This effect is an effect that may occur in small-scale field effect transistors, and its influence on device characteristics becomes more and more significant as the channel width is further reduced.

In FinFETs, heavy doping of the portion of the fin below the channel is often used to suppress the channel punch-through effect. The current general doping method is ion implantation to form the required heavily doped region. However, the depth of ion implantation is difficult to control precisely, and at the same time it will cause damage to the channel surface. In order to eliminate the damage, a thin layer is usually formed on the channel surface. The oxide layer increases the process complexity.

Another way to form a penetration barrier is side scattering, that is, instead of implanting impurities directly into the bottom of the channel, the required impurities are injected into the isolation layers on both sides of the fin, and a penetration barrier is formed at the bottom of the channel through side scattering. layer. This method effectively reduces the defects and impurities introduced in the channel by direct ion implantation, and improves the performance of the device. However, due to the relatively large ion implantation energy and dose required to form scattering, this method will inevitably Damage forms the dielectric properties of the isolation layer.

Contents of the invention

In view of the above problems, the present invention provides a FINFET manufacturing method, which can effectively suppress the punch-through current without affecting other characteristics of the device. Specifically, the manufacturing method provided by the invention comprises the following steps:

a. providing a semiconductor substrate on which a first fin is formed;

b. covering the first fin with a mask layer;

c. forming a punch-through barrier layer in the semiconductor substrate;

d. using the first fin and the mask layer as a mask to sequentially etch the pass barrier layer and a part of the semiconductor substrate, expand the first fin into a second fin, and remove the mask membrane;

e. forming a trench isolation structure on the semiconductor substrate, forming a source and drain region on the second fin, and forming a gate stack and an interlayer dielectric layer on the semiconductor substrate and the second fin.

Wherein, in step a, the height of the first fin depends on the height difference between the predetermined height of the second fin to be formed and the height of the isolation layer; the height of the first fin is 30-50 nm, and the thickness is 10 nm. ~30nm.

Wherein, in step b, the material for forming the mask layer is silicon nitride and/or silicon oxide. Wherein, in step c, the penetration barrier layer is located at the bottom of the first fin, and its boundary close to the substrate is set to be located within the second fin to be formed.

Wherein, in step c, the method of forming the punch-through barrier layer is side scattering; the type of impurity forming the punch-through barrier layer is the same as that of the substrate; the impurity concentration of the punch-through barrier layer is 1e17cm ^-3 -1e19cm ^-3 .

According to the FINFET manufacturing method provided by the present invention, the fins are etched twice, the first etching makes the height of the fins equal to the effective height of the channel, and the rest of the silicon material is reserved, and it is doped with silicon nitride as a mask. Miscellaneous ion implantation and annealing to form a punch-through barrier layer; the second etching makes the fin reach the actual required height, and then forms the isolation layer, source and drain regions and other parts. The present invention adopts the method of lateral scattering of doped ions to form a penetration barrier layer, and at the same time uses the substrate material as a carrier for scattering impurities, and removes this part of the material after forming the penetration barrier layer to form an isolation layer, which effectively solves the problem of lateral Impurities and damage introduced to the isolation layer during scattering greatly improve device performance.

Description of drawings

Other characteristics, objects and advantages of the present invention will become more apparent by reading the detailed description of non-limiting embodiments made with reference to the following drawings:

1 to 6 are cross-sectional views of various manufacturing stages of a MOS device according to a specific embodiment of the present invention;

FIG. 7 is a three-dimensional perspective view of a FinFET according to a specific embodiment of the present invention after fabrication;

The same or similar reference numerals in the drawings represent the same or similar components.

Detailed ways

In order to make the object, technical solution and advantages of the present invention clearer, the embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

Embodiments of the present invention are described in detail below, examples of which are shown in the drawings, wherein the same or similar reference numerals designate the same or similar elements or elements having the same or similar functions throughout. The embodiments described below by referring to the figures are exemplary only for explaining the present invention and should not be construed as limiting the present invention.

The embodiment of the present invention provides a FINFET manufacturing method, which can effectively suppress the punch-through current without affecting other characteristics of the device. Specifically, the method includes the following steps:

a. providing a semiconductor substrate 100 on which a first fin 201 is formed;

b. Covering the mask layer 202 on the first fin 201;

c. forming a punch-through barrier layer 300 in the surface of the semiconductor substrate 100;

d. Using the first fin 201 and the mask layer 202 as a mask to further etch the semiconductor substrate 100 to form the second fin 200, and remove the mask 202;

e. Forming an isolation layer 400 , source and drain regions, an interlayer dielectric layer 500 and a gate stack 600 sequentially on the semiconductor substrate 100 and the second fin 200 . Specifically, a trench isolation structure is formed on the semiconductor substrate, a source-drain region is formed on the second fin, and a gate stack and an interlayer dielectric layer are formed on the semiconductor substrate and the second fin.

Wherein, in step a, the height of the first fin 201 is equal to the height difference between the second fin 200 and the isolation layer 400; the height of the first fin 201 is 30-50 nm, and the thickness is 10-30 nm.

Wherein, in step b, the material for forming the mask layer 202 is silicon nitride and/or silicon oxide. Wherein, in step c, the penetration barrier layer 300 is located at the bottom of the first fin 201 , and its border close to the substrate 100 is located within the second fin 200 .

Wherein, in step c, the method of forming the punch-through barrier layer 300 is side scattering; the type of impurity forming the punch-through barrier layer 300 is the same as that of the substrate; the impurity concentration of the punch-through barrier layer 300 is 1e17cm ⁻³ to 1e19cm ^{−3 3} .

According to the FINFET manufacturing method provided by the present invention, the fins are etched twice, the first etching makes the height of the fins equal to the effective height of the channel, and the rest of the silicon material is retained, and the silicon nitride is used as a mask to ionize the fins. Implantation and annealing form a punch-through barrier layer; the second etching makes the fin reach the actual required height, and then forms the isolation layer, source and drain regions and other parts. The impurity and damage introduced into the isolation layer during side scattering are effectively solved, and the performance of the device is greatly improved.

The manufacturing method of the present invention will be described in detail below in conjunction with the accompanying drawings, including the following steps. It should be noted that the drawings of the various embodiments of the present invention are only for illustrative purposes, and therefore are not necessarily drawn to scale.

Referring to FIG. 1 , firstly, the first fin 201 located above the substrate 100 is fabricated. Merely by way of example, both the substrate 100 and the first fin 201 are composed of silicon. The first fin 201 is formed by epitaxially growing a semiconductor layer on the surface of the substrate 100 and etching the semiconductor layer. The epitaxial growth method may be molecular beam epitaxy (MBE) or other methods, and the etching method may be dry etching or dry/wet etching. The height of the first fin 201 is 30-50 nm, and the bottom of the fin 201 is located at the position where the through current is generated.

Next, a mask layer 202 is covered on the surface of the first fin 201 , as shown in FIG. 2 . The function of the mask 202 is to protect the first fin 201 in the subsequent ion implantation, and avoid introducing impurities into the fin. As an example, the material for forming the mask 202 in this embodiment is silicon nitride, and its thickness can be adjusted according to the ions and energy of particle implantation, and is 20-60 nm.

Next, as shown in FIG. 3 , ion implantation is performed to implant impurities into the semiconductor substrate 100 not covered by the first fins 201 . Because the fins of FinFET are very thin, during the ion implantation process, due to the scattering effect, the impurity ions injected into the substrate on both sides of the first fin can easily reach the substrate under the fin through thermal movement, forming the The required doping profile, therefore, the punch-through barrier layer can be formed at the bottom of the channel where the punch-through current occurs without going through the fin. In this embodiment, for an N-type device, the particles forming the punch-through barrier layer 300 are As; for a P-type device, the particles for programming the punch-through barrier layer 300 are B; the impurity concentration of the punch-through barrier layer 300 is 1e17cm ⁻³ to 1e19cm ^-3 . The formed penetration barrier layer 300 is uniformly distributed under the first fin 201 , as shown in FIG. 4 .

Next, as shown in FIG. 5 , using the first fin 201 and the mask layer 202 as a mask, the first fin 201 is further etched to form the final second fin 200 . The specific etching method is the same as the method for forming the first fins 201 until the actual required height of the fins is reached. In this step, only the substrate region under the first fin 201 together with the punch-through barrier layer 300 therein remains, forming the final second fin 200 together with the first fin 201 . After the above steps, after the etching is completed, the formed second fin 200 still contains a punch-through barrier layer, and its distribution is concentrated, located at the place where the punch-through current is generated at the bottom of the channel, effectively suppressing the punch-through current; at the same time, using the lateral The method of scattering forms a punch-through barrier layer, which effectively avoids the introduction of impurities and defects in the channel, and optimizes device performance.

Next, as shown in FIG. 6 , a row isolation layer 400 is formed on the semiconductor structure. Preferably, silicon nitride and buffer silicon dioxide are first patterned on the second fin 200 as a mask for trench etching. Next, trenches with a certain depth and sidewall angles are etched on the substrate 100 . A thin layer of silicon dioxide is then grown to round the top corners of the trenches and remove damage introduced to the silicon surface during the etch process. Oxidation is followed by trench filling, and the filling medium may be silicon dioxide. Next, a CMP process is used to planarize the surface of the semiconductor substrate to expose the mask layer 202 on the top of the second fin 200 , and use it as a mask to perform anisotropic etching to expose the second fin 200 .

Next, a dummy gate structure is formed, the dummy gate structure is perpendicular to the second fin 200 and its width is equal to the channel length on the fin of the semiconductor structure. Specifically, the dummy gate stack may be single-layer or multi-layer. The dummy gate stack may include polymer material, amorphous silicon, polysilicon or TiN, and the thickness may be 10-100 nm. Processes such as thermal oxidation, chemical vapor deposition (CVD), and atomic layer deposition (ALD) can be used to form the dummy gate stack. Optionally, sidewalls are formed on the sidewalls of the gate stack to separate the gates. The sidewalls may be formed of silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, combinations thereof, and/or other suitable materials. The side walls may have a multi-layer structure. The sidewall can be formed by deposition and etching process, and its thickness range can be 10nm-100nm, such as 30nm, 50nm or 80nm.

Next, source and drain regions are formed on both sides of the dummy gate stack. Specifically, the dummy gate structure is used as a mask to perform ion implantation on the semiconductor structure, and the isolation layer 400 serves as a protective layer for ion implantation to avoid damage to the surface of the fin 200 when impurity ions are injected into the second fin 200 . Since silicon and silicon dioxide have little difference in the impact of the impurity incident depth during ion implantation, after the ion implantation is completed, heavy doping will be formed at the second fin 200 and the isolation layer 400 not covered by the dummy gate structure. district. Next, annealing is performed on the semiconductor structure. Specifically, the annealing temperature is 950° C. and the annealing time is 15-30 minutes to activate the second fin 200 and remove impurities in the source and drain regions to form a uniform source and drain doped region.

Next, an interlayer dielectric layer 500 is deposited and planarized in parallel to expose the dummy gate stack. Specifically, the interlayer dielectric layer 500 can be formed by CVD, high density plasma CVD, spin coating or other suitable methods. The material of the interlayer dielectric layer 500 may include SiO ₂ , carbon-doped SiO ₂ , BPSG, PSG, UGS, silicon oxynitride, low-k materials or combinations thereof. The thickness range of the interlayer dielectric layer 500 may be 40nm-150nm, such as 80nm, 100nm or 120nm. Next, a planarization process is performed to expose the dummy gate stack and be flush with the interlayer dielectric layer 500 (the term "flush" in the present invention refers within the range).

Next, the dummy gate stack is removed to form dummy gate vacancies, exposing the surface of the isolation layer 400 below the dummy gate stack. Specifically, the dummy gate structure can be removed by dry etching. Next, the isolation layer 300 under the dummy gate vacancy is removed to expose the channel portion. Specifically, the dummy gate structure can be removed by wet etching and/or dry etching. In one embodiment, plasma etching is used. Next, a gate structure 600 is formed in the dummy gate vacancy. The gate structure 600 includes a gate dielectric layer, a work function adjustment layer and a gate metal layer. After the gate structure 600 is formed, the semiconductor structure is shown in FIG. 7 .

The above embodiments use the gate-last process to fabricate FinFETs, but are not limited to the above-mentioned embodiments, and the present invention is also applicable to the gate-first process.

According to the FINFET structure provided by the present invention, after the interlayer dielectric layer is formed, the sidewall is etched away, vacancies are formed in the interlayer dielectric layer above the gate and the source and drain regions, and the previous sidewall material is replaced with air, effectively reducing the The dielectric constant of the material in the outer edge region is reduced, and the capacitive coupling effect between the source drain region and the gate is weakened, thereby effectively reducing parasitic capacitance and optimizing device performance.

Although the example embodiments and their advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made to these embodiments without departing from the spirit and scope of the invention as defined by the appended claims. For other examples, those of ordinary skill in the art will readily understand that the order of process steps may be varied while remaining within the scope of the present invention.

In addition, the scope of application of the present invention is not limited to the process, structure, manufacture, material composition, means, methods and steps of the specific embodiments described in the specification. From the disclosure of the present invention, those of ordinary skill in the art will easily understand that for the processes, structures, manufacturing, material compositions, means, methods or steps that currently exist or will be developed in the future, where they are implemented in accordance with the description of the present invention Corresponding embodiments that perform substantially the same function or achieve substantially the same results can be applied in accordance with the present invention. Therefore, the appended claims of the present invention are intended to include such processes, structures, manufactures, compositions of matter, means, methods or steps within their protection scope.

Claims (8)

1. A manufacturing method of FINFET, comprising: a. providing a semiconductor substrate (100) on which a first fin (201) is formed; b. covering the first fin (201) with a mask layer (202); c. forming a punch-through barrier layer (300) in the semiconductor substrate (100); d. Using the first fin (201) and the mask layer (202) as a mask to sequentially etch the through barrier layer (300) and a part of the semiconductor substrate (100), the first The fin (201) is expanded into a second fin (200), and the mask (202) is removed; e. Forming a trench isolation structure (400) on the semiconductor substrate (100), forming a source and drain region on the second fin (200), forming a gate stack on the semiconductor substrate and the second fin layers and interlayer dielectric layers. 2. The manufacturing method according to claim 1, characterized in that, in step a, the height of the first fin (201) depends on the predetermined height of the second fin (200) to be formed and the isolation layer (400) height difference. 3. The manufacturing method according to claim 2, characterized in that, in step a, the height of the first fin (201) is 30-50 nm, and the thickness is 10-30 nm. 4. The manufacturing method according to claim 1, characterized in that, in step b, the material for forming the mask layer (202) is silicon nitride and/or silicon oxide. 5. The manufacturing method according to claim 1, characterized in that, the punch-through barrier layer (300) formed in step c is located at the bottom of the first fin (201), and is located close to the boundary of the substrate (100). positioned within the second fin (200) to be formed. 6. The manufacturing method according to claim 1, characterized in that, in step c, the method of forming the punch-through barrier layer (300) is side scattering of doped ions. 7. The manufacturing method according to claim 1 or 6, characterized in that, in step c, the type of impurity forming the punch-through barrier layer (300) is the same as that of the substrate. 8. The manufacturing method according to claim 1 or 6, characterized in that, in step c, the impurity concentration of the punch-through barrier layer (300) is 1e17cm ^-3 - 1e19cm ^-3 .