CN105515577B - A kind of reinforcing ring oscillator of anti-SET - Google Patents

Abstract

The invention discloses a SET-resistant reinforced ring oscillator, comprising: an N-level main ring oscillator, which includes an N-level delay unit, each delay unit outputs 3 pairs of differential outputs, and outputs 3N pairs of differential outputs in total ; and N output voters, each output voter is connected with the first-stage delay unit in the N-stage main ring oscillator and receives 3 pairs of differential outputs from the first-stage delay unit as input, and to the described Input a valid value after majority voting, where N is an integer greater than 1. The anti-SET reinforced ring oscillator of the present invention has strong immunity to SET, can generate uniform multi-phase output, can avoid the phase synchronization problem of redundant loop caused by traditional reinforced VCO, and does not add additional delay in the loop, The effect on the loop oscillation frequency is minimal.

Description

A Hardened Ring Oscillator Against SET

technical field

The invention relates to the technical field of oscillators, in particular to a single-event transient (Single-Event Transient, SET) reinforced ring oscillator.

Background technique

In the radiation environment, after the high-energy particles bombard the sensitive nodes of the circuit, the "electron-hole" pairs produced by the impact ionization are transmitted and collected under the action of the electric field and concentration gradient of the transistor, so that the output voltage or current fluctuates, resulting in The circuit produces erroneous outputs, creating a SET effect. Integrated circuits are susceptible to various failures caused by SET.

Ring oscillators are mainly used in circuits such as clock generation, frequency multiplication and frequency synthesis. The ring oscillator is a typical feedback system, which works in a periodic oscillation state. An error generated by a sensitive node will be transmitted to the entire oscillator along with the feedback, so the ring oscillator is very sensitive to SET. When a ring oscillator is bombarded by high-energy particles, it may cause phase and frequency deviations in its output, or even stop oscillation (even-order oscillators are particularly sensitive).

Relevant studies have shown that the effect of strengthening the ring oscillator can be achieved by increasing the number of delay unit stages in the ring oscillator and improving the circuit structure, but the strengthening effect is limited. Triple-mode redundancy technology uses three circuit copies to obtain three output signals, and then determines the effective output through majority voting. When a circuit copy is disturbed by SET, as long as the majority result is obtained, the influence of SET on the circuit output can be eliminated or weakened, making SET immunity possible.

FIG. 1 shows a VCO structure based on a conventional voltage-controlled oscillator (Voltage-Controlled Oscillator, VCO) directly using triple-mode redundancy technology. The VCO structure is composed of three ring oscillators and a voting circuit. Wherein, the control voltage is connected to the control voltage input terminal Vcont of the three ring oscillators, the output out of the first oscillator is connected to the input terminal A of the voting circuit, the output out of the second oscillator is connected to the input terminal B of the voting circuit, and the output of the third oscillator is connected to the input terminal B of the voting circuit. The output out of the oscillator is connected to the input terminal C of the voting circuit, and the output Z of the voting circuit is used as the output of the whole circuit. Figure 2 shows the structure of a voltage-controlled ring oscillator, each VCO structure is formed by a delay unit ring and a shaping circuit in series. The common terminal of the three VCO loops is only the control voltage Vcont, which can only ensure that the oscillation frequency of the three VCO loops is the same, but cannot control the phase of the loop, so the phases of the clocks generated by the three loops are random, resulting in the voting circuit The correct clock cannot be output.

Figure 3 is a schematic diagram of a patent applied by the PLA National University of Defense Technology in 2010 (application number: 201010295620.4). This patent changes the feedback of the oscillator loop to feed back the output after voting to the VCO branch, thereby eliminating three loops. The problem of random road phase. However, the voting structure introduced by it destroys the consistency of the structure of each level of the loop, which will cause the phase difference of the output of the VCO at all levels to be uneven, which is difficult to apply in the occasion where multi-phase output is required. In addition, the introduced voting structure increases the loop Delay will reduce the operating frequency of the VCO.

Contents of the invention

(1) Technical problems to be solved

In order to solve the above-mentioned problems in the related art, the present invention provides an anti-SET reinforced ring oscillator. The anti-SET reinforced ring oscillator of the present invention has strong immunity to SET, can generate uniform multi-phase output, and can Avoid the phase synchronization problem of the redundant loop caused by the traditional reinforced VCO, no additional delay is added in the loop, and the impact on the loop oscillation frequency is small.

(2) Technical solutions

According to one aspect of the present invention, there is provided a kind of anti-SET reinforced ring oscillator, comprising: N-level main ring oscillator, which includes N-level delay units, each delay unit outputs 3 pairs of differential outputs, and the total output 3N pairs of differential outputs; and N output voters, each output voter is connected to the first-stage delay unit in the N-stage main ring oscillator and receives 3 pairs of differential outputs from the stage delay unit as input, and output an effective value after performing a majority vote on the input, wherein, N is an integer greater than 1.

Preferably, each output voter includes: three shaping circuit modules, each shaping circuit module has a pair of differential input terminals and a pair of positive output terminals and negative output terminals, and the pair of differential input terminals is from N The first-stage delay unit in the primary ring oscillator receives a pair of differential outputs as input, and each shaping circuit module amplifies and shapes the input into a digital level signal that changes between high and low levels, and according to the digital level signal The positive and negative phase relationship outputs digital level signals from the pair of positive output terminals and negative output terminals; the forward voting circuit module has three input terminals, and receives digital signals from the positive output terminals of the three shaping circuit modules respectively. A level signal, which generates a positive output result after a majority vote; and a negative voting circuit module, which has three input terminals, respectively receiving digital level signals from the negative output terminals of the three shaping circuit modules, and after a majority vote A negative output result is generated, wherein the positive output result and the negative output result are a pair of differential outputs as an effective value output by the output voter.

Preferably, the N-stage master ring oscillator only includes one oscillation loop.

Preferably, when N is an odd number greater than 2, the oscillation loop of the N-level main ring oscillator is composed of N identical delay units cascaded, and each delay unit has three pairs of differential input terminals and three pairs of differential outputs terminal, and control voltage terminal, in all N-level delay units, the three pairs of differential output terminals of the previous delay unit are connected in reverse to the three pairs of differential input terminals of the secondary delay unit, and the last delay unit The three pairs of differential output terminals of the first-stage delay unit are connected in antiphase to the three pairs of differential input terminals of the first-stage delay unit, so that the N-stage delay units are connected end to end to form a ring structure.

Preferably, when N is an even number greater than 2, the oscillation loop of the N-stage main ring oscillator is composed of N identical delay units cascaded, and each delay unit has three pairs of differential input terminals, three pairs of Differential output terminals, and control voltage terminals, in all N-level delay units, the three pairs of differential output terminals of the first-level delay unit are connected to the three pairs of differential input terminals of the secondary delay unit in positive phase, for the other N-1 stage delay unit, the three pairs of differential output terminals of the previous stage delay unit are connected in reverse phase to the three pairs of differential input terminals of the secondary delay unit, and the three pairs of differential output terminals of the last stage delay unit are connected in reverse phase to the first stage delay unit Three pairs of differential input terminals of the first-level delay unit, so that the N-level delay units are connected end to end to form a ring structure.

Preferably, each delay unit includes three identical basic units, each basic unit has three pairs of differential input terminals, a pair of differential output terminals and control voltage terminals, and the three basic units of a delay unit receive the same Three pairs of differential inputs, wherein, when only one of the three pairs of differential inputs in a basic unit has an error due to the SET effect, the basic unit can make a judgment and generate a correct output.

Preferably, the three basic units of a delay unit output three pairs of differential outputs independent of each other, wherein, when a basic unit in a delay unit outputs a wrong differential output due to the SET effect, the other two basic units are normal output.

Preferably, when three pairs of differential input terminals of a basic unit are connected together to form a pair of differential input terminals, the ring oscillator is formed by ring cascading such basic units.

Preferably, each basic unit includes two identical resistive loads, two identical voting switches and a controlled tail current source, wherein the controlled tail current source changes the basic by adjusting the current under the control of the control voltage. The delay of the unit, two voting switches perform majority voting on the three pairs of differential inputs, and the resistive load determines the output swing of the basic unit.

Preferably, the two identical voting switches include a first voting switch and a second voting switch, and the first voting switch includes a first MOS device, a second MOS device, a third MOS device, a fourth MOS device, a fifth MOS device and The sixth MOS device, and the second voting switch includes a seventh MOS device, an eighth MOS device, a ninth MOS device, a tenth MOS device, an eleventh MOS device and a twelfth MOS device, wherein the three pairs of differential input terminals They are respectively the first non-inverting input terminal and the first inverting input terminal, the second non-inverting input terminal and the second inverting input terminal, the third non-inverting input terminal and the third inverting input terminal, wherein a pair of differential outputs The terminals are the non-inverting output terminal and the inverting output terminal respectively, wherein the first MOS device is connected in series with the second MOS device, that is, the source of the first MOS device is connected to the drain of the second MOS device, and the first MOS device The drain is connected to the inverting output terminal, the source of the second MOS device is connected to the controlled tail current source, the gate of the first MOS device is connected to the first non-inverting input terminal, and the gate of the second MOS device is connected to the The second positive phase input terminal is connected; the third MOS device is connected in series with the fourth MOS device, that is, the source of the third MOS device is connected to the drain of the fourth MOS device, and the drain of the third MOS device is connected to the Inverting output terminal, the source of the fourth MOS device is connected to the controlled tail current source, the gate of the third MOS device is connected to the second non-inverting input terminal, the gate of the fourth MOS device is connected to the third non-inverting input terminal connected; the fifth MOS device is connected in series with the sixth MOS device, that is, the source of the fifth MOS device is connected to the drain of the sixth MOS device, the drain of the fifth MOS device is connected to the inverting output terminal, and the fifth MOS device is connected to the drain of the sixth MOS device. The sources of the six MOS devices are connected to the controlled tail current source, the gate of the fifth MOS device is connected to the third non-inverting input terminal, and the gate of the sixth MOS device is connected to the first non-inverting input terminal; wherein, the seventh The MOS device is connected in series with the eighth MOS device, that is, the source of the seventh MOS device is connected to the drain of the eighth MOS device, the drain of the seventh MOS device is connected to the non-inverting output terminal, and the eighth MOS device The source is connected to the controlled tail current source, the gate of the seventh MOS device is connected to the first inverting input terminal, the gate of the eighth MOS device is connected to the second inverting input terminal; the ninth MOS device is connected to the tenth MOS The devices are connected in series, that is, the source of the ninth MOS device is connected to the drain of the tenth MOS device, the drain of the ninth MOS device is connected to the non-inverting output terminal, and the source of the tenth MOS device is connected to the controlled tail current source, the gate of the ninth MOS device is connected to the second

_

The inverting input terminal is connected, the gate of the tenth MOS device is connected to the third inverting input terminal; the eleventh MOS device is connected in series with the twelfth MOS device, that is, the source of the eleventh MOS device is connected to the twelfth MOS device The drains of the devices are connected, the drain of the eleventh MOS device is connected to the non-inverting output terminal, the source of the twelfth MOS device is connected to the controlled tail current source, and the gate of the eleventh MOS device is connected to the first MOS device. The three inverting input terminals are connected, and the gate of the twelfth MOS device is connected to the first inverting input terminal.

(3) Beneficial effects

The beneficial effects of the present invention are:

(1) The ring oscillator of the present invention has stronger immunity to SET:

In the present invention, the delay units at all levels in the main ring oscillator have the majority voting ability for three pairs of differential inputs, and can generate independent three pairs of differential outputs, and errors caused by SET will not propagate in the oscillation loop, and Due to the majority voting mechanism of the output voter, the wrong output of the main ring oscillator due to SET will not affect the output result of the ring oscillator.

(2) The ring oscillator of the present invention can produce uniform multi-phase output:

Because the output stage voter of the ring oscillator is outside the oscillation loop, it does not affect the consistency of the delay units at all levels in the main oscillation loop, so the output phase difference of each level in the main oscillation loop is uniform.

(3) The ring oscillator of the present invention can avoid the phase synchronization problem of the redundant loop caused by the traditional reinforced VCO:

In the present invention, the redundant generation and voting judgment of the main ring oscillator are completed in the delay unit, so the main ring oscillator only includes one oscillation loop, so the redundant loop problem introduced by traditional reinforcement does not occur.

(4) The present invention directly introduces the redundant structure into the basic delay unit, does not add extra delay in the loop, and has little influence on the loop oscillation frequency.

Description of drawings

FIG. 1 shows a VCO structure based on a conventional voltage-controlled oscillator (Voltage-Controlled Oscillator, VCO) directly using triple-mode redundancy technology. The VCO structure is composed of three ring oscillators and a voting circuit.

Figure 2 shows the structure of a voltage-controlled ring oscillator, each VCO structure is formed by a delay unit ring and a shaping circuit in series.

Fig. 3 shows the VCO structure disclosed in the patent document with the application number 201010295620.4.

FIG. 4 shows a schematic structure of a SET-resistant hardened ring oscillator according to the present invention.

FIG. 5A shows a schematic structure of an embodiment of a master ring oscillator in a SET-resistant hardened ring oscillator according to the present invention.

FIG. 5B shows a schematic structure of another embodiment of the main ring oscillator in the SET-resistant hardened ring oscillator according to the present invention.

FIG. 6 shows a schematic structure of an embodiment of a delay unit in the main ring oscillator in the SET-resistant hardened ring oscillator according to the present invention.

FIG. 7 shows a schematic structure of an embodiment of a basic unit in a delay unit in a main ring oscillator in a SET-resistant hardened ring oscillator according to the present invention.

Detailed ways

In order to make the object, technical solution and advantages of the present invention clearer, the present invention will be described in further detail below in conjunction with specific embodiments and with reference to the accompanying drawings. In the drawings of the present invention, the same reference numerals denote the same components.

FIG. 4 shows a schematic structure of a SET-resistant hardened ring oscillator according to the present invention.

As shown in FIG. 4, a kind of anti-SET reinforced ring oscillator according to the present invention includes: N-level main ring oscillator 401, which includes N-level delay units, and each level of delay units outputs 3 pairs of differential outputs ( For example, (O1_n1, O1_p1), (O1_n2, O1_p2), (O1_n3, O1_p3)), a total of 3N pairs of differential outputs are output; and N output voters 402, each output voter 402 is connected to the N-stage main ring oscillator The first-level delay unit in 401 is connected and receives 3 pairs of differential outputs from the first-level delay unit as input, and outputs an effective value (for example, (Z1+, Z1-), (Z2+ , Z2-)...(Zn+, Zn-)), wherein, N is an integer greater than 1.

Preferably, each output voter 402 includes: three shaping circuit modules, each of which has a pair of differential input terminals (for example, (in1+, in-), (in2+, in2-), (in3+, in3-)) and a pair of positive output terminals out+ and negative output terminals out-, the pair of differential input terminals receive a pair of differential outputs from the primary delay unit in the N-stage main ring oscillator 401 as input, each A shaping circuit module amplifies and shapes the input into a digital level signal that changes between high and low levels, and outputs from the pair of positive output terminals out+ and negative output terminals out- according to the positive and negative phase relationship of the digital level signal Digital level signal; forward voting circuit module 403, which has three input terminals A, B, C, and receives digital level signals from the positive output terminals out+ of the three shaping circuit modules respectively, and generates a positive signal after majority voting. and the negative voting circuit module 403, which has three input terminals A, B, and C, respectively from the digital level signals received from the negative output terminals out- of the three shaping circuit modules, which are generated after majority voting A negative output result, wherein the positive output result and the negative output result are a pair of differential outputs, which are used as the effective value output by the output voter 402 .

Specifically, as shown in FIG. 4, the anti-SET reinforced ring oscillator of the present invention may include N-stage main ring oscillator 401 and N output voters 402, and the main ring oscillator sends its 3N sets of differential outputs to the output In the voter, the effective value is output after the voter shaping and majority voting. Vcon is the control voltage of the main ring oscillator, which is connected to the external control voltage or the control voltage output by the filter in the phase-locked loop. O1_n1, O1_n2, O1_n3, O1_p1, O1_p2, O1_p3, etc. are the outputs of the first stage of the main ring oscillator , where (O1_n1, O1_p1), (O1_n2, O1_p2), (O1_n3, O1_p3) are three pairs of differential outputs, similarly, On_n1, On_n2, On_n3, On_p1, On_p2, On_p3, etc. are the N'th stage of the main ring oscillator , wherein (On_n1, On_p1), (On_n2, On_p2), (On_n3, On_p3) are three pairs of differential outputs, and the three pairs of differentials of each stage of the main ring oscillator are connected to the input end of the output voting device 402, and the output voting The device 402 conducts a majority vote on the three sets of differential signal inputs to obtain effective differential outputs out+ and out-. The structure of the output voter 402 is shown in the dotted box in Figure 4, including three shaping circuit modules and two voting circuit modules 403, the shaping circuit module amplifies and shapes the differential output of the main ring oscillator into a digital level signal, and then Effective output is obtained after voting through the voting circuit.

The working principle of the anti-SET reinforced ring oscillator of the present invention is as follows: the main ring oscillator oscillates stably under the control of the control voltage, and the three pairs of differential outputs output by each stage delay unit in the main ring oscillator 401 pass through the output voter The shaping circuit module of 402 becomes three pairs of digital signals varying between high and low levels, and the digital level signals after shaping are sent to two voting circuit modules 403 for voting according to the positive and negative phase relationship. The voting circuit module 403 adopts a majority voting mechanism, that is, the output value is the same as the majority logic value among A, B, and C.

The working mode of the anti-SET reinforced ring oscillator of the present invention is illustrated in the following example: three pairs of differential outputs (On_n1, On_p1), (On_n2, On_p2), (On_n3, Qn_p3) of the Nth stage of the main ring oscillator are respectively sent to Differential input terminals (in1+, in-), (in2+, in2-), (in3+, in3-) of the three shaping circuit modules. After amplification and shaping, the three pairs of differential outputs are sent to two voting circuits for voting according to the positive and negative phase relationship, that is, the positive outputs of the three shaping circuit modules are sent to the three input terminals A, B, and C of the forward voting circuit. After the majority vote, the output result out+ is generated, and the negative outputs of the three shaping circuit modules are sent to the three input terminals A, B, and C of the negative voting circuit, and the output result out- is generated after the majority vote, and out+ and out- are A pair of differential outputs. One of the working characteristics is that each delay unit of the main ring oscillator has three pairs of differential outputs, and another working characteristic is that the output voting circuit is outside the main ring oscillator and does not affect the structure of the main ring oscillator.

The preferred embodiment of the structure of the main ring oscillator of the SET-resistant reinforced ring oscillator of the present invention is shown in Figures 5A and 5B. Since the structure of the odd-numbered ring oscillator is slightly different from that of the even-numbered ring oscillator, the structure of the ring oscillator is slightly different in the present invention. Described separately.

FIG. 5A shows a schematic structure of an embodiment of a master ring oscillator in a SET-resistant hardened ring oscillator according to the present invention.

FIG. 5B shows a schematic structure of another embodiment of the main ring oscillator in the SET-resistant hardened ring oscillator according to the present invention.

In the SET-resistant hardened ring oscillator of the present invention, preferably, the N-stage main ring oscillator includes only one oscillation loop.

In a preferred embodiment of the main ring oscillator in the anti-SET reinforced ring oscillator of the present invention, when N is an odd number greater than 2, the oscillation loop of the N-stage main ring oscillator 401 consists of N identical delays Units 501 are cascaded, and each delay unit 501 has three pairs of differential input terminals, three pairs of differential output terminals, and control voltage terminals. Among all N-level delay units, the three pairs of differential The output terminals are invertingly connected to the three pairs of differential input terminals of the secondary delay unit, and the three pairs of differential output terminals of the last-stage delay unit are invertingly connected to the three pairs of differential input terminals of the first-stage delay unit, so that N stages The delay units are connected end to end to form a ring structure.

FIG. 5A shows a schematic structure of an embodiment of an odd-level main ring oscillator, which is a three-stage ring oscillator structure. The VCO is composed of three identical delay units 501 cascaded, and each delay unit has three pairs Differential inputs (in1_p, in1_n), (in2_p, in2_n), (in3_p, in3_n), three pairs of differential outputs (out1_p, out1_n), (out2_p, out2_n), (out3_p, out3_n), and control voltage terminal Vcon. The control voltage terminal Vct of each delay unit is connected to the control voltage Vcon, and the output of the previous delay unit is connected in reverse to the input of the secondary delay unit, thus forming a ring structure end to end. Specifically in Figure 5A, the three pairs of differential outputs of the first-stage delay unit are connected to the input terminals of the second-stage delay unit in reverse, that is, (O1_n1, O1_n2, O1_n3, O1_p1, O1_p2, O1_p3) and the second-stage delay unit The unit input terminals (in1_p, in2_p, in3_p, in1_n, in2_n, in3_n) are connected in sequence, and the second-stage differential output is inversely connected to the differential input of the third-stage delay unit, namely (O2_n1, O2_n2, O2_n3, O2_p1, O2_p2, O2_p3) are connected to the input terminals of the third-level delay unit (in1_p, in2_p, in3_p, in1_n, in2_n, in3_n) in sequence, and the differential output of the third-level delay unit is reversed and returned to the first-level delay unit The differential inputs of , namely (O3_n1, O3_n2, O3_n3, O3_p1, O3_p2, O3_p3) are sequentially connected to the first stage input terminals (in1_p, in2_p, in3_p, in1_n, in2_n, in3_n).

In another preferred embodiment of the main ring oscillator in the anti-SET reinforced ring oscillator of the present invention, when N is an even number greater than 2, the oscillation loop of the N-stage main ring oscillator 401 consists of N identical Delay units 501 are cascaded, and each delay unit has three pairs of differential input terminals, three pairs of differential output terminals, and control voltage terminals. Among all N-level delay units, the three pairs of first-level delay units The differential output terminals are positively connected to the three pairs of differential input terminals of the secondary delay unit, and for other N-1 level delay units, the three pairs of differential output terminals of the previous delay unit are connected to the secondary delay unit in reverse phase The three pairs of differential input terminals of the last-stage delay unit are connected in reverse phase to the three pairs of differential input terminals of the first-stage delay unit, so that the N-stage delay units are connected end to end to form a ring structure.

Fig. 5B shows a schematic structure of an embodiment of an even-numbered main ring oscillator. The structure of the even-numbered ring oscillator is slightly different from that of the odd-numbered ring oscillator. In order to meet the oscillation conditions, only one of the delay units in one of the stages needs to be It is only necessary to connect the differential output to the secondary delay unit in the forward direction, and the connection method of other delay units is the same as that of the odd-numbered stages. The even-numbered oscillator structure shown in Figure 5B is a four-stage ring oscillator, wherein the differential output of the second-stage delay unit is positively connected to the third-stage delay unit, namely (O2_n1, O2_n2, O2_n3, O2_p1, O2_p2, O2_p3) is connected to the third-stage input terminal (in1_n, in2_n, in3_n, in1_p, in2_p, in3_p) in turn, and the connection relationship of the delay units at other levels is the same as that of the odd-numbered stages, that is, the differential output of the previous delay unit is reversed. Phase connected to the input of the secondary delay unit.

FIG. 6 shows a schematic structure of an embodiment of a delay unit in the main ring oscillator in the SET-resistant hardened ring oscillator according to the present invention.

Preferably, in the main ring oscillator in the SET-resistant ruggedized ring oscillator according to the present invention, each delay unit 501 may include three identical basic units 601, and each basic unit 601 has three pairs of differential inputs terminal, a pair of differential output terminals and a control voltage terminal, the three basic units 601 of a delay unit 501 receive the same three pairs of differential inputs, wherein, when there is only one pair of inputs in the three pairs of differential inputs in one basic unit When an error occurs because of the SET effect, the basic unit can make a judgment and produce a correct output.

Preferably, in the main ring oscillator in the anti-SET reinforced ring oscillator according to the present invention, the three basic units 601 of a delay unit 501 output three pairs of differential outputs independent of each other, wherein when a delay unit When one basic unit 601 in 501 outputs a wrong differential output due to the SET effect, the other two basic units output normally.

Preferably, in the main ring oscillator in the SET-resistant ruggedized ring oscillator according to the present invention, when three pairs of differential input terminals of one basic unit 601 are connected together to form a pair of differential input terminals, by pairing such basic The units are ring cascaded to form a ring oscillator.

Specifically, as shown in FIG. 6, the delay unit 501 of the main ring oscillator is composed of three identical basic units 601. The basic unit 601 has three pairs of differential inputs and control voltage terminals, and can perform majority voting on the three pairs of inputs. When only one of the three pairs of inputs has an error due to the SET effect, the basic unit can judge and produce a correct output, so it has immunity to the SET error of the input signal. Since the three basic units 601 included in the delay unit 501 output independently, when bombarded by a single particle, the SET effect will only affect one of the basic units, and the other two unit circuits are normally output, so that the next stage The delay unit can make an effective judgment. The structure of the 501 unit is characterized by the ability to perform majority voting on three pairs of inputs and produce three pairs of independent differential outputs. Another structural feature of the 501 unit is that it contains three identical basic unit 601 modules, each basic unit 601 has three pairs of inputs and one pair of outputs, and the inputs of the three basic units are the same, all coming from the three pairs of inputs of the 501 unit. The structural feature of the basic unit 601 is that it has three pairs of inputs and one pair of outputs, and can perform majority voting on the three pairs of inputs. Another structural feature of the basic unit 601 is that when all three pairs of inputs are connected together to form a pair of inputs, a ring oscillator can be formed by ring cascading the basic unit 601 .

Preferably, in the main ring oscillator in the SET-resistant hardened ring oscillator according to the invention, each elementary cell comprises two identical resistive loads, two identical voting switches and a controlled tail current source, Among them, the controlled tail current source changes the delay of the basic unit by adjusting the current under the control of the control voltage Vct, two voting switches perform majority voting on the three pairs of differential inputs, and the resistive load determines the output swing of the basic unit.

Specifically, a structure (but not limited to this structure) of the basic unit 601 is shown as a rectangular box in FIG. 6 , which consists of two identical resistive loads, two identical voting switches and a controlled tail current source, The controlled current source is controlled by the control voltage Vct to change the delay of the unit by adjusting the current, two voting switches perform majority voting on three pairs of differential inputs, and the resistive load determines the output swing of the circuit module. The two voting switches in Figure 6 are composed of N-type MOS transistors MN1, MN2, MN3, MN4, MN5, MN6, and MN7, MN8, MN9, MN10, MN11, and MN12. MN1 and MN2 are connected in series (the source of MN1 is connected to the The drain is connected), the drain of MN1 is connected to the inverting output out- of the basic unit, the source of MN2 is connected to the tail current source, the gate of MN1 is connected to the input terminal in1+, and the gate of MN2 is connected to the input terminal in2+; MN3 and MN4 are connected in series (the source of MN3 is connected to the drain of MN4), the drain of MN3 is connected to the inverting output out- of the basic unit, the source of MN4 is connected to the tail current source, and the gate of MN3 is connected to the input terminal in2+ The gate of MN4 is connected to the input terminal in3+; MN5 and MN6 are connected in series (the source of MN5 is connected to the drain of MN6), the drain of MN5 is connected to the inverting output out- of the basic unit, and the source of MN6 is connected to Tail current source, the gate of MN5 is connected to the input terminal in3+, the gate of MN6 is connected to the input terminal in1+; MN7 and MN8 are connected in series (the source of MN7 is connected to the drain of MN8), and the drain of MN7 is connected to the basic unit The positive phase output is out+, the source of MN8 is connected to the tail current source, the gate of MN7 is connected to the input terminal in1-, the gate of MN8 is connected to the input terminal in2-; MN9 and MN10 are connected in series (the source of MN9 is connected to the drain of MN10 The drain of MN9 is connected to the basic unit’s positive phase output out+, the source of MN10 is connected to the tail current source, the gate of MN9 is connected to the input terminal in2-, and the gate of MN10 is connected to the input terminal in3-; MN11 and MN10 are connected in series (the source of MN11 is connected to the drain of MN12), the drain of MN11 is connected to the positive phase output out+ of the basic unit, the source of MN12 is connected to the tail current source, and the gate of MN11 is connected to the input terminal in3- Connection, the gate of MN12 is connected to the input terminal in1-. (MN1, MN2), (MN3, MN4) and (MN5, MN6) constitute the three-way forward voting switch of the basic unit, (MN7, MN8), (MN9, MN10) and (MN11, MN12) constitute the basic unit The three-way reverse voting switch.

FIG. 7 shows a schematic structure of an embodiment of a basic unit in a delay unit in a main ring oscillator in a SET-resistant hardened ring oscillator according to the present invention.

A structure (but not limited to this structure) of the basic unit is shown as 701 in Fig. 7, which consists of two identical resistive loads, two identical voting switches and a controlled tail current source, and the controlled current source is controlled The control of the voltage Vct changes the delay of the unit by adjusting the current, two voting switches perform majority voting on the three pairs of differential inputs, and the resistive load determines the output swing of the circuit module. The two voting switches in Figure 7 are composed of P-type MOS tubes MP1, MP2, MP3, MP4, MP5, MP6 and MP7, MP8, MP9, MP10, MP11, MP12 respectively, MP1 and MP2 are connected in series (the source of MP1 is connected with the source of MP2 The drain is connected), the drain of MP1 is connected to the inverting output out- of the basic unit, the source of MP2 is connected to the tail current source, the gate of MP1 is connected to the input terminal in1+, and the gate of MP2 is connected to the input terminal in2+; MP3 and MP4 are connected in series (the source of MP3 is connected to the drain of MP4), the drain of MP3 is connected to the inverting output out- of the basic unit, the source of MP4 is connected to the tail current source, and the gate of MP3 is connected to the input terminal in2+ connection, the gate of MP4 is connected to the input terminal in3+; MP5 and MP6 are connected in series (the source of MP5 is connected to the drain of MP6), the drain of MP5 is connected to the inverting output out- of the basic unit, and the source of MP6 is connected to Tail current source, the gate of MP5 is connected to the input terminal in3+, the gate of MP6 is connected to the input terminal in1+; MP7 and MP8 are connected in series (the source of MP7 is connected to the drain of MP8), and the drain of MP7 is connected to the basic unit The positive phase output is out+, the source of MP8 is connected to the tail current source, the gate of MP7 is connected to the input terminal in1-, the gate of MP8 is connected to the input terminal in2-; MP9 and MP10 are connected in series (the source of MP9 is connected to the drain of MP10 The drain of MP9 is connected to the basic unit’s positive phase output out+, the source of MP10 is connected to the tail current source, the gate of MP9 is connected to the input terminal in2-, and the gate of MP10 is connected to the input terminal in3-; MP11 and MP12 are connected in series (the source of MP11 is connected to the drain of MP12), the drain of MP11 is connected to the basic unit positive phase output out+, the source of MP12 is connected to the tail current source, and the gate of MP11 is connected to the input terminal in3- Connection, the gate of MP12 is connected to the input terminal in1-. (MP1, MP2), (MP3, MP4) and (MP5, MP6) constitute the three-way forward voting switch of the basic unit, (MP7, MP8), (MP9, MP10) and (MP11, MP12) constitute the basic unit The three-way reverse voting switch.

In the anti-SET reinforced ring oscillator according to the present invention, the working principle of the ring oscillator is as follows: As shown in FIG. The three differential outputs in the timing unit 501 are also identical, so the three pairs of differential outputs of any stage in the ring oscillator are the same, since the output of the upper stage delay unit is used as the input of the secondary delay unit, so the secondary The three pairs of differential inputs of the delay unit are also exactly the same, therefore, under normal conditions, the delay unit shown in Figure 6 can be equivalent to only one differential input and differential output, so that the oscillation ring structure described in the present invention is equivalently based on Oscillating ring structures well known in the art. When the ring oscillator of the present invention is bombarded by a single event, the node of the basic unit circuit in the delay unit produces a SET effect, so that an error occurs in the output of the basic unit, that is, one of the three pairs of differential outputs of the delay unit The differential output produces an error, and this error will be passed to the secondary delay unit as an input, because the input of the basic unit in the delay unit adopts the redundant input shown in the basic unit 601 in Figure 6 or the basic unit 701 in Figure 7 structure, that is, as long as two of the three pairs of input signals are normal, the redundant switch in the basic unit can be guaranteed to work normally, so as not to affect the normal output of the secondary delay unit, so the temporary error caused by the SET effect will not The transmission in the ring oscillator will not affect the normal operation of the ring oscillator. The output stage shown in Figure 4 uses a majority-voting circuit so that errors in only one of the three pairs of differential outputs from a stage in the ring oscillator will not affect the result of the output stage.

In addition, the above definition of each element and method is not limited to the various specific structures, shapes or methods mentioned in the embodiments, and those of ordinary skill in the art can easily modify or replace it, for example: (1) the main ring Oscillator also can adopt current control oscillator structure (ICO) well known in the art; MOS tube or transmission pair tube replacement.

The SET-resistant hardened ring oscillator according to the present invention has the following characteristics:

(1) The output stage voting structure 402 of the ring oscillator 401 is outside the oscillation loop, which does not affect the structural consistency of the main oscillation loop;

(2) The main ring oscillator 401 in the present invention only includes one oscillation loop;

(3) Each stage of delay unit in the main ring oscillator 401 in the present invention can output three pairs of differential outputs;

(4) Delay unit 501 unit can carry out majority vote to three pairs of inputs and produce three pairs of independent differential outputs, and the redundant generation and voting judgment of oscillating signal are completed in delay unit 501;

(5) Delay unit 501 includes three identical basic unit 601 or 701 modules, each basic unit 601 or 701 has three pairs of inputs and a pair of outputs, and the inputs of the three basic units are the same, all from three pairs of 501 units enter;

(6) The basic unit 601 or 701 has three pairs of inputs and one pair of outputs, and has a voting switch capable of performing a majority vote on the three pairs of inputs;

(7) Another structural feature of the basic unit 601 or 701 is that when three pairs of inputs are connected together to form a pair of inputs, a ring oscillator can be formed by ring cascading the modified basic unit 601 or 701;

(8) The voting switch in the basic unit 601 or 701 adopts a majority voting structure.

The beneficial effects of the present invention are as follows:

(1) The ring oscillator of the present invention has stronger immunity to SET:

In the present invention, the delay units at all levels in the main ring oscillator have the majority voting ability for three pairs of differential inputs, and can generate independent three pairs of differential outputs, and errors caused by SET will not propagate in the oscillation loop, and Due to the majority voting mechanism of the output voter 402, the erroneous output of the main ring oscillator due to SET will not affect the output result of the ring oscillator.

(2) The ring oscillator of the present invention can produce uniform multi-phase output;

Because the output stage voter of the ring oscillator is outside the oscillation loop, it does not affect the consistency of the delay units at all levels in the main oscillation loop, so the output phase difference of each level in the main oscillation loop is uniform.

(3) The ring oscillator of the present invention can avoid the phase synchronization problem of the redundant loop caused by the traditional reinforced VCO:

In the present invention, the redundant generation and voting judgment of the main ring oscillator are completed in the delay unit, so the main ring oscillator only includes one oscillation loop, so the redundant loop problem introduced by traditional reinforcement does not occur.

(4) The present invention directly introduces the redundant structure into the basic delay unit, does not add extra delay in the loop, and has little influence on the loop oscillation frequency.

The specific embodiments described above have further described the purpose, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above descriptions are only specific embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention shall be included within the protection scope of the present invention.

Claims (10)

1. An anti-SET reinforced ring oscillator, characterized in that, comprising: N-level main ring oscillators, which include N-level delay units, each of which outputs 3 pairs of differential outputs, and outputs 3N pairs of differential outputs in total; and N output voters, each output voter is connected to the first-stage delay unit in the N-stage main ring oscillator and receives 3 pairs of differential outputs from the first-stage delay unit as input, and performs the input on the input Output effective value after majority vote, Wherein, N is an integer greater than 1. 2. The SET-resistant hardened ring oscillator of claim 1, wherein each output voter comprises: Three shaping circuit blocks, each shaping circuit block having a pair of differential input terminals and a pair of positive-going and negative-going output terminals, the pair of differential input ends being delayed from one stage of the N-stage master ring oscillator The unit receives a pair of differential outputs as input, and each shaping circuit module amplifies and shapes the input into a digital level signal that changes between high and low levels, and outputs positively from the pair according to the positive and negative phase relationship of the digital level signal Output digital level signal at terminal and negative output terminal; A positive voting circuit module, which has three input terminals, respectively receives digital level signals from the positive output terminals of the three shaping circuit modules, and generates positive output results after majority voting; and The negative voting circuit module has three input terminals, and receives digital level signals from the negative output terminals of the three shaping circuit modules respectively, and generates negative output results after majority voting, Wherein, the positive output result and the negative output result are a pair of differential outputs, which are used as the effective value output by the output voter. 3. The SET-resistant hardened ring oscillator as claimed in claim 1, wherein the N-stage master ring oscillator only includes one oscillation loop. 4. the anti-SET reinforced ring oscillator as claimed in claim 3 is characterized in that, when N is an odd number greater than 2, the oscillation loop of the N-level main ring oscillator is formed by cascading N identical delay units , each delay unit has three pairs of differential input terminals, three pairs of differential output terminals, and control voltage terminals. In all N-level delay units, the three pairs of differential output terminals of the previous delay unit are connected to The three pairs of differential input terminals of the secondary delay unit, and the three pairs of differential output terminals of the last delay unit are connected in reverse phase to the three pairs of differential input terminals of the first delay unit, so that the N-level delay units are connected end to end form a ring structure. 5. The reinforced ring oscillator of anti-SET as claimed in claim 3 is characterized in that, when N is 2 and greater than 2 even numbers, the oscillation loop of N-level main ring oscillator is composed of N identical delay unit stages Each delay unit has three pairs of differential input terminals, three pairs of differential output terminals, and control voltage terminals. Among all N-level delay units, the three pairs of differential output terminals of the first-level delay unit are connected in normal phase. To the three pairs of differential input terminals of the secondary delay unit, for other N-1 level delay units, the three pairs of differential output terminals of the previous delay unit are connected in reverse to the three pairs of differential input terminals of the secondary delay unit , the three pairs of differential output terminals of the last-stage delay unit are connected in reverse phase to the three pairs of differential input terminals of the first-stage delay unit, so that the N-stage delay units are connected end to end to form a ring structure. 6. The reinforced ring oscillator of anti-SET as claimed in claim 1, is characterized in that, each delay unit all comprises three identical basic units, and each basic unit has three pairs of differential input terminals, a pair of differential outputs Terminal and control voltage terminal, the three basic units of a delay unit receive the same three pairs of differential inputs, wherein, when only one pair of the three pairs of differential inputs in a basic unit has an error due to the SET effect, the The basic unit is able to make judgments and produce correct output. 7. The anti-SET reinforced ring oscillator as claimed in claim 6, characterized in that, three basic units of a delay unit output three pairs of differential outputs independent of each other, wherein, when a basic unit in a delay unit When the unit outputs a wrong differential output due to the SET effect, the other two basic units output normally. 8. The SET-resistant ruggedized ring oscillator as claimed in claim 6, wherein when three pairs of differential input terminals of a basic unit are connected together to form a pair of differential input terminals, by ringing such a basic unit cascaded to form a ring oscillator. 9. The SET-resistant hardened ring oscillator of claim 6, wherein each base unit comprises two identical resistive loads, two identical voting switches, and a controlled tail current source, wherein, The controlled tail current source changes the delay of the basic unit by adjusting the current under the control of the control voltage, two voting switches perform majority voting on three pairs of differential inputs, and the resistive load determines the output swing of the basic unit. 10. The anti-SET hardened ring oscillator according to claim 9, wherein the two identical voting switches comprise a first voting switch and a second voting switch, the first voting switch comprises a first MOS device, a second MOS device, third MOS device, fourth MOS device, fifth MOS device and sixth MOS device, and the second voting switch includes seventh MOS device, eighth MOS device, ninth MOS device, tenth MOS device, sixth MOS device The eleventh MOS device and the twelfth MOS device, wherein the three pairs of differential input terminals are respectively the first non-inverting input terminal and the first inverting input terminal, the second non-inverting input terminal and the second inverting input terminal, the third a non-inverting input terminal and a third inverting input terminal, wherein a pair of differential output terminals are respectively a non-inverting output terminal and an inverting output terminal, Wherein, the first MOS device is connected in series with the second MOS device, that is, the source of the first MOS device is connected to the drain of the second MOS device, the drain of the first MOS device is connected to the inverting output terminal, and the second The sources of the two MOS devices are connected to the controlled tail current source, the gate of the first MOS device is connected to the first positive input terminal, and the gate of the second MOS device is connected to the second positive input terminal; the third MOS device connected in series with the fourth MOS device, that is, the source of the third MOS device is connected to the drain of the fourth MOS device, the drain of the third MOS device is connected to the inverting output terminal, and the source of the fourth MOS device connected to a controlled tail current source, the gate of the third MOS device is connected to the second non-inverting input terminal, the gate of the fourth MOS device is connected to the third non-inverting input terminal; the fifth MOS device is connected in series with the sixth MOS device , that is, the source of the fifth MOS device is connected to the drain of the sixth MOS device, the drain of the fifth MOS device is connected to the inverting output terminal, and the source of the sixth MOS device is connected to the controlled tail current source, the gate of the fifth MOS device is connected to the third non-inverting input terminal, and the gate of the sixth MOS device is connected to the first non-inverting input terminal; Wherein, the seventh MOS device is connected in series with the eighth MOS device, that is, the source of the seventh MOS device is connected to the drain of the eighth MOS device, the drain of the seventh MOS device is connected to the non-inverting output terminal, and the seventh MOS device is connected to the drain of the eighth MOS device. The sources of the eight MOS devices are connected to the controlled tail current source, the gate of the seventh MOS device is connected to the first inverting input terminal, the gate of the eighth MOS device is connected to the second inverting input terminal; the ninth MOS device connected in series with the tenth MOS device, that is, the source of the ninth MOS device is connected to the drain of the tenth MOS device, the drain of the ninth MOS device is connected to the non-inverting output terminal, and the source of the tenth MOS device connected to the controlled tail current source, the gate of the ninth MOS device is connected to the second inverting input terminal, the gate of the tenth MOS device is connected to the third inverting input terminal; the eleventh MOS device is connected to the twelfth MOS The devices are connected in series, that is, the source of the eleventh MOS device is connected to the drain of the twelfth MOS device, the drain of the eleventh MOS device is connected to the non-inverting output terminal, and the source of the twelfth MOS device connected to the controlled tail current source, the gate of the eleventh MOS device is connected to the third inverting input terminal, and the gate of the twelfth MOS device is connected to the first inverting input terminal.