CN105609470A - Semiconductor device having uniform threshold voltage distribution and method of manufacturing the same - Google Patents

Abstract

Provided are a semiconductor device having a uniform threshold voltage distribution and a method of manufacturing the same. According to an embodiment, a semiconductor device may include: a fin formed on a substrate extending in a first direction; a gate stack formed on the substrate extending in a second direction crossing the first direction, wherein the gate stack includes sequentially stacked The gate dielectric layer and the metal gate layer, wherein, relative to the sidewalls of the metal gate layer on the opposite sides of the fin, the top wall of the metal gate layer on the top surface of the fin contains higher dopants of the first type and higher dopant of the second type complementary to the first type, so that the overall metal gate layer exhibits approximately uniform doping of the first type.

Description

Semiconductor device with uniform threshold voltage distribution and manufacturing method thereof

technical field

The present disclosure relates to the field of semiconductors, and more particularly, to a semiconductor device with uniform threshold voltage distribution and a manufacturing method thereof.

Background technique

As the size of planar semiconductor devices becomes smaller and smaller, the short channel effect becomes more and more obvious. For this reason, three-dimensional semiconductor devices such as FinFETs (Fin Field Effect Transistors) have been proposed. In general, a FinFET includes a fin formed vertically on a substrate and a gate stack intersecting the fin. The gate stack may include a high-K/metal gate configuration. Through injection, the work function of the metal gate can be adjusted, and the threshold voltage of the FinFET can be adjusted. However, with this method, it is difficult to uniformly distribute the implanted ions in the metal gate, so that it is difficult to achieve uniform distribution of the threshold voltage.

Contents of the invention

It is an object of the present disclosure, at least in part, to provide a semiconductor device having a uniform threshold voltage distribution and a method of manufacturing the same.

According to an aspect of the present disclosure, there is provided a method of manufacturing a semiconductor device, including: forming fins extending in a first direction on a substrate; forming gates extending in a second direction crossing the first direction on the substrate stacking, wherein the gate stack includes a gate dielectric layer and a metal gate layer stacked in sequence; using a first type of dopant to perform a first oblique implantation, wherein the direction of the first oblique implantation is toward the metal gate layer on the first side of the fin sidewall; using a dopant of the first type to perform a second oblique implantation, wherein the direction of the second oblique implantation is toward the sidewall of the metal gate layer on the second side of the fin opposite to the first side; using the dopant of the first type A third implant of complementary dopants of the second type is performed, wherein the direction of the third implant is substantially perpendicular to the surface of the substrate.

According to another aspect of the present disclosure, there is provided a semiconductor device including: fins formed on a substrate extending in a first direction; gates formed on the substrate extending in a second direction crossing the first direction stack, wherein the gate stack includes a gate dielectric layer and a metal gate layer stacked in sequence, wherein the top wall of the metal gate layer on the top surface of the fin contains a higher The dopant of the first type is higher and the dopant of the second type complementary to the first type is higher, so that the metal gate layer as a whole exhibits substantially uniform doping of the first type.

According to an embodiment of the present disclosure, the oblique implantation of the first type may be performed twice. In this way, both sidewalls of the metal gate layer on both sides of the fin can receive approximately uniform doping. On the other hand, the top wall of the metal gate layer on the top surface of the fin receives more doping of the first type. A second type of vertical implant complementary to the first type can be performed. Therefore, the top wall of the metal gate layer is more compensated, so that the metal gate layer can exhibit substantially uniform doping of the first type. In this way, the work function of the metal gate layer can be substantially uniformly adjusted, and thus the semiconductor device can exhibit substantially uniformly distributed threshold voltages.

Description of drawings

The above and other objects, features and advantages of the present disclosure will be more clearly described through the following description of the embodiments of the present disclosure with reference to the accompanying drawings, in which:

Figure 1-Figure 20C is a schematic diagram of the process of manufacturing a semiconductor device according to an embodiment of the present disclosure, wherein Figure 9A is a cross-sectional view along the AA' line in Figure 9; Figure 11A is a cross-sectional view along the AA' line in Figure 11, Figure 11B It is a sectional view along BB' line in Fig. 11, and Fig. 11C is a sectional view along CC' line in Fig. 11; Fig. 12A is a sectional view along AA' line in Fig. 12, and Fig. 12B is a sectional view along BB' in Fig. 12 line, and Figure 12C is a cross-sectional view along line CC' in Figure 12; Figures 13A, 13B, and 13C are cross-sectional views corresponding to Figures 12A, 12B, and 12C, respectively; Figure 20A is a cross-sectional view along line AA' in Figure 20 Figure 20B is a cross-sectional view along the BB' line in Figure 20, and Figure 20C is a cross-sectional view along the CC' line in Figure 20;

detailed description

Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. It should be understood, however, that these descriptions are exemplary only, and are not intended to limit the scope of the present disclosure. Also, in the following description, descriptions of well-known structures and techniques are omitted to avoid unnecessarily obscuring the concepts of the present disclosure.

Various structural schematic diagrams according to embodiments of the present disclosure are shown in the accompanying drawings. The figures are not drawn to scale, with certain details exaggerated and possibly omitted for clarity of presentation. The shapes of the various regions and layers shown in the figure, as well as their relative sizes and positional relationships are only exemplary, and may deviate due to manufacturing tolerances or technical limitations in practice, and those skilled in the art will Regions/layers with different shapes, sizes, and relative positions can be additionally designed as needed.

In the context of the present disclosure, when a layer/element is referred to as being "on" another layer/element, the layer/element may be directly on the other layer/element, or there may be intervening layers/elements in between. element. Additionally, if a layer/element is "on" another layer/element in one orientation, the layer/element can be located "below" the other layer/element when the orientation is reversed.

According to an embodiment of the present disclosure, after the fins and the gate stack intersecting the fins (including the gate dielectric layer and the metal gate layer) are formed on the substrate, the metal gate layer may be implanted to adjust its work function. For uniformity, this injection can be carried out in several times. For example, a first oblique implant may be performed using a first type of dopant, wherein the direction of the first oblique implant is toward the sidewall of the metal gate layer on one side of the fin; a second oblique implant may be performed using a first type of dopant. An oblique implant, wherein the direction of the second oblique implant is towards the sidewall of the metal gate layer on the other side of the fin. The direction of the first oblique implantation and the direction of the second oblique implantation may be substantially symmetrical with respect to the direction perpendicular to the substrate surface, and the implantation energy and implantation dose of the two may be substantially the same. In this way, the sidewalls of the metal gate layer on both sides can be substantially uniformly doped. However, the top wall of the metal gate layer on the top surface of the fin receives more doping of the first type. Thus, a vertical implant of a second type complementary to the first type can be performed, the direction of which is substantially perpendicular to the substrate surface. The implant energy and implant dose of the vertical implant may be approximately the same as those of the first and second oblique implants. Therefore, the top wall of the metal gate layer is more compensated, so that substantially uniform doping of the first type can be achieved on the sidewall of the metal gate layer.

The order of the first oblique implant, the second oblique implant, and the vertical implant may be changed. In addition, the implantation direction, implantation energy and implantation dose can also be changed in each implantation.

Thus, such a semiconductor device is obtained, which includes a fin and a gate stack (including a gate dielectric layer and a metal gate layer) intersecting the fin. Compared with the sidewalls of the metal gate layer, the top wall of the metal gate layer may contain higher dopants of the first type and higher dopants of the second type complementary to the first type, so that the overall metal gate layer exhibits substantially uniform doping of the first type.

Accordingly, substantially uniform work function adjustment can be achieved for the metal gate layer, and thus the semiconductor device can have substantially uniformly distributed threshold voltages.

The disclosure can be presented in various forms, some examples of which are described below. In the following description, numerous details are provided for thorough explanation. It is understood, however, that the techniques of the present disclosure may be practiced without some or all of these details.

As shown in Figure 1, a substrate 1002 is provided. The substrate 1002 may be various forms of substrates, such as but not limited to bulk semiconductor material substrates such as bulk Si substrates, semiconductor-on-insulator (SOI) substrates, SiGe substrates, and the like. In the following description, for convenience of description, a bulk Si substrate is used as an example for description.

In the substrate 1002, an n-type well 1002-1 and a p-type well 1002-2 may be formed for subsequent formation of p-type devices and n-type devices therein, respectively. For example, the n-type well 1002 - 1 can be formed by implanting n-type impurities such as P or As in the substrate 1002 , and the p-type well 1002 - 2 can be formed by implanting p-type impurities such as B in the substrate 1002 . Annealing can also be performed after implantation, if desired. Those skilled in the art can think of multiple ways to form the n-type well and the p-type well, which will not be repeated here.

It should be noted here that although the process of forming complementary devices in the n-type well and the p-type well respectively is described in the following description, the present disclosure is not limited thereto. For example, the present disclosure is equally applicable to non-complementary processes. Also, some of the processing below that involves complementary devices may not be necessary in some implementations.

Subsequently, the substrate 1002 may be patterned to form fins. For example, this can be done as follows. Specifically, a patterned photoresist 1004 is formed on the substrate 1002 as designed. Typically, the photoresist 1004 is patterned as a series of parallel, equally spaced lines extending along a first direction (a direction perpendicular to the paper in the figure). Then, as shown in FIG. 3 , using the patterned photoresist 1004 as a mask, the substrate 1002 is selectively etched such as reactive ion etching (RIE), thereby forming a fin structure 1006-1 extending along the first direction. , 1006-2 and 1006-3.

In the case of a complementary process, it is also possible to form an isolation between the n-type region and the p-type region as shown in FIGS. 4 and 5 . Specifically, as shown in FIG. 4 , a photoresist 1008 may be formed on the substrate 1002 and patterned to expose a certain area around the interface between the n-type region and the p-type region. Then, as shown in FIG. 5 , the portion of the substrate (including the fin structure 1006 - 3 ) existing in this region is removed by selective etching such as RIE. An isolation zone is thus formed between the n-type region and the p-type region, which can then be filled with a dielectric. Then, photoresist 1008 may be removed.

It can be seen that in the operation of FIG. 3, the etching step of forming the fin structure enters the wells 1002-1, 1002-2; then, through the operations in FIGS. 4 and 5, the p-type well and the n-type well can be made The contact area between them (that is, the area of the formed pn junction) is smaller. However, the present disclosure is not limited thereto. For example, in a non-complementary process, or in a local area of a single type (p-type or n-type) device, the etching of the substrate 1002 in FIG. 3 may not enter the well; the operations shown in FIGS. 4 and 5 may also It is not necessary.

In the example of FIG. 3 , the fin structure is formed by directly patterning the substrate 1002 . However, the present disclosure is not limited thereto. For example, the fin structure may also be formed by forming (eg, depositing) an additional semiconductor layer on the substrate and patterning the additional semiconductor layer. With sufficient etch selectivity between this additional semiconductor layer and the substrate, the etch can be stopped at the substrate so that the height of the resulting fin structure can be well controlled. Therefore, in the context of the present disclosure, the expression "fins (structures) formed on a substrate" includes forming fins (structures) on a substrate in any suitable manner, and the expression "fins (structures) formed on a substrate " includes any suitable fin (structure) formed on a substrate.

In addition, due to the nature of etching, the shape of the formed trench (between the fin structures) may be tapered from top to bottom. It should be noted that the position, number and layout of the formed fin structures are not limited to the example shown in FIG. 3 .

In the example shown in FIG. 3, at the interface between the n-type well 1002-1 and the p-type well 1002-2, a fin structure 1006-3 is also formed. This fin structure is also removed due to the isolation formation process shown in FIGS. 4 and 5 .

After the fin structure is formed through the above processes, gate stacks can be formed across the fin structure, and a final semiconductor device can be formed.

To isolate the gate stack and the substrate, an isolation layer may be formed on the substrate. For example, the isolation layer can be formed as follows. Specifically, as shown in FIG. 6 , a dielectric material 1010 may be formed (eg, deposited) on the substrate 1002 on which the fin structure is formed. Dielectric material 1010 may include an oxide (eg, silicon oxide) having a thickness sufficient to cover the entire height of fin structures 1006-1 and 1006-2. The deposited dielectric material 1010 may be planarized, such as chemical mechanical polishing (CMP), to have a substantially planar surface. Then, as shown in FIG. 7, the dielectric material 1010 is etched back so that the fin structures 1006-1 and 1006-2 are exposed. The dielectric material after etching back forms the isolation layer 1010'. The exposed portions of fin structures 1006-1 and 1006-2 are then used as the actual fins of the final device. Here, the top surface of the isolation layer 1010' may be approximately equal to or slightly lower than the top surfaces of the well regions 1002-1, 1002-2 (the height difference between them is not shown in the figure).

Optionally, to improve device performance, a punch through stopper (PTS) may be formed in the substrate below the fin. PTSs can be formed separately for n-type devices and p-type devices. For example, photoresist can be used to cover the top of the n-type well 1002-1, and then ion implantation is performed. The implanted ions diffuse through the isolation layer 1010' into the substrate surrounded by the isolation layer 1010'. For the n-type device to be formed in the p-type well 1002-2, p-type impurities such as B, BF ₂ or In can be implanted. The peak concentration of the implant may be, for example, about 1E18-2E19 cm ⁻³ . The photoresist can then be removed. Likewise, the top of the p-type well 1002-2 can be covered with photoresist, and then ion implantation can be performed. For the p-type device to be formed in the n-type well 1002-1, n-type impurities such as As or Sb can be implanted. The peak concentration of the implant may be, for example, about 1E18-2E19 cm ⁻³ . The photoresist can then be removed. Due to the fin's form factor (elongated shape), most of the ions can be scattered out of the fin, which favors a steep doping profile in the depth direction. Annealing may be performed to activate the implanted impurities.

Subsequently, a sacrificial gate stack spanning the fin may be formed on the isolation layer 1010'. For example, this can be done as follows.

Specifically, as shown in FIG. 8 , sacrificial gate dielectric layers 1012 - 1 and 1012 - 2 are formed, for example, by deposition. For example, the sacrificial gate dielectric layers 1012-1 and 1012-2 may include oxide with a thickness of about 0.8-1.5 nm. In the example shown in FIG. 8 , only the “Π”-shaped sacrificial gate dielectric layer is shown. However, the sacrificial gate dielectric layer may also include a portion extending on the top surface of the isolation layer 1010'. A sacrificial gate conductor layer 1014 is then formed, eg, by deposition. For example, the sacrificial gate conductor layer 1014 may include polysilicon. The sacrificial gate conductor layer 1014 may fill the gaps between the fins and may be subjected to a planarization process such as CMP. Afterwards, the sacrificial gate conductor layer 1014 is patterned to form a sacrificial gate stack. As shown in FIGS. 9 and 9A, the sacrificial gate conductor layer 1014 is patterned as stripes 1014-1 and 1014-2 extending in a second direction (horizontal direction in FIG. 9 ) crossing (eg, perpendicular to) the first direction, and thereby intersect with the corresponding fins, respectively. According to another embodiment, the patterned sacrificial gate conductor layers 1014-1 and 1014-2 may also be used as masks to further pattern the sacrificial gate dielectric layers 1012-1 and 1012-2. The source/drain extension region can be implanted by sacrificing the gate stack as a mask; optionally, the halo implant can also be performed. For n-type devices and p-type devices, source/drain extension region implantation and halo implantation can be performed separately (when one device is implanted, a mask such as photoresist can be used to block the other device).

Next, as shown in FIG. 10 , gate spacers 1016 - 1 and 1016 - 2 may be formed on sidewalls of the sacrificial gate stack (in this example, on sacrificial gate conductors 1014 - 1 and 1014 - 2 ). For example, a dielectric layer (for example, a nitride with a thickness of about 5-30 nm) may be formed on the isolation layer, and the dielectric layer may be anisotropically etched to form sidewalls. Those skilled in the art know many ways to form such sidewalls, which will not be repeated here. The height of the sacrificial gate stack (mainly the sacrificial gate conductor) can be set to be at least twice the height of the fin so that substantially no sidewalls are formed on the sidewalls of the fin. Source/drain implantation can be performed by sacrificial gate stack and gate spacer as a mask. For n-type devices and p-type devices, source/drain implantation can be performed separately (when implanting one device, another device can be blocked by a mask such as photoresist). Subsequently, annealing may be performed to activate the implanted ions and thereby form source and drain regions.

After the source/drain regions of the n-type device and the p-type device are respectively formed as described above, a replacement gate process may be performed to replace the sacrificial gate stack to form a real gate stack of the final device. For example, this can be done as follows.

As shown in Figures 11, 11A, 11B and 11C, a dielectric layer 1018 is formed, for example by deposition. The dielectric layer 1018 may comprise oxide, for example. Subsequently, the dielectric layer 1018 is planarized such as CMP. The CMP may stop at the sidewalls 1016-1, 1016-2, exposing the sacrificial gate conductors 1014-1, 1014-2.

Subsequently, as shown in FIGS. 12, 12A, 12B and 12C, the sacrificial gate conductors 1014-1, 1014-2 are selectively removed, for example, by TMAH solution, thereby forming gate grooves 1020 inside the sidewalls 1016-1, 1016-2. -1, 1020-2. According to another example, the sacrificial gate dielectric layers 1012-1 and 1012-2 may be further removed.

Then, as shown in FIGS. 13A, 13B and 13C, in the gate trenches 1020-1, 1020-2, interface layers 1022-1, 1022-2 are formed on the surfaces of the fins 1006-1, 1006-2. For example, the interfacial layers 1022-1, 1022-2 may comprise oxide (eg, formed by thermal oxidation or deposition) with a thickness of about 0.2-1.1 nm. Then, gate dielectric layers 1024-1, 1024-2 and metal gate layers 1026-1, 1026-2 may be formed (eg, deposited) in the gate trenches 1020-1, 1020-2. The gate dielectric layer 1024-1, 1024-2 may include a high-K gate dielectric such as HfO ₂ with a thickness of about 1-5 nm. The metal gate layers 1026-1, 1026-2 may include a metallic gate conductor such as TiN. It should be pointed out here that for n-type devices and p-type devices, the gate dielectric layer/metal gate layer stack may have different configurations (different materials and/or different thicknesses, etc.). In this case, gate stacks may be formed separately for the n-type device and the p-type device. In this example, the gate dielectric layer and the metal gate layer do not completely fill the gate grooves 1020-1, 1020-2.

According to an embodiment of the present disclosure, the work function of the metal gate layers 1026-1, 1026-2, and thus the threshold voltage of the device, may be adjusted by implantation. For example, this can be done as follows.

As shown in FIG. 14, a photoresist 1028-1 may be used to mask the p-type device region. The photoresist 1028-1 preferably extends onto the dielectric layer 1018 between the p-type device region and the n-type device region to ensure complete shading of the p-type device region. Then, a first angled implant can be performed on the n-type device side (in particular, the metal gate layer 1026-2) with the first type of dopant. Here, the so-called "tilt" refers to tilting relative to the substrate surface (ie, deviate from the direction perpendicular to the substrate surface). The direction of the first oblique implantation may be toward the sidewall of the first side (right side in the figure) of the metal gate layer 1026-2 in the second direction (horizontal direction in the figure). Here, the so-called "towards the sidewall" means that relative to vertical implantation (ie, the implantation direction is substantially perpendicular to the substrate surface), the angle formed by the implantation direction and the normal direction of the sidewall is smaller. In the example of FIG. 14, the direction of the first oblique implant is within the plane of the paper (ie, the plane defined by the second direction and the direction perpendicular to the substrate surface). However, the present disclosure is not limited thereto, and the direction of the first oblique injection may deviate from the plane of the paper. For n-type devices, the first obliquely implanted dopant may include one or more of P, As, Sb, La, Er, Dy, Gd, Sc, Yb, and Tb, and the implantation energy may be about 0.2-30keV , the injection dose may be about 1E13-1E15 cm ^-2 .

Next, as shown in FIG. 15, a second oblique implant may be performed using the same type of dopant as in the first oblique implant. The direction of the second oblique implantation may be towards the sidewall of the second side (left side in the figure) opposite to the first side in the second direction (horizontal direction in the figure) of the metal gate layer 1026-2. In the example of Figure 15, the direction of the second oblique injection is in the plane of the paper. However, the present disclosure is not limited thereto, and the direction of the second oblique injection may deviate from the plane of the paper. For n-type devices, the dopant for the second oblique implantation may include one or more of P, As, Sb, La, Er, Dy, Gd, Sc, Yb, and Tb, and the implantation energy may be about 0.2-30keV , the injection dose may be about 1E13-1E15 cm ^-2 .

Preferably, the direction of the first oblique implantation and the direction of the second oblique implantation are substantially symmetrical with respect to the direction perpendicular to the substrate surface, and the implantation energy and implantation dose of the two are substantially the same. In this case, the sidewalls on the left and right sides of the metal gate layer 1026 - 2 receive approximately the same amount of implantation, so that they each have approximately the same (and uniform) doping of the first type (for example, the doping concentration is C).

However, the present disclosure is not limited thereto. The respective directions, implantation energy and implantation dose of the first oblique implantation and the second oblique implantation can be adjusted according to the actual situation (for example, the inclination of the sidewalls on the left and right sides of the metal gate layer 1026-2), as long as the sidewalls can obtain substantially the same Just doping.

On the other hand, the top wall of the metal gate layer 1026-2 is implanted in both the first and second oblique implants, and thus has a relatively high doping of the first type (for example, a doping concentration of about 2C, which This is because the top and side walls are affected approximately equally by the injection in each injection, unless the injection is angled too steeply, which is not common).

Compensation may be performed for the top wall of the metal gate layer 1026-2. Specifically, as shown in FIG. 16 , a third implantation can be performed using a second type of dopant complementary to the first type, and the implantation direction is approximately perpendicular to the substrate surface. Also, the third implant can have about the same implant energy and about the same implant dose as the first and second implants (and thus result in an offset of about -C at the top wall; vertical implants have less effect for the side walls) . For n-type devices, the third implanted dopant may include one or more of In, B, BF ₂ , Ru, W, Mo, Al, Ga, and Pt, the implantation energy may be about 0.2-30keV, and the implantation The dosage may be about 1E13-1E15 cm ^-2 . In this way, the first type doping at the top wall of the metal gate layer 1026-2 (the oblique line from the upper right to the lower left in the figure) is reduced so that it is different from the first type doping at the side wall of the metal gate layer 1026-2. The type doping remains approximately the same (eg, 2C+(-C)=C). Thus, substantially uniform doping of the first type at the top and sidewalls of the metal gate layer 1026-2 is achieved.

It should be noted here that the top wall and side wall of the metal gate layer 1026-2 mentioned here refer to the top wall and side wall of the metal gate layer 1026-2 located on the fin 1006-2. However, other parts of the metal gate layer 1026-2 extending in the gate groove 1020-2 (for example, the part located on the sidewall 1016-2) do not directly affect the threshold voltage of the device, so the doping concentration in these parts is This is not of special concern. In addition, the dopants used in the first and second oblique implants may be exchanged with the dopants used in the third implant. Specifically, a second type of dopant, such as one or more of In, B, BF ₂ , Ru, W, Mo, Al, Ga, and Pt, may be used in the first and second oblique implants. The first type of dopant, such as one or more of P, As, Sb, La, Er, Dy, Gd, Sc, Yb and Tb, may be used in the third implantation.

After uniform doping of the top and sidewalls of the metal gate layer 1026-2 is achieved, the photoresist 1028-1 may be removed. Next, similar operations can be performed for p-type devices.

Specifically, as shown in FIG. 17, a photoresist 1028-2 may be used to shield the n-type device region. The photoresist 1028-2 preferably extends over the dielectric layer 1018 between the p-type device region and the n-type device region to ensure complete shading of the n-type device region. Then, a first angled implant can be performed on the p-type device side (in particular, the metal gate layer 1026-1) with a second type of dopant. The direction of the first oblique implantation may be toward the sidewall of the first side (right side in the figure) of the metal gate layer 1026-1 in the second direction (horizontal direction in the figure). In the example of Figure 17, the direction of the first oblique injection is in the plane of the paper. However, the present disclosure is not limited thereto, and the direction of the first oblique injection may deviate from the plane of the paper. For a p-type device, the dopant for the first oblique implantation may include one or more of In, B, BF ₂ , Ru, W, Mo, Al, Ga, and Pt, and the implantation energy may be about 0.2-30keV, The injection dose may be about 1E13-1E15 cm ⁻² .

Next, as shown in FIG. 18, a second oblique implant may be performed using the same type of dopant as in the first oblique implant. The direction of the second oblique implantation may be towards the sidewall of the second side (left side in the figure) opposite to the first side in the second direction (horizontal direction in the figure) of the metal gate layer 1026-1. In the example of Figure 18, the direction of the second oblique injection is in the plane of the paper. However, the present disclosure is not limited thereto, and the direction of the second oblique injection may deviate from the plane of the paper. For a p-type device, the dopant for the second oblique implantation may include one or more of In, B, BF ₂ , Ru, W, Mo, Al, Ga, and Pt, and the implantation energy may be about 0.2-30keV, The injection dose may be about 1E13-1E15 cm ⁻² .

Preferably, the direction of the first oblique implantation and the direction of the second oblique implantation are substantially symmetrical with respect to the direction perpendicular to the substrate surface, and the implantation energy and implantation dose of the two are substantially the same. In this case, the sidewalls on the left and right sides of the metal gate layer 1026 - 1 receive approximately the same amount of implantation, so that they each have approximately the same (and uniform) doping of the second type.

However, the present disclosure is not limited thereto. The respective directions, implantation energy and implantation dose of the first oblique implantation and the second oblique implantation can be adjusted according to the actual situation (for example, the inclination of the sidewalls on the left and right sides of the metal gate layer 1026-1), as long as the sidewalls can obtain roughly the same Just doping.

On the other hand, the top wall of the metal gate layer 1026-1 is implanted in both the first and second oblique implants, and thus has relatively higher doping of the second type.

Compensation may be performed for the top wall of the metal gate layer 1026-1. Specifically, as shown in FIG. 19 , the third implantation can be performed using the first type of dopant complementary to the second type, and the implantation direction is approximately perpendicular to the substrate surface. Additionally, the third implant may have approximately the same implant energy and approximately the same implant dose as the first and second implants. For a p-type device, the third implanted dopant may include one or more of P, As, Sb, La, Er, Dy, Gd, Sc, Yb and Tb, and the implantation energy may be about 0.2-30keV, The injection dose may be about 1E13-1E15 cm ⁻² . In this way, the second type doping at the top wall of the metal gate layer 1026-1 (the oblique dashed line from the upper left to the lower right in the figure) is reduced, so that it is different from the first doping at the top wall of the metal gate layer 1026-1. The two-type doping remains about the same. Thus, substantially uniform doping of the second type at the top and sidewalls of the metal gate layer 1026-1 is achieved.

In this way, uniform second-type doping to the top and side walls of the metal gate layer 1026-1 is achieved. Then, photoresist 1028-2 may be removed.

Likewise, the dopants used in the first and second angled implants can be swapped with the dopants used in the third implant. Specifically, the first type of dopant, such as one or more of P, As, Sb, La, Er, Dy, Gd, Sc, Yb and Tb, can be used in the first and second oblique implantation, A second type of dopant, such as one or more of _In , B, BF2, Ru, W, Mo, Al, Ga, and Pt, may be used in the third implant.

It should be pointed out here that, in the case of the complementary process in this example, n-type devices and p-type devices are processed separately. However, the present disclosure is not limited thereto. For example, in non-complementary processes, such masking may not be performed. In addition, in this example, the p-type device region is shielded first, and the n-type device region is treated. However, the present disclosure is not limited thereto. The order of processing the n-type device region and the p-type device region may be swapped. Moreover, for the same device, the order of each injection can also be changed.

After the work function of the metal gate layer is uniformly adjusted as described above, subsequent fabrication of the device can be completed. For example, as shown in FIGS. 20 , 20A, 20B and 20C, gate electrode layers 1030-1, 1030-2 may be further formed in the gate grooves 1020-1, 1020-2. For example, the gate electrode layer may include W or TiAl, and its thickness is sufficient to fill the gate trenches 1020-1, 1020-2. Then, a planarization process such as CMP may be performed to remove portions of the gate dielectric layer, the metal gate layer and the gate electrode layer outside the gate groove. The planarization process may terminate at the dielectric layer 1018 . Next, an interlayer dielectric layer may be further deposited and a contact portion (not shown) formed therein.

In this way, the semiconductor device according to this embodiment is obtained. As shown in FIGS. 20, 20A, 20B, and 20C, the semiconductor device includes fins 1006-1/1006-2 formed on a substrate 1002 extending in a first direction (vertical direction in FIG. The gate stack extending along the second direction (horizontal direction in FIG. 20 ) is formed on the top, and the gate stack includes gate dielectric layers 1024-1/1024-2 and metal gate layers 1026-1/1026-2 stacked in sequence. With respect to the sidewalls on opposite sides of the metal gate layer in the second direction (the left and right sides in FIG. 20A ), the top wall of the metal gate layer contains higher dopants of the first type and higher and first type dopants. The dopant of the second type is complementary in type, so that the overall metal gate layer exhibits substantially uniform doping of the first type. In the above description, the cases of the n-type device and the p-type device are combined, and they are separated from each other by "/".

Furthermore, in the above examples, the description is made for the replacement gate process. However, the present disclosure is not limited thereto. For example, the present disclosure is equally applicable to gate-first processes.

In the above description, technical details such as patterning and etching of each layer are not described in detail. However, those skilled in the art should understand that various technical means can be used to form layers, regions, etc. of desired shapes. In addition, in order to form the same structure, those skilled in the art can also design a method that is not exactly the same as the method described above. In addition, although the various embodiments are described above separately, this does not mean that the measures in the various embodiments cannot be advantageously used in combination.

The embodiments of the present disclosure have been described above. However, these examples are for illustrative purposes only and are not intended to limit the scope of the present disclosure. The scope of the present disclosure is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of the present disclosure, and these substitutions and modifications should all fall within the scope of the present disclosure.

Claims (10)

1. a method of manufacturing semiconductor devices, comprising:

On substrate, form the fin extending along first direction;

On substrate, form along the grid of the second direction extension intersecting with first direction stacking, wherein gridThe stacking gate dielectric layer and the metal gate layer that stack gradually of comprising;

Utilize the adulterant of the first kind to carry out the first inclination injection, wherein the first side that tilts to injectTo the sidewall in the first side at fin towards metal gate layer;

Utilize the adulterant of the first kind to carry out the second inclination injection, wherein the second side that tilts to injectTo the sidewall in second side contrary with the first side at fin towards metal gate layer;

Utilize with the adulterant of the Second Type of first kind complementation and carry out the 3rd injection, wherein the 3rdThe direction of injecting is approximately perpendicular to the surface of substrate.

2. method according to claim 1, wherein, the first direction and second that tilts to injectThe direction that tilts to inject is roughly symmetrical about the direction perpendicular to substrate surface, and both injection energyAmount and implantation dosage are roughly the same.

3. method according to claim 1, wherein, the 3rd injects and the first and second injectionsThere is roughly the same Implantation Energy and roughly the same implantation dosage.

4. method according to claim 1, wherein,

The adulterant of the first kind comprise P, As, Sb, La, Er, Dy, Gd, Sc, Yb andOne or more in Tb, the adulterant of Second Type comprises In, B, BF₂、Ru、W、Mo、One or more in Al, Ga and Pt; Or

First kind adulterant comprises In, B, BF₂, in Ru, W, Mo, Al, Ga and PtOne or more, the adulterant of Second Type comprise P, As, Sb, La, Er, Dy, Gd,One or more in Sc, Yb and Tb.

5. method according to claim 1, wherein, the first inclination is injected, the second inclination noteEntering with the 3rd Implantation Energy injecting is separately about 0.2-30keV, and implantation dosage is about 1E13-1E15cm^-2。

6. method according to claim 1, wherein, forms that grid are stacking comprises:

On substrate, form the sacrificial gate of extending along second direction stacking, sacrificial gate is stacking to be comprised successivelyStacking sacrificial gate dielectric layer and sacrificial gate conductor layer;

On the stacking sidewall of sacrificial gate, form grid side wall;

On substrate, form dielectric layer, and carry out planarization, stacking to expose sacrificial gate;

Selective removal sacrificial gate is stacking, thereby forms grid groove in grid side wall inner side;

In grid groove, form gate dielectric layer and metal gate layer.

7. method according to claim 6, also comprises:

In the grid groove that is formed with gate dielectric layer and metal gate layer, further form gate electrode layer.

8. a semiconductor devices, comprising:

The fin extending along first direction forming on substrate;

The grid that extend along the second direction of intersecting with first direction that form on substrate are stacking, whereinThe stacking gate dielectric layer and the metal gate layer that stack gradually of comprising of grid,

Wherein, the sidewall with respect to metal gate layer on the relative both sides of fin, metal gate layer is at finThe adulterant that roof on end face comprises the higher first kind and higher and first kind complementationThe adulterant of Second Type, mix thereby metal gate layer presents roughly the first kind uniformly on the wholeAssorted.

9. semiconductor devices according to claim 8, wherein,

First kind adulterant comprises P, As, Sb, La, Er, Dy, Gd, Sc, Yb and TbIn one or more, the adulterant of Second Type comprises In, B, BF₂、Ru、W、Mo、One or more in Al, Ga and Pt; Or

First kind adulterant comprises In, B, BF₂, in Ru, W, Mo, Al, Ga and PtOne or more, the adulterant of Second Type comprise P, As, Sb, La, Er, Dy, Gd,One or more in Sc, Yb and Tb.

10. semiconductor devices according to claim 8, wherein, metal gate layer comprises TiN.