CN106409960A - Solar cell and manufacturing method thereof - Google Patents

Abstract

A solar cell and a manufacturing method thereof are disclosed. A solar cell according to the present invention includes: a substrate on which a unit solar cell area is arranged, and the unit solar cell area is composed of a cell area and a wiring area; a first semiconductor layer is formed on the substrate, and is formed on the wiring area of the substrate A first trench is formed on the first semiconductor layer; a second semiconductor layer is formed on the first semiconductor layer, and a second trench is formed on the wiring region of the substrate to expose a part of the first semiconductor layer; a third semiconductor layer is formed on the On the second semiconductor layer, and form a third trench on the wiring area of the substrate to expose a part of the second semiconductor layer; the side wall insulating layer is embedded in the first trench to make the battery cell area of the substrate The first, second and third semiconductor layers are insulated from each other; the electrode layer is formed on the third semiconductor layer and connected to the first semiconductor layer through the second groove.

Description

Solar cell and manufacturing method thereof

technical field

The present invention relates to solar cells and methods for their manufacture. More particularly, the present invention relates to a solar cell capable of simplifying a patterning process and a series connection structure and effectively preventing electrical interference between battery cells and a method of manufacturing the same.

Background technique

Since the photoelectric conversion efficiency of conventional thin-film solar cells is approximately less than 10%, there are many difficulties in practical commercialization. In order to solve the problem, a technique of electrically connecting a plurality of photoelectric elements in series to realize excellent photoelectric conversion efficiency has been developed.

In this series-connected solar cell, multiple photoelectric elements arranged horizontally are connected in series through electrodes (wiring) to obtain the required power.

However, in order to manufacture solar cells of the conventional tandem type, in order to perform at least three etching (patterning) processes, the process of repeatedly inverting the substrate is performed, so the process and equipment are complicated, and physical interference is caused in the process of inverting the substrate , which has the problem of generating bad.

Moreover, conventional solar cells in series have a structure in which solar cells composed of stacked photoelectric elements between the lower electrode and the upper electrode are connected in series. Therefore, the structure is complicated, and the electrical interference between the cells has reduced The problem of photoelectric conversion efficiency.

Contents of the invention

problem to be solved

Therefore, the present invention was made in order to solve the problems of the prior art as described above, and an object of the present invention is to provide a solar cell capable of performing multiple etching steps on the front surface of a substrate and a method of manufacturing the same.

In addition, another object of the present invention is to provide a solar cell that does not require a separate lower electrode when connected in series, and a method for manufacturing the same.

In addition, another object of the present invention is to provide a solar cell including a sidewall insulating layer for electrically separating battery cells and a manufacturing method thereof.

Technical solution to the problem

A solar cell according to the present invention includes: a substrate on which a unit solar cell region is arranged, the unit solar cell region consisting of a cell region and a wiring region; a first semiconductor layer formed on the substrate, and on the substrate. A first trench is formed on the wiring region of the substrate; a second semiconductor layer is formed on the first semiconductor layer, and a second trench is formed on the wiring region of the substrate to expose A part of the first semiconductor layer; a third semiconductor layer formed on the second semiconductor layer, and forming a third groove on the wiring region of the substrate to expose the second semiconductor layer A part of a sidewall insulating layer, embedded in the first trench, to insulate the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer on the battery cell area of the substrate from each other; The electrode layer is formed on the third semiconductor layer and connected to the first semiconductor layer through the second trench.

At this time, an anti-reflection layer may also be formed between the substrate and the first semiconductor layer.

The anti-reflection layer may be silicon oxide (SiO _x ) or silicon nitride (SiN _x ).

The first semiconductor layer, the second semiconductor layer and the third semiconductor layer may be n, i, p or p, i, n.

In addition, the object of the present invention can be achieved by a method for manufacturing a solar cell, which includes the following steps: step (a), providing a substrate on which unit solar cell areas are arranged, and the unit solar cell areas are composed of battery cell areas and wiring Regional composition; step (b), sequentially forming a first semiconductor layer, a second semiconductor layer, and a third semiconductor layer on the substrate; step (c), a first etching process: etching a first semiconductor layer on the wiring region a semiconductor layer, a second semiconductor layer, and a third semiconductor layer to form a first trench separated from other adjacent unit solar cell regions; step (d), burying the first trench to form sidewall insulation layer; step (e), a second etching process: forming a first mask layer on the third semiconductor layer and the sidewall insulating layer, and using the first mask layer on the wiring region Etching the third semiconductor layer and the second semiconductor layer simultaneously to form a second trench exposing a part of the first semiconductor layer; step (f), removing the first mask layer, and Forming an electrode layer on the third semiconductor layer and the sidewall insulating layer; step (g), a third etching process: forming a second mask layer on the electrode layer, and on the wiring region, Etching the electrode layer and the third semiconductor layer simultaneously by using the second mask layer to form a third groove exposing a part of the second semiconductor layer; step (h), removing the second mask film layer.

At this time, the step of forming an anti-reflection layer between the substrate and the first semiconductor layer may also be included.

The anti-reflection layer may be formed of silicon oxide (SiO _x ) or silicon nitride (SiN _x ).

The first groove may be etched by a laser scribing method.

The second trench and the third trench may be etched by wet etching.

The first, second, and third etching processes may be performed on the upper portion of the substrate.

The electrode layer may be formed of transparent conductive material or metal material or their laminated structure.

The first semiconductor layer, the second semiconductor layer, and the third semiconductor layer can be formed as n, i, p or p, i, n.

Invention effect

According to the present invention, multiple etching processes can be performed on the front of the substrate, so there is no need to invert (turn over) the substrate, the process and equipment can be simplified, and defective products can be prevented.

In addition, according to the present invention, a separate lower electrode is not required for series connection, and the effect of simplifying the structure and process can be obtained.

Furthermore, according to the present invention, the photoelectric conversion efficiency can be improved by including a side wall insulating layer that can be used to prevent electrical interference between battery cells.

Description of drawings

1 to 9 are schematic diagrams sequentially showing a manufacturing process of a solar cell according to an embodiment of the present invention.

10 and 11 are schematic diagrams showing a detailed configuration of a photoelectric element unit according to an embodiment of the present invention.

reference sign

100: Substrate

200: anti-reflection layer

310: first semiconductor layer (first amorphous silicon layer)

311: first polysilicon layer

320: second semiconductor layer (second amorphous silicon layer)

321: second polysilicon layer

330: third semiconductor layer (third amorphous silicon layer)

331: the third polysilicon layer

400: sidewall insulation

500: electrode layer

detailed description

The detailed description of the present invention to be described later refers to the accompanying drawings, which illustrate specific embodiments in which the present invention can be carried out. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. It should be understood that the various embodiments of the invention differ from each other, but are not mutually exclusive. For example, the specific shape, structure and characteristics of an embodiment described herein can be implemented by other embodiments without departing from the spirit and scope of the present invention. In addition, it should be understood that the positions and arrangements of individual components in the respective disclosed embodiments can be changed without departing from the spirit and scope of the present invention. Therefore, the following detailed description is not intended to be limiting, and it is accurately stated that the protection scope of the present invention is based only on the contents described in the claims, and includes all equivalent scopes to the claims. In the drawings, similar reference numerals refer to the same or similar functions in various respects, and the length, area, thickness, etc., and their shapes may also be exaggerated for easy understanding.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings, so that those skilled in the art to which the present invention pertains can easily implement the present invention.

Preferred Embodiments of the Invention

In this specification, the battery cell region A means that the photovoltaic element (including the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer) is located between the electrodes (between the first semiconductor layer and the electrode layer) so that the solar cell is substantially formed. area on the substrate for photoelectric conversion.

In addition, in this specification, the wiring region B refers to a region on the substrate that is located between the battery cell regions A and separates the battery cells from each other while performing the function of electrical connection (for example, series connection). A dead region of photoelectric conversion of the solar cell does not occur.

As described above, one battery cell region A and one wiring region B are aggregated to form unit solar cell regions A and B, and on such unit solar cell regions A and B, formation can be performed through the manufacturing process according to the embodiment of the present invention. A unit solar cell with photoelectric conversion and wiring functions.

As an example, on the substrate, a plurality of unit solar cell regions A, B can be arranged in the direction of rows and columns, and in any row, the nth (n is a natural number) unit solar cell region can include battery cell regions A _n and configuration Line area B _n .

At this time, in one side region adjacent to the nth unit solar cell region A _n , B _n , the n+1th unit solar cell region (battery cell region A _n+1 and wiring region B _n+1 ), the n+2th unit solar cell region (battery cell region A _n+2 and wiring region B _n+2 ) sequentially arrange the unit solar cell regions.

In addition, in the other side region adjacent to the n-th unit solar cell region, the n-1th unit solar cell region (battery cell region A _n-1 and wiring region B _n-1 ), the n-th Two unit solar cell regions (battery cell region A _n-2 and wiring region B _n-2 ) are sequentially arranged up to the first unit solar cell region.

In the following examples, for convenience of description, a cross section of the n-th unit solar cell region (battery cell region A _n and wiring region B _n ) among the plurality of unit solar cell regions on the substrate is shown as the center. Be explained.

1 to 9 are schematic diagrams sequentially showing a manufacturing process of a solar cell according to an embodiment of the present invention.

First, referring to FIG. 1 , a substrate 100 in which unit solar cell regions A and B composed of a cell region A and a wiring region B are arranged may be provided. The material of the substrate 100 may be a transparent glass substrate, but the present invention is not limited thereto. For example, the substrate 100 may be made of transparent materials such as glass and plastic or opaque materials such as silicon and metal (eg, SUS (Stainless Steel)) according to the direction in which light is received.

Next, texturing may be performed on the surface of the substrate 100 . The texture treatment of the present invention is to prevent the phenomenon that the light incident on the surface of the solar cell substrate is reflected to cause optical loss and reduce its characteristics. That is, roughening the substrate surface means forming a concavo-convex pattern (not shown) on the substrate surface. For example, if the surface of the substrate is roughened by texture treatment, the light once reflected on the surface can be reflected again toward the solar cell, thereby reducing light loss and increasing the amount of light captured, thereby improving the photoelectric conversion efficiency of the solar cell.

At this time, as a representative texture processing method, a sandblasting method can be used. The blasting treatment in the present invention includes dry blasting treatment in which etching particles are sprayed with compressed air to perform etching, and wet blasting treatment in which etching is performed by jetting liquid and etching particles together. On the other hand, as the etching particles used in the blasting treatment of the present invention, particles such as sand, small metals, etc. that form unevenness on the substrate by physical impact can be used without limitation.

Next, an anti-reflection layer 200 may be formed on the substrate 100 . The anti-reflection layer 200 functions to prevent sunlight incident on the substrate 100 from being absorbed by a photovoltaic element (semiconductor layer) formed later and directly reflected to the outside, thereby preventing a reduction in the efficiency of the solar cell. The material of the anti-reflection layer may be silicon oxide (SiO _x ), silicon nitride (SiN _x ), but not limited thereto.

The formation methods of the anti-reflection layer include low pressure chemical vapor deposition (LPCVD: Low Pressure Chemical Vapor Deposition) and plasma chemical vapor deposition (PECVD: Plasma Enhanced Chemical Vapor Deposition).

Next, the first semiconductor layer 310 , the second conductor layer 320 , and the third semiconductor layer 330 are sequentially formed on the upper surface of the antireflection layer 200 . Next, the first, second, and third semiconductor layers 300 : 310 , 320 , and 330 can function as photoelectric elements that convert light energy into electrical energy.

Such first, second, and third semiconductor layers 300 : 310 , 320 , and 330 may be commonly used silicon (Si), but are not limited thereto, and known semiconductor materials may be used without limitation. As an example, p-type, i-type, and n-type semiconductor layers 300 may be sequentially formed.

The formation method of the semiconductor layer 300 may include chemical vapor deposition methods such as PECVD or LPCVD, and the semiconductor layer 300 may perform the function of a photoelectric element that receives light from the battery cell region A through a subsequent process to generate electricity. Specifically, it can be understood by referring to the following detailed description with reference to FIG. 10 and FIG. 11 .

Next, referring to FIG. 2, on the wiring region B on the substrate 100, first etch (that is, etch P1 width) part of the first, second, and third semiconductor layers 300: 310, 320, and 330 to form the first Trench T1.

More specifically, the plurality of unit solar cell regions A and B composed of the cell region A and the wiring region B can be separated from each other by the first etching step P1. For example, the nth unit solar cell area (cell area A _n and wiring area B _n ) can be connected to the n+1th unit solar cell area (battery cell area A _n+1 and wiring area B n ) in the adjacent side area. Region _Bn+1 ) is physically and electrically separated from the n-1th unit solar cell region (battery cell region A _n-1 and wiring region _Bn-1 ) in the other region.

Such a method of the first etching step P1 may use a laser scribing method using a laser, for example, a laser with an ultraviolet (ultraviolet) or green (green) wavelength.

However, the present invention is not limited thereto, and etching methods including known photolithography methods may be used without limitation. When using the laser scribing method, the irradiation direction of the laser light can be irradiated on the upper side or the lower side of the substrate 100, but in the present invention, it is preferable to irradiate from the upper side of the substrate 100 as shown in the figure so that the laser can be irradiated on the front side. Carry out the composition process.

Next, referring to FIG. 3 , on the third semiconductor layer 330 , an insulating substance is embedded in the first trench T1 to form a sidewall insulating layer 400 . Such a sidewall insulating layer 400 can insulate the first semiconductor layer 310 , the second semiconductor layer 320 , the third semiconductor layer, and 330 of the battery cell region A from each other.

The material for forming the sidewall insulating layer 400 may be any one of silicon oxide (SiO _x ), silicon nitride (SiN _x ), polymer, resin (resin) or a mixture of at least two of them. Various known materials can be used. The formation method of the side wall insulating layer 400 can use the inkjet printing method (ink jet printing) that ejects predetermined ink with the head that consists of nozzles, but is not limited to this, can use known photolithography method, screen printing method without limitation. Screen printing, roller coating, etc.

Since such a side wall insulating layer 400 is embedded in a trench forming a certain space, the phenomenon of diffusion to the side is reduced, and the entire width can be minimized. That is, the conventional side wall insulating layer is formed by ink jet printing by ejecting a predetermined ink, which causes ink to spread unnecessarily to the side, thereby increasing the overall width. However, the side wall insulating layer according to the present invention The layer 400 can prevent these phenomena by the first trench T1, so that the width can be relatively reduced.

Therefore, in the entire substrate 100, the area ratio of the cell region A that receives light and generates electricity is relatively increased, so that a solar cell having excellent photoelectric conversion efficiency may be realized.

Next, referring to FIG. 4 , a first mask layer 10 may be formed on the substrate 100 including the third semiconductor layer 330 . Such a first mask layer 10 may be a resin, for example, a known photoresist used in a photolithography process may be used.

Next, a part of the first mask layer 10 is patterned on the wiring region B on the substrate 100 to form the first mask layer 10 having a predetermined pattern as shown in the figure. The patterning of the first mask layer 10 may be laser patterning or inkjet patterning, but is not limited thereto, and various known patterning methods may be used.

Then, referring to FIG. 5 , on the wiring region B, using the first mask layer 10 having a predetermined pattern, the second semiconductor layer 320 and the third semiconductor layer 330 are etched (that is, the width of P2 is etched) to form an exposed A part of the second trench T2 of the first semiconductor layer 310 .

As the method of the second etching step P2, a wet etching method with excellent etching selectivity in which only the first semiconductor layer 310 is exposed without damage by using the first mask layer 10 of the present invention made of resin (resin), can be used. However, the present invention is not limited thereto, and known etching methods including dry etching methods may be used without limitation.

Next, a process of removing the first mask layer 10 may be performed, and known resin stripping process techniques may be used without limitation.

Next, referring to FIG. 6 , an electrode layer 500 may be formed on the substrate 100 including the third semiconductor layer 300 and the sidewall insulating layer 400 . A material of such an electrode layer 500 may use a conductive material without limitation. For example, TCO can be used for the transparent conductive layer, which can be AZO (ZnO:Al), ITO (Indium-Tin-Oxide), GZO (ZnO:Ga), BZO (ZnO:B) and FTO (SnO ₂ :F) of any kind. In addition, for the opaque conductive layer, ordinary metal materials can be used, such as aluminum (Al), silver (Ag), gold (Au), copper (Cu), zinc (Zn), titanium (Ti) and other metals and their alloys .

In addition, the electrode layer 500 may be formed as a stacked structure of a transparent conductive layer and a metal layer, for example, may be BZO(ZnO:B)/Al.

The formation method of the electrode layer 500 includes physical vapor deposition (PVD: Physical Vapor Deposition) such as thermal evaporation (Thermal Evaporation), electron beam evaporation (E-beam Evaporation), sputtering (sputtering), LPCVD, PECVD, metal A chemical vapor deposition method (CVD: Chemical Vapor Deposition) such as an organic chemical vapor deposition method (MOCVD: Metal Organic Chemical Vapor Deposition).

On the other hand, the electrode layer 500 can function as an upper electrode in the battery cell region A by utilizing its conductivity.

Next, referring to FIG. 7 , the second mask layer 20 may be formed on the electrode layer 500 . Such a second mask layer 20 can be patterned to have a predetermined pattern similarly to the first mask layer 10 described in detail with reference to FIG. 5 .

Next, referring to FIG. 8 , on the wiring region B, the electrode layer 500 and the third semiconductor layer 330 can be etched thirdly (that is, the width of P3 is etched) with the second mask layer 20 having a predetermined pattern to form an exposed A part of the third trench T3 of the second semiconductor layer 320 .

In the method of the third etching step P3, a wet etching method with excellent etching selectivity in which only the second semiconductor layer 320 is exposed without damage by using the second mask layer 20 of the present invention made of resin can be used. However, the present invention is not limited thereto, and known etching methods including dry etching methods may be used without limitation.

Finally, referring to FIG. 9 , a process of removing the second mask layer 20 may be performed, and known resin stripping process techniques may be used without limitation.

Therefore, the electrode layer 500 can implement solar cells in a series manner in which the first semiconductor layer 310 exposed through the second trench T2 is electrically connected to the third semiconductor layer 330 on other adjacent unit solar cell regions.

As an example, one end of the electrode layer 500 may be connected to the first semiconductor layer 310 through the second trench T2 on the wiring region B _n of the n-th unit solar cell regions A _n and B _n . In addition, the other end of the electrode layer 500 may cover the side wall insulating layer 400 and at the same time be connected to the cell area A n-1 of the adjacent n-1th unit solar cell area A _n-1 and B _{n- 1} . The upper part of the third semiconductor layer 330 is connected.

Thus, the n-th unit solar cell A _n , B _n can be connected in series with the n-1 th unit solar cell A _n-1 , B _n-1 adjacent to one side area. The n+1th unit solar cells A _n+1 and B _n+1 adjacent to the other side area are connected in series, so as to realize solar cells in series.

As described above, the solar cell of the present invention can sequentially perform laser scribing and etching processes (eg, wet etching) on the upper portion of the substrate 100 , thereby reducing processes and process equipment.

In addition, series connection can be realized without another lower electrode, and the effects of simplifying the structure and shortening the process can be obtained.

In addition, a solar cell having excellent photoelectric conversion efficiency is realized by including a side wall insulating layer that electrically separates battery cells.

Structure of the photoelectric element section

10 and 11 are schematic diagrams showing a detailed configuration of a photoelectric element unit according to an embodiment of the present invention.

First, referring to FIG. 10 , as an example, the photoelectric element unit 300 may be formed of three amorphous silicon layers 310 , 320 , and 330 . More specifically, a first amorphous silicon layer 310 may be formed on the substrate 100, then a second amorphous silicon layer 320 may be formed on the first amorphous silicon layer 310, and then a second amorphous silicon layer may be formed on the second amorphous silicon layer The third amorphous silicon layer 330 is formed on the 320 to form a photoelectric element. In this case, the first, second and third amorphous silicon layers 310, 320 and 330 can be formed by chemical vapor deposition methods such as PECVD or LPCVD.

Next, referring to FIG. 11 , as an example, the photoelectric element unit 300 may be formed of three polysilicon layers 311 , 321 , and 331 . More specifically, a first polysilicon layer 311 may be formed on the substrate 100, then a second polysilicon layer 321 may be formed on the first polysilicon layer 311, and then a second polysilicon layer 321 may be formed on the second polysilicon layer The third polysilicon layer 331 is formed on the 321 to form a photoelectric element.

At this time, as a method for forming the first, second, and third polysilicon layers 311, 321, and 331, heat treatment may be performed on the first, second, and third amorphous silicon layers 310, 320, and 330 shown in FIG. and the process of crystallization. That is, the first amorphous silicon layer 310 can be crystallized into the first polysilicon layer 311, the second amorphous silicon layer 320 can be crystallized into the second polysilicon layer 321, and the third amorphous silicon layer 330 can be crystallized. is the third polysilicon layer 331 .

At this time, SPC (Solid Phase Crystallization: solid phase crystallization), ELA (Excimer Laser Annealing: excimer laser annealing) can be used to crystallize the first, second, and third amorphous silicon layers 310, 320, and 330. , SLS (Sequential Lateral Solidification: Sequential Lateral Crystallization), MIC (Metal Induced Crystallization: Metal Induced Crystallization), and MILC (Metal Induced Lateral Crystallization: Metal Induced Lateral Crystallization). The crystallization method of amorphous silicon is a known technique, and a detailed description thereof will be omitted in this specification.

In the above description, the case where the first, second, and third amorphous silicon layers 310 , 320 , and 330 are formed and crystallized simultaneously is described, but the present invention is not limited thereto. For example, each amorphous silicon layer can be crystallized separately, or two amorphous silicon layers can be crystallized simultaneously, and the remaining amorphous silicon layer can be crystallized separately.

As a result, the first amorphous silicon layer 310, the second amorphous silicon layer 320, the third amorphous silicon layer, 330 or the first polysilicon layer 311, the second polysilicon layer 321, The photoelectric element formed by the third polysilicon layer 331 . However, the present invention is not limited thereto, and a photovoltaic element made of a microcrystalline silicon layer may be used as needed. In addition, as the material of the light absorbing layer of the solar cell, known materials other than silicon can be used without limitation.

Such a photoelectric element may be a p-i-n diode structure in which p-type, i-type, and n-type silicon layers are sequentially stacked. The above-mentioned p-type, i-type, and n-type silicon layers can generate electricity by receiving photovoltaic power generated by light. Here, i-type means intrinsic (intrinsic) not doped with impurities. In addition, for n-type or p-type doping, it is preferable to dope impurities in situ when forming the amorphous silicon layer. In the case of p-type doping, boron (B) is generally used as an impurity, and in the case of n-type doping, phosphorus (P) or arsenic (As) is generally used as an impurity. Technology.

On the other hand, in addition to p, i, n types, photoelectric elements can also be made of p+, i, n+ type, n, i, p type (especially n+, i, p+), p, p, n type (especially p+, p-, n+), p, n, n-type (especially p+, n-, n+) or n, n, p-type (especially n+, n-, p+) silicon layer formation. Wherein, the meanings of + and - represent the relative difference of doping concentration, and + has a higher concentration of doping concentration than -. For example, n+ means a higher concentration of doping than n-. The case where + or - is not indicated means that the doping concentration is not particularly limited. In addition, the semiconductor layer positioned between p-type and n-type functions as a light-absorbing layer (for example, i-type).

On the other hand, in order to improve the various characteristics of the first polysilicon layer 311, the second polysilicon layer 321, and the third polysilicon layer 331, additional heat treatment can be performed on these polysilicon layers at a specified temperature to eliminate A defect removal process of defects, or a hydrogen passivation (hydrogen passivation) process of removing dangling bonds present in the polysilicon layer by subjecting these polysilicon layers to hydrogen plasma treatment.

As another example, the photoelectric element unit 300 may have a stacked structure (ie, a tandem structure) in which one photoelectric element is further formed on another photoelectric element. That is, the photoelectric element part may have a structure in which a polycrystalline photoelectric element layer and an amorphous photoelectric element layer are stacked, a structure in which a microcrystalline photoelectric element layer and an amorphous photoelectric element layer are stacked, etc., but it should be understood that it includes stacking two or more layers. Structure.

Referring to Fig. 9, it is applied to the present invention as follows. When the photoelectric elements arranged in the lower part are referred to as the first, second, and third semiconductor layers, and the photoelectric elements arranged in the upper part are referred to as the fourth, fifth, and sixth semiconductor layers, in FIG. 9, reference numerals 310 The illustrated semiconductor layer can be configured with the first semiconductor layer, the semiconductor layer illustrated with reference numeral 320 can be configured with the second, third, fourth, and fifth semiconductor layers, and the semiconductor layer illustrated with reference numeral 330 can be configured with The sixth semiconductor layer, thereby forming a series structure.

On the other hand, in the photoelectric element unit 300 having a series structure, a connecting layer (not shown) as a transparent conductor is additionally formed between one photoelectric element and the other photoelectric element. The connecting layer forms an ohmic contact between stacked photovoltaic elements (for example, between a polycrystalline photovoltaic element and an amorphous photovoltaic element), thereby improving the photoelectric conversion efficiency of the solar cell. Preferably, the connection layer is AZO (ZnO:Al) in which a small amount of Al is added to ZnO, but it is not limited thereto, and ordinary ITO, ZnO, IZO, FTO (SnO ₂ :F), Transparent conductive materials such as BZO.

In the above detailed description, the present invention has been described using specific matters such as specific constituent elements and limited examples and drawings. However, these are provided to facilitate an overall understanding of the present invention, and the present invention is not limited to the above-described Examples, various modifications and variations can be made by those skilled in the art to which the present invention pertains based on the description. Therefore, the idea of the present invention is not limited to the above-described embodiments, not only the claims described later, but also modifications equal to or equivalent to the scope of the claims all belong to the scope of the idea of the present invention.

Claims (12)

1. a kind of solaode is it is characterised in that comprise：

Substrate, is arranged with unit solar-electricity pool area, and this unit solar-electricity pool area is by battery unit Region and distribution region are constituted；

First semiconductor layer, forms on the substrate, and on the described distribution region of described substrate Form first groove；

Second semiconductor layer, is formed on described first semiconductor layer, and is joining described in described substrate Form second groove, to expose a part for described first semiconductor layer on line region；

3rd semiconductor layer, is formed on described second semiconductor layer, and is joining described in described substrate Form the 3rd groove, to expose a part for described second semiconductor layer on line region；

Side wall insulating layer, is embedded in inside described first groove, makes the described battery unit area of described substrate Described first semiconductor layer on domain, the second semiconductor layer, the 3rd semiconductor layer mutually insulated；And

Electrode layer, is formed on described 3rd semiconductor layer, by described second groove with described first Semiconductor layer connects.

2. solaode according to claim 1 it is characterised in that

It is also formed with anti-reflecting layer between described substrate and described first semiconductor layer.

3. solaode according to claim 2 it is characterised in that

Described anti-reflecting layer is silicon oxide (SiO_x) or silicon nitride (SiN_x).

4. solaode according to claim 1 it is characterised in that

Described first semiconductor layer, the second semiconductor layer, the 3rd semiconductor layer are n, i, p or p, i, n.

5. a kind of manufacture method of solaode is it is characterised in that comprise the steps：

Step (a), provides the substrate being arranged with unit solar-electricity pool area, this unit solaode Region is made up of battery cell region and distribution region；

Step (b), sequentially form on the substrate the first semiconductor layer, the second semiconductor layer, the 3rd Semiconductor layer；

Step (c), the first etching work procedure：Described distribution region etches described first semiconductor layer, Second semiconductor layer, the 3rd semiconductor layer, are divided with adjacent other unit solar-electricity pool area with being formed From first groove；

Step (d), imbeds described first groove, to form side wall insulating layer；

Step (e), the second etching work procedure：On described 3rd semiconductor layer and described side wall insulating layer Form the first mask layer, and on described distribution region, etch institute using described first mask layer simultaneously State the 3rd semiconductor layer and described second semiconductor layer, expose the one of described first semiconductor layer to be formed Partial second groove；

Step (f), removes described first mask layer, and exhausted in described 3rd semiconductor layer and described side wall Electrode layer is formed on edge layer；

Step (g), the 3rd etching work procedure：Second mask layer is formed on described electrode layer, and in institute State on distribution region, etch described electrode layer and the described 3rd half using described second mask layer simultaneously and lead Body layer, to form the 3rd groove of the part exposing described second semiconductor layer；

Step (h), removes described second mask layer.

6. the manufacture method of solaode according to claim 5 is it is characterised in that also include Following steps：

Form anti-reflecting layer between described substrate and described first semiconductor layer.

7. solaode according to claim 6 manufacture method it is characterised in that

Described anti-reflecting layer is by silicon oxide (SiO_x) or silicon nitride (SiN_x) formed.

8. solaode according to claim 5 manufacture method it is characterised in that

Described first groove is etched by laser scribing method.

9. solaode according to claim 5 manufacture method it is characterised in that

Described second groove and described 3rd groove are etched by wet etch process.

10. solaode according to claim 5 manufacture method it is characterised in that

Described first, second, third etching work procedure is carried out on the top of described substrate.

The manufacture method of 11. solaodes according to claim 5 it is characterised in that

Described electrode layer is formed by transparent conductive material or metal material or their stepped construction.

The manufacture method of 12. solaodes according to claim 5 it is characterised in that

Described first semiconductor layer, the second semiconductor layer, the 3rd semiconductor layer be formed as n, i, p or p, i、n.