KR101039148B1 - Solar cell and manufacturing method - Google Patents

Abstract

A solar cell and a method of manufacturing the same are disclosed. According to the present invention, there is provided a solar cell comprising: a substrate 100 having unit solar cell regions A and B composed of a unit cell region A and a wiring region B; A lower electrode 200a formed on the unit cell region A _n on the substrate 100; It is connected to the same layer as one side of the lower electrode 200a on the wiring area B _n on the substrate 100, and the other unit solar cell areas A _{n +1} and B _{n +1} and the first trench are adjacent to each other. A lower connection electrode 200b formed to be left; An optoelectronic device portion 300a formed on the lower electrode 200a and having a plurality of semiconductor layers stacked thereon; A first dummy photoelectric device 310 having a second trench T2 in the same layer as the photoelectric device unit 300a and formed in a predetermined pattern on the lower connection electrode 200b; A second dummy photoelectric device 320 having a third trench T3 in the same layer as the first dummy photoelectric device 310 and formed in a predetermined pattern on the lower connection electrode 200b; An upper electrode 400a formed on the optoelectronic device portion 300a; First and second dummy upper electrodes 410 and 420 formed on the first and second dummy photoelectric devices 310 and 320, respectively; A first sidewall insulating layer 510 embedded in the first trench T1 and formed on the substrate 100; And a wiring layer electrically connecting the upper electrode 400a on another unit solar cell region A _{n +1} , B _{n +1} adjacent to an upper surface of the lower connection electrode 200b exposed by the third trench T3. Characterized in that it comprises 600.

Description

SOLAR CELL AND METHOD FOR FABRICATING THE SAME

The present invention relates to a solar cell and a method of manufacturing the same. In more detail, by embedding the sidewall insulating layer in the trench to precisely control the shape (especially the width), the area ratio of the unit cell area is increased to obtain an excellent photoelectric conversion efficiency, and a method of manufacturing the same It is about.

Conventional thin-film solar cells have a variety of difficulties in actual commercialization because the photoelectric conversion efficiency is less than about 10%. In order to solve this problem, a technique of realizing excellent photoelectric conversion efficiency by connecting a plurality of photoelectric devices in series has been developed.

Such a series solar cell is a method of obtaining a necessary power by connecting a plurality of horizontally arranged photoelectric elements in series with an electrode (wiring).

However, in order to manufacture a conventional series solar cell, at least three etching (pattern) processes are required, which increases the processing time and cost, and reduces the area ratio of the unit cell area (that is, the solar cell wiring (dead). ) Area is increased] There is a problem that the photoelectric conversion efficiency is lowered. In particular, since a plurality of deposition processes and a plurality of etching processes are repeatedly performed, the number of process steps and process equipment is increased, and the number of cleaning processes is also increased to satisfactorily remove residues generated by each etching process.

Accordingly, an object of the present invention is to provide a solar cell and a method for manufacturing the same, which are devised to solve the above-mentioned problems of the prior art and which can separate a plurality of deposition processes and a plurality of etching processes from each other.

In addition, another object of the present invention is to provide a solar cell having a sidewall insulating layer capable of minimizing a width while preventing a short circuit occurring in series connection, and a method of manufacturing the same.

Another object of the present invention is to provide a solar cell and a method for manufacturing the same, which can reduce the area (particularly, length) of a lower electrode (specifically, a lower connection electrode) connected in series in a wiring area.

The object of the present invention is a substrate in which a unit solar cell region consisting of a unit cell region and a wiring region is arranged; A lower electrode formed on the unit cell area on the substrate; A lower connection electrode connected to one side of the lower electrode on the wiring area on the substrate, the lower connection electrode being formed to have a first trench with another adjacent unit solar cell area; An optoelectronic device portion formed on the lower electrode and having a plurality of semiconductor layers stacked thereon; A first dummy photoelectric device formed in a predetermined pattern on the lower connection electrode with a second trench in the same layer as the optoelectronic device portion; A second dummy photoelectric device formed in a predetermined pattern on the lower connection electrode with a third trench in the same layer as the first dummy photoelectric device; An upper electrode formed on the optoelectronic device portion; First and second dummy upper electrodes formed on the first and second dummy photoelectric devices, respectively; A first sidewall insulating layer buried in the first trench and formed on the substrate; And a wiring layer electrically connecting an upper surface of the lower connection electrode exposed by the third trench and an upper electrode on the adjacent other unit solar cell region.

In addition, the object of the present invention is a substrate in which a unit solar cell region consisting of a unit cell region and a wiring region is arranged; A lower electrode formed on the unit cell area on the substrate; A dummy lower electrode formed in the same layer on the wiring area on the substrate with a predetermined distance from the lower electrode, and formed in a predetermined pattern with another adjacent unit solar cell area and a first trench; A lower connection electrode connected to one side of the lower electrode with a third trench in the same layer as the dummy lower electrode; An optoelectronic device portion formed on the lower electrode and having a plurality of semiconductor layers stacked thereon; A first dummy photoelectric device formed in a predetermined pattern on the lower connection electrode with a second trench in the same layer as the optoelectronic device portion; A second dummy photoelectric device formed on the dummy lower electrode in the same layer as the first dummy photoelectric device; An upper electrode formed on the optoelectronic device portion; First and second dummy upper electrodes formed on the first and second dummy photoelectric devices, respectively; A first sidewall insulating layer buried in the first trench and formed on the substrate; And a wiring layer electrically connecting a side surface of the lower connection electrode exposed by the third trench and an upper electrode on the adjacent other unit solar cell region.

In this case, the semiconductor device may further include a second sidewall insulating layer buried in the second trench and formed on the lower connection electrode.

The material of the first and second sidewall insulating layers may include silicon oxide (SiO _x ), silicon nitride (SiN _x ), a polymer, or a resin.

The first and second sidewall insulating layers may be formed by an inkjet printing method.

The wiring layer may be formed by an inkjet printing method.

The upper electrode may be a transparent conductive material or a metal material or a stacked structure thereof.

The optoelectronic device portion may include a first amorphous semiconductor layer formed on the lower electrode; A second amorphous semiconductor layer formed on the first amorphous semiconductor layer; It may include a third amorphous semiconductor layer formed on the second amorphous semiconductor layer.

The optoelectronic device portion may include a stack of one or more optoelectronic devices, and the at least one optoelectronic device formed on the lower electrode may include a first polycrystalline semiconductor layer; A second polycrystalline semiconductor layer formed on the first polycrystalline semiconductor layer; It may include a third polycrystalline semiconductor layer formed on the second polycrystalline semiconductor layer.

The semiconductor layer may be a silicon layer.

The polycrystalline semiconductor layer may be crystallized by any one of Solid Phase Crystallization (SPC), Excimer Laser Annealing (ELA), Sequential Lateral Solidification (SLS), Metal Induced Crystallization (MIC), and Metal Induced Lateral Crystallization (MILC). have.

In addition, the object of the present invention comprises the steps of (a) providing a substrate in which a unit solar cell region consisting of a unit cell region and a wiring region is arranged; (b) sequentially forming a lower conductive layer, a plurality of semiconductor layers, and an upper conductive layer on the substrate; (c) a first etching step of simultaneously etching a portion of the lower conductive layer, the semiconductor layer, and the upper conductive layer on the wiring region to form a first trench which is separated from another adjacent unit solar cell region; (d) etching a portion of the semiconductor layer and the upper conductive layer patterned by the first etching step on the wiring region at the same time to form the third trench and the third trench and the predetermined pattern formed with a predetermined pattern with the first trench; A second etching step of forming a second trench formed with a gap; (e) filling the first trenches to form a first sidewall insulating layer on the substrate; And (f) forming a wiring layer electrically connecting an upper surface of the lower conductive layer exposed by the third trench and an upper conductive layer on the adjacent other unit solar cell region. It is also achieved by the manufacturing method of.

In addition, the object of the present invention comprises the steps of (a) providing a substrate in which a unit solar cell region consisting of a unit cell region and a wiring region is arranged; (b) sequentially forming a lower conductive layer, a plurality of semiconductor layers, and an upper conductive layer on the substrate; (c) a portion of the lower conductive layer, the semiconductor layer, and the upper conductive layer is simultaneously etched on the wiring region to form a first trench and a first pattern which are separated from other adjacent unit solar cell regions and a predetermined pattern with the first trench A first etching step of forming a third trench to be formed; (d) a second etching step of simultaneously etching a portion of the semiconductor layer and the upper conductive layer patterned by the first etching step on the wiring region to form a second trench; (e) filling the first trenches to form a first sidewall insulating layer on the substrate; And (f) forming a wiring layer electrically connecting a side surface of the lower conductive layer exposed by the third trench and an upper conductive layer on the adjacent other unit solar cell region. It is also achieved by a method for producing a battery.

In this case, the method may further include forming a second sidewall insulating layer embedded in the second trench and formed on the lower connection electrode.

The material of the first and second sidewall insulating layers may include silicon oxide (SiO _x ), silicon nitride (SiN _x ), a polymer, or a resin.

The first and second sidewall insulating layers may be formed by an inkjet printing method.

The wiring layer may be formed by an inkjet printing method.

The method may further include forming a metal layer on the upper conductive layer.

According to the present invention, the pattern process may be continuously performed to completely separate the deposition process and the etching process. Therefore, the number of cleaning processes can be shortened during solar cell manufacturing.

In addition, according to the present invention, by forming the sidewall insulating layer embedded in the trench, it is possible to minimize the width while preventing the short circuit occurring in series connection, it is possible to improve the photoelectric conversion efficiency of the solar cell.

In addition, according to the present invention, since the wiring layer can be connected to the side surface of the lower electrode (specifically, the lower connection electrode) through the trench, the area (particularly, length) of the lower electrode can be reduced, thereby reducing the current loss of the solar cell. Can be reduced.

1 to 5 are views sequentially showing a manufacturing process of the solar cell according to the first embodiment of the present invention.
6 is a view showing another embodiment of the solar cell according to the first embodiment of the present invention.
7 is a view showing another embodiment of the solar cell according to the first embodiment of the present invention.
8 to 11 are views sequentially showing a manufacturing process of a solar cell according to a second embodiment of the present invention.
12 is a view showing another embodiment of the solar cell according to the second embodiment of the present invention.
13 is a view showing a solar cell of another form according to a second embodiment of the present invention.
14 and 15 are views illustrating a detailed configuration of an optoelectronic device portion according to an embodiment of the present invention.

DETAILED DESCRIPTION The following detailed description of the invention refers to the accompanying drawings that show, by way of illustration, specific embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. It should be understood that the various embodiments of the present invention are different but need not be mutually exclusive. For example, certain features, structures, and characteristics described herein may be implemented in other embodiments without departing from the spirit and scope of the invention in connection with an embodiment. It is also to be understood that the position or arrangement of the individual components within each disclosed embodiment may be varied without departing from the spirit and scope of the invention. The following detailed description, therefore, is not to be taken in a limiting sense, and the scope of the present invention, if properly described, is defined only by the appended claims, along with the full range of equivalents to which such claims are entitled. In the drawings, like reference numerals refer to the same or similar functions throughout the several aspects, and length, area, thickness, and the like may be exaggerated for convenience.

DETAILED DESCRIPTION Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily implement the present invention.

Embodiment of the Invention

In the present specification, the unit cell region A refers to an area on a substrate on which a photoelectric device (semiconductor layer) is positioned between electrodes (between the lower electrode and the upper electrode), where photoelectric conversion of the solar cell is substantially performed.

In addition, in the present specification, the wiring area B is positioned between the unit cell areas A, and separates the unit cells from each other and at the same time electrically connects (eg, series connection) each other. By region, it can be understood as a dead region where substantially no photoelectric conversion of the solar cell occurs.

One unit cell region (A) and one wiring region (B) gather together to form the unit solar cell regions (A, B). On the unit solar cell regions (A, B), embodiments of the present invention are described. According to the manufacturing process according to the unit solar cell capable of performing both photoelectric conversion and wiring functions are formed.

For example, a plurality of unit solar cell regions A and B may be arranged in a row and column direction on a substrate, and in an arbitrary row, the n th (n is a natural number) unit solar cell region may be a unit cell region A _n . And a wiring region B _n .

In this case, the n + 1 th unit solar cell region (unit cell region (A _{n +1} ) and the wiring region (B _{n +1} )) is provided in one region adjacent to the n th unit solar cell region (A _n , B _n ). The unit solar cell regions may be arranged in an order of an n + 2 th unit solar cell region (a unit cell region A _{n +2} and a wiring region B _{n +2} ).

In addition, the n-th unit solar cell region (unit cell region A _{n -1} and wiring region B _{n -1} ) is provided in the other region adjacent to the n-th unit solar cell region, and the n-second unit solar cell. The first unit solar cell region may be arranged in the order of the region (unit cell region A _{n -2} and wiring region B _{n -2} ).

In the following embodiments, a cross-sectional view of the n-th solar cell region (unit cell region A _n and wiring region B _n ) of a plurality of unit solar cell regions on a substrate is illustrated for convenience of description. Do it.

First Example

1 to 5 are views sequentially showing a manufacturing process of the solar cell according to the first embodiment of the present invention.

First, referring to FIG. 1, a substrate 100 in which unit solar cell regions A and B including unit cell regions A and wiring regions B are arranged is provided. The material of the substrate 100 may be a transparent glass substrate, but the present invention is not limited thereto. For example, the substrate 100 may use both a transparent material such as glass and plastic or an opaque material such as silicon and metal (for example, SUS (Stainless Steel)) according to the direction of receiving light.

Subsequently, texturing may be performed on the surface of the substrate 100. Texturing in the present invention is intended to prevent the phenomenon that the characteristics of the light is reduced by reflecting the light incident on the substrate surface of the solar cell is optically lost. In other words, the surface of the substrate is roughened to form an uneven pattern (not shown) on the surface of the substrate. For example, if the surface of the substrate is roughened by texturing, the light reflected once from the surface may be reflected back toward the solar cell, thereby reducing the loss of light and increasing the amount of light trapping to increase the photoelectric conversion efficiency of the solar cell. Can be improved.

In this case, a sand blasting method may be used as a representative texturing method. Sand blasting in the present invention includes both dry blasting for etching by etching the etching particles with compressed air and wet blasting for etching by etching the etching particles together with the liquid. On the other hand, the etching particles used in the sand blasting of the present invention can be used without limitation, particles that can form irregularities on the substrate by physical impact, such as sand, small metal.

Subsequently, an antireflection layer (not shown) may be formed on the substrate 100. The anti-reflection layer serves to prevent a phenomenon in which solar light incident through the substrate 100 is not absorbed by the photoelectric device (semiconductor layer) and is directly reflected to the outside, thereby degrading the efficiency of the solar cell. The material of the anti-reflection layer may be silicon oxide (SiO _x ) or silicon nitride (SiN _x ), but is not limited thereto.

The method of forming the reflective ring layer may include low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), and the like.

Subsequently, a lower conductive layer 200 of a conductive material may be formed on the entire upper surface of the substrate 100. The material of the lower conductive layer 200 may be a transparent or opaque conductive material according to the direction in which the solar cell of the present invention receives light without limitation. For example, in the case of a transparent conductive material, a transparent conductive oxide (TCO), which is a transparent electrode having low contact resistance and transparent properties, may be used. For example, AZO (ZnO: Al) and ITO (Indium-Tin-Oxide) may be used. , GZO (ZnO: Ga), BZO (ZnO: B), and FTO (SnO ₂ : F) or any combination thereof. In the case of the opaque material, any one of opaque molybdenum (Mo), tungsten (W), and molybdenum tungsten (MoW), or an alloy thereof, which has low contact resistance and does not degrade electrical properties even when a high temperature process is performed. However, the present invention is not limited thereto, and may include copper, aluminum, titanium, and the like, which are conventional conductive materials.

The lower conductive layer 200 may be formed by physical vapor deposition (PVD), such as thermal evaporation, e-beam evaporation, sputtering, and LPCVD, PECVD, and metal organic compounds. Chemical Vapor Deposition (CVD), such as Metal Organic Chemical Vapor Deposition (MOCVD).

Subsequently, the p-type and n-type semiconductor layers 300 may be stacked on the upper entire surface of the lower conductive layer 200, or the p-type, i-type, and n-type semiconductor layers 300 may be stacked. The material of the semiconductor layer 300 may be silicon (Si) that is commonly used. Hereinafter, a case where the p-type, i-type, and n-type silicon layers 300 are stacked will be described. The invention is not limited thereto.

The method of forming the silicon layer 300 may include chemical vapor deposition such as PECVD or LPCVD. The silicon layer 300 receives power in the unit cell region A by a subsequent process to produce power. Can function as an optoelectronic device. This will be described in detail with reference to the following detailed description with reference to FIGS. 14 and 15.

Subsequently, an upper conductive layer 400 of a conductive material may be formed on the entire upper surface of the silicon layer 300. The material of the upper conductive layer 400 may use any conductive material without limitation. For example, in the case of a transparent conductive layer, TCO may be used, such as AZO (ZnO: Al), ITO (Indium-Tin-Oxide), GZO (ZnO: Ga), BZO (ZnO: B), and FTO (SnO ₂ : F) can be any one. In addition, in the case of an opaque conductive layer, a conventional metal material may be used, and metals such as aluminum (Al), silver (Ag), gold (Au), copper (Cu), zinc (Zn), titanium (Ti), and the like It may be an alloy of. In addition, the upper conductive layer 400 may be formed of a structure in which a transparent conductive layer and a metal layer are stacked. In this case, the materials of the transparent conductive layer and the metal layer may apply the materials listed above without limitation. The method of forming the upper conductive layer 400 may include physical vapor deposition, chemical vapor deposition, and the like, similarly to the lower conductive layer 200.

Next, referring to FIG. 2, a portion of the lower conductive layer 200, the silicon layer 300, and the upper conductive layer 400 positioned on the wiring area B on the substrate 100 may be simultaneously (collectively). The first trenches T1 may be formed by first etching (that is, etching by P1 width).

In more detail, the unit solar cell regions A and B including the unit cell region A and the wiring region B may be separated from each other by the first etching process P1. For example, the n th unit solar cell region (unit cell region A _n and wiring region B _n ) is the n + 1 th unit solar cell region [unit cell region A _{n +1} ) of one adjacent region. And wiring region (B _{n +1} )] and the n-1th unit solar cell region (unit cell region (A _{n -1} ) and wiring region (B _{n -1} )) of the other region. have.

As the method of the first etching process P1, a laser scribing method using a laser of infrared rays or ultraviolet rays may be used. However, the present invention is not limited thereto, and an etching method including a known photolithography method may be used without limitation. When using the laser scribing method, the irradiation direction of the laser may be irradiated from the lower side of the substrate 100 as shown, but may be irradiated from both the upper side and the upper side and the lower side of the substrate 100 as necessary. .

Meanwhile, in the following detailed description, in order to explain equivalently to the driving circuit of the solar cell, the patterned lower conductive layer 200 is lowered on the wiring region B as the lower electrode 200a on the unit cell region A. The description will be made by separating the connection electrode 200b. That is, the lower electrode 200a functions as an electrode of the photoelectric device unit 300a which will be described later, and since the lower connection electrode 200b is connected to one side of the lower electrode 200a, an arbitrary unit solar cell may be replaced with another unit. By performing the function of the connection unit connected in series with the battery it is possible to implement a good series connection type solar cell.

For example, referring to the n-th unit solar cell region, the lower electrode 200a is formed on the unit cell region A _n on the substrate 100. At the same time, a lower portion connected to the lower electrode 200a on the wiring region B _n on the substrate 100 by the same layer and having another unit cell region A _{n +1} and the first trench T1 adjacent thereto. The connection electrode 200b may be formed.

In addition, the patterned silicon layer 300 is divided into a photoelectric device unit 300a on the unit cell region A and a dummy photoelectric device 300b on the wiring region B. That is, the photoelectric device unit 300a may receive light to move electrons and holes to the lower electrode 200a and the upper electrode 400a described later to produce photovoltaic power. In contrast, the dummy photoelectric device 300b does not substantially generate power.

In addition, the patterned upper conductive layer 400 is divided into an upper electrode 400a on the unit cell region A and a dummy upper electrode 400b on the wiring region B. That is, the upper electrode 400a may perform an electrode function of the optoelectronic device portion 300a. In contrast, the dummy upper electrode 400b does not function as an electrode.

Next, referring to FIG. 3, a portion of the dummy photoelectric device 300b and the dummy upper electrode 400b positioned on the lower connection electrode 200b and patterned by the first etching process P1 are simultaneously (collectively). ) Second etching (ie, etching by P2 width) to form second and third trenches T2 and T3.

In more detail, the first dummy photoelectric device formed in a predetermined pattern on the lower connection electrode 200b by the second etching process P2 may have the second trench T2 in the same layer as the photoelectric device unit 300a. The second dummy photoelectric device 320 formed in a predetermined pattern may be formed on the same layer as the first dummy photoelectric device 310 and the third trench T3. In this case, the first and second dummy upper electrodes 410 and 420 may be positioned on the first and second dummy photoelectric devices 310 and 320, respectively.

In the present invention, the second trenches T2 and the third trenches T3 may be formed at the same time, but the present invention is not limited thereto and may be performed continuously (for example, T2-> T3 or T3-> T2) with a time difference. It may be. In addition, the widths of the second trenches T2 and the third trenches T3 during the second etching P2 may be equally patterned as shown, but the present invention is not limited thereto and may be different from each other as necessary. It may be formed.

In particular, since the third trench T3 functions as a passage for connecting the wiring layer 600 and the lower connection electrode 200b to be described later, the first and second parts may be used for good electrical connection (increasing the connection area). It may be desirable to form larger than the width of the trenches T1, T2.

As the method of the second etching process P2, laser scribing using a laser having a green wavelength (532 nm) may be used. However, the present invention is not limited thereto, and an etching method including a known photolithography method may be used without limitation. When using the laser scribing method, the irradiation direction of the laser may be irradiated from the lower side of the substrate 100 as shown, but may be irradiated from both the upper side and the upper side and the lower side of the substrate 100 as necessary. .

On the other hand, the order of the first etching process (P1) and the second etching process (P2) of the present invention may be performed in reverse, if necessary, which is the first etching after performing the second etching process (P2) It is because the pattern of the same structure can be obtained even if process (P2) is performed.

Next, referring to FIG. 4, the first sidewall insulating layer 510 and the second sidewall insulating layer 520 are formed by filling an insulating material in the first trench T1 and the second trench T2, respectively.

In more detail, an insulating material is formed in the first trench T1 that separates the second dummy photoelectric device 320 from another adjacent unit cell region and exposes a part of the wiring region B on the substrate 100. The first sidewall insulating layer 510 may be formed by being buried. For example, the first sidewall insulating layer 510 may include the n + 1 th unit solar cell regions A _{n +1} , B _{n +1} , which are adjacent to both n th unit solar cell regions A _n and B _n , respectively. A function of electrically separating (isolating) the n−1 th unit solar cell region A _{n −1} , B _{n −1} may be performed.

In addition, a second trench separating the optoelectronic device portion 300a and the upper electrode 400a from the first dummy photoelectric device 310 and the first dummy upper electrode 410 and exposing a portion of the lower connection electrode 200b ( The second sidewall insulating layer 520 may be formed by filling an insulating material in T2).

The material for forming the sidewall insulating layers 500: 510 and 520 may be any one of silicon oxide (SiO _x ), silicon nitride (SiN _x ), polymer, resin, or a mixture of two or more thereof. In addition, various known materials can be used. As a method of forming the sidewall insulating layer 500, ink jet printing may be used, in which predetermined ink is injected through a head composed of a nozzle. However, the present invention is not limited thereto, and a known photolithography method and a screen printing method are used. (screen printing), roller coating (roller coating) and the like can be used without limitation.

Since the side wall insulating layer 500 is embedded in the trench in which a predetermined space is formed, the sidewall insulating layer 500 may reduce the spreading side and minimize the overall width I. That is, since the conventional side wall insulating layer is formed by ink jet printing in which a predetermined ink is injected, the phenomenon of unnecessarily spreading to the side is caused, thereby increasing the overall width I, but according to the present invention. In the first and second sidewall insulating layers 510 and 520, the first trenches T1 and the third trenches T3 may prevent this, thereby relatively reducing the width I.

Therefore, the area ratio of the unit cell region A, which receives electrical light to produce electrical energy, of the entire substrate 100 is increased, thereby realizing a solar cell having excellent photoelectric conversion efficiency.

Finally, referring to FIG. 5, a wiring layer electrically connected to an upper surface of the lower connection electrode 200b exposed by the third trench T3 to electrically connect the upper electrode 200a on another adjacent unit solar cell region. Form 600.

For example, one end of the wiring layer 600 is the n-th unit of the solar cell area (A _n, B _n) wiring region (B _n) may be connected with the upper first lower connection electrodes (200b) through a third trenches (T3) on the have. In addition, the other end of the wiring layer 600 covers the first sidewall insulating layer 510 while the unit cell region A _{n + of} the n + 1 th unit solar cell region A _{n +1} , B _{n +1} adjacent thereto. ₁ ) may be connected to an upper portion of the upper electrode 400a.

Thus, the n th unit solar cell (A _n , B _n ) may be connected in series with the n + 1 th unit solar cell (A _{n +1} , B _{n +1} ) adjacent to one side region, and the same as the other side region. A series solar cell may be implemented by being connected in series with adjacent n-1 th unit solar cells A _{n -1} and B _{n -1} .

The material of the wiring layer 600 may be any conductive material. For example, transparent conductive oxide (TCO), which is a transparent conductive material, and aluminum (Al), silver (Ag), gold (Au), copper (Cu), zinc (Zn), titanium (Ti), etc. Metals and alloys thereof. In addition, various known materials such as resin and conductive polymer may be used. An inkjet printing method may be used as a method of forming the wiring layer 600, but is not limited thereto. A known screen printing method, a photolithography method, or the like may be used without limitation.

Meanwhile, in FIG. 5, the wiring layer 600 is connected to the second sidewall insulating layer 520 as well as the first dummy upper electrode 410, but is not necessarily limited thereto. For example, by more precisely controlling the inkjet printing process conditions in the process of forming the wiring layer 600, as shown in FIG. 6, the wiring layer 600 may be connected to only the first dummy upper electrode 410. In this case, the second sidewall insulating layer 520 described with reference to FIG. 4 may be omitted as shown in FIG. 7. Therefore, only the empty space may be formed in the second trench T2 without filling the insulating material.

As described above, the solar cell according to the first embodiment of the present invention can reduce the number of etching processes compared to the conventional three times by performing only two etching (pattern) processes P1 and P2 in total. . In addition, after the lower conductive layer 200, the silicon layer 300, and the upper conductive layer 400 are continuously deposited, the first etching process P1 and the second etching process P2 are performed continuously (P1-> P2 or P2-). > P1 order), the deposition process and the etching process can be separated from each other. Therefore, a single laser scribing apparatus is equipped with lasers required for the first and second etching processes simultaneously, for example, green wavelength, infrared and ultraviolet lasers, to simultaneously perform the first and second etching processes in a single scan or a dual scan method. Alternatively, the process can be performed sequentially, thereby reducing process steps and process equipment.

In addition, in order to remove residues caused during the etching process by repeatedly performing a plurality of deposition processes and a plurality of etching processes in the related art, in the present invention, two etching processes are continuously performed. After that, residues can be collectively removed in one washing step, thereby shortening the washing step. Of course, such a cleaning process may be omitted.

In particular, in the present invention, as described above, since the sidewall insulating layer is formed by filling the inside of the trench having a predetermined space, the sidewall insulating layer may be reduced to minimize the width I of the sidewall insulating layer. .

Therefore, the area of the wiring area B in which the sidewall insulating layer is formed in the entire substrate 100 is reduced, and the area ratio of the unit cell area A, which receives electric light and produces electric energy, can be increased. It is possible to implement a solar cell having excellent photoelectric conversion efficiency.

2nd Example

The solar cell according to the second embodiment of the present invention has the same configuration except for the wiring area B of the solar cell of the first embodiment with reference to FIGS. 1 to 7. Therefore, in the following second embodiment, the detailed description of the unit cell region A is omitted in order to avoid duplication of description, and the description will be made mainly on the wiring region B. FIG.

On the other hand, in the following description, in order to explain equivalently to the driving circuit of the solar cell, as described in the first embodiment will be described based on the electrical function for each layer. However, when the lower conductive layer 200 is separated into the lower electrode 200a on the unit cell region A and the lower electrode 200a on one side of the wiring region B, the lower conductive layer 200 is a dummy. The lower electrode 210 will be described in detail. At this time, the dummy lower electrode 210 does not perform the function of the electrode.

8 to 11 are views sequentially showing a manufacturing process of a solar cell according to a second embodiment of the present invention.

First, referring to FIG. 8, the lower conductive layer 200 positioned on the wiring region B of the substrate 100 on which the lower conductive layer 200, the silicon layer 300, and the upper conductive layer 400 are sequentially formed. ), The silicon layer 300 and a portion of the upper conductive layer 400 are simultaneously (collectively) first etched (that is, etched by P1 width) to form first and third trenches T1 and T3. .

In more detail, the first etching process P1 is performed on the wiring region B on the substrate 100 in the same layer as the lower electrode 200a, but the other unit cell regions and the first trenches T1 are adjacent to each other. The dummy lower electrode 210 may be formed to be formed. At the same time, the second dummy photoelectric device 320 and the second dummy upper electrode 420 may be formed on the dummy lower electrode 210.

In addition, the lower connection electrode 200b connected to one side of the lower electrode 200a may be formed on the same layer as the dummy lower electrode 210 with the third trench T3. At the same time, the dummy photoelectric device 300b and the dummy upper electrode 400b formed on the lower connection electrode 200b may be patterned again by the second etching process P2 described below with reference to FIG. 9.

In the present invention, the first trenches T1 and the third trenches T3 may be formed at the same time, but the present invention is not limited thereto and may be performed continuously (for example, T1-> T3 or T3-> T1) with a time difference. It may be. In addition, the widths of the first trenches T1 and the third trenches T3 during the first etching P1 may be patterned by the same width as illustrated, but the present invention is not limited thereto and may be different from each other as necessary. It may be formed.

In particular, since the third trench T3 functions as a passage for connecting the wiring layer 600 and the lower connection electrode 200b to be described later, the first and second parts may be used for good electrical connection (increasing the connection area). It may be desirable to form larger than the width of the trenches T1, T2.

As the method of the first etching process P1, a laser scribing method using a laser of infrared rays or ultraviolet rays may be used. However, the present invention is not limited thereto, and an etching method including a known photolithography method may be used without limitation. When using the laser scribing method, the irradiation direction of the laser may be irradiated from the lower side of the substrate 100 as shown, but may be irradiated from both the upper side and the upper side and the lower side of the substrate 100 as necessary. .

Next, referring to FIG. 9, a portion of the dummy photoelectric device 300b and the dummy upper electrode 400b positioned on the lower connection electrode 200b and patterned by the first etching process P1 are simultaneously (collectively). ) A second trench (ie, a P2 width) to form a second trench (T2).

In more detail, the first dummy photoelectric device of a predetermined pattern is formed on the lower connection electrode 200b by the second etching process P2 with the second trench T2 in the same layer as the photoelectric device unit 300a. 310 may be formed. In this case, the first dummy upper electrode 410 may be positioned on the first dummy photoelectric device 310.

As the method of the second etching process P2, laser scribing using a laser having a green wavelength (532 nm) may be used. However, the present invention is not limited thereto, and an etching method including a known photolithography method may be used without limitation. When using the laser scribing method, the irradiation direction of the laser may be irradiated from the lower side of the substrate 100 as shown, but may be irradiated from both the upper side and the upper side and the lower side of the substrate 100 as necessary. .

On the other hand, the order of the first etching process (P1) and the second etching process (P2) of the present invention may be performed in reverse, if necessary, which is the first etching after performing the second etching process (P2) It is because the pattern of the same structure can be obtained even if process (P2) is performed.

Next, referring to FIG. 10, an insulating material is filled in the first trenches T1 and the second trenches T2 to form the first sidewall insulating layer 510 and the second sidewall insulating layer 520, respectively. These sidewall insulating layers 500 (510, 520) are the same as in the first embodiment of the present invention.

Therefore, the area ratio of the unit cell region A, which receives electrical light to produce electrical energy, of the entire substrate 100 is increased, thereby realizing a solar cell having excellent photoelectric conversion efficiency.

Finally, referring to FIG. 11, a wiring layer connected to the side surface of the lower connection electrode 200b exposed by the third trench T3 and electrically connected to the upper electrode 200a on another adjacent unit solar cell region. Form 600.

For example, one end of the wiring layer 600 is the n-th unit of the solar cell area is connected to the side of the wiring region (B _n) lower through the third trenches (T3) on the connection electrode (200b) of (A _n, B _n) Can be. In addition, the other end of the wiring layer 600 covers the first sidewall insulating layer 510 while the unit cell region A _{n + of} the n + 1 th unit solar cell region A _{n +1} , B _{n +1} adjacent thereto. ₁ ) may be connected to an upper portion of the upper electrode 400a.

Thus, the n th unit solar cell (A _n , B _n ) may be connected in series with the n + 1 th unit solar cell (A _{n +1} , B _{n +1} ) adjacent to one side region, and the same as the other side region. A series solar cell may be implemented by being connected in series with adjacent n-1 th unit solar cells A _{n -1} and B _{n -1} .

The material of the wiring layer 600 may be any conductive material. For example, transparent conductive oxide (TCO), which is a transparent conductive material, and aluminum (Al), silver (Ag), gold (Au), copper (Cu), zinc (Zn), titanium (Ti), etc. Metals and alloys thereof. An inkjet printing method may be used as a method of forming the wiring layer 600, but is not limited thereto. A known photolithography method may be used without limitation.

Meanwhile, in FIG. 11, the wiring layer 600 is connected to not only the first dummy upper electrode 410 but also the second sidewall insulating layer 520, but is not limited thereto. For example, by more precisely controlling the inkjet printing process conditions during the formation of the wiring layer 600, as shown in FIG. 12, the wiring layer 600 may be connected to only the first dummy upper electrode 410. In this case, the second sidewall insulating layer 520 described with reference to FIG. 10 may be omitted as shown in FIG. 13. Therefore, only the empty space may be formed in the second trench T2 without filling the insulating material.

As described above, the solar cell according to the second embodiment of the present invention can reduce the etching process and the cleaning process as in the first embodiment, and can separate the deposition process and the etching process from each other. In addition, since the sidewall insulating layer is formed by filling the inside of the trench having a predetermined space, the sidewall spreading layer may be reduced to minimize the width I of the sidewall insulating layer.

In particular, in the second embodiment of the present invention, since the lower connection electrode 200b extends only to the first dummy photoelectric device 310, the lower connection electrode 200b extends to the second dummy photoelectric device 320. Compared to the embodiment, the area (length) of the lower connection electrode 200b can be reduced. Therefore, it is possible to improve the photoelectric conversion efficiency of the solar cell by reducing the loss of current generated in the optoelectronic device portion 300a.

Optoelectronic device  Configuration

14 and 15 are views illustrating a detailed configuration of an optoelectronic device according to an embodiment of the present invention.

First, referring to FIG. 14, as an example, three layers of amorphous silicon layers 331, 332, and 333 may be formed. More specifically, the first amorphous silicon layer 331 may be formed on the lower electrode 200a, and then the second amorphous silicon layer 332 may be formed on the first amorphous silicon layer 331. The second amorphous silicon layer 333 may be formed on the second amorphous silicon layer 332 to form one optoelectronic device. In this case, the first, second, and third amorphous silicon layers 331, 332, and 333 may be formed by chemical vapor deposition such as PECVD or LPCVD.

Next, referring to FIG. 15, as an example, three layers of polycrystalline silicon layers 341, 342, and 343 may be formed. More specifically, the first polycrystalline silicon layer 341 may be formed on the lower electrode 200a, and then the second polycrystalline silicon layer 342 may be formed on the first polycrystalline silicon layer 341. The third polycrystalline silicon layer 343 may be formed on the second polycrystalline silicon layer 342 to form one optoelectronic device.

In this case, the first, second, and third polycrystalline silicon layers 341, 342, and 343 may be formed by thermally treating the first, second, and third amorphous silicon layers 331, 332, and 333 of FIG. 14. Can be performed. That is, the first amorphous silicon layer 331 is the first polycrystalline silicon layer 341, the second amorphous silicon layer 332 is the second polycrystalline silicon layer 342, and the third amorphous silicon layer 333 is made of Each of the three polycrystalline silicon layers 343 can be crystallized.

In this case, the crystallization methods of the first, second, and third amorphous silicon layers 331, 332, and 333 may include Solid Phase Crystallization (SPC), Excimer Laser Annealing (ELA), Sequential Lateral Solidification (SLS), and Metal Induced Crystallization (MIC). ) And MILC (Metal Induced Lateral Crystallization) can be used. Since the crystallization method of the amorphous silicon is a known technique, a detailed description thereof will be omitted herein.

In the above description, the first, second, and third amorphous silicon layers 331, 332, and 333 are all formed, and the layers are simultaneously crystallized, but the present invention is not limited thereto. For example, the crystallization process may be performed separately for each amorphous silicon layer, and the two amorphous silicon layers may simultaneously undergo a crystallization process and the other amorphous silicon layer may be separately crystallized.

As a result, on the lower electrode 200a, an optoelectronic device including first, second, and third amorphous silicon layers 331, 332, and 333 or first, second, and third polycrystalline silicon layers 341, 342, and 343. Is formed. The photoelectric device is a structure in which an amorphous or polycrystalline silicon layer is stacked, and a pin diode in which p-type, i-type, n-type amorphous or polycrystalline silicon layers are stacked in order to generate power with photovoltaic power generated by light reception. It may be a structure. Where i means intrinsic without impurities. In addition, in the n-type or p-type doping, it is preferable to dope the impurities in situ when forming the amorphous silicon layer. It is common to use boron (B) as an impurity in P-type doping and phosphorus (P) or arsenic (As) as an impurity in n-type doping, but it is not limited to this, and well-known techniques can be used without limitation.

On the other hand, in the photoelectric device, p +, i, n + type, n, i, p type (especially n +, i, p +), p, n, n type (especially p +, p-, n +) ) Or n, n, p type (especially n +, n −, p +) silicon layers. Here, the meaning of + and-represents a relative difference in doping concentration, and means that + has a higher concentration of doping than-. For example, n + is higher doped than n−. If there is no indication of + or-, there is no particular restriction on the doping concentration. In addition, the semiconductor layer located between p and n type functions as a light absorbing layer (for example, i type).

On the other hand, in order to further improve the overall characteristics of the first polycrystalline silicon layer 341, the second polycrystalline silicon layer 342, and the third polycrystalline silicon layer 343, these polycrystalline silicon layers are further heat-treated at a predetermined temperature for defects. The polysilicon layer may be subjected to a hydrogen passivation process to remove dangling bonds present in the polycrystalline silicon layer by performing hydrogen plasma treatment on the polycrystalline silicon layer.

Meanwhile, the optoelectronic device portion 300a described above may have a stacked structure in which another optoelectronic device is further formed on one optoelectronic device. For example, a structure in which a polycrystalline optoelectronic device and an amorphous optoelectronic device are stacked (that is, a tandem structure) may be stacked, but it is to be understood as broadly meaning a stacked structure of two or more.

In addition, a connection layer (not shown), which is a transparent conductor, may be further formed between the polycrystalline optoelectronic device and the amorphous optoelectronic device. The connection layer may make an ohmic contact between the polycrystalline optoelectronic device and the amorphous optoelectronic device, and as a result, may improve the photoelectric conversion efficiency of the solar cell. The connecting layer is AZO Al is a small amount in the ZnO: one or preferably a (ZnO Al) must not be limited to conventional ITO, ZnO, IZO, FTO ( SnO 2: F) a special transparent conductive material such as, BZO Can be used without limitation.

In the above description, an amorphous silicon layer and a polycrystalline silicon layer have been described as an example of the layer constituting the optoelectronic device (particularly, the light absorbing layer), but the present invention is not limited thereto. If necessary, a microcrystalline silicon layer is used as the light absorbing layer. Can also be used. In addition, a known material other than silicon may be used as a material of the light absorbing layer of the solar cell without limitation.

In the foregoing detailed description, the present invention has been described by specific embodiments such as specific components and the like, but the embodiments and drawings are provided only to help a more general understanding of the present invention, and the present invention is limited to the above embodiments. However, one of ordinary skill in the art can make various modifications and variations from this description. Therefore, the spirit of the present invention should not be construed as being limited to the above-described embodiments, and all of the equivalents or equivalents of the claims, as well as the following claims, I will say.

100: substrate
200: lower conductive layer
200a: lower electrode
200b: lower connection electrode
210: dummy lower electrode
300: semiconductor layer (silicon layer)
300a: photoelectric element (photoelectric element)
300b: dummy photoelectric device
310: first dummy photoelectric device
320: second dummy photoelectric device
400: upper conductive layer
400a: upper electrode
400b: dummy upper electrode
410: first dummy upper electrode
420: second dummy upper electrode
500 (510, 520): sidewall insulation layer
510: first sidewall insulating layer
520: second sidewall insulating layer
600: wiring layer

Claims (19)

A substrate on which a unit solar cell region including a unit cell region and a wiring region is arranged;
A lower electrode formed on the unit cell area on the substrate;
A lower connection electrode connected to one side of the lower electrode on the wiring area on the substrate, the lower connection electrode being formed to have a first trench with another adjacent unit solar cell area;
An optoelectronic device portion formed on the lower electrode and having a plurality of semiconductor layers stacked thereon;
A first dummy photoelectric device formed in a predetermined pattern on the lower connection electrode with a second trench in the same layer as the optoelectronic device portion;
A second dummy photoelectric device formed in a predetermined pattern on the lower connection electrode with a third trench in the same layer as the first dummy photoelectric device;
An upper electrode formed on the optoelectronic device portion;
First and second dummy upper electrodes formed on the first and second dummy photoelectric devices, respectively;
A first sidewall insulating layer buried in the first trench and formed on the substrate; And
A wiring layer electrically connecting an upper surface of the lower connection electrode exposed by the third trench and an upper electrode on another adjacent unit solar cell region;
Solar cell comprising a. A substrate on which a unit solar cell region including a unit cell region and a wiring region is arranged;
A lower electrode formed on the unit cell area on the substrate;
A dummy lower electrode formed in the same layer on the wiring area on the substrate with a predetermined distance from the lower electrode, and formed in a predetermined pattern with another adjacent unit solar cell area and a first trench;
A lower connection electrode connected to one side of the lower electrode with a third trench in the same layer as the dummy lower electrode;
An optoelectronic device portion formed on the lower electrode and having a plurality of semiconductor layers stacked thereon;
A first dummy photoelectric device formed in a predetermined pattern on the lower connection electrode with a second trench in the same layer as the optoelectronic device portion;
A second dummy photoelectric device formed on the dummy lower electrode in the same layer as the first dummy photoelectric device;
An upper electrode formed on the optoelectronic device portion;
First and second dummy upper electrodes formed on the first and second dummy photoelectric devices, respectively;
A first sidewall insulating layer buried in the first trench and formed on the substrate; And
A wiring layer electrically connecting a side surface of the lower connection electrode exposed by the third trench and an upper electrode on another adjacent unit solar cell region;
Solar cell comprising a. The method according to claim 1 or 2,
And a second sidewall insulating layer buried in the second trench and formed on the lower connection electrode. The method of claim 3,
The material of the first and second sidewall insulating layer is any one of silicon oxide (SiO _x ), silicon nitride (SiN _x ), a polymer, a resin or two or more thereof. The method of claim 3,
The first and the second side wall insulating layer is a solar cell, characterized in that formed by any one of the inkjet printing method, screen printing method, roller coating method. The method according to claim 1 or 2,
The wiring layer is a solar cell, characterized in that formed by inkjet printing method. The method according to claim 1 or 2,
The upper electrode is a solar cell, characterized in that the transparent conductive material or metal material or a laminated structure thereof. The method according to claim 1 or 2,
The optoelectronic device portion,
A first amorphous semiconductor layer formed on the lower electrode;
A second amorphous semiconductor layer formed on the first amorphous semiconductor layer;
A third amorphous semiconductor layer formed on the second amorphous semiconductor layer
Solar cell comprising a. The method according to claim 1 or 2,
The optoelectronic device portion may include a stack of one or more optoelectronic devices,
At least one photoelectric device formed on the lower electrode,
A first polycrystalline semiconductor layer;
A second polycrystalline semiconductor layer formed on the first polycrystalline semiconductor layer;
A third polycrystalline semiconductor layer formed on the second polycrystalline semiconductor layer
Solar cell comprising a. The method of claim 8,
The semiconductor layer is a solar cell, characterized in that the silicon layer. 10. The method of claim 9,
The semiconductor layer is a solar cell, characterized in that the silicon layer. 10. The method of claim 9,
The polycrystalline semiconductor layer is crystallized by any one of Solid Phase Crystallization (SPC), Excimer Laser Annealing (ELA), Sequential Lateral Solidification (SLS), Metal Induced Crystallization (MIC), and Metal Induced Lateral Crystallization (MILC). A solar cell characterized by the above-mentioned. (a) providing a substrate on which unit solar cell regions comprising unit cell regions and wiring regions are arranged;
(b) sequentially forming a lower conductive layer, a plurality of semiconductor layers, and an upper conductive layer on the substrate;
(c) a first etching step of simultaneously etching a portion of the lower conductive layer, the semiconductor layer, and the upper conductive layer on the wiring region to form a first trench which is separated from another adjacent unit solar cell region;
(d) etching a portion of the semiconductor layer and the upper conductive layer patterned by the first etching step on the wiring region at the same time to form the third trench and the third trench and the predetermined pattern formed with a predetermined pattern with the first trench; A second etching step of forming a second trench formed with a gap;
(e) filling the first trenches to form a first sidewall insulating layer on the substrate; And
(f) forming a wiring layer electrically connecting an upper surface of the lower conductive layer exposed by the third trench and an upper conductive layer on the adjacent other unit solar cell region;
Method for manufacturing a solar cell comprising a. (a) providing a substrate on which unit solar cell regions comprising unit cell regions and wiring regions are arranged;
(b) sequentially forming a lower conductive layer, a plurality of semiconductor layers, and an upper conductive layer on the substrate;
(c) a portion of the lower conductive layer, the semiconductor layer, and the upper conductive layer is simultaneously etched on the wiring region to form a first trench and a first pattern which are separated from other adjacent unit solar cell regions and a predetermined pattern with the first trench A first etching step of forming a third trench to be formed;
(d) a second etching step of simultaneously etching a portion of the semiconductor layer and the upper conductive layer patterned by the first etching step on the wiring region to form a second trench;
(e) filling the first trenches to form a first sidewall insulating layer on the substrate; And
(f) forming a wiring layer electrically connecting side surfaces of the lower conductive layer exposed by the third trenches and an upper conductive layer on the adjacent other unit solar cell region;
Method for manufacturing a solar cell comprising a. The method according to claim 13 or 14,
And forming a second sidewall insulating layer embedded in the second trench and formed on the lower connection electrode. 16. The method of claim 15,
The material of the first and second sidewall insulating layer is any one or more of silicon oxide (SiO _x ), silicon nitride (SiN _x ), a polymer, a resin, or a method of manufacturing a solar cell. 16. The method of claim 15,
And the first and second sidewall insulating layers are formed by any one of an inkjet printing method, a screen printing method, and a roller coating method. The method according to claim 13 or 14,
The wiring layer is a method of manufacturing a solar cell, characterized in that formed by inkjet printing method. The method according to claim 13 or 14,
The method of manufacturing a solar cell further comprising the step of forming a metal layer on the upper conductive layer.

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