CN108052153A - The LDO linear voltage regulators of New-type CMOS structure - Google Patents

Abstract

The invention discloses a kind of LDO linear voltage regulators of New-type CMOS structure, including：Biasing circuit module, band-gap reference source circuit module, error amplifier circuit module, comparator circuit module and output circuit module.The LDO linear voltage regulators of the New-type CMOS structure of the present invention, can work under negative supply voltage, and low in energy consumption, bandwidth is constant, and system transients responding ability is strong, can realize and itself fix 5V outputs, external feedback resistance can also be used to realize adjustable output.

Description

LDO Linear Regulator with New CMOS Structure

technical field

The invention relates to the technical field of circuits, in particular to a novel CMOS structure LDO linear regulator.

Background technique

With the rapid popularization of consumer electronic products and the gradual improvement of semiconductor manufacturing technology, low-dropout linear regulators are widely used in consumer electronic products because they supply the required stable DC voltage to each module in the entire system It has very excellent performance. However, traditional capacitor-less LDOs often have to sacrifice the stability of a part of the circuit while meeting certain indicators and processes, resulting in the circuit not having a constant bandwidth, the system’s transient response capability is not high enough, and the output cannot be adjusted. High-performance LDO is the research object of many analog IC designers.

Contents of the invention

In order to solve the problems in the prior art, an embodiment of the present invention provides a novel LDO linear regulator with a CMOS structure. Described technical scheme is as follows:

On the one hand, a new type of CMOS structure LDO linear regulator, including: bias circuit (BIAS) module, bandgap reference source circuit (VREF) module, error amplifier circuit (EA) module, comparator circuit (COMP) module and an output circuit module;

The bias circuit module provides a suitable bias voltage for the subsequent circuit;

The bandgap reference source circuit module provides a stable voltage for the subsequent circuit and serves as the input stage of the new LDO;

The error amplifier circuit module is used to compare the output feedback sampling signal with the reference voltage, and control the working state of the subsequent stage circuit to keep the output stable;

The output terminal of the comparator circuit module is connected with the double-throw switch SW to control the output of the LDO;

The output circuit module is composed of a power regulating tube, a double-throw switch SW and a load.

Furthermore, the bias circuit module adopts a self-bias structure to provide a reliable and stable bias voltage for the entire circuit.

Further, the bandgap reference source circuit module adopts a β second-order compensated bandgap reference circuit structure to provide a temperature-independent and stable reference voltage for subsequent circuits.

Further, the error amplifier circuit module adopts a folded cascode structure, which has high gain.

Further, the error amplifier circuit module has lower power supply voltage, lower quiescent working current, wide bandwidth, higher open-loop gain and high power supply rejection ratio.

Further, the comparator circuit module adopts a two-stage operational amplifier structure.

Further, the comparator circuit module achieves the purpose of adjusting the output of the LDO by selecting the nodes A and B of the double-throw switch SW.

The beneficial effects brought by the technical solutions provided by the embodiments of the present invention are: the novel CMOS structure LDO linear regulator of the present invention can work under negative power supply voltage, has low power consumption, constant bandwidth, and strong transient response capability of the system. It can realize its own fixed -5V output, and can also use an external feedback resistor to achieve adjustable output.

Description of drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings that need to be used in the description of the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present invention. For those skilled in the art, other drawings can also be obtained based on these drawings without creative effort.

Fig. 1 is the module schematic diagram of the LDO linear regulator embodiment of novel CMOS structure of the present invention;

Fig. 2 is the circuit diagram of bias circuit module in the LDO linear regulator embodiment of novel CMOS structure of the present invention;

Fig. 3 is the circuit diagram of the middle bandgap reference source circuit module of the LDO linear regulator embodiment of the novel CMOS structure of the present invention;

Fig. 4 is the circuit diagram of the middle error amplifier circuit module of the LDO linear regulator embodiment of novel CMOS structure of the present invention;

Fig. 5 is the circuit diagram of the middle comparator circuit module of the LDO linear regulator embodiment of novel CMOS structure of the present invention;

Fig. 6 is the circuit diagram of the middle output circuit module of the LDO linear regulator embodiment of the novel CMOS structure of the present invention;

Fig. 7 is the symbol schematic diagram of the overall circuit embodiment of the LDO linear regulator of the novel CMOS structure of the present invention;

FIG. 8 is a stability simulation curve of an embodiment of a novel CMOS structure LDO linear regulator of the present invention.

Detailed ways

In order to make the object, technical solution and advantages of the present invention clearer, the implementation manner of the present invention will be further described in detail below in conjunction with the accompanying drawings.

Example

As shown in Figure 1, the LDO linear voltage regulator 10 of novel CMOS structure provided by the present invention comprises: bias circuit (BIAS) module 100, bandgap reference source circuit (VREF) module 200, error amplifier circuit (EA) module 300 , a comparator circuit (COMP) module 400 and an output circuit module 500 .

The bias circuit module 100 provides a suitable bias voltage for the post-stage circuit; the bandgap reference source circuit module 200 provides a stable voltage for the post-stage circuit and is used as the input stage of the novel LDO; the error amplifier circuit module 300 is used for comparing the output feedback Sampling the signal and the reference voltage, and controlling the working state of the subsequent stage circuit to keep the output stable; the output terminal of the comparator circuit module 400 is connected with the double-throw switch SW to control the output of the LDO; the output circuit module 500 is composed of a power adjustment tube, a double-throw The switch SW and the load are jointly constituted.

As shown in FIG. 2 , the bias circuit module 100 adopts a self-bias structure, including: PMOS transistors P1 and P2 , NMOS transistors N1 and N2 and a resistor R. NMOS transistors N1 and N2 form a current mirror, and PMOS transistors P1, P2 and R form a logarithmic current source. The bias circuit module 100 serves as the output end of the bias circuit, has a simple circuit structure, and provides a reliable and stable bias voltage for the entire circuit.

As shown in FIG. 3 , the bandgap reference source circuit module 200 adopts a β second-order compensated bandgap reference circuit structure, including: PMOS transistors P1, P2, P3, and P4, NMOS transistors N1, N2, N3, N4, and N5, and triode NPN1 , NPN2, NPN3, capacitor Cc and resistors R1, R2. In the figure, VIN is the input negative power supply, GND is the ground wire, PMOS transistors P1, P2, P3, P4 and NMOS transistors N1, N2 form an operational amplifier unit, and the potentials of nodes A and B are equalized through a feedback loop. The capacitor Cc acts as Miller compensation for the loop, and the PMOS transistor P2 is the starting transistor. Resistors R1, R2, transistors NPN1, NPN2 and NMOS transistors N3, N4, N5 constitute the bandgap reference core, the number ratio of transistors NPN1 and NPN2 is 7:1; NMOS transistors N3, N4, N5 constitute a 1:1:1 Mirror current source, drain current I _D3 =I _D4 =I _D5 =I _D , transistor NPN3 plays a role in reducing the channel length modulation effect of NMOS transistor N3; REF_OUT is the output terminal of the reference source.

The bandgap reference source circuit module 200 provides a temperature-independent and stable voltage for the subsequent circuit, and the bandgap voltage output by the bandgap voltage circuit is expressed as:

As shown in FIG. 4, the error amplifier circuit module 300 adopts a folded cascode structure, including: PMOS transistors P1, P2, P3, P4, P5, P6, P7, P8, and NMOS transistors N1, N2, N3 , N4, N5. VBIAS is the bias input voltage, V-, V+ are the input terminals of the amplifier, and Vout is the output terminal. The error amplifier circuit module 300 has a high gain, and uses a PMOS transistor as an input, which reduces input noise.

The error amplifier circuit module 300 has low power supply voltage, low quiescent current, wide bandwidth, high open-loop gain and high power supply rejection ratio.

As shown in FIG. 5 , the comparator circuit module 400 adopts a two-stage operational amplifier structure, including: PMOS transistors P1 , P2 , P3 , and NMOS transistors N1 , N2 , N3 , N4 . The first stage is a double-ended to single-ended output operational amplifier composed of NMOS transistors N1, N2 and PMOS transistors P1, P2; the second stage is an amplifying circuit composed of PMOS transistor P3 and NMOS transistor N4, providing rail-to-rail output voltage. The NMOS transistors N3 and N4 provide bias current, the gate voltage is provided by the bias circuit module 100, at room temperature VIN=-9V, the quiescent current of the comparator circuit is about 50nA, and all MOS transistors work in the subthreshold region.

The comparator circuit module 400 has high stability under the condition of higher gain, and is connected to the double-throw switch SW of the output circuit module 500 through the output terminal, and controls the output of the LDO by selecting the nodes A and B of the double-throw switch SW, To achieve the purpose of LDO output adjustable.

As shown in FIG. 6 , the output circuit module 500 includes: a power regulating tube Mp, regulating resistors R1 , R2 , R1S, R2S, a double-throw switch SW, a load resistor RL and a load capacitor CL. R1 and R2 are integrated inside the chip to provide a fixed -5V output. R1S and R2S are external feedback resistors with adjustable resistance. The output circuit module 500 provides adjustable output by adjusting the resistance values of the external feedback resistors R1S and R2S.

In this embodiment, a schematic diagram of a symbol of an LDO linear regulator with a new CMOS structure is also provided, as shown in FIG. The device circuit module 400symbol and the output circuit module 500.

The bias circuit module 100 provides a suitable bias voltage for all levels of circuits; the bandgap reference source circuit module 200 provides a stable voltage for the subsequent stage circuit and is used as the input stage of the new LDO; the error amplifier circuit module 300 is used to compare the output feedback sampling The signal and the reference voltage control the working state of the subsequent stage circuit to keep the output stable; the output terminal of the comparator circuit module 400 is connected with the double-throw switch SW to control the output of the LDO; the output circuit module 500 is composed of a power adjustment tube, a double-throw The switch SW and the load are jointly formed, wherein the power adjustment tube, the feedback resistor and the error amplifier circuit module 300 form a negative feedback loop, and the output Vout is drawn out at the drain end of the power adjustment tube.

The bias circuit module 100 is connected to the -9V power supply at room temperature; the output terminal is Vout, and the bandgap reference source circuit module 200, the error amplifier circuit module 300 and the comparator circuit module 400 are connected through Vout to form the bandgap reference source circuit module 200 , error amplifier circuit block 300 and comparator circuit block 400 provide appropriate bias.

The bandgap reference source circuit module 200 is connected to the -9V power supply at room temperature, and the BIAS terminal is connected to the bias voltage provided by the bias circuit module 100; the output terminal is REF_OUT, which is connected to the negative input terminal of the error amplifier circuit module 300, which is the error The amplifier circuit module 300 provides a stable reference voltage.

The error amplifier circuit module 300 adopts a PMOS transistor as an input, which can reduce the influence of input noise, and what the current mirror adopts is a self-biased folded cascode (cascode) current mirror, which has a very high gain; the error amplifier circuit module 300 The negative input terminal of the negative input terminal is connected to the REF_OUT terminal of the bandgap reference source circuit module 200, the positive terminal is connected to the double-throw switch SW in the output circuit module 500, and the output terminal is connected to the gate of the power regulator Mp in the output circuit module 500 , VBIAS is the bias voltage.

The comparator circuit module 400 is connected to the -9V power supply at room temperature, and the BIAS terminal is connected to the bias voltage provided by the bias circuit module 100; the non-inverting input terminal of the inverter is connected to GND, the reverse input terminal is SET, and the switch SWO is connected; is the OUT terminal, which is connected to the double-throw switch SW in the output circuit module 500 .

The gate of the power regulator Mp in the output circuit module 500 is connected to the output of the error amplifier circuit module 300, and the drain is connected to the load resistors R1, R2, R1S, R2S and the load capacitor CL. The load resistor RL constitutes the output of the new LDO.

When the power supply voltage VIN is -2～-18V, the adjustable output voltage is -1.3V～VIN+0.5V, Iout=15mA, the linear adjustment rate is 0.015%, the load adjustment rate is 0.85Ω, and adopts 0.6um full dielectric isolation CMOS Under the conditions of the technology, the stability simulation curve of the LDO linear voltage regulator with the new CMOS structure of the present invention is measured, and the result is shown in Figure 8, from which it can be seen that the system has very high stability.

The novel CMOS structure LDO linear regulator of the present invention can work under negative power supply voltage, has low power consumption, constant bandwidth, strong system transient response capability, can realize self-fixed -5V output, and can also use an external feedback resistor to realize Adjustable output.

The above descriptions are only preferred embodiments of the present invention, and are not intended to limit the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention shall be included in the protection of the present invention. within range.

Claims (7)

1. the LDO linear voltage regulators of New-type CMOS structure, which is characterized in that including：Biasing circuit module, band-gap reference source circuit Module, error amplifier circuit module, comparator circuit module and output circuit module；

The biasing circuit module provides suitable bias voltage for late-class circuit；

The band-gap reference source circuit module provides stable voltage and as the input stage of new LDO for late-class circuit；

The error amplifier circuit module for comparing output feedback sample signal and reference voltage, and controls late-class circuit Working condition, make output keep stablize；

The comparator circuit module output terminal is connected with commutator, controls the output of LDO；

The output circuit module, is collectively formed by power adjustment pipe, commutator and load.

2. the LDO linear voltage regulators of New-type CMOS structure as described in claim 1, which is characterized in that the biasing circuit mould Block uses automatic biasing structure, and bias voltage that is reliable and stablizing is provided to entire circuit.

3. the LDO linear voltage regulators of New-type CMOS structure as claimed in claim 2, which is characterized in that the band gap reference Circuit module uses β second order compensation band-gap reference circuit structures, and benchmark electricity that is temperature independent and stablizing is provided for late-class circuit Pressure.

4. the LDO linear voltage regulators of New-type CMOS structure as claimed in claim 3, which is characterized in that the error amplifier Circuit module uses Foldable cascade structure, has high-gain.

5. the LDO linear voltage regulators of New-type CMOS structure as claimed in claim 4, which is characterized in that the comparator circuit Module uses two stage amplifer structure.

6. the LDO linear voltage regulators of New-type CMOS structure as claimed in claim 5, which is characterized in that the error amplifier Circuit module has low operating supply voltage, low static working current, wide bandwidth, high open-loop gain and high PSRR.

7. the LDO linear voltage regulators of New-type CMOS structure as claimed in claim 6, which is characterized in that the comparator circuit Module reaches LDO and exports adjustable purpose by selecting node A, B of commutator SW.