CN116243749A - Low-dropout linear voltage regulator and electronic equipment - Google Patents
Low-dropout linear voltage regulator and electronic equipment Download PDFInfo
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- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is DC
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- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
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Abstract
The application discloses a low dropout linear voltage regulator and electronic equipment, this LDO utilizes the output current of current sampling module acquisition output module to adjust the size of mirror image current mirror image to the error amplifier in order to realize the purpose of adjusting mirror image current according to the size of the output load of LDO, realized when light load or zero load, reduced the static power consumption's of LDO purpose. Meanwhile, the error amplifier of the LDO provided by the embodiment of the application amplifies the reference voltage by at least two stages, which is favorable for improving the loop gain of the LDO, and the high loop gain and the good open loop gain are favorable for improving the power supply rejection ratio of the LDO. In addition, the LDO adopts a mode that the output voltage follows the reference voltage, so that the noise influence caused by a feedback network is cut off, the noise performance is greatly optimized, and meanwhile, the noise of the error amplifier is reduced along with the increase of the current in a mode of dynamically adjusting the mirror current, so that the noise performance is optimized in two aspects.
Description
Technical Field
The present disclosure relates to integrated circuit technology, and more particularly, to a low dropout linear voltage regulator and an electronic device.
Background
The low dropout linear regulator (Low Dropout Regulator, LDO) is a very important product in the category of power management products, and the product is widely applied to consumer electronics such as mobile phones, computers, tablets and the like. Because the low dropout linear voltage regulator has the characteristics of small ripple and small noise, the low dropout linear voltage regulator is required to be used for supplying power in all circuits with high requirements on noise and interference.
With the wider and wider use of low dropout linear regulators, certain application scenarios (e.g., wearable devices, internet of things (Internet of Things, IOT) devices) put higher demands on the static power consumption of the low dropout linear regulators.
Disclosure of Invention
In order to solve the technical problems, the application provides a low dropout linear voltage regulator and electronic equipment, so as to achieve the purpose of reducing the static power consumption of the low dropout linear voltage regulator.
In order to achieve the technical purpose, the embodiment of the application provides the following technical scheme:
a low dropout linear regulator comprising: the device comprises a reference voltage module, an error amplifier, a current sampling module, a buffer module and an output module; wherein,,
the reference voltage module is used for generating a reference voltage;
the current sampling module is used for obtaining the output current of the output module and adjusting the magnitude of the mirror current mirrored in the error amplifier based on the output current, and the magnitude of the mirror current is positively related to the magnitude of the output current;
the error amplifier is used for amplifying the reference voltage at least two stages based on the reference voltage, the mirror current and the output voltage of the output module so as to obtain a driving voltage;
the buffer module is used for buffering the driving voltage;
and the output module is used for determining and outputting an output voltage based on the driving voltage after the buffer processing.
Optionally, the mirrored current includes a first current and a second current;
the error amplifier includes: a first-stage amplifying unit and a second-stage amplifying unit; wherein,,
the first-stage amplifying unit is used for amplifying the reference voltage for the first time based on the reference voltage, the first current and the output voltage of the output module;
the second-stage amplifying unit is configured to amplify the reference voltage after the first amplification for the second time based on the reference voltage, the second current, and the output voltage of the output module, so as to obtain the driving voltage.
Optionally, the first stage amplifying unit includes: a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and a first current source; wherein,,
the control end of the first transistor is electrically connected with the control end of the second transistor, the second end of the first transistor and the second end of the third transistor, and the first end of the first transistor is electrically connected with the first end of the second transistor and the working power supply input end;
a second terminal of the second transistor is electrically connected to a second terminal of the fourth transistor and to a first terminal of the compensation network;
the control end of the third transistor is electrically connected with the control end of the fourth transistor, and the control end of the third transistor is used for receiving the reference voltage;
a first end of the third transistor is electrically connected with a second end of the fifth transistor, and a first end of the fourth transistor is electrically connected with a second end of the sixth transistor;
the control end of the fifth transistor is used for receiving the reference voltage, and the first end of the fifth transistor is electrically connected with the first end of the sixth transistor and the second end of the seventh transistor;
the control end of the sixth transistor is used for receiving the output voltage;
the control end of the seventh transistor is electrically connected with the output end of the current sampling module, and the first end of the seventh transistor is grounded;
one end of the first current source is electrically connected with the first end of the fifth transistor, and the other end of the first current source is grounded;
the second-stage amplifying unit includes: an eighth transistor, a ninth transistor, and a second current source; wherein,,
the first end of the eighth transistor is electrically connected with the working voltage input end, the control end of the eighth transistor is electrically connected with the second end of the second transistor and the first end of the compensation network, and the second end of the eighth transistor is electrically connected with the input end of the buffer unit, the second end of the ninth transistor, one end of the second current source and the second end of the compensation network;
the control end of the ninth transistor is electrically connected with the output end of the current sampling module, and the first end of the ninth transistor is grounded;
one end of the second current source far away from the eighth transistor is grounded;
the first transistor, the second transistor and the eighth transistor are of a first type, and the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor and the ninth transistor are of a second type.
Optionally, the error amplifier further includes: a compensation network;
the compensation network is connected between the first-stage amplifying unit and the second-stage amplifying unit, and is used for adjusting zero point based on a dynamic Miller compensation mode.
Optionally, the compensation network includes: the first resistor, the second resistor, the first capacitor and the second capacitor; wherein,,
one end of the first resistor is connected with one end of the second resistor and is used as a first end of the compensation network;
the other end of the first resistor is electrically connected with one end of the first capacitor, and the other end of the first capacitor is connected with one end of the second capacitor and serves as a second end of the compensation network;
one end of the second capacitor, which is far away from the first capacitor, is electrically connected with one end of the second resistor, which is far away from the first resistor; the second resistor is a resistor with a variable resistance.
Optionally, the output module includes an output transistor;
the control end of the output transistor is connected with the output end of the buffer module, the second end of the output transistor is electrically connected with the working voltage input end, and the first end of the output transistor is used as the output end of the output module.
7. The low dropout linear regulator according to claim 6, wherein said current sampling module comprises: a tenth transistor, an eleventh transistor, a twelfth transistor, a thirteenth transistor, a fourteenth transistor, a third resistor, and a third capacitor; wherein,,
a first end of the tenth transistor is electrically connected with the working voltage input end, a control end of the tenth transistor is electrically connected with the control end of the output transistor, and a second end of the tenth transistor is electrically connected with the first end of the eleventh transistor;
the control end of the eleventh transistor is electrically connected with the control end of the twelfth transistor and the second end of the twelfth transistor, and the second end of the eleventh transistor is electrically connected with the second end of the thirteenth transistor, the control end of the fourteenth transistor and one end of the third resistor;
a first terminal of the twelfth transistor is for receiving the output voltage;
a first end of the thirteenth transistor is electrically connected with a first end of the fourteenth transistor and one end of the third capacitor, and is grounded;
one end of the third resistor, which is far away from the thirteenth transistor, is electrically connected with the other end of the third capacitor and is used as an output end of the current sampling module;
the tenth transistor, the eleventh transistor, and the twelfth transistor are all transistors of a first type, and the thirteenth transistor and the fourteenth transistor are all transistors of a second type.
Optionally, the buffer module includes: a fifteenth transistor, a sixteenth transistor, a seventeenth transistor, and an eighteenth transistor; wherein,,
the second end of the fifteenth transistor is electrically connected with the second end of the sixteenth transistor, one end of the third current source and the working voltage input end, the control end of the fifteenth transistor is electrically connected with the control end of the sixteenth transistor, and the first end of the fifteenth transistor is electrically connected with the other end of the third current source, the second end of the seventeenth transistor, the control end of the seventeenth transistor and the control end of the eighteenth transistor as the input ends of the buffer module;
a first end of the sixteenth transistor is electrically connected with a second end of the eighteenth transistor and is used as an output end of the buffer module;
a first terminal of the seventeenth transistor is electrically connected to the first terminal of the eighteenth transistor and is grounded;
the fifteenth transistor, the sixteenth transistor, the seventeenth transistor, and the eighteenth transistor are all transistors of a second type.
Optionally, the first type transistor includes a P-type MOS transistor, and the second type transistor includes an N-type MOS transistor.
Correspondingly, the invention also provides electronic equipment, which comprises: such as the low dropout linear regulator described above.
According to the technical scheme, the embodiment of the application provides the low-dropout linear voltage regulator and the electronic equipment, wherein the low-dropout linear voltage regulator obtains the output current of the output module by using the current sampling module, and adjusts the magnitude of the mirror current mirrored in the error amplifier based on the output current, so that the purpose of adjusting the mirror current according to the magnitude of the output load of the low-dropout linear voltage regulator is achieved, the purpose of reducing the magnitude of the mirror current in the error amplifier during light load or zero load is achieved, and the purpose of reducing the static power consumption of the low-dropout linear voltage regulator is achieved.
Meanwhile, the error amplifier of the low dropout linear voltage regulator provided by the embodiment of the application amplifies the reference voltage by at least two stages, which is favorable for improving the loop gain of the low dropout linear voltage regulator, and the high loop gain and the good open loop gain are favorable for improving the power supply rejection ratio (Power Supply Rejection Ratio, PSRR) of the low dropout linear voltage regulator.
In addition, the low dropout linear voltage regulator provided by the embodiment of the application adopts a mode that the output voltage follows the reference voltage, so that noise influence caused by a feedback network is cut off, noise performance is greatly optimized, and meanwhile, due to the mode of dynamically adjusting mirror current, noise of an error amplifier is reduced along with the increase of current, and noise performance is optimized in two aspects.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are required to be used in the embodiments or the description of the prior art will be briefly described below, and it is obvious that the drawings in the following description are only embodiments of the present application, and that other drawings may be obtained according to the provided drawings without inventive effort to a person skilled in the art.
FIG. 1 is a schematic diagram of a frame structure of a low dropout linear regulator according to an embodiment of the present application;
FIG. 2 is a schematic diagram of a low dropout linear regulator according to an embodiment of the present disclosure;
fig. 3 is a schematic diagram of a frame structure of a low dropout linear regulator according to another embodiment of the present application.
Detailed Description
The following description of the embodiments of the present application will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all, of the embodiments of the present application. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the present disclosure, are within the scope of the present disclosure.
The embodiment of the application provides a low dropout linear voltage regulator, as shown in fig. 1, comprising: a reference voltage module 10, an error amplifier 20, a current sampling module 50, a buffer module 30, and an output module 40; wherein,,
the reference voltage module 10 is used for generating a reference voltage;
the current sampling module 50 is configured to obtain an output current of the output module 40, and adjust a magnitude of an image current mirrored into the error amplifier 20 based on the output current, where the magnitude of the image current is positively correlated with the magnitude of the output current;
the error amplifier 20 is configured to amplify the reference voltage at least in two stages based on the reference voltage, the mirror current, and the output voltage of the output module 40, so as to obtain a driving voltage;
the buffer module 30 is configured to buffer the driving voltage;
the output module 40 is configured to determine an output voltage based on the buffered driving voltage and output the determined output voltage.
In fig. 1, vout represents the output voltage, RL represents the output resistance of the output module, CL represents the capacitance in the output application, and VDD represents the power supply voltage.
In this embodiment, the low dropout linear regulator obtains the output current of the output module 40 by using the current sampling module 50, and adjusts the magnitude of the mirror current mirrored in the error amplifier 20 based on the output current, so as to achieve the purpose of adjusting the mirror current according to the magnitude of the output load of the low dropout linear regulator, and achieve the purpose of reducing the magnitude of the mirror current in the error amplifier 20 during light load or zero load, thereby achieving the purpose of reducing the static power consumption of the low dropout linear regulator.
Meanwhile, the error amplifier 20 of the low dropout linear regulator provided in the embodiment of the present application amplifies the reference voltage by at least two stages, which is favorable for improving the loop gain of the low dropout linear regulator, and the high loop gain and the good open loop gain are favorable for improving the power supply rejection ratio (Power Supply Rejection Ratio, PSRR) of the low dropout linear regulator.
In addition, the low dropout linear voltage regulator provided by the embodiment of the application adopts a mode that the output voltage follows the reference voltage, thus cutting down the noise influence caused by the feedback network, greatly optimizing the noise performance, and simultaneously optimizing the noise performance in two aspects because the noise of the error amplifier 20 is reduced along with the increase of the current in a mode of dynamically adjusting the mirror current.
The following describes possible structures of each module of the low dropout linear regulator provided in the embodiments of the present application.
Optionally, referring to fig. 2, the mirrored current includes a first current and a second current;
the error amplifier 20 includes: a first-stage amplification unit 21 and a second-stage amplification unit 22; wherein,,
the first stage amplifying unit 21 is configured to amplify the reference voltage for the first time based on the reference voltage, the first current, and the output voltage of the output module 40;
the second stage amplifying unit 22 is configured to amplify the reference voltage after the first amplification for the second time based on the reference voltage, the second current, and the output voltage of the output module 40, so as to obtain the driving voltage.
Optionally, still referring to fig. 2, the first stage amplifying unit 21 includes: a first transistor Q1, a second transistor Q2, a third transistor Q3, a fourth transistor Q4, a fifth transistor Q5, a sixth transistor Q6, a seventh transistor Q7, and a first current source I1; wherein,,
the control end of the first transistor Q1 is electrically connected to the control end of the second transistor Q2, the second end of the first transistor Q1 and the second end of the third transistor Q3, and the first end of the first transistor Q1 is electrically connected to the first end of the second transistor Q2 and the working power input end;
a second end of the second transistor Q2 is electrically connected to a second end of the fourth transistor Q4 and a first end of the compensation network;
the control end of the third transistor Q3 is electrically connected to the control end of the fourth transistor Q4, and the control end of the third transistor Q3 is configured to receive the reference voltage;
a first terminal of the third transistor Q3 is electrically connected to a second terminal of the fifth transistor Q5, and a first terminal of the fourth transistor Q4 is electrically connected to a second terminal of the sixth transistor Q6;
the control terminal of the fifth transistor Q5 is configured to receive the reference voltage, and the first terminal of the fifth transistor Q5 is electrically connected to the first terminal of the sixth transistor Q6 and the second terminal of the seventh transistor Q7;
the control end of the sixth transistor Q6 is used for receiving the output voltage;
the control end of the seventh transistor Q7 is electrically connected to the output end of the current sampling module 50, and the first end of the seventh transistor Q7 is grounded;
one end of the first current source I1 is electrically connected to the first end of the fifth transistor Q5, and the other end of the first current source I1 is grounded;
the second-stage amplification unit 22 includes: an eighth transistor Q8, a ninth transistor Q9, and a second current source I2; wherein,,
the first end of the eighth transistor Q8 is electrically connected to the working voltage input end, the control end of the eighth transistor Q8 is electrically connected to the second end of the second transistor Q2 and the first end of the compensation network, and the second end of the eighth transistor Q8 is electrically connected to the input end of the buffer unit, the second end of the ninth transistor Q9, one end of the second current source I2 and the second end of the compensation network;
a control end of the ninth transistor Q9 is electrically connected to the output end of the current sampling module 50, and a first end of the ninth transistor Q9 is grounded;
one end of the second current source I2, which is far away from the eighth transistor Q8, is grounded;
the first transistor Q1, the second transistor Q2, and the eighth transistor Q8 are transistors of a first type, and the third transistor Q3, the fourth transistor Q4, the fifth transistor Q5, the sixth transistor Q6, the seventh transistor Q7, and the ninth transistor Q9 are transistors of a second type.
Optionally, the first type transistor is a P-type MOS transistor (Metal-Oxide-Semiconductor Field-Effect Transistor), and the second type transistor is an N-type MOS transistor.
With respect to the error amplifier 20, optionally, still referring to fig. 2, the error amplifier 20 further comprises: a compensation network 23;
the compensation network 23 is connected between the first stage amplification unit 21 and the second stage amplification unit 22, and the compensation network 23 is used for adjusting zero point based on a dynamic miller compensation mode.
In this embodiment, the compensation network 23 is implemented in a dynamic miller compensation manner, and is used to adjust the zero points under different load output currents, so as to follow the change of the poles and improve the stability of the whole feedback system.
Optionally, the compensation network 23 includes: the first resistor R1, the second resistor R2, the first capacitor C1 and the second capacitor C2; wherein,,
one end of the first resistor R1 is connected with one end of the second resistor R2 and is used as a first end of the compensation network;
the other end of the first resistor R1 is electrically connected with one end of the first capacitor C1, and the other end of the first capacitor C1 is connected with one end of the second capacitor C2 to serve as a second end of the compensation network;
one end of the second capacitor C2 away from the first capacitor C1 is electrically connected with one end of the second resistor R2 away from the first resistor R1; the second resistor R2 is a resistor with a variable resistance.
Referring to fig. 2, optionally, the output module 40 includes an output transistor Q19;
the control terminal of the output transistor Q19 is connected to the output terminal of the buffer module 30, the second terminal of the output transistor Q19 is electrically connected to the operating voltage input terminal, and the first terminal of the output transistor Q19 is used as the output terminal of the output module 40.
Still referring to fig. 2, the current sampling module 50 includes: a tenth transistor Q10, an eleventh transistor Q11, a twelfth transistor Q12, a thirteenth transistor Q13, a fourteenth transistor Q14, a third resistor R3, and a third capacitor C3; wherein,,
a first end of the tenth transistor Q10 is electrically connected to the operating voltage input end, a control end of the tenth transistor Q10 is electrically connected to the control end of the output transistor Q19, and a second end of the tenth transistor Q10 is electrically connected to the first end of the eleventh transistor Q11;
a control terminal of the eleventh transistor Q11 is electrically connected to the control terminal of the twelfth transistor Q12 and the second terminal of the twelfth transistor Q12, and the second terminal of the eleventh transistor Q11 is electrically connected to the second terminal of the thirteenth transistor Q13, the control terminal of the fourteenth transistor Q14 and one terminal of the third resistor R3;
a first terminal of the twelfth transistor Q12 is configured to receive the output voltage;
a first end of the thirteenth transistor Q13 is electrically connected to the first end of the fourteenth transistor Q14 and one end of the third capacitor C3, and is grounded;
one end of the third resistor R3 far away from the thirteenth transistor Q13 is electrically connected to the other end of the third capacitor C3, and is used as an output end of the current sampling module 50;
the tenth transistor Q10, the eleventh transistor Q11, and the twelfth transistor Q12 are all transistors of a first type, and the thirteenth transistor Q13 and the fourteenth transistor Q14 are all transistors of a second type.
The buffer module 30 includes: a fifteenth transistor Q15, a sixteenth transistor Q16, a seventeenth transistor Q17, and an eighteenth transistor Q18; wherein,,
a second end of the fifteenth transistor Q15 is electrically connected to the second end of the sixteenth transistor Q16, one end of the third current source I3, and an operating voltage input end, a control end of the fifteenth transistor Q15 is electrically connected to the control end of the sixteenth transistor Q16, and as an input end of the buffer module 30, a first end of the fifteenth transistor Q15 is electrically connected to the other end of the third current source I3, the second end of the seventeenth transistor Q17, the control end of the seventeenth transistor Q17, and the control end of the eighteenth transistor Q18;
a first terminal of the sixteenth transistor Q16 is electrically connected to a second terminal of the eighteenth transistor Q18 as an output terminal of the buffer module 30;
a first terminal of the seventeenth transistor Q17 is electrically connected to the first terminal of the eighteenth transistor Q18 and is grounded;
the fifteenth transistor Q15, the sixteenth transistor Q16, the seventeenth transistor Q17, and the eighteenth transistor Q18 are all transistors of the second type.
Similarly, the first type transistor may be a P-type MOS transistor, and the second type transistor may be an N-type MOS transistor.
Optionally, the control end of the first type transistor may be a gate of the P-type MOS transistor, the first end of the first type transistor may be a source of the P-type MOS transistor, and the second end of the first type transistor may be a drain of the P-type MOS transistor. Correspondingly, the control end of the second type transistor can be the grid electrode of the N type MOS transistor, the first end of the second type transistor can be the source electrode of the N type MOS transistor, and the second end of the second type transistor can be the drain electrode of the N type MOS transistor.
In fig. 2, PGATE represents the control terminal potential of the output transistor Q19.
Referring to fig. 3, the reference voltage module 10 includes a voltage generating unit 11 and a voltage filtering unit 12, the voltage generating unit 11 generating an adjustable voltage to fix an output feedback loop of the low dropout linear regulator to 1 such that a performance parameter of the low dropout linear regulator does not vary with a variation in a ratio of an output voltage to the reference voltage. The voltage generated by the voltage generating unit 11 realizes the reference voltage with low noise and high power supply rejection ratio through a voltage filtering unit 12, thereby providing the front-stage assurance for the performance parameters of the low dropout linear voltage regulator. Optionally, the voltage filtering unit 12 may include a third resistor R3 and a third capacitor C3, where a resistance value of the third resistor R3 is adjustable.
The buffer module 30 of the low dropout linear regulator follows the filtered reference voltage to the output voltage, thus cutting down the noise influence caused by the feedback network, greatly optimizing the noise performance, and simultaneously, the noise of the error amplifier 20 is reduced along with the increase of the current due to the mode of dynamically adjusting the mirror current, and the noise performance is optimized in two aspects.
For the low dropout linear regulator shown in fig. 2, the seventh transistor Q7, the fifth transistor Q5, the sixth transistor Q6, the first transistor Q1, and the second transistor Q2 serve as a first stage differential to single ended output gain stage; the eighth transistor Q8 and the ninth transistor Q9 provide a higher gain as a second stage common source stage output gain stage. The output transistor Q19 provides a large current drive capability as a power stage output; a first stage buffer module 30 is interposed between the output transistor Q19 and the second stage output, the B buffer module 30 providing unity gain output capability, pushing the pole of the power stage output to high frequency, while enhancing transient response.
The power-up process and the working state of the low dropout linear regulator shown in fig. 2 include: when the power supply voltage VDD is powered up, the reference voltage VREF is first established, and then the paths of the third transistor Q3, the first transistor Q1, the fifth transistor Q5 and the first current source I1 are established, the drain voltage of the second transistor Q2 is pulled to the power supply VDD by the second transistor Q2, the gate-source voltage vgs=0 of the eighth transistor Q8 is pulled to the ground by the second current source I2, the output transistor Q19 is driven by the following buffer module 30, and at this time, the output transistor Q19 is turned on, the pull-up current is strong, the output voltage of the low dropout regulator is driven to be established, the whole loop also follows the function, and since the loop adopts the negative feedback, the gate voltage of the sixth transistor Q6 is virtually shortened to the ground, that is, the output voltage is equal to the reference voltage after the establishment is stabilized.
This time is divided into two cases of load current magnitude:
when the low dropout linear regulator output is driven in the light load mode (the output current range is in the order of 0-1 mA), the pole formed by the external capacitor and the output resistor of the output transistor Q19 is closer to the origin, the output of the first stage amplifying unit of the error amplifier 20 is also lower in frequency because the pole generated by miller compensation is very low, and a zero point is also required to compensate for the phase margin, so that the output resistor R2 of the second stage amplifying unit becomes larger at this time, thereby generating a zero point of low frequency, as expressed by the following expression:
when the output drive of the low dropout linear regulator is in a heavy load mode (the output current range is 1mA to the magnitude of full load current), the bias currents of the first-stage amplifying unit and the second-stage amplifying unit are increased along with the increase of load current, which is called a dynamic bias current technology. The positions of all poles are changed at this time, the output pole becomes higher to become a non-main pole point due to the reduction of the output resistance, and the output of the first-stage amplifying unit becomes a main pole due to the miller compensation effect, and a zero is needed to compensate for the reduced output pole at this time, so that the output resistance R2 of the second-stage amplifying unit becomes smaller and a smaller zero is generated. In the heavy load mode, the buffer module 30 has the advantage of pushing the poles of the output and output transistors Q19 of the second stage amplifying unit outside the bandwidth of the whole system, so that the influence on the phase margin is reduced.
In the above formula, P0 represents a pole (i.e., an output pole) of the output of the first stage amplifying unit of the error amplifier 20 due to miller compensation, P1 represents a pole formed by a plug-in capacitance and an output resistance of the output transistor Q19, Z0 represents a zero point, ri represents an output resistance of the first stage amplifying unit, gm2 represents a transconductance of the second stage amplifying unit, rj represents an output resistance of the second stage amplifying unit, RL represents an output resistance of the output transistor Q19, CL represents a capacitance in output application, ci represents miller capacitance, cj represents parallel miller capacitance, and compensation effects caused by equivalent series resistances (Equivalent Series Resistance, ESR) are ignored at this time.
Correspondingly, the embodiment of the application also provides electronic equipment comprising the low dropout linear regulator according to any one of the embodiments.
In summary, the embodiments of the present application provide a low dropout linear voltage regulator and an electronic device, where the low dropout linear voltage regulator obtains an output current of an output module 40 by using a current sampling module 50, and adjusts a magnitude of a mirror current mirrored in an error amplifier 20 based on the output current, so as to achieve a purpose of adjusting the mirror current according to a magnitude of an output load of the low dropout linear voltage regulator, and achieve a purpose of reducing the magnitude of the mirror current in the error amplifier 20 during light load or zero load, thereby achieving a purpose of reducing static power consumption of the low dropout linear voltage regulator.
Meanwhile, the error amplifier 20 of the low dropout linear voltage regulator provided by the embodiment of the application amplifies the reference voltage by at least two stages, which is favorable for improving the loop gain of the low dropout linear voltage regulator, and the high loop gain and the good open loop gain are favorable for improving the power supply rejection ratio of the low dropout linear voltage regulator.
In addition, the low dropout linear voltage regulator provided by the embodiment of the application adopts a mode that the output voltage follows the reference voltage, thus cutting down the noise influence caused by the feedback network, greatly optimizing the noise performance, and simultaneously optimizing the noise performance in two aspects because the noise of the error amplifier 20 is reduced along with the increase of the current in a mode of dynamically adjusting the mirror current.
Features described in the embodiments in this specification may be replaced or combined with each other, and each embodiment is mainly described in the differences from the other embodiments, and identical and similar parts between the embodiments are all enough to be referred to each other.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the application. Thus, the present application is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (10)
1. A low dropout linear regulator, comprising: the device comprises a reference voltage module, an error amplifier, a current sampling module, a buffer module and an output module; wherein,,
the reference voltage module is used for generating a reference voltage;
the current sampling module is used for obtaining the output current of the output module and adjusting the magnitude of the mirror current mirrored in the error amplifier based on the output current, and the magnitude of the mirror current is positively related to the magnitude of the output current;
the error amplifier is used for amplifying the reference voltage at least two stages based on the reference voltage, the mirror current and the output voltage of the output module so as to obtain a driving voltage;
the buffer module is used for buffering the driving voltage;
and the output module is used for determining and outputting an output voltage based on the driving voltage after the buffer processing.
2. The low dropout linear regulator of claim 1, wherein the mirror current comprises a first current and a second current;
the error amplifier includes: a first-stage amplifying unit and a second-stage amplifying unit; wherein,,
the first-stage amplifying unit is used for amplifying the reference voltage for the first time based on the reference voltage, the first current and the output voltage of the output module;
the second-stage amplifying unit is configured to amplify the reference voltage after the first amplification for the second time based on the reference voltage, the second current, and the output voltage of the output module, so as to obtain the driving voltage.
3. The low dropout linear regulator according to claim 2, wherein said first stage amplifying unit includes: a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and a first current source; wherein,,
the control end of the first transistor is electrically connected with the control end of the second transistor, the second end of the first transistor and the second end of the third transistor, and the first end of the first transistor is electrically connected with the first end of the second transistor and the working power supply input end;
a second terminal of the second transistor is electrically connected to a second terminal of the fourth transistor and to a first terminal of the compensation network;
the control end of the third transistor is electrically connected with the control end of the fourth transistor, and the control end of the third transistor is used for receiving the reference voltage;
a first end of the third transistor is electrically connected with a second end of the fifth transistor, and a first end of the fourth transistor is electrically connected with a second end of the sixth transistor;
the control end of the fifth transistor is used for receiving the reference voltage, and the first end of the fifth transistor is electrically connected with the first end of the sixth transistor and the second end of the seventh transistor;
the control end of the sixth transistor is used for receiving the output voltage;
the control end of the seventh transistor is electrically connected with the output end of the current sampling module, and the first end of the seventh transistor is grounded;
one end of the first current source is electrically connected with the first end of the fifth transistor, and the other end of the first current source is grounded;
the second-stage amplifying unit includes: an eighth transistor, a ninth transistor, and a second current source; wherein,,
the first end of the eighth transistor is electrically connected with the working voltage input end, the control end of the eighth transistor is electrically connected with the second end of the second transistor and the first end of the compensation network, and the second end of the eighth transistor is electrically connected with the input end of the buffer unit, the second end of the ninth transistor, one end of the second current source and the second end of the compensation network;
the control end of the ninth transistor is electrically connected with the output end of the current sampling module, and the first end of the ninth transistor is grounded;
one end of the second current source far away from the eighth transistor is grounded;
the first transistor, the second transistor and the eighth transistor are of a first type, and the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor and the ninth transistor are of a second type.
4. The low dropout linear regulator according to claim 2, wherein said error amplifier further comprises: a compensation network;
the compensation network is connected between the first-stage amplifying unit and the second-stage amplifying unit, and is used for adjusting zero point based on a dynamic Miller compensation mode.
5. The low dropout linear regulator according to claim 4, wherein said compensation network comprises: the first resistor, the second resistor, the first capacitor and the second capacitor; wherein,,
one end of the first resistor is connected with one end of the second resistor and is used as a first end of the compensation network;
the other end of the first resistor is electrically connected with one end of the first capacitor, and the other end of the first capacitor is connected with one end of the second capacitor and serves as a second end of the compensation network;
one end of the second capacitor, which is far away from the first capacitor, is electrically connected with one end of the second resistor, which is far away from the first resistor; the second resistor is a resistor with a variable resistance.
6. The low dropout linear regulator according to claim 1, wherein said output module comprises an output transistor;
the control end of the output transistor is connected with the output end of the buffer module, the second end of the output transistor is electrically connected with the working voltage input end, and the first end of the output transistor is used as the output end of the output module.
7. The low dropout linear regulator according to claim 6, wherein said current sampling module comprises: a tenth transistor, an eleventh transistor, a twelfth transistor, a thirteenth transistor, a fourteenth transistor, a third resistor, and a third capacitor; wherein,,
a first end of the tenth transistor is electrically connected with the working voltage input end, a control end of the tenth transistor is electrically connected with the control end of the output transistor, and a second end of the tenth transistor is electrically connected with the first end of the eleventh transistor;
the control end of the eleventh transistor is electrically connected with the control end of the twelfth transistor and the second end of the twelfth transistor, and the second end of the eleventh transistor is electrically connected with the second end of the thirteenth transistor, the control end of the fourteenth transistor and one end of the third resistor;
a first terminal of the twelfth transistor is for receiving the output voltage;
a first end of the thirteenth transistor is electrically connected with a first end of the fourteenth transistor and one end of the third capacitor, and is grounded;
one end of the third resistor, which is far away from the thirteenth transistor, is electrically connected with the other end of the third capacitor and is used as an output end of the current sampling module;
the tenth transistor, the eleventh transistor, and the twelfth transistor are all transistors of a first type, and the thirteenth transistor and the fourteenth transistor are all transistors of a second type.
8. The low dropout linear regulator according to claim 6, wherein said buffer module comprises: a fifteenth transistor, a sixteenth transistor, a seventeenth transistor, and an eighteenth transistor; wherein,,
the second end of the fifteenth transistor is electrically connected with the second end of the sixteenth transistor, one end of the third current source and the working voltage input end, the control end of the fifteenth transistor is electrically connected with the control end of the sixteenth transistor, and the first end of the fifteenth transistor is electrically connected with the other end of the third current source, the second end of the seventeenth transistor, the control end of the seventeenth transistor and the control end of the eighteenth transistor as the input ends of the buffer module;
a first end of the sixteenth transistor is electrically connected with a second end of the eighteenth transistor and is used as an output end of the buffer module;
a first terminal of the seventeenth transistor is electrically connected to the first terminal of the eighteenth transistor and is grounded;
the fifteenth transistor, the sixteenth transistor, the seventeenth transistor, and the eighteenth transistor are all transistors of a second type.
9. The low dropout linear regulator according to any one of claims 3 or 7, wherein said first type transistor comprises a P-type MOS transistor and said second type transistor comprises an N-type MOS transistor.
10. An electronic device, comprising: the low dropout linear regulator according to any one of claims 1 to 9.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN118264210A (en) * | 2024-04-01 | 2024-06-28 | 合肥市山海半导体技术有限公司 | LDO circuit and amplifier loop compensation circuit and method thereof |
| CN118426533A (en) * | 2024-07-03 | 2024-08-02 | 深圳飞渡微电子有限公司 | A low noise and high power supply rejection ratio LDO |
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2022
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN118264210A (en) * | 2024-04-01 | 2024-06-28 | 合肥市山海半导体技术有限公司 | LDO circuit and amplifier loop compensation circuit and method thereof |
| CN118426533A (en) * | 2024-07-03 | 2024-08-02 | 深圳飞渡微电子有限公司 | A low noise and high power supply rejection ratio LDO |
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